Intel IXP400 User Manual
Intel® IXP400 Software
Programmer’s Guide
April 2005
Document Number: 252539, Revision: 007
®
IXP400 Software
Intel
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Contents
Contents
1 Introduction..................................................................................................................................19
1.1 Versions Supported by this Document ...............................................................................19
1.2 Hardware Supported by this Release.................................................................................19
1.3 Intended Audience..............................................................................................................19
1.4 How to Use this Document .................................................................................................20
1.5 About the Processors .........................................................................................................20
1.6 Related Documents ............................................................................................................21
1.7 Acronyms............................................................................................................................22
2 Software Architecture Overview ................................................................................................27
2.1 High-Level Overview...........................................................................................................27
2.2 Deliverable Model...............................................................................................................28
2.3 Operating System Support .............................................. ... ... .............................................29
2.4 Development Tools.............................................................................................................29
2.5 Access Library Source Code Documentation.....................................................................29
2.6 Release Directory Structure................................................................................................30
2.7 Threading and Locking Policy.............................................................................................32
2.8 Polled and Interrupt Operation............................................................................................32
2.9 Statistics and MIBs ......... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ...................................................32
2.10 Global Dependency Chart ............................................... ... ... .............................................33
3 Buffer Management.....................................................................................................................35
3.1 What’s New.........................................................................................................................35
3.2 Overview.............................................................................................................................35
3.3 IXP_BUF Structure .............................................................................................................38
3.3.1 IXP_BUF Structure and Macros ............................................................................38
3.4 Mapping of IX_MBUF to Shared Structure .........................................................................43
3.5 IX_MBUF Structure.............................................................................................................44
3.6 Mapping to OS Native Buffer Types ...................................................................................46
3.6.1 VxWorks* M_BLK Buffer........................................................................................46
3.6.2 Linux* skbuff Buffer................................................................................................47
3.7 Caching Strategy ................................................................................................................49
3.7.1 Tx Path ..................................................................................................................49
3.7.2 Rx Path.............................. ... .... ... ... ... ....................................... ... .... ......................50
3.7.3 Caching Strategy Summary...................................................................................50
4 Access-Layer Components:
ATM Driver Access (IxAtmdAcc) API.........................................................................................53
4.1 What’s New.........................................................................................................................53
4.2 Overview.............................................................................................................................53
4.3 IxAtmdAcc Component Features........................................................................................53
4.4 Configuration Services........................................................................................................55
4.4.1 UTOPIA Port-Configuration Service ......................................................................55
4.4.2 ATM Traffic-Shaping Services...............................................................................55
4.4.3 VC-Configuration Services ................................. ... ... ... ....................................... ...56
4.5 Transmission Services........................................................................................................57
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4.5.1 Scheduled Transmission .......................................................................................58
4.5.1.1 Schedule Table Description............................ ... .... ... ... ... .... ... ... ... ... .... ...59
4.5.2 Transmission Triggers (Tx-Low Notification).........................................................60
4.5.2.1 Transmit-Done Processing .......... ... ... .... ... ... ... ... .... ... ... ... .... ... ... .............60
4.5.2.2 Transmit Disconnect..............................................................................62
4.5.3 Receive Services...................................................................................... ... ... .... ...63
4.5.3.1 Receive Triggers (Rx-Free-Low Notification).........................................64
4.5.3.2 Receive Processing...............................................................................64
4.5.3.3 Receive Disconnect...............................................................................66
4.5.4 Buffer Management...............................................................................................67
4.5.4.1 Buffer Allocation.............. ... ... .... ...................................... .... ... ... ... ... .......67
4.5.4.2 Buffer Contents............................... .......................................................67
4.5.4.3 Buffer-Size Constraints..........................................................................69
4.5.4.4 Buffer-Chaining Constraints...................................................................69
4.5.5 Error Handling........................................................................................................69
4.5.5.1 API-Usage Errors......................... ... .......................................... ... ... .......69
4.5.5.2 Real-Time Errors....................................................................................70
5 Access-Layer Components:
ATM Manager (IxAtmm) API .......................................................................................................71
5.1 What’s New.........................................................................................................................71
5.2 IxAtmm Overview................................................................................................................71
5.3 IxAtmm Component Features.............................................................................................71
5.4 UTOPIA Level-2 Port Initialization......................................................................................72
5.5 ATM-Port Management Service Model...............................................................................73
5.6 Tx/Rx Control Configuration ...............................................................................................75
5.7 Dependencies.....................................................................................................................77
5.8 Error Handling.....................................................................................................................77
5.9 Management Interfaces......................................................................................................77
5.10 Memory Requirements .......................................................................................................77
5.11 Performance.......................................................................................................................78
6 Access-Layer Components:
ATM Transmit Scheduler (IxAtmSch) API.................................................................................79
6.1 What’s New.........................................................................................................................79
6.2 Overview.............................................................................................................................79
6.3 IxAtmSch Component Features............................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..........79
6.4 Connection Admission Control (CAC) Function..................................................................81
6.5 Scheduling and Traffic Shaping..........................................................................................82
6.5.1 Schedule Table......................................................................................................82
6.5.1.1 Minimum Cells Value (minCellsToSchedule).........................................83
6.5.1.2 Maximum Cells Value (maxCells)..........................................................83
6.5.2 Schedule Service Model........................................................................................83
6.5.3 Timing and Idle Cells......................... ... ....................................... ... .... ... ... ... ... .... ...84
6.6 Dependencies.....................................................................................................................84
6.7 Error Handling.....................................................................................................................85
6.8 Memory Requirements .......................................................................................................85
6.8.1 Code Size..............................................................................................................85
6.8.2 Data Memory..................... ... ... .... ... ....................................... ... ... ... .... ... ................85
6.9 Performance.......................................................................................................................85
6.9.1 Latency..................................................................................................................86
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7 Access-Layer Components:
Security (IxCryptoAcc) API.........................................................................................................87
7.1 What’s New.........................................................................................................................87
7.2 Overview.............................................................................................................................87
7.3 IxCryptoAcc API Architecture .............................................................................................88
7.3.1 IxCryptoAcc Interfaces...........................................................................................88
7.3.2 Basic API Flow.......................................................................................................89
7.3.3 Context Registration and the Cryptographic Context Database............................90
7.3.4 Buffer and Queue Management ............................................................................93
7.3.5 Memory Requirements ..........................................................................................93
7.3.6 Dependencies........................................................................................................94
7.3.7 Other API Functionality......... .... ... ... ....................................... ... ... .... ... ... ... ... .... ......95
7.3.8 Error Handling........................................................................................................96
7.3.9 Endianness............................................................................................................96
7.3.10 Import and Export of Cryptographic Technology ...................................................96
7.4 IPSec Services ............................................ ... .... ... ... ... .... ... ... ....................................... ......96
7.4.1 IPSec Background and Implementation ...................................... .... ... ... ... ... .... ... ...96
7.4.2 IPSec Packet Formats.............................. ... ... .... ... ... ... ... .... ... ... .............................98
7.4.2.1 Reference ESP Dataflow.......................................................................99
7.4.2.2 Reference AH Dataflow .......................................................................100
7.4.3 Hardware Acceleration for IPSec Services..........................................................101
7.4.4 IPSec API Call Flow..... ... ... ... .... ... ... ....................................... ... ... .... ... ... ... ... .... ....101
7.4.5 Special API Use Cases........................................................................................103
7.4.5.1 HMAC with Key Size Greater Than 64 Bytes ......................................103
7.4.5.2 Performing CCM (AES CTR-Mode Encryption and AES
CBC-MAC Authentication) for IPSec ...................................................103
7.4.6 IPSec Assumptions, Dependencies, and Limitations...........................................106
7.5 WEP Services........................................................ ... ... .... ... ... ... ... .... .................................106
7.5.1 WEP Background and Implementation................................................................106
7.5.2 Hardware Acceleration for WEP Services ...........................................................107
7.5.3 WEP API Call Flow................................ ... ... ... .... ... ...................................... .... ... .108
7.6 SSL and TLS Protocol Usage Models ..............................................................................110
7.7 Supported Encryption and Authentication Algorithms ......................................................111
7.7.1 Encryption Algorithms..........................................................................................111
7.7.2 Cipher Modes .................................... ....................................... ... .... ... ... ... ...........112
7.7.2.1 Electronic Code Book (ECB)................................................................112
7.7.2.2 Cipher Block Chaining (CBC) ..............................................................112
7.7.2.3 Counter Mode (CTR) ...........................................................................112
7.7.2.4 Counter-Mode Encryption with CBC-MAC Authentication (CCM)
for CCMP in 802.11i........... .... ... ... ... .... ... ..............................................112
7.7.3 Authentication Algorithms............................... .... ... ... ... ... .... ... ... ... .... ... ... ..............113
Contents
8 Access-Layer Components:
DMA Access Driver (IxDmaAcc) API........................................................................................115
8.1 What’s New.......................................................................................................................115
8.2 Overview...........................................................................................................................115
8.3 Features............................................................................................................................115
8.4 Assumptions .....................................................................................................................115
8.5 Dependencies...................................................................................................................116
8.6 DMA Access-Layer API ....................................................................................................116
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8.6.1 IxDmaAccDescriptorManager..............................................................................118
8.7 Parameters Description............................ ... ... ..................................................................118
8.7.1 Source Address.................... ... ....................................... ... .... ... ... ... .....................119
8.7.2 Destination Address.............................................................................................119
8.7.3 Transfer Mode .....................................................................................................119
8.7.4 Transfer Width.....................................................................................................119
8.7.5 Addressing Modes...............................................................................................120
8.7.6 Transfer Length ...................................................................................................120
8.7.7 Supported Modes ................................................................................................121
8.8 Data Flow.............................. .... ... ... ... ... .... ...................................... .... ... ... ... .....................123
8.9 Control Flow................................. ... ... ... .... ... ... ... .... ... ....................................... ... ... ... ........123
8.9.1 DMA Initialization.................................................................................................124
8.9.2 DMA Configuration and Data Transfer ................................................................125
8.10 Restrictions of the DMA Transfer......................................................................................127
8.11 Error Handling...................................................................................................................128
8.12 Little Endian............. .... ... ... ... .... ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ...........128
9 Access-Layer Components:
Ethernet Access (IxEthAcc) API...............................................................................................129
9.1 What’s New.......................................................................................................................129
9.2 IxEthAcc Overview............................................................................................................129
9.3 Ethernet Access Layers: Architectural Overview..............................................................130
9.3.1 Role of the Ethernet NPE Microcode...................................................................130
9.3.2 Queue Manager...................................................................................................131
9.3.3 Learning/Filtering Database.................................................................................131
9.3.4 MAC/PHY Configuration................................................. ... .... ... ... ... .... ... ... ... ... .... .131
9.4 Ethernet Access Layers: Component Features................................................................132
9.5 Data Plane......... ... ... ....................................... ... .... ... ... ... ....................................... ... ........133
9.5.1 Port Initialization ..................................................................................................134
9.5.2 Ethernet Frame Transmission .............................................................................134
9.5.2.1 Transmission Flow....................................................... ... .... ... ... ... ... .... .134
9.5.2.2 Transmit Buffer Management and Priority...........................................135
9.5.2.3 Using Chained IX_OSAL_MBUFs for Transmission / Buffer Sizing ....137
9.5.3 Ethernet Frame Reception...................................................................................137
9.5.3.1 Receive Flow.......................................................................................138
9.5.3.2 Receive Buffer Management and Priority............................................139
9.5.3.3 Additional Receive Path Information............................................... .... .142
9.5.4 Data-Plane Endianness.......................................................................................143
9.5.5 Maximum Ethernet Frame Size......................... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... .143
9.6 Control Path .... ... ... ... .... ... ... ... ....................................... ... .... ... ... ... .....................................143
9.6.1 Ethernet MAC Control..........................................................................................145
9.6.1.1 MAC Duplex Settings...........................................................................145
9.6.1.2 MII I/O................................................ ....................................... ... ... .... .145
9.6.1.3 Frame Check Sequence......................................................................145
9.6.1.4 Frame Padding....................................................................................145
9.6.1.5 MAC Filtering.......................................................................................146
9.6.1.6 802.3x Flow Control.............................................................................146
9.6.1.7 NPE Loopback.......................... ... ... ... .... ... ... ... ... .... ..............................147
9.6.1.8 Emergency Security Port Shutdown............................................... .... .147
9.7 Initialization.......................................................................................................................147
9.8 Shared Data Structures....................................................................................................147
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9.9 Management Information..................................................................................................152
10 Access-Layer Components:
Ethernet Database (IxEthDB) API.............................................................................................155
10.1 Overview...........................................................................................................................155
10.2 What’s New.......................................................................................................................155
10.3 IxEthDB Functional Behavior............................................................................................155
10.3.1 MAC Address Learning and Filtering...................................................................156
10.3.1.1 Learning and Filtering..........................................................................156
10.3.1.2 Other MAC Learning/Filtering Usage Models......................................158
10.3.1.3 Learning/Filtering General Characteristics...........................................158
10.3.2 Frame Size Filtering.............................................................................................160
10.3.2.1 Filtering Example Based Upon Maximum Frame Size ........................161
10.3.3 Source MAC Address Firewall.............................................................................161
10.3.4 802.1Q VLAN............ ... ... ... ....................................... ... ... .... ... ... ... .... ... .................162
10.3.4.1 Background – VLAN Data in Ethernet Frames....................................163
10.3.4.2 Database Records Associated With VLAN IDs....................................164
10.3.4.3 Acceptable Frame Type Filtering.........................................................164
10.3.4.4 Ingress Tagging and Tag Removal......................................................165
10.3.4.5 Port-Based VLAN Membership Filtering..............................................165
10.3.4.6 Port and VLAN-Based Egress Tagging and Tag Removal..................166
10.3.4.7 Port ID Extraction.................................................................................169
10.3.5 802.1Q User Priority / QoS Support ................................................ ... ... ... ... .... ... .169
10.3.5.1 Priority Aware Transmission........................................ .... ... ... ... ... .... ... .169
10.3.5.2 Receive Priority Queuing.....................................................................170
10.3.5.3 Priority to Traffic Class Mapping..........................................................171
10.3.6 802.3 / 802.11 Frame Conversion .......................................................................172
10.3.6.1 Background — 802.3 and 802.11 Frame Formats...............................172
10.3.6.2 How the 802.3 / 802.11 Frame Conversion Feature Works.................174
10.3.6.3 802.3 / 802.11 API Details.................................................................176
10.3.7 Spanning Tree Protocol Port Settings .................................................................177
10.4 IxEthDB API......................................................................................................................177
10.4.1 Initialization..........................................................................................................177
10.4.2 Dependencies......................................................................................................177
10.4.3 Feature Set..........................................................................................................178
10.4.4 Additional Database Features .................................................. ... .... ... ... ... ... .... ... .178
10.4.4.1 User-Defined Field...............................................................................178
10.4.4.2 Database Clear......... ... ... ... .... ..............................................................1 79
10.4.5 Dependencies on IxEthAcc Configuration ...........................................................179
10.4.5.1 Promiscuous-Mode Requirement ........................................................179
10.4.5.2 FCS Appending......................................... ... ... .... ... ... ... .... ... ... ... ... ........179
Contents
11 Access-Layer Components:
Ethernet PHY (IxEthMii) API .....................................................................................................181
11.1 What’s New.......................................................................................................................181
11.2 Overview...........................................................................................................................181
11.3 Features............................................................................................................................181
11.4 Supported PHYs...............................................................................................................181
11.5 Dependencies...................................................................................................................182
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12 Access-Layer Components:
Feature Control (IxFeatureCtrl) API.........................................................................................183
12.1 What’s New.......................................................................................................................183
12.2 Overview...........................................................................................................................183
12.3 Hardware Feature Control..................................... ... ... ... .... ... ... ... .....................................183
12.3.1 Using the Product ID-Related Functions .............................................................184
12.3.2 Using the Feature Control Register Functions.....................................................185
12.4 Component Check by Other APIs.....................................................................................186
12.5 Software Configuration.....................................................................................................186
12.6 Dependencies...................................................................................................................187
13 Access-Layer Components:
HSS-Access (IxHssAcc) API.....................................................................................................189
13.1 What’s New.......................................................................................................................189
13.2 Overview...........................................................................................................................189
13.3 IxHssAcc API Overview....................................................................................................190
13.3.1 IxHssAcc Interfaces.............................................................................................190
13.3.2 Basic API Flow.....................................................................................................191
13.3.3 HSS and HDLC Theory and Coprocessor Operation............ ... ... ... .... ... ..............192
13.3.4 High-Level API Call Flow.....................................................................................195
13.3.5 Dependencies......................................................................................................196
13.3.6 Key Assumptions.................................................................................................196
13.3.7 Error Handling......................................................................................................197
13.4 HSS Port Initialization Details...........................................................................................197
13.5 HSS Channelized Operation.............................................................................................199
13.5.1 Channelized Connect and Enable.......................................................................199
13.5.2 Channelized Tx/Rx Methods........................... ... .... ... .......................................... .201
13.5.2.1 CallBack...............................................................................................202
13.5.2.2 Polled...................................................................................................202
13.5.3 Channelized Disconnect.... ... ... .......................................... .... ... ... ........................204
13.6 HSS Packetized Operation...............................................................................................204
13.6.1 Packetized Connect and Enable..........................................................................204
13.6.2 Packetized Tx................. ... ... ....................................... ... ... .... ... ...........................206
13.6.3 Packetized Rx.......................... .... ... ... ... .... ...................................... .... ... ... ... ... .....2 08
13.6.4 Packetized Disconnect ...................................................... .... ... ... ... .... ... ... ... ... .....211
13.6.5 56-Kbps, Packetized Raw Mode..........................................................................211
13.7 Buffer Allocation Data-Flow Overview..............................................................................211
13.7.1 Data Flow in Packetized Service................. ... ... .... ..............................................211
13.7.2 Data Flow in Channelized Service.................................. ... ..................................214
14 Access-Layer Components:
NPE-Downloader (IxNpeDl) API................................................................................................219
14.1 What’s New.......................................................................................................................219
14.2 Overview...........................................................................................................................219
14.3 Microcode Images ............................................................................................................219
14.4 Standard Usage Example......... ........................................................................................220
14.5 Custom Usage Example........... ... ............................................................................. ... .... .223
14.6 IxNpeDl Uninitialization.....................................................................................................223
14.7 Deprecated APIs...............................................................................................................224
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15 Access-Layer Components:
NPE Message Handler (IxNpeMh) API.....................................................................................225
15.1 What’s New.......................................................................................................................225
15.2 Overview...........................................................................................................................225
15.3 Initializing the IxNpeMh.....................................................................................................226
15.3.1 Interrupt-Driven Operation...................................................................................226
15.3.2 Polled Operation..................................................................................................226
15.4 Uninitializing IxNpeMh ......................................................................................................227
15.5 Sending Messages from an Intel XScale
®
Core Software Client to an NPE....................227
15.5.1 Sending an NPE Message...................................................................................227
15.5.2 Sending an NPE Message with Response..........................................................228
15.6 Receiving Unsolicited Messages from an NPE to Client Software...................................229
15.7 Dependencies...................................................................................................................231
15.8 Error Handling...................................................................................................................231
16 Access-Layer Components:
Parity Error Notifier (IxParityENAcc) API ................................................................................233
16.1 What’s New.......................................................................................................................233
16.2 Introduction.......................................................................................................................233
16.2.1 Background..........................................................................................................233
16.2.2 Parity and ECC Capabilities in the
®
Intel
IXP45X and Intel® IXP46X Product Line ...................................................234
16.2.2.1 Network Processing Engines...............................................................234
16.2.2.2 Switching Coprocessor in NPE B (SWCP) ..........................................235
16.2.2.3 AHB Queue Manager (AQM)...............................................................235
16.2.2.4 DDR SDRAM Memory Controller Unit (MCU)......................................235
16.2.2.5 Expansion Bus Controller ....................................................................235
16.2.2.6 PCI Controller ......................................................................................235
16.2.2.7 Secondary Effects of Parity Interrupts .................................................236
16.2.3 Interrupt Prioritization...........................................................................................236
16.3 IxParityENAcc API Details.................................. ... ... ... .... ... ... ... ... .... .................................237
16.3.1 Features...............................................................................................................237
16.3.2 Dependencies......................................................................................................237
16.4 IxParityENAcc API Usage Scenarios................................................................................238
16.4.1 Summary Parity Error Notification Scenario ....................................................... .239
16.4.2 Summary Parity Error Recovery Scenario...........................................................241
16.4.3 Summary Parity Error Prevention Scenario.........................................................242
16.4.4 Parity Error Notification Detailed Scenarios. ... .... ... ... ... ... .....................................242
Contents
17 Access-Layer Components:
Performance Profiling (IxPerfProfAcc) API.............................................................................247
17.1 What’s New.......................................................................................................................247
17.2 Overview...........................................................................................................................247
17.3 Intel XScale
®
Core PMU...................................................................................................248
17.3.1 Counter Buffer Overflow ......................................................................................249
17.4 Internal Bus PMU..............................................................................................................249
17.5 Idle-Cycle Counter Utilities (‘Xcycle’)................................................................................250
17.6 Dependencies...................................................................................................................250
17.7 Error Handling...................................................................................................................251
17.8 Interrupt Handling.............................................................................................................251
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17.9 Threading..........................................................................................................................252
17.10 Using the API.. ... ... ... .... ...................................... .... ... ... ... .... ... ... ... .....................................252
17.10.1 API Usage for Intel XScale
®
Core PMU ..............................................................253
17.10.1.1 Event and Clock Counting ...................................................................253
17.10.1.2 Time-Based Sampling..........................................................................255
17.10.1.3 Event-Based Sampling........................................................................257
17.10.1.4 Using Intel XScale
®
Core PMU to Determine Cache Efficiency ..........260
17.10.2 Internal Bus PMU.................................................................................................261
17.10.2.1 Using the Internal Bus PMU Utility to Monitor
Read/Write Activity on the North Bus...................................................262
17.10.3 Xcycle (Idlecycle Counter)...................................................................................263
18 Access-Layer Components:
Queue Manager (IxQMgr) API...................................................................................................265
18.1 What’s New.......................................................................................................................265
18.2 Overview...........................................................................................................................265
18.3 Features and Hardware Interface.....................................................................................266
18.4 IxQMgr Initialization and Uninitialization...........................................................................267
18.5 Queue Configuration.........................................................................................................267
18.6 Queue Identifiers ..............................................................................................................267
18.7 Configuration Values ........................................................................................................268
18.8 Dispatcher.........................................................................................................................268
18.9 Dispatcher Modes.............................................................................................................269
18.10 Livelock Prevention............................ ... .... ... ... ... .... ... ... ... ..................................................272
18.11 Threading..........................................................................................................................274
18.12 Dependencies...................................................................................................................274
19 Access-Layer Components:
Synchronous Serial Port (IxSspAcc) API................................................................................275
19.1 What’s New.......................................................................................................................275
19.2 Introduction.......................................................................................................................275
19.3 IxSspAcc API Details........................................................................................................275
19.3.1 Features...............................................................................................................275
19.3.2 Dependencies......................................................................................................276
19.4 IxSspAcc API Usage Models............................................................................................277
19.4.1 Initialization and General Data Model..................................................................277
19.4.2 Interrupt Mode .....................................................................................................277
19.4.3 Polling Mode......... ....................................... ... ... .... ... ... ... ... .... ..............................280
20 Access-Layer Components:
Time Sync (IxTimeSyncAcc) API..............................................................................................283
20.1 What’s New.......................................................................................................................283
20.2 Introduction.......................................................................................................................283
20.2.1 IEEE 1588 PTP Protocol Overview .....................................................................284
20.2.2 IEEE 1588 Hardware Assist Block.......................................................................285
20.2.3 IxTimeSyncAcc....................................................................................................288
20.2.4 IEEE 1588 PTP Client Application.......................................................................288
20.3 IxTimeSyncAcc API Details......................... ... ... .... ... ... ... .... ... ...........................................288
20.3.1 Features...............................................................................................................288
20.3.2 Dependencies......................................................................................................289
20.3.3 Error Handling......................................................................................................289
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20.4 IxTimeSyncAcc API Usage Scenarios..............................................................................290
20.4.1 Polling for Transmit and Receive Timestamps ....................................................290
20.4.2 Interrupt Mode Operations...................................................................................290
20.4.3 Polled Mode Operations ......................................................................................291
21 Access-Layer Components:
UART-Access (IxUARTAcc) API...............................................................................................293
21.1 What’s New.......................................................................................................................293
21.2 Overview...........................................................................................................................293
21.3 Interface Description.........................................................................................................293
21.4 UART / OS Dependencies................................................................................................294
21.4.1 FIFO Versus Polled Mode .................................................. ... ... ... .... ... ... ... ... .... ... .294
21.5 Dependencies...................................................................................................................295
22 Access-Layer Components:
USB Access (ixUSB) API ..........................................................................................................297
22.1 What’s New.......................................................................................................................297
22.2 Overview...........................................................................................................................297
22.3 USB Controller Background...................... ... ... ..................................................................297
22.3.1 Packet Formats....................................................................................................298
22.3.2 Transaction Formats............................................................................................299
22.4 ixUSB API Interfaces ........................................................................................................302
22.4.1 ixUSB Setup Requests ........................................................................................302
22.4.1.1 Configuration........................................................................................304
22.4.1.2 Frame Synchronization...... .... ... .......................................... ... ... ... ........305
22.4.2 ixUSB Send and Receive Requests ....................................................................305
22.4.3 ixUSB Endpoint Stall Feature ..............................................................................305
22.4.4 ixUSB Error Handling...........................................................................................306
22.5 USB Data Flow................................................... ... ... ... .... ... ... ... ... .....................................308
22.6 USB Dependencies ............................................ ... ... ... .... ... ...................................... .... ... .308
Contents
23 Codelets .....................................................................................................................................309
23.1 What’s New.......................................................................................................................309
23.2 Overview...........................................................................................................................309
23.3 ATM Codelet (IxAtmCodelet)............................................................................................309
23.4 Crypto Access Codelet (IxCryptoAccCodelet)..................................................................310
23.5 DMA Access Codelet (IxDmaAccCodelet)........................................................................310
23.6 Ethernet AAL-5 Codelet (IxEthAal5App)...........................................................................310
23.7 Ethernet Access Codelet (IxEthAccCodelet) ....................................................................310
23.8 HSS Access Codelet (IxHssAccCodelet)..........................................................................311
23.9 Parity Error Notifier Codelet (IxParityENAccCodelet)............... ... .... ... ... ... .... ... ... ... ... .... ... .311
23.10 Performance Profiling Codelet (IxPerfProfAccCodelet)....................................................312
23.11 Time Sync Codelet (IxTimeSyncAccCodelet)...................................................................312
23.12 USB RNDIS Codelet (IxUSBRNDIS)........................... .... ... ... ... ... .... .................................312
24 Operating System
Abstraction Layer (OSAL).........................................................................................................313
24.1 What’s New.......................................................................................................................313
24.2 Overview...........................................................................................................................313
24.3 OS-Independent Core Module..................... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ........................3 15
24.4 OS-Dependent Module.....................................................................................................315
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Contents
24.4.1 Backward Compatibility Module...........................................................................316
24.4.2 Buffer Translation Module....................................................................................316
24.5 OSAL Library Structure.....................................................................................................316
24.6 OSAL Modules and Related Interfaces ............................................................................319
24.6.1 Core Module........................................................................................................319
24.6.2 Buffer Management Module ................................................................................322
24.6.3 I/O Memory and Endianness Support Module.....................................................322
24.7 Supporting a New OS.......................................................................................................324
24.8 Supporting New Platforms................................................................................................325
25 ADSL Driver ...............................................................................................................................327
25.1 What’s New.......................................................................................................................327
25.2 Device Support.................................................................................................................327
25.3 ADSL Driver Overview......................................................................................................327
25.3.1 Controlling STMicroelectronics* ADSL Modem Chipset Through CTRL-E..........328
25.4 ADSL API..........................................................................................................................328
25.5 ADSL Line Open/Close Overview.....................................................................................328
25.6 Limitations and Constraints ..............................................................................................330
26 I
2
C Driver (IxI2cDrv)...................................................................................................................331
26.1 What’s New.......................................................................................................................331
26.2 Introduction.......................................................................................................................331
26.3 I
2
C Driver API Details.......................................................................................................331
26.3.1 Features...............................................................................................................331
26.3.2 Dependencies......................................................................................................332
26.3.3 Error Handling......................................................................................................333
26.3.3.1 Arbitration Loss Error...........................................................................333
26.3.3.2 Bus Error..............................................................................................334
C Driver API Usage Models...........................................................................................334
26.4 I
2
26.4.1 Initialization and General Data Model..................................................................334
26.4.2 Example Sequence Flows for Slave Mode..........................................................336
26.4.3 I
27 Endianness in Intel
2
C Using GPIO Versus Dedicated I2C Hardware............. .... ... ... ... .... ... ... ... ... .....339
®
IXP400 Software.....................................................................................341
27.1 Overview...........................................................................................................................341
27.2 The Basics of Endianness................................................................................................341
27.2.1 The Nature of Endianness: Hardware or Software?............................................342
27.2.2 Endianness When Memory is Shared .................................................................342
27.3 Software Considerations and Implications........................................................................343
27.3.1 Coding Pitfalls — Little-Endian/Big-Endian..........................................................343
27.3.1.1 Casting a Pointer Between Types of Different Sizes...........................343
27.3.1.2 Network Stacks and Protocols.............................................................344
27.3.1.3 Shared Data Example: LE Re-Ordering Data for BE Network Traffic..344
27.3.2 Best Practices in Coding of Endian-Independence .............................................345
27.3.3 Macro Examples: Endian Conversion..................................................................345
27.3.3.1 Macro Source Code.............................................................................345
27.4 Endianness Features of the Intel
®
IXP4XX
Product Line of Network Processors
and IXC1100 Control Plane Processor.............................................................................346
27.4.1 Supporting Little-Endian Mode ....................................................... .... ... ..............348
27.4.2 Reasons for Choosing a Particular LE Coherency Mode............ ... .... ... ... ... ........348
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27.4.3 Silicon Endianness Controls........................................ ... .... ... ... ... .... ... ... ... ... .... ... .349
27.4.3.1 Hardware Switches............ .......................................... .... ....................349
27.4.3.2 Intel XScale
®
Core Endianness Mode................................... ... ... .... ... .350
27.4.3.3 Little-Endian Data Coherence Enable/Disable.....................................351
27.4.3.4 MMU P-Attribute Bit.............................................................................351
27.4.3.5 PCI Bus Swap......................................................................................352
27.4.3.6 Summary of Silicon Controls................................................................352
27.4.4 Silicon Versions ........ ... ... ... ... .... ...................................... .... ... ... ... .... ... ... ... ...........352
27.5 Little-Endian Strategy in Intel
®
IXP400 Software and Associated BSPs..........................353
27.5.1 APB Peripherals ..................................................................................................354
27.5.2 AHB Memory-Mapped Registers........................................ ... ... ... .... ... ... ... ... .... ... .355
27.5.3 Intel
®
IXP400 Software Core Components..........................................................355
27.5.3.1 Queue Manager — IxQMgr..................................................................355
27.5.3.2 NPE Downloader — IxNpeDl...............................................................356
27.5.3.3 NPE Message Handler — IxNpeMh ....................................................356
27.5.3.4 Ethernet Access Component — IxEthAcc ...........................................356
27.5.3.5 ATM and HSS......................................................................................361
27.5.4 PCI.......................................................................................................................361
27.5.5 Intel
®
IXP400 Software OS Abstraction...............................................................361
27.5.6 VxWorks* Considerations....................................................................................362
27.5.7 Software Versions........... .....................................................................................364
Contents
Figures
1 Intel® IXP400 Software v2.0 Architecture Block Diagram ..........................................................28
2 Global Dependencies .................................................................................................................33
3 Intel
4 IXP_BUF User Interface............ .... ... ... ....................................... ... ... ... .... ... ... ... .... ......................37
5 IXP_BUF Structure........... ...................................... .... ... ... ... .... ...................................... ... ..........38
6 OSAL IXP_BUF structure and macros .......................................................................................39
7 API User Interface to IXP_BUF ..................................................................................................40
8 Access-Layer Component Interface to IXP_BUF .......................................................................40
9 Pool Management Fields.. ... ... ... .... ... ... ............................................................................. .... ......41
10 IXP_BUF: IX_MBUF Structure...................................................................................................41
11 IXP_BUF: ix_ctrl Structure..........................................................................................................42
12 IXP_BUF: NPE Shared Structure ...............................................................................................43
13 Internal Mapping of IX_MBUF to the Shared NPE Structure......................................................44
14 Buffer Transmission for a Scheduled Port..................................................................................58
15 IxAtmdAccScheduleTable Structure and Order Of ATM Cell .....................................................60
16 Tx Done Recycling — Using a Threshold Level .........................................................................61
17 Tx Done Recycling — Using a Polling Mechanism.....................................................................62
18 Tx Disconnect.. .... ... ... ... .... ... ... ....................................... ... ... .... ... ... ... ... .... ... ... ... .... ... ...................63
19 Rx Using a Threshold Level........................................................................................................65
20 RX Using a Polling Mechanism ..................................................................................................66
21 Rx Disconnect.............................................................................................................................67
22 Services Provided by Ixatmm .....................................................................................................74
23 Configuration of Traffic Control Mechanism ...............................................................................76
24 Component Dependencies of IxAtmm..................................................... ... ... ... .... ... ... ... ... .... ... ...77
25 Multiple VCs for Each Port, Multiplexed onto Single Line by the ATM Scheduler......................82
26 Translation of IxAtmScheduleTable Structure to ATM Tx Cell Ordering ....................................83
®
IXP400 Software Buffer Flow............................................................................................36
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Contents
27 Basic IxCryptoAcc API Flow.......................................................................................................90
28 IxCryptoAcc API Call Process Flow for CCD Updates ...............................................................92
29 IxCryptoAcc Component Dependencies.....................................................................................94
30 IxCryptoAcc, NPE and IPSec Stack Scope................................................................................97
31 Relationship Between IPSec Protocol and Algorithms...............................................................98
32 ESP Packet Structure.................................................................................................................98
33 Authentication Header............................................ ....................................... ... ... .... ... ... ... ..........99
34 ESP Data Flow ............................................. ............................................................................100
35 AH Data Flow ...................................... ... ... ... .... ... ....................................... ... ... ... .... ... ..............101
36 IPSec API Call Flow ......................................... ... ... ... .... ... ... ... ....................................... ... ........102
37 CCM Operation Flow................................................................................................................104
38 CCM Operation on Data Packet...............................................................................................104
39 AES CBC Encryption For MIC..................................................................................................1 05
40 AES CTR Encryption For Payload and MIC.............................................................................105
41 WEP Frame with Request Parameters.....................................................................................107
42 WEP Perform API Call Flow.....................................................................................................109
43 ixDmaAcc Dependencies .................................... ... ... .... ... ....................................... ... ... ... ... .... .116
44 IxDmaAcc Component Overview..............................................................................................117
45 IxDmaAcc Control Flow............................................................................................................124
46 IxDMAcc Initialization ...............................................................................................................125
47 DMA Transfer Operation ..........................................................................................................126
48 Ethernet Access Layers Block Diagram ...................................................................................133
49 Ethernet Transmit Frame API Overview...................................................................................134
50 Ethernet Transmit Frame Data Buffer Flow..............................................................................136
51 Ethernet Receive Frame API Overview....................................................................................138
52 Ethernet Receive Plane Data Buffer Flow................................................................................142
53 IxEthAcc and Secondary Components.....................................................................................144
54 Example Network Diagram for MAC Address Learning and Filtering with Two Ports..............157
55 Egress VLAN Control Path for Untagged Frames....................................................................168
56 QoS on Receive for 802.1Q Tagged Frames...........................................................................170
57 QoS on Receive for Untagged Frames ....................................................................................171
58 AP-STA and AP-AP Modes......................................................................................................173
59 HSS/HDLC Access Overview...................................................................................................192
60 T1 Tx Signal Format.................................................................................................................194
61 IxHssAcc Component Dependencies.......................................................................................196
62 Channelized Connect ...............................................................................................................201
63 Channelized Transmit and Receive..........................................................................................203
64 Packetized Connect..................................................................................................................206
65 Packetized Transmit.................................................................................................................208
66 Packetized Receive..................................................................................................................210
67 HSS Packetized Receive Buffering ............................................................... ... ... .... ... ... ... ... .... .213
68 HSS Packetized Transmit Buffering .... ... ... ... .... ........................................................................214
69 HSS Channelized Receive Operation ......................................................................................216
70 HSS Channelized Transmit Operation ....................................... ... .......................................... .217
71 Message from Intel XScale
72 Message with Response from Intel XScale
®
Core Software Client to an NPE.................................................228
®
Core Software Client to an NPE ........................229
73 Receiving Unsolicited Messages from NPE to Software Client................................................230
74 ixNpeMh Component Dependencies........................................................................................231
75 IxParityENAcc Dependency Diagram........ ... .... ... ... ... .... ... ... ... .......................................... ... .... .238
76 Parity Error Notification Sequence ...........................................................................................239
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Contents
77 Data Abort with No Parity Error ................................................................................................243
78 Parity Error with No Data Abort ................................................................................................243
79 Data Abort followed by Unrelated Parity Error Notification.......................................................244
80 Unrelated Parity Error Followed by Data Abort.........................................................................244
81 Data Abort Caused by Parity Error ...........................................................................................245
82 Parity Error Notification Followed by Related Data Abort.........................................................245
83 Data Abort with both Related and Unrelated Parity Errors......................... ... ... .... ... ... ... ... .... ... .246
84 IxPerfProfAcc Dependencies..................... .... ... ... ... .... ..............................................................251
85 IxPerfProfAcc Component API ...................................................... ... ... .... ... ... ... .... ... ... ... ... .... ... .253
86 Display Performance Counters............................ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ..............255
87 Display Clock Counter............ ... .... ... ... ... ....................................... ... ... .... ... ... ... .... ... .................256
88 Display Xcycle Measurement ...................................................................................................264
89 AQM Hardware Block...............................................................................................................266
90 Dispatcher in Context of an Interrupt........................................................................................271
91 Dispatcher in Context of a Polling Mechanism .........................................................................272
92 IxSspAcc Dependencies......................... ... .... ... ... ... ..................................................................276
93 Interrupt Scenario.....................................................................................................................279
94 Polling Scenario........................................................................................................................281
95 IxTimeSyncAcc Component Dependencies .............................................................................284
96 Block Diagram of Intel
®
IXP46X Network Processor................................................................286
97 Polling for Timestamps of Sync or Delay_Req.........................................................................290
98 Interrupt Servicing of Target Time Reached Condition.................. ... ... .... ... ... ... .... ... ... ... ... .... ... .291
99 Polling for Auxiliary Snapshot Values.......................................................................................292
100 UART Services Models.............................................................................................................295
101 USBSetupPacket......................................................................................................................303
102 STALL on IN Transactions........................................................................................................305
103 STALL on OUT Transactions....................................................................................................306
104 USB Dependencies..................................................................................................................308
105 OSAL Architecture...................................................................................................................314
106 OSAL Directory Structure.........................................................................................................318
107 STMicroelectronics* ADSL Chipset
on the Intel
108 Example of ADSL Line Open Call Sequence ...........................................................................329
2
109 I
C Driver Dependencies..........................................................................................................333
®
IXDP425 / IXCDP1100 Development Platform....................................................328
110 Sequence Flow Diagram for Slave Receive / General Call in Interrupt Mode..........................336
111 Sequence Flow Diagram for Slave Transmit in Interrupt Mode................................................337
112 Sequence Flow Diagram for Slave Receive in Polling Mode....................................................338
113 Sequence Flow Diagram for Slave Transmit in Polling Mode...................................................339
114 32-Bit Formats.................. ... ....................................... ... ... ... .... ... ... ... ... .....................................342
115 Endianness in Big-Endian-Only Software Release..................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... .347
116 Intel
®
IXP4XX Product Line of Network Processors and IXC1100
Control Plane Processor Endianness Controls.............................. ... ... .... ... ... ... .... ... ... ... ... .... ... .350
117 Ethernet Frame (Big-Endian)....................................................................................................357
118 One Half-Word-Aligned Ethernet Frame (LE Address Coherent).............................................358
119 Intel XScale
®
Core Read of IP Header (LE Data Coherent).....................................................359
120 VxWorks* Data Coherent Swap Code......................................................................................363
Tables
1 Internal IX_MBUF Field Format..................................................................................................44
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Intel® IXP400 Software
Contents
2 IX_MBUF Field Details ...............................................................................................................45
3 IX_MBUF to M_BLK Mapping ....................................................................................................47
4 Buffer Translation Functions.......................................................................................................48
5 IXP_BUF Fields Required for Transmission..............................................................................68
6 IXP_BUF Fields of Available Buffers for Reception....................................................................68
7 IXP_BUF Fields Modified During Reception...............................................................................68
8 Real-Time Errors ........................................................................................................................70
9 Supported Traffic Types ......... ... ... .... ..........................................................................................80
10 IxAtmSch Data Memory Usage ..................................................................................................85
11 IxCryptoAcc Data Memory Usage ..............................................................................................93
12 Supported Encryption Algorithms.............................................................................................111
13 Supported Authentication Algorithms ............................................................... ........................113
14 DMA Modes Supported for Addressing Mode of Incremental Source Address and
Incremental Destination Address..............................................................................................121
15 DMA Modes Supported for Addressing Mode of Incremental Source Address and
Fixed Destination Address........................................................................................................122
16 DMA Modes Supported for Addressing Mode of Fixed Source Address and
Incremental Destination Address..............................................................................................123
17 IX_OSAL_MBUF Structure Format ..........................................................................................148
18 ixp_ne_flags Field Format ........................................................................................................148
19 IX_OSAL_MBUF Header Definitions for the Ethernet Subsystem ...........................................149
20 IX_OSAL_MBUF “Port ID” Field Format...................................................................................151
21 IX_OSAL_MBUF “Port ID” Field Values...................................................................................152
22 ixp_ne_flags.link_prot Field Values..........................................................................................152
23 Managed Objects for Ethernet Receive.. ... ... .... ... ... ... .... ... ... ....................................... ... ... ... .... .153
24 Managed Objects for Ethernet Transmit...................................................................................154
25 Untagged MAC Frame Format .................................................................................................163
26 VLAN Tagged MAC Frame Format ..........................................................................................163
27 VLAN Tag Format.....................................................................................................................164
28 Egress VLAN Tagging/Untagging Behavior Matrix...................................................................168
29 Default Priority to Traffic Class Mapping ..................................................................................172
30 IEEE802.11 Frame Format.......................................................................................................172
31 IEEE802.11 Frame Control (FC) Field Format........................... ... ... ... ... .... ... ... ........................173
32 802.3 to 802.11 Header Conversion Rules ..............................................................................175
33 802.11 to 802.3 Header Conversion Rules ..............................................................................176
34 IxEthDB Feature Set.................................................................................................................178
35 PHYs Supported by IxEthMii ....................................................................................................182
36 Product ID Values.....................................................................................................................184
37 Feature Control Register Values ..............................................................................................185
38 HSS Tx Clock Output frequencies and PPM Error........................................ ... ... .... .................193
39 HSS TX Clock Output Frequencies and Associated Jitter Characterization ............................193
40 Jitter Definitions........................................................................................................................194
41 HSS Frame Output Characterization........................................................................................194
42 NPE-A Images..........................................................................................................................221
43 NPE-B Images..........................................................................................................................222
44 NPE-C Images..........................................................................................................................222
45 Parity Error Interrupts ...............................................................................................................236
46 Parity Capabilities Supported by IxParityENAcc ......................................................................237
47 Parity Error Interrupt Deassertion Conditions...........................................................................240
48 AQM Configuration Attributes..................................................................................................268
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Contents
49 Default IEEE 1588 Hardware Assist Block States upon Hardware/Software Reset............. ....287
50 IN, OUT, and SETUP Token Packet Format............................................................................298
51 SOF Token Packet Format.......................................................................................................298
52 Data Packet Format..................................................................................................................299
53 Handshake Packet Format.......................................................................................................299
54 Bulk Transaction Formats.........................................................................................................300
55 Isochronous Transaction Formats ............................................................................................300
56 Control Transaction Formats, Set-Up Stage.............................................................................301
57 Control Transaction Formats....................................................................................................301
58 Interrupt Transaction Formats ..................................................................................................301
59 API interfaces Available for Access Layer................................................................................302
60 Host-Device Request Summary .................................................... ... ... .... ... ... ... .... ... ... ..............303
61 Detailed Error Codes................................................................................................................307
62 OSAL Core Interface ................................................................................................................320
63 OSAL Buffer Management Interface.........................................................................................322
64 OSAL I/O Memory and Endianness Interface...........................................................................323
65 Endian Hardware Summary......................................................................................................352
66 Intel
67 Intel
®
IXP42X Product Line of Network Processors A-0 Stepping Part Numbers ....................353
®
IXP400 Software Macros................................................................................................362
68 Endian Conversion Macros.......................................................................................................362
69 Intel
®
IXP400 Software Versions..............................................................................................364
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Intel® IXP400 Software
Contents
Revision History
Date Revision Description
April 2005 007
November 2004 006
December 2003 005
September 2003 004 Made two minor corrections.
August 2003 003 Updated manual for IXP400 Software Version 1.3.
February 2003 002 Removed “Intel Confidential” classification.
February 2003 001 Initial release of document.
Updated guide for IXP400 Software Version 2.0. Added:
• Chapter 16, “Access-Layer Components: Parity Error Notifier
(IxParityENAcc) API”
• Chapter 19, “Access-Layer Components: Synchronous Serial Port
(IxSspAcc) API”
• Chapter 20, “Access-Layer Components: Time Sync
(IxTimeSyncAcc) API”
• Chapter 26, “I2C Driver (IxI2cDrv)”
Removed:
Access-Layer Components: Fast-Path Access (IxFpathAcc) API
Change bars indicate areas of change.
Updated guide for IXP400 Software Version 1.5. Added Chapter 24,
“Endianness in Intel
• Chapter 3, “Buffer Management”
• Chapter 9, “Access-Layer Components: Ethernet Access
(IxEthAcc) API”
• Chapter 10, “Access-Layer Components: Ethernet Database
(IxEthDB) API”
• Chapter 18, “Access-Layer Components: Queue Manager (IxQMgr)
API”
• Chapter 22, “Operating System Abstraction Layer (OSAL)”
Change bars indicate areas of change.
Updated manual for IXP400 Software Version 1.4. Removed API
documentation (now in a separate reference).
®
IXP400 Software v1.5”, and revised:
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Intel® IXP400 Software
Introduction 1
This chapter contains important information to help you learn about and use the Intel® IXP400
Software v2.0 release.
1.1 Versions Supported by this Document
This programmer’s guide is intended to be used in conjunction with software release 2.0. Always
refer to the accompanying release notes for information about the latest information regarding the
proper documentation sources to be used.
Previous versions of the programmer’s guide for earlier IXP400 software releases can be found on
the following Web site:
http://developer.intel.com/design/network/products/npfamily/docs/ixp4xx.htm
To identify your version of software:
1. Open the file ixp400_xscale_sw/src/include/IxVersionId.h.
2. Check the value of IX_VERSION_ID.
1.2 Hardware Supported by this Release
The Intel® IXP400 Software v2.0 release supports the following processors:
• All Intel
• All variants of the Intel
Warning: Processor capabilities differ between processor product lines or processor variants. Not all
capabilities of the processor may be supported by this software release.
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP46X Product Line of Network Processors
1.3 Intended Audience
This document describes the software release 2.0 architecture and is intended for software
developers and architects employing IXP42X product line processors or Intel
line processors. The document defines each component’s functionality, demonstrates the
behavioral links between the components, and presents the common design policies of each
component.
®
IXP46X product
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 19
Intel® IXP400 Software
Introduction
1.4 How to Use this Document
This programmer’s guide is organized as follows:
Chapters Description
Chapters 1 and 2
Chapters 4 through 22
Chapter 3 and 24
Chapter 23 and 25–27
For the developer interested in a limited number of specific features of the IXP400 software, a
recommended reading procedure would be:
1. Read Chapters 1 through 3 to get a general knowledge of the products’ software and hardware
architecture.
Introduces the Intel
processors, including an overview of the software architecture.
Provide functional descriptions of the various access-layer
components.
Describe the memory buffer management and operating system
abstraction layers, needed for a more in-depth architectural
understanding of the software.
Describe codelets (example applications), ADSL driver, I
endianness.
®
IXP400 Software v2.0 and the supported
2
C driver, and
2. Read the chapters on the specific access-layer component(s) of interest.
Note: Many of the access-layer components have dependencies on other components —
particularly on IxNpeDl and IxQmgr. For that reason, developers also should review
those chapters.
3. Review the codelet descriptions in Chapter 23 and their respective source code for those
codelets that offer features of interest.
4. Refer to the API source code and source code documentation found in the software release
documents folder as necessary.
1.5 About the Processors
Next-generation networking solutions must meet the growing demands of users for highperformance data, voice, and networked multimedia products. Manu factu rers of networking
equipment must develop new products under stringent time-to-market deadlines and deliver
products whose software can be easily upgraded. The IXP4XX product line and IXC1100 control
plane processors family is designed to meet the needs of broadband and embedded networking
products such as high-end residential gateways; small to medium enterprise (SME) routers,
switches, security devices; DSLAMs (Digital Subscriber Line Access Multiplexers) for multidwelling units (MxU); wireless access points; industrial control systems; and networked printers.
The IXP4XX product line and IXC1100 control plane processors deliver wire-speed performance
and sufficient “processing headroom” for manufacturers to add a variety of rich software services
to support their applications. These are highly integrated network processors that support multiple
WAN and LAN technologies, giving customers a common architecture for multiple applications.
With their development platform, a choice of operating systems, and a broad range of development
tools, the processor family is supported by a complete development environment for faster time-tomarket. This network processor family offers the choice of multiple clock speeds at 266, 400, 533
and 667 MHz, with both commercial (0° to 70° C) and extended (-40° to 85° C) temperature
options.
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Intel® IXP400 Software
Introduction
The IXP4XX product line and IXC1100 control plane processors have a unique distributed
processing architecture that features the performance of the Intel XScale
Network Processor Engines (NPEs). The combination of the four high-performance processors
provides tremendous processing power and enables wire-speed performance at both the LAN and
WAN ports. The three NPEs are designed to offload many computationally intensive data plane
operations from the Intel XScale core. This provides ample “processing headroom” on the Intel
XScale core for developers to add differentiating product features. Software development is made
easier by the extensive Intel XScale core tools environment that includes compilers, debuggers,
operating systems, models, support services from third party vendors, and fully documented
evaluation hardware platforms and kits. The compiler, assembler, and linker support specific
optimizations designed for the Intel XScale microarchitecture, the ARM
Intel DSP extensions.
For a list of IXP42X product line features, please see the Intel
Processors and IXC1100 Control Plane Processor Datasheet.
For a list of IXP46X product line features, please see the Intel
Processors Datasheet.
1.6 Related Documents
Users of this document should always refer to the associated Software Release Notes for the
specific release. Additional Intel documents listed below are available from your field
representative or from the following Web site:
http://www.intel.com/design/network/products/npfamily/docs/ixp4xx.htm
®
Core and up to three
*
instruction set v.5TE and
®
IXP42X Product Line of Network
®
IXP46X Product Line of Network
Document Title Document #
®
Intel
IXP400 Software Specification Update 273795
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane
Intel
Processor Developer’s Manual
®
Intel
IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor Datasheet
®
Intel
IXP46X Product Line of Network Processors Datasheet 306261
®
IXP46X Product Line of Network Processors Developer’s Manual 306262
Intel
®
IXP4XX Product Line of Network Processors Specification Update 306428
Intel
Intel® IXDP425 / IXCDP1100 Development Platform Specification Update 253527
®
IXDP465 Development Platform Specification Update 306509
Intel
*
Architecture Version 5TE Specification
ARM
PCI Local Bus Specification, Revision 2.2 –
Universal Serial Bus Specification, Revision 1.1 –
UTOPIA Level 2 Specification, Revision 1.0
IEEE 802.3 Specification
IEEE 1149.1 Specification
252480
252479
ARM DDI 0100E
(ISBN 0 201 737191)
–
–
–
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 21
Intel® IXP400 Software
Introduction
IEEE Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems (IEEE Std. 1588™ - 2002)
ARM Ltd., AMBA Specification, Rev. 2.0, May 1999 –
http://www.pcisig.com/reflector/msg01668.html, a discussion on a PCI bridge
between little and big endian devices.
1.7 Acronyms
Acronym Description
AAL ATM Adaptation Layer
ABR Available Bit Rate
ACK Acknowledge Packet
ADSL Asymmetric Digital Subscriber Line
AES Advanced Encryption Standard
AH Authentication Header (RFC 2402)
AHB Advanced High-Performance Bus
AL Adaptation Layer
AP Access Permission
APB Advanced Peripheral Bus
API Application Programming Interface
AQM AHB Queue Manager
ARC4 Alleged RC4
ATM Asynchronous Transfer Mode
ATU-C ADSL Termination Unit — Central Office
ATU-R ADSL Termination Unit — Remote
BE Big-Endian
BSD Berkeley Software Distribution
BSP Board Support Package
CAC Connection Admission Control
CAS Channel Associated Signaling
CBC Cipher Block Chaining
CBR Constant Bit Rate
CCD Cryptographic Context Database
CCM
CDVT Cell Delay Variation Tolerance
CFB Cipher FeedBack
CPCS Common Part Convergence Sublayer
CPE Customer Premise Equipment
Document Title Document #
–
Counter mode encryption with CBC-MAC
authentication
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Acronym Description
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CSR Customer Software Release
CTR Counter Mode
DDR Double Data Rate
DES Data Encryption Standard
DMT Discrete Multi-Tone
DOI Domain of Interpretation
DSL Digital Subscriber Line
DSP Digital Signal Processor
EEmpty
E1 Euro 1 trunk line (2.048 Mbps)
ECB Electronic Code Book
ECC Error Correction Code
EISA Extended ISA
ERP Endpoint Request Packet
ESP Encapsulation Security Payload (RFC2406)
Eth0 Ethernet NPE A
Eth1 Ethernet NPE B
FFull
FCS Frame Check Sequence
FIFO First In First Out
FRAD Frame Relay Access Device
FRF Frame Relay Forum
FXO Foreign Exchange Office
FXS Foreign Exchange Subscriber
G.SHDSL
GCI General Circuit Interface
GE Gigabit Ethernet
GFR Guaranteed Frame Rate
GPIO General Purpose Input/Output
HDLC High-Level Data Link Control
HDSL2 High Bit-Rate Digital Subscriber Line version 2
HEC Header Error Check
HLD High Level Design
HMAC Hashed Message Authentication Code
HPI Host Port Interface
HPNA Home Phone Network Alliance
ITU G series specification for symmetric High Bit Rate
Digital Subscriber Line
Intel® IXP400 Software
Introduction
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 23
Intel® IXP400 Software
Introduction
Acronym Description
HSS High Speed Serial
HSSI High Speed Serial Interface
HW Hardware
IAD Integrated Access Device
ICV Integrity Check Value
IKE Internet Key Exchange
IMA Inverse Multiplexing over ATM
IP Internet Protocol
IPsec Internet Protocol Security
IRQ Interrupt Request
ISA Industry Standard Architecture
ISR Interrupt Service Routine
ISR Interrupt Sub-Routine
IV Initialization Vector
IX_OSAL_MBUF
IX_MBUF
IXA Internet Exchange Architecture
IXP Internet Exchange Processor
IXP_BUF
LAN Local Area Network
LE Little-Endian
LSB Least Significant Bit
MAC Media Access Control
MAC Message Authentication Code (in SSL or TLS)
MBS Maximum Burst Size
MCR Minimum Cell Rate
MCU Memory Controller Unit
MD5 Message Digest 5
MFS Maximum Frame Size
MIB Management Information Base
MII Media-Independent Interface
MLPPP Multi-Link Point-to-Point Protocol
MMU Memory Management Unit
MPHY Multi PHY
MPI Memory Port Interface
BSD 4.4–like mbuf implementation for IXP400
software. Referred to as IX_MBUF, IXP_BUF and
IX_OSAL_MBUF interchangeably.
BSD 4.4–like mbuf implementation for IXP400
software. Referred to as IX_MBUF, IXP_BUF and
IX_OSAL_MBUF interchangeably.
BSD 4.4–like mbuf implementation for IXP400
software. Referred to as IX_MBUF, IXP_BUF and
IX_OSAL_MBUF interchangeably.
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
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Acronym Description
MSB Most Significant Bit
MVIP Multi-Vendor Integration Protocol
MxU Multi-dwelling Unit
NAK Not-Acknowledge Packet
NAPT Network Address Port Translation
NAT Network Address Translation
NE Nearly Empty
NF Nearly Full
NOTE Not Empty
NOTF Not Full
NOTNE Not Nearly Empty
NOTNF Not Nearly Full
NPE Network Processing Engine
OC3 Optical Carrier - 3
OF Overflow
OFB Output FeedBack
OS Operating System
OSAL Operating System Abstraction Layer
PBX Private Branch Exchange
PCI Peripheral Control Interconnect
PCI Peripheral Component Interface
PCR Peak Cell Rate
PDU Protocol Data Unit
PHY Physical Layer Interface
PID Packet Identifier
PMU Performance Monitoring Unit
PRE Preamble Packet
PTP Precision Time Protocol
QM or QMgr Queue Manager
rt-VBR Real Time Variable Bit Rate
Rx Receive
SA Security Association
SAR Segmentation and Re-assembly
SCR Sustainable Cell Rate
SDRAM Synchronous Dynamic Random Access Memory
SDSL Symmetric Digital Subscriber Line
SDU Service Data Unit
SHA1 Secure Hash Algorithm 1
SIO Standard I/O (input/output)
Intel® IXP400 Software
Introduction
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 25
Intel® IXP400 Software
Introduction
Acronym Description
SIP Session Initiation Protocol
SNMP Simple Network Management Protocol
SOF Start of Frame
SPHY Single PHY
SSL Secure Socket Layer
SSP Synchronous Serial Port
SVC Switched Virtual Connection
SWCP Switching Coprocessor
TCD Target Controller Driver
TCI Transmission Control Interface
TCP Transmission Control Protocol
TDM Time Division Multiplexing
TLB Translation Lookaside Buffer
TLS Transport Level Security
ToS Type of Service
Tx Transmit
UBR Unspecified Bit Rate
UDC Universal Serial Bus Device Controller
UF Underflow
USB Universal Serial Bus
UTOPIA Universal Test and Operation PHY Interface for ATM
VBR Variable Bit Rate
VC Virtual Connection
VCC Virtual Circuit Connection
VCI Virtual Circuit Identifier
VDSL Very High Speed Digital Subscriber Line
VoDSL Voice over Digital Subscriber Line
VoFR Voice over Frame Relay
VoIP Voice over Internet Protocol
VPC Virtual Path Connection
VPI Virtual Path Identifier
VPN Virtual Private Network
WAN Wide Area Network
WEP Wired Equivalent Privacy
Xcycle Idle-Cycle Counter Utilities
xDSL Any Digital Subscriber Line
XOR Exclusive OR
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Intel® IXP400 Software
Software Architecture Overview 2
2.1 High-Level Overview
The primary design principles of the Intel® IXP400 Software v2.0 architecture are to enable the
supported processors’ hardware in a manner which allows maximum flexibility. Intel
Software v2.0 consists of a collection of software components specific to the IXP4XX product line
and IXC1100 control plane processors and their supported development and reference boards.
This section discusses the software architecture of this product, as shown in “Intel® IXP400
Software v2.0 Architecture Block Diagram” on page 28
The NPE microcode consists of one or more loadable and executable NPE instruction files that
implement the NPE functionality behind the IXP40 0 so ftware library. The NPEs are RISC
processors embedded in the main processor that are surrounded by multiple coprocessor
components. The coprocessors provide specific hardware services (for example, Ethernet
processing and MAC interfaces, cryptographic processing, etc.). The NPE instruction files are
incorporated into the IXP400 software library at build time (or at run-time for Linux). The library
includes a NPE downloader component that provides NPE code version selection and downloading
services. A variety of NPE microcode images are provided, enabling different combinations of
services.
The Access Layer provides a software interface which gives customer code access to the
underlying capabilities of the supported processors. This layer is made up of a set of software
components (access-layer components), which clients can use to configure, control and
communicate with the hardware. Specifically, most access-layer components provide an API
interface to specific NPE-hosted hardware capabilities, such as AAL 0 and AAL 5 on UTOPIA,
Cryptography , Ethernet, HSS, or DMA. The remaining access-layer components provide an API
interface to peripherals on the processors (for example, UART and USB) or features of the Intel
XScale core (for example, Product ID Registers or Performance Monitoring Unit).
®
IXP400
The example Codelets are narrowly focused example applications that show how to use many of
the services or functions provided by the Intel XScale core library and the underlying hardware.
Many codelets are organized by hardware port type and typically exercise some Layer-2
functionality on that port, such as: AAL 5 PDU Transmit / Receive over UTOPIA, Channelized or
HDLC Transmit / Receive over HSS, Ethernet frame Transmit / Receive.
The Operating System Abstraction Layer (OSAL) defines a portable interface for operating
system services. The access-layer components and the codelets abstract their OS dependency to
this module.
Device Driver modules translate the generic Operating System specific device interface
commands to the Access Layer software APIs. Some device driver modules are provided by the OS
vendors’ Board Support Packages. Others may be provided in conjunction with the IXP400
software.
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 27
Intel® IXP400 Software
Software Architecture Over view
Figure 1. Intel
Intel® IX P4 X X N etwor k P ro cesso r
Intel XScale® Core
®
IXP400 Software v2.0 Architecture Block Diagram
Board
Support
Package
Drivers
Ethernet
ADSL
I2C
USB
Custom er Applicat ion
Operating System
Parity
OSAL
OSSL
IxAtmdAcc Ix C ryptoAcc
IxHssAcc
IxTimeSyncAcc IxNpeMhIxSspAcc ix...Acc
IxQmgr
TimeSync
Ethernet
IxDmaAcc
IxNpeDl
Codelets
ATM
HSSPerf Prof Crypto
Access Layer
IxEthAcc
IxParityENAcc
DMA
GPIO PCI UART
IEEE
1588
SSP I2C MCU
USB
2.2 Deliverable Model
Intel® IXP400 Software v2.0 consists of these elements:
®
• Intel
• Complete documentation and source code for IXP400 software com ponents
• NPE microcode images
• Example codelets
Note: The software releases do not include tools to develop NPE software. The supplied NPE
functionality is accessible through the access-layer APIs provided by the software release 2.0
library. The NPE microcode is provided as a .c file that must be compiled with the access-layer
library. NPE microcode is compatible only with the specific access-layer it is provided with.
IXP400 Software v2.0 access-layer components and OSAL layer
NPE - A
UTOPIA II
Ethernet
Board Har dwar e
HSS
NPE -B
Ethernet
DMA
NPE -C
Ethernet Crypto
B2909-05
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2.3 Operating System Support
The Intel XScale microarchitecture offers a broad range of tools together with support for two
widely adopted operating systems. The software release 2.0 supports VxWorks* and the standard
Linux* 2.4 kernel. MontaVista* software will provide the support for Linux. Support for other
operating systems may be available. For further information, visit the following Internet site:
http://developer.intel.com/design/network/products/npfamily/ixp425.htm
The software release 2.0’s software library is OS-i ndependent in tha t all components are written in
ANSI-C with no direct calls to any OS library function that is not covered by ANSI-C. A thin
abstraction layer is provided for some operating services (timers, mutexs, semiphores, and thread
management), which can be readily modified to support additional operating systems. This enables
the devices to be compatible with multiple operating systems and allows customers the flexibility
to port the IXP4XX product line and IXC1100 control plane processors to their OS of choice.
2.4 Development Tools
The Intel XScale microarchitecture offers a broad range of tools together with support for two
widely adopted operating systems. Developers have a wide choice of third-party tools including
compilers, linkers, debuggers and board-support packages (BSPs). Tools include Wind River*
Tornado* 2.2.1 for the VxWorks 5.5.1 real-time operating system, Wind River’s PLATFORM for
Network Equipment* and the complete GNU* Linux* development suite.
Intel® IXP400 Software
Software Architecture Over view
Refer to the release notes accompanying the software for information on specific OS support.
2.5 Access Library Source Code Documentation
The access library source code uses a commenting style that supports the Doxygen* tool for use in
creating source code documentation. Doxygen is an open-source tool, that reads appropriately
commented source code and produces hyper-linked documentation of the APIs suitable for on-line
browsing (HTML).
The documentation output is typically multiple HTML files, but Doxygen can be configured to
produce LaTeX*, RTF (Rich Text Format*), PostScript, hyper-linked PDF, compressed HTML,
and Unix* man pages. Doxygen is available for Linux, Windows* and other operating systems.
For more information, use the following Web URL:
http://www.doxygen.org.
The IXP400 software compressed file contains the HTML source code documentation at
ixp400_xscale_sw\doc\index.html. This output is suitable for online browsing. For a
printable reference, see the Adobe* Portable Document Format (PDF) file, contained in the
compressed software-download file.
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 29
Intel® IXP400 Software
Software Architecture Over view
2.6 Release Directory Structure
The software release 2.0 includes the following directory structure:
\---ixp_osal
+---doc
+---include
+---os
+---src
\---ixp400_xscale_sw
+---buildUtils
+---doc (API Reference in HTML and PDF format)
\---src (contains access-layer and codelet source code)
+---adsl (separate package)
+---atmdAcc
+---atmm
+---atmsch
+---codelets
| +---atm
(API References in HTML and PDF format)
(setting environment vars. in VxWorks and Linux)
(sub-directory for codelet source)
| +---cryptoAcc
| +---dmaAcc
| +---ethAal5App
| +---ethAcc
| +---hssAcc
| +---parityENAcc
| +---perfProfAcc
| +---timeSyncAcc
| \---usb
| +---drivers
| \---include
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
30 Document Number: 252539, Revision: 007
(separate package)
(for crypto version only)
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