Intel iSBC 80, iSBC 30, iSBC 80/30 Hardware Reference Manual

iSBC 80/30

SINGLE BOARD

COMPUTER

HARDWARE

REFERENCE MANUAL

Manual Order Number: 9800611 A

I

Corporation. 3065 Bowers Avenue, Santa Clara, California 95051

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l

1978 Intel Corporation

I

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makes

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limited

no

prior

ICE
INSITE
INTEL
INTELLEC
iSBC

ii

LIBRARY

MANAGER
MCS
MEGACHASSIS
MICROMAP
MULTI

BUS

Printed in

PROMPT
RMX
UPI
"SCOPE

U.S.A./852/067817.5K

TL

PREFACE

This manual provides general information, installation, programming information,

of

principles
Computer. Additional information

• Intel MCS-85 User's Manual, Order No. 98-366

• Intel UPI-41 User's Manual, Order No. 9800504

• Intel 8080/8085 Assembly Language Programming Manual, Order No. 9800301

• Intel 8255A Programmable Peripheral Interface, Application Note AP-15

• Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter, Application

Note AP-16

• Intel MULTIBUS Interfacing, Application Note AP-28

• Intel 8259 Programmable Interrupt Controller, Application Note AP-31

operation, and service information for the Intel iSBC 80/30 Single Board

is

available

in

the following documents:

iii

CHAPTER 1
GENERAL INFORMATION

Introduction

Description
System Software Development

Equipment Supplied . . . . . . . . . . . . ... . . . . . . . . . . . . . .

Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifications

..............

.....................................

...................................

: . . . . . . . . . . . . . . . . . . . .

..............

'

.......

CHAPTER 2

FOR

PREPARATION

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Unpacking and Inspection

Installation Considerations . . . . . . . . . . . . . . . . . . . . . . .

User-Furnished Components

Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . .

Cooling Requirement
Physical Dimensions

Component Installation

ROM/EPROM Chips
Universal Peripheral Interface

Line Drivers and

Rise Time/Noise Capacitors

Jumper Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . .

ROM/EPROM Configuration
On-Board RAM Addresses

On-Board 8085A Access
System Access

Priority Interrupts

8251A

Port Configuration
Port Configuration

8255A

8041/8741A

Multibus Configuration

Signal Characteristics
Serial Priority Resolution

Parallel Priority Resolution
Power Fail/Memory Protect Configuration
Parallel
Serial
Board Installation

I/O Cabling

I/O Cabling

I/O Terminators . . . . . . . . . . . . . . .

..............................

..............................

Port Configuration

..............................

................................

................................

USE

.........................

.....................

..

. . . . . . . . . . . . . . . . . . . . . . .

............................

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....................

......................

.....................

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......................

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.......................

...................

...........................

...........................

........................

......................

............

CHAPTER 3
PROGRAMMING INFORMATION

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer.

Failsafe
Memory Addressing
I/O Addressing
System Initialization
8251A USART Programming

Mode Instruction Format

Sync Characters

Command Instruction Format
Reset
Addressing
Initialization

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

..............................

..................................

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PAGE

..

1-1
1-1
1-3

..

1-4

..

1-4
1-4

..

2-1
2-1

..

2-1

2-1

..

2-1

..

2-1

2-1
2-3
2-3

2-4

..

2-4

2-4

..

2-4

2-4

2-4

2-7

2-7

2-8

2-12
2-12
2-12
2-15
2-15
2-23
2-24
2-24
2-27
2-27
2-29

..

3-1

..

3-1

3-1

3-2

3-2

3-3

3-3
3-3

3-3
3-4
3-4
3-4

CONTENTS

Operation

8253

Mode Control Word and Count
Addressing
Initialization
Operation

8255A

Control Word Format
Addressing
Initialization
Operation

8259A

Interrupt Priority Modes

Interrupt Mask
Status Read
Initialization Command Words
Operation Command Words
Addressing
Initialization

Operation
8041/8741A UPI Programming
Interrupt Handling

TRAP Input

RST 7.5, 6.5, 5.5 Inputs

INTR Input

CHAPTER 4
PRINCIPLES

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . .

Interval
Serial
Parallel
Universal Peripheral Interface

Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ROM/EPROM Configuration. . . . . . . . . . . . . . . . . . .

RAM Configuration
Bus Interface
Dual-Port Control

Circuit Analysis

.....................................

Data

Input/Output

Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIT Programming

...................................

.....................................

Counter Read
Clock Frequency/Divide Ratio Selection
Rate Generator/Interval Timer

Interrupt Timer

PPI Programming

...................................

.....................................

Read

Operation

Operation

Write

PIC Programming

Fully Nested Mode

Auto-Rotating Mode
Specific Rotating Mode

...................................

.....................................

Timer.

I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

............................

...........................

...................

..................................

...............................

..................

..............................

..........................

...........................

..................................

..............................

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................................

...................

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.....................

...............................

...................................

........................

...................................

OF

OPERATION

. . . . . . . . . . . . . . . . . . . . .

..

. . . . . . . . . . . . . . . .

............................

..................................

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...................

'

..........

..

. . . . . . .

............. ; ....

PAGE

3-5
3-5

..

3-6
3-6

3-7
3-10
3-10
3-11
3-11
3-11
3-12
3-12
3-13
3-13
3-14
3 -14

3-14
3-14
3-14
3-14

3-14

3-14

3-15

3-15

3-15

3-15
3-15
3-16
3-16
3 -16
3-16

3-17

3-22
3-22
3-23

3 -

..

4-1

..

4-1

..

4-1

..

4-1

..

4-1

..

4-1

..

4-1

..

4-2

..

4-2

..

4-2
4-2
4-2
4-2

'.

4-2

23

iv

CONTENTS (Continued)

Initialization
Clock Circuits
SOS5A

Instruction Timing

Opcode Fetch Timing. . . . . . . . . . . . . . . . . . . . . . .

Memory Read Timing
I/O Read Timing
Memory Write Timing
I/O Write Timing

Interrupt Acknowledge Timing
Address Bus
Bus Time
Data Bus
Read/Write

I/O Control Signals. . . . . . . . . . . . . . . . . . . . . . . . .

Memory Control

_ Dual Port Control Logic. . . . . . . . . . . . . . . . . . . . . . .

Bus Access Timing

CPU Access Timing
Multibus Interface
I/O Operation

........ -..........................

.................................

CPU Timing

Out

.....................................

Signal Generation . . . . . . . . . . . . . . . . . .

....

'"

.....................

...........................

........................

.............................

........................

............................

.................

..................................

.................................

Signals

.............................

................................

......................

..........................

.........................

PAGE

4-2
4-3
4-3
4-3

..

4-4
4-6
4-6
4-6
4-7
4-7
4-9
4-9

'4-9

..

4-9

..

4-9

4-9

..

4-9
.4-12
.4-12
.4-12
.4-13

On-Board I/O Operation

System I/O Operation
ROM/EPROM Operation
RAM

Operation
RAM Controller
On-Board Read/Write Operation

Bus Read/Write

Interrupt

Operation

..............................

............................

Operation

............................

.....................

........................

........ ' ...............

...............

....................

CHAPTER 5
SERVICE

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Replaceable
Service Diagrams
Service and Repair Assistance

INFORMATION

Parts

............................

................................

......................

;

APPENDIX A
8085

INSTRUCTION SET

APPENDIX B
TELETYPEWRITER

MODIFICATIONS

PAGE

.4-13
.4-13
.4-13
.4-14
.4-14

.4-14
.4-14
.4-15

..

5-1

...

5-1
5-1
5-1

TABLE

1-1.
2-1.

2-2.
2-3.
2-4.
2-5.
2-6.

2-7.

2-8.

2-9.
2-10.

2-11.
2-12.
2-13.
2-14.

TITLE

Specifications
User-Furnished and Installed Components
User-Furnished Connector Details
Line Driver and I/O Terminator Locations

Jumper
ROM/EPROM Configuration Jumpers
Jumper Configuration for

8085A CPU

65K

Page System Memory Selection
SK/16K
Priority
Connector

Jumper Configuration
8255A
Multibus Connector
Multibus Signal Functions
iSBC 80/30 DC Characteristics

...........................

...........

Selectable Options. . . . . . . . . . . . . . .

.......

Access

Block Selection Within 65K Page

Interrupt Jumper Matrix

13

Pin Assignments Vs.

Port Configuration Jumpers

On-Board

of

On-Board RAM

...................

PI

Pin Assignments

.................

........

............

..........

.............

....

....

....

....

.....

PAGE

1-4
2-2
2-3
2-4

..

2-5
2-7

2-7
2-S
2-S

2-11

2-12
2-13
2-16
2-17
2-18

TABLE

2-15.

2-16.
2-17.

2-18.

2-19.

2-20.

2-21.

2-22.

3-1.

3-2.
3-3.

3-4.

TABLES

TITLE PAGE

lSBC 80/30

(Master Mode)
iSBC
AuxHiary Connector P2 Pin Assignments

Auxiliary

DC Characteristics

Connector
Connector 12 Pin Assignments
Parallel I/O Signal (Connector 11/12)

DC Characteristics

Connector
On-Board
I/O Address Assignments
Typical USART Mode or Command

Instruction

Typical USART Data Character

Read Subroutine

'At

Characteristics

SO/3~

Signal (Connector P2)

........................

AC Characteristics (Slave Mode) .2-21

11

Pin Assignments

13

Vs. RS232C Pin COITl!spondence2-29

Memory Address (for CPU Access) 3-1

Subroutine

.....................

.............

.............

.....................

.........•........

..................

.......................

.....

2-21
2-26

2-26
2-27
2-27

2-2S

3-2

3-5

3-6

v

TABLES (Continued)

TABLE

3-5.

3-6.
3-7.
3-8.
3-9.
3-10.
3-11.

3-12.

3-13.
3-14.
3-15.
3-16.
3-17.

TITLE

Typical USART Data Character

Write Subroutine
Typical
PIT Counter Operation Vs. Gate Inputs
Typical
Typical
Typical
PIT Count Value Vs. Rate Multiplier

PIT Rate Generator Frequencies and

PIT Time Intervals Vs. Timer Counts
Typical
Typical
Typical
PIC Device Address Insertion

USART Status Read Subroutine
PIT Control Word Subroutine

PIT Count Value Load Subroutine
PIT Counter Read Subroutine

for Each Baud Rate

Timer Intervals

PPI Initialization Subroutine
PPI Port Read Subroutine
PPI Port Write Subroutine

.......................

...................

....

c

••••••••••••••••••••

..............

.........

...........

..........

.....

......

.......

.......

.......

PAGE

3-6

3-7
3-10
3-10

...

3-11
3-11

.3-12

3-13
3-13
3-14
3-14
3 -15
3-16

TABLE

3~18.

3-19.
3-20.

3-21.

3-22.
3-23.
3-24.

3-25.
3-26.
3-27.
4-1.

5-1.

5-2.

TITLE

Typical PIC Initialization Subroutine

PIC Operation Procedures

Typical

Typical PIC In-Service Register

Typical PIC Set Mask Register Subroutine
Typical PIC Mask Register Read Subroutine
Typical

Typical UPI Data Byte Read Subroutine
Typical

CPU Status and Control Lines. . . . . . . . . . . .

Replaceable

PIC Interrupt Request Register

Read Subroutine

Read Subroutine

PIC End-of-Interrupt

Command Subroutine

UPI Data Byte Write Subroutine

8085A CPU Restart Interrupt

Parts

List of Manufacturers' Codes

..........

.................

.......................

..... ' .. ' ................

...................

........

.....

.....

V~ctors

........

,.............

..............

....

ILLUSTRATIONS

PAGE

3'-17
3-19

3-20

3-20
3-20

..

3-21

3-21
3-22
3-22
3-22

..

4-4
5-1
5-3

FIGURE

1-1.
2-1.

2-2.
2-3.

2-4.
2-5.
2-6.
3-1.

3-2.

3-3.

3-4.

3-5.
3-6.

. 3-7.

3-8.
3-9.
3-10.

3-11.

TITLE

iSBC 80/30 Single Board Computer . . . . . . .

Jumper Configuration for Multibus Access

On-Board RAM (16-Bit Address System)

Jumper Configuration for Multibus Access

On-Board RAM (20-Bit Address System)
Bus Exchange Timing (Master Mode)
Bus Exchange Timing (Slave Mode)

Priority Resolution Scheme

Serial
Parallel Priority Resolution Scheme
USART Synchronous Mode Instruction

Word Format

USART Synchronous Mode Transmission

Format

USART Asynchronous Mode Instruction

Word Format

USART Asynchronous Mode Transmission

Format
USART Command Instruction Word Format
Typical

USART Status Read Format
PIT Mode Control Word Format
PIT Programming Sequence Examples
PIT Counter Register Latch Control

PPI Control Word Format

USART Initialization and

I/O Data Sequence

Word Format.

..........................

...............................

..........................

...............................

.....................

...............

.........................

.................

.......

.........

...........

.........

............

.......

PAGE

..

of

..

of

..

..

1-1

2-9

2-10
2-22
2-23
2-24

2-25

3-3

3-3

3-3

3-4
3-4

3-5
3-7
3-8
3-9

3-.12

3-13

FIGURE

3-12.

3-13.
3-14.
3-15.
3-16.

4.-1.
4-2.

4-3.
4-4.
4-5.
4-6.
4-7.

4-8.

4-9.

4-10.

5-1.

5-2.

5-3.

5-4.

TITLE

PPI Port C Bit Set/Reset Control

Word Format
PIC Device Interrupt Addresses
PIC Initialization Command Word Formats
PIC Operation Control Word Formats
UPI Data Bus Buffer and

Status Registers

80/30 Input/Output and

iSBC

Interrupt Block Diagram
iSBC

80/30 ROM/EPROM and Dual Port

RAM Block Diagram
Typical
Opcode Fetch Machine Cycle
Opcode Fetch Machine Cycle (With Wait)
Memory Read (or
Memory Write (or
Interrupt Acknowledge Machine Cycles
Dual

Port Control Bus Access Timing

With

Port Control CPU Access Timing

Dual

With Bus Lockout
iSBC

80/30 Parts Locations Diagram

iSBC

80/30 Schematic Diagram

iSBC

604 Schematic Diagram

iSBC 614 Schematic Diagram

..........................

........................

...............

CPU Instruction Cycle

CPU Lockout

..................

I/O Read) Machine Cycles . 4-6

I/O Write) Machine Cycles 4-7

....................

....................

.............

........

.............

..............

......

........

............

..............

..............

PAGE

...

....

3-15
3-16
3 -17
3-18

3-21

.4-17
.4-19

4-4
4-5
4-5

4-8

.4-10

.4-11

5-5
5-7

5-25

5-27

vi

CHAPTER 1

1-1. INTRODUCTION

The iSBC 80/30 Single Board Computer, which
member
products,
circuit assembly. The iSBC
cessor unit

of

Intel's complete line

is

a computer system on a single printed-

of

iSBC 80 computer

80/30 includes a central pro-

(CPU),

16K

bytes

of

dynamic random access
memory (RAM), one serial and three parallel I/O ports,
a programmable
bus control logic. Also included
to allow the iSBC
to

other bus masters
for user-installation
only memory

timer~

80/30 to act

in

of

(ROM

or

priority interrupt logic, and Multi-

is

dual port control logic

as

a slave RAM device

the system. Provision is made

masked or programmable read

EPROM) and an Intel 8041

8741A Universal Peripheral Interface.

is

or

1-2. DESCRIPTION

The iSBC 80/30 Single Board Computer (figure 1-1)
controlled by an Intel 8085A Microprocessor (CPU),
which includes six 8-bit general-purpose registers and an
accumulator. The six general-purpose registers may be
addressed individually

or

in pairs, which allows both

single precision and double precision operations. The

CPU has a 16-bit program counter which allows direct

is

GENERAL

addressing
located within any portion
used

as

a

a last-in/first-out storage area for the contents

of

up

INFORMATION

to

65K

of

memory. An external stack,

of

read/write memory, may be

the program counter, flags, accumulator, and all six
general-purpose registers. A 16-bit stack pointer controls
the addressing
routine nesting that

of

this external stack, which allows sub-

is

bounded only by the 65K address

limitation.

The iSBC

80/30 has an internal bus for all on-board
memory and I/O operations and accesses the system bus
(Multibus) for all external memory and
Hence, local (on-board) operations do not involve the
Multibus and allow true parallel processing when several
bus masters (e.g., DMA devices and other single board
computers) are used in a multimaster scheme.

The

16K

of

dynamic RAM

2717 chips and an Intel

is

implemented with eight Intel

8202 Dynamic RAM Controller.
Dual port control logic is included to interface this 16K
RAM with the Multibus

so

that the iSBC 80/30 can func­tion as a slave RAM device when not in control
Multibus. The
RAM. After the
tion, the controlling bus master

CPU has priority when accessing on-board

CPU completes its read

is

allowed
and complete its operation. Where both the
controlling bus master have the need to write

of

I/O operations.

of

the

or

write opera-

to

access RAM

CPU and the

or

read

611-1

PARALLEL

1/0

(MULTIBUS) (AUXILIARY)

OPTIONAL

8041/8741

1/0

SERIAL

1/0

Figure 1-1. iSBC 80/30 Single Board Computer

1-1

General Information

iSBC

80/30

several words to

or

from on-board RAM, their operations

are interleaved. The slave RAM decode logic allows ex-

so

tended Multibus addressing

that bus masters having a
20-bit address capability can partition the iSBC 80/30
RAM into any 8K
address space. The
lines and memory must therefore reside in the
address space. There

addresses for

or

16K segment in a I-megabyte

CPU, however, has only

16

address

0-65K byte

is

no conflict in assigning RAM

CPU access and slave access since separate

decoding logic is used.

Jumpers are included to allow the user to reserve 8K
bytes

of

on-board RAM for use by the 8085A CPU only.

This reserved RAM address space

is

not accessible via the

Multibus and does not occupy any system address space.
Two IC sockets are included to accommodate up

user-installed ROM
allow

ROM

or

increments. All on-board

or

EPROM

EPROM. Configuration jumpers

to

be installed in

ROM/EPROM operations are

lK,

2K,

to

.8K

or

of

4K

performed at maximum processor speed.

iSBC 80/30 includes 24 programmable parallel I/O

The
lines implemented by means

of

an Intel 8255A Program­mable Peripheral Interface (PPI). The system software is
used to configure

the I/O lines in any combination

of
unidirectional input/output and bidirectional ports. The
I/O interface may be customized to meet specific periph­eral requirements and, in order
of

the large number

of

possible I/O configurations, IC
sockets are provided for interchangeable
and terminators. Hence, the flexibility
I/O interface

is

further enhanced by the capability

selecting the appropriate combination

drivers and terminators

to

current, polarity, and drive/termination

to

take full advantage

I/O line drivers

of

the parallel

of

of

optional line

provide the required sink

characteristi9s

for each application. The 24 programmable I/O lines and

signal ground lines are brought out to a

connector

(11)

that mates with flat, woven, or round

50-pin edge

cable.
Sockets are provided

Universal Programmable Interface

fora

user-supplied Inte18041/8741A

(UPI) and associated
line drivers and terminators. The 8041/8741A is a single­chip microcomputer which contains a
ROM (8041)

or

EPROM

(8741),64

CPU, ) K bytes

bytes

of

RAM,

of

16
programmable I/O lines, and an 8-bit timer. Special inter­face registers are included in the chip which enable the
UPI to function as a slave processor to the 8085A CPU.
The UPI allows the user to specify algorithms for con-

trolling user peripherals directly in the chip, thereby

relieving the

RS232C driver and an RS232C receiver are included

8085A CPU for other system functions. An

so

that the UPI may optionally be used to handle a simple

serial

I/O interface. In addiiion to providing the capability

of

user-supplied algorithms for the 8041/8741A the
iSBC 80/30 supports all the preprogrammed 8041/8741A
devices such

Data Encryption Controller, and 8295 Matrix

as

the Intel 8278 Keyboard Encoder, 8294

Printer

Driver.

The RS232C compatible serial I/O port

interfaced

by

an Intel 8251A

US

is

controlled and

ART (Universal Syn­chronous/Asynchronous Receiver/Transmitter) chip. The
USART
most synchronous

is

individually programmable for operation in

or

asynchronous serial data transmission

formats (including IBM Bi-Sync).

In

the synchronous mode the following are programmable:

a.

Character length,

b.

Sync character (or characters), and

c.

Parity.
In the asynchronous mode the following are programmable:
a.

Character length,

b.

Baud rate factor (clock divide ratios

Stop bits, and

c.
d

..

Parity.

of

1, 16,

or

64).

In both the synchronous and asynchronous modes, the

I/O port features half-

serial

transmit and receive capability. In addition,

or

full-duplex, double-buffered

USART error
detection circuits can check for parity, overrun, and fram­ing errors. The

USART transmit and receive clock rates are
supplied by a programmable baud rate/time generator.
These clocks may optionally be supplied from an external
source. The RS232C command lines, serial data lines, and
signal ground lines are brought. out to a

(13)

connector

that mates with flat

or

50-pin edge

round cable.

Three independent, fully programmable 16-bit interval
timer/event counters are provided by an Intel 8253
Programmable Interval Timer (PIT). Each counter
capable
of

of

operating in either BCD

or

binary modes; two

these counters are available to the systems designer to

is

generate accurate time intervals under software control.
Routing for the outputs and gate/trigger inputs
these counters

is

jumper-selectable; the outputs

of

of

two

these

of

two counters may be independently routed to the 8259A
Programmable Interrupt Controller (PIC), the
drivers associated with the 8255A Programmable

I/O line

Periph-

eral Interface (PPI), the 8041/8741A Universal Program-

mable Interface, or used
and 8041/8741A (UPI). The gate/trigger inputs

counters may be routed

the 8255A

PPI

or

as
PPI. The third counter
rate generator for the serial
80/30,

the systems designer simply configures, via
software, each counter independently
requirements. Whenever a given time delay
needed, software commands
desired function. The contents

as

inputs to the 8255A PPI

ofthe

two

to

I/O terminators associated with

output connections from the 8255A

is

used

as

a programmable baud

I/O port. In utilizing the iSBC

to

meet system

or

count

is

to

·the 8253 PIT select the
of

each counter may be
read at any time during system operation with simple
operations for event counting applications, and special

so

commands are included
counter can be read

"on

that the contents

the

fly."

of

each

1-2

iSBC 80/30

The iSBC 80/30 provides vectoring for

of

levels, four
processing capability

(TRAP, RST

levels
(in decreasing order
interrupts
ate the following unique
RST

7.5
8085A JUMP instruction at each
provides linkage

which are handled directly by the interrupt

of

the 8085A CPU. These four

7.5;

RST

6.5,

and RST 5.5) represent

of

priority) the four highest priority

of

the iSBC 80/30. These four interrupts gener-

memory address: TRAP (24H),

(3CH), RST 6.5 (34H), and RST 5.5 (2CH). An

of

these addresses then

to

interrupt service routines located in­dependently anywhere in the lower65K bytes
All interrupt inputs with the exception
masked via software. The

TRAP interrupt should be used

12

interrupt

of

memory.

of

TRAP may be

for conditions such as power-down sequences which re­quire immediate attention by the

An Intel

8259A

Programmable Interrupt Controller

8085A CPU.

(PIC) provides vectoring for the next eight interrupt
levels. The

PIC treats each true input signal condition

as

an interrupt request. After resolving the interrupt priority,

PIC issues a single interrupt request to the CPU.

the
Interrupt priorities are independently programmable
under software control. Similarly, an interrupt can be

masked under software control. The programmable inter­rupt priority modes are:

a. Fully Nested

fixed priority: input

b. Auto-Rotating

Priority. Each interrupt request has a

0

is

highest, input 7 is lowest.

Priority. Each interrupt request has
equal priority. Each level, after receiving service,
becomes the lowest priority level until the next
interrupt occurs.

c. Specific

Priority

Priority. Software assigns lowest priority.

of

all other levels

is

in numerical sequence

based on lowest priority.

PIC, which can be programmed

The

or

sensitive

level-sensitive inputs, generates a unique

to

respond to edge-

memory address for each interrupt level. These addresses

of

are equally spaced at intervals

or

able) bytes. This 32­begin at any 32-

64-byte block may be located to

or

64-byte boundary in the 65,536 byte

4 to 8 (software select-

memory space. A single 8085A JUMP instruction at each
of

these addresses then provides linkage

to

locate each
interrupt service routine independently anywhere in
memory.

General Information

of

request can be generated by two

counters and by the Universal

Peripheral Interface (UPI).

the programmable

Eight additional interrupt request lines are available to the
user for direct interfaces to user designated periphral
devices via the Multibus, and two interrupt request lines
may be jumper routed directly from peripherals via the
parallel

Control logic is also included for generation

I/O driver/ terminator section.

of

a Power-

Fail Interrupt, which works in conjunction with an AC

LOW signal from an Intel iSBC 635 Power Supply

or

equivalent.

iSBC 80/30 includes the resources for supporting a

The

of

OEM

variety

system requirements.

For

those appli­cations requiring additional processing capacity and the
benefits

multiprocessing (i.e., several

CPU's

and/or

of
controllers logically sharing systems tasks with com­munication over the Multibus), the

iSBC 80/30 provides

full bus arbitration control logic . This control logic allows

of

up to three bus masters (e.g., any combination

80/30, iSBC 80/20,
etc.)

to

share the Multibus in serial (daisy-chain) fashion

or

up

to

16

bus masters to share the Multibus using an

DMA controller, diskette

iSBC

cont~oller,

external parallel priority resolving network.

The Multibus arbitration logic operates synchronously

with the bus clock, which is derived either from the

or

80/30

master. Data, however,

can be optionally generated by some other bus

is

transferred via a handshake

iSBC

between the controlling master and the addressed slave
module. This arrangement allows different speed control­lers to share resources on the same bus, and transfers via
the bus proceed asynchronously. Thus, the transfer speed
is

dependent on transmitting and receiving devices only.

This design prevents slower master modules from being

of

handicapped in their attempts to gain control

the bus,
but does not restrict the speed at which faster modules can
transfer data via the same bus. The most obvious appli-

of

cations for the master-slave capabilities

mUltiprocessor configurations, high-speed direct

the bus are

memory

access (DMA) operations, and high-speed peripheral

no

control, but are by

means limited to these three.

Interrupt requests may originate from
jumper-selectable interrupt requests can be automatically
generated by the
(PPI) when a byte
to

the 8085A CPU (i.e., input buffer

Programmable Peripheral Interface

of

information

information has been transferred to a peripheral device
(i.e.,

output buffer

is

empty). Two jumper-selectable

interrupt requests can be automatically generated by the

USART when a character

8085A CPU
character

(i.e.,

receive channel buffer

is

ready to be transmitted (i.e., transmit channel

is

ready to be transferred to the

data buffer is empty). A jumper-selectable interrupt

18

sources. Two

is

ready to be transferred

is

full)

or

a byte

is

full)

or

when a

1-3. SYSTEM SOFTWARE

DEVELOPMENT

Intel's RMX/80 Real-Time Multitasking Software, spe-

of

cifically designed for Intel
puters, provides the capability to monitor and control

mUltiple asynchronous external events. The RMX/80
Executive, which synchronizes and controls the execu-

of

tion

multiple tasks,
relocatable module that requires
memory. Optional linkage and relocatable modules for

iSBC 80 single board com-

is

provided as a linkable and

only

2K

bytes

of

1-3

General Information

iSBC 80/30

teletypewriter and CRT control, diskette file system,
high-speed mathematics unit, and analog subsystems are

also available.

The development cycle

of

iSBC 80/30 based products
may be significantly reduced using an Intel Intellec
Microcomputer Development System. The resident
macroassembler, text editor, and system monitor greatly
simplify the design, development, and debug

system software. An optional diskette operating

80/30

system provides

-a

relocating macro assembler, relocating

of

iSBC

loader and linkage editor, and a library manager. A
unique In-Circuit Emulator (lCE-85) option provides the

of

capability
on the

Intel's high level programming language, PL/M,
available

developing and debugging software directly

iSBC 80/30.

as

a resident Intellec Microcomputer Develop-

is

also

ment System option. PL/M provides the capability to pro-

gram

in

a natural, algorithmic language and eliminates the

or

need to manage register usage

allocate memory. PL/M
programs can be written in a much shorter time than
assembly language programs for a given application.

Table

1-1. Specifications

1-4. EQUIPMENT SUPPLIED

The following are supplied with the iSBC 80/30 Single
Board Computer:

a. Schematic diagram,
b.

Assembly drawing, dwg no. 1001576

d,wg

no. 2002132

1-5. EQUIPMENT REQUIRED

Because the iSBC 80/30
applications, the user must purchase and install only those
components required to satisfy his particular needs. A list
of

components required to configure all the intended

applications

of

the iSBC 80/30

is

designed to satisfy a variety

is

provided in table 2-1.

of

1-6. SPECIFICATIONS

Specifications
are listed

of

the iSBC 80/30 Single Board Computer

in

table 1-1.

WORD SIZE

Instruction:
Data:

CYCLE

TIME:

MEMORY CAPACITY

On-Board ROMIE PROM:
On-Board RAM:

Off-Board Expansion:

MEMORY ADDRESSING

On-Board ROM/EPROM:

On-Board

On-Board

RAM

(CPU Access):

RAM

(Multibus Access):

8,

16,

or

24

8 bits.

1.44

Up

to

16K bytes of dynamic RAM; integrity maintained during power

furnished batteries.

Up

to

0-07FF
EPROM's or 2316E ROM's);

Jumpers

addresses may be set on 8K boundaries
access, addresses may
or both

Jumpers allow board to act as slave for
bus master; 16-bit or
irrespective
may
addressing, boundaries may
address space.

bits.

f.Lsec

±0.1 % for fastest executable instruction; i.e., four clock cycles.

8K bytes; user installed

65K bytes of user-specified.combinations of RAM,

(using 2708 or 2758 EPROM's or 8308 ROM's);

allow on-board

8K

segments may be reserved for CPU use only.

of

be

addresses used for

set

on

any

8K

in 1 K,

2K,

or 4K increments.

ROM,

0-1

FFF (using 2332 ROM's).

CPU

to· access either

be

set

on

16K boundaries 4000, 8000, or

20-bit addressing is accommodated and addresses are

or

CPU

16K

be

access. For 16-bit addrljssing, boundaries

segment of 65K byte address space. For 20-bit

set

on

8K

or 16K. For

2000, 4000,

8K

or 16K

any 8K or 16K segment of 1 M byte

RAM

O-OFFF

...

failure with user-

and EPROM.

(using 2716

8K

RAM

EOOO.

access by another

access,

For 16K

COOO.

One

1-4

iSBC

80/30

SERIAL COMMUNICATIONS

Synchronous:

Table 1-1. Specifications (Continued)

S-,

6-, 7-, or 8-bit characters.
Internal; 1 or 2 sync characters.
Automatic sync insertion.

General Information

Asynchronous:

Sample Baud Rate:

5-, 6-, 7-, or 8-bit characters.
Break character generation.

1,

1

'12,

or 2 stop bits.

False start bit detection.

Frequency'

(kHz, Software Selectable)

153.6

76.8

38.4

19.2

9.6 9600 600 150

4.8

2.4

1.76

Notes:

1.

Frequency selected by
Baud Rate Register.

2.

Baud rates shown here are only a sample subset of possible software­programmable rates available. Any frequency from 18.75 Hz to 614.4 kHz
may

be

generated utilizing on-board crystal oscillator and 16-bit Program-

mable Interval Timer (used here as frequency divider).

Baud Rate

Synchronous

-

-

38400
19200

4800 300
2400
1760

1/0

writes of appropriate 16-bit frequency factor to

(Hz)2

Asynchronous

+16

9600
4800 1200
2400
1200

150
110

2400

+64

600
300

75

-

-

INTERVAL
GENERATOR

Input Frequency (selectable):

Output Frequencies:

SYSTEM CLOCK (808SA CPU):

TIMER AND BAUD RATE

±0.1%

2.46 MHz

1.23 MHz ±0.1% (0.82

153.6 kHz

Function

Real-Time
Interrupt

Interval

Rate
Generator
(Frequency)

2.7648 MHz

(0.41

±0.1% (6.5

1.63/-L

2.348 Hz 614.4 kHz

±0.1%.

/-Lsec

period nominal),

/-Lsec

period nominal), and

/-Lsec

period nominal).

Single Timer

Min.

sec

Max.

426 msec

Dual Timers

(Two Timers Cascaded)

Min.

3.26/-Lsec

0.000036 Hz

Max.

46528

minutes

307.2 kHz

1-5

General Information

iSBC 80/30

Table 1-1. Specifications (Continued)

I/O ADDRESSING:

INTERFACE COMPATIBILITY

Serial I/O:

Parallel I/O:

Optional I/O:

INTERRUPTS:

All communication
is via read and write commands from on-board 8085A CPU. Refer to table 3-2.

EIA Standard RS232C signals provided and supported:

Carrier Detect Receive Data
Clear to Send Ring Indicator
Data Set Ready Secondary Receive Data
Data Terminal Ready Secondary Transmit Data
Request to Send Transmit Clock
Receive Clock Transmit Data

24 programmable lines (8 lines per port); one port includes bidirectional bus driver.
IC sockets included for user installation of line drivers and/or I/O terminators as
required for interface ports. Refer to table 2-1.

IC socket included for Intel 8041/8741 Universal Peripheral Interface (UPI). Also
included are
required for interface. Refer to table 2-1.

8085A CPU includes five interrupt inputs, each of which vectors processor to the
following unique memory locations for entry point to service routine:

Interrupt Vector

Input

TRAP

RST

7.5

RST 6.5 34H

RST

5.5

INTR

to

Parallel I/O and Serial I/O Ports, Timer, and Interrupt Controller

IC

sockets for user installation of line drivers and/or I/O terminators as

Address

24H Highest

3CH
2CH

Note

Priority

Lowest

t

Type

Non-maskable

Maskable
Maskable
Maskable
Maskable

COMPATIBLE CONNECTORS/CABLES:

ENVIRONMENTAL REQUIREMENTS

Operating Temperature:

Relative Humidity:

PHYSICAL CHARACTERISTICS

Width:

Depth:
Thickness:
Weight:

Note:

INTR input provided by 8259A PIC, which
vide vector CALL address of service routine for interrupting device.

Jumpers
be programmed to respond to edge-sensitive or level-sensitive inputs.

Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-29 and

2-30 for recommended types and lengths of I/O cables.

To

30.48

17.15

1.27 cm

425 gm (15 ounces).

allow selection of 12 priority interrupts from 18 interrupt sources. PIC may

90% without condensation.

cm

(12.00 inches).

cm

(6.75 inches).

(0.50 inch).

is

programmable to pro-

1-6

iSBC 80/30

POWER REQUIREMENTS:

General Information

Table 1-1. Specifications (Continued)

CONFIGURATION
Without EPROM'
With 8041/8741

RAM Only3
With iSSC
With 2K EPROM5

(using
With 2K EPROM5

(Using 8758)
With 4K EPROM5

(Using 2716)
With 8K ROM5

(Using 2332)

Notes:

53Q4

8708)

1.

Does not include power for optional ROM/EPROM, 8041/8741 UPI, I/O drivers, and I/O terminators.

2.

Does not include power required for optional ROM/EPROM, I/O drivers and I/O terminators.

3.

RAM chips powered via auxiliary power bus.

4.

Does not include power for optional ROM/EPROM, 8041/8741 UPI, I/O drivers, and I/O terminators.
is supplied via serial port connector.

5.

Includes power required for two ROM/EPROM chips, 8041/8741 UPI, and I/O terminators installed for
terminator inputs low.

UPI2

Vce = +5V±5%

3.5A

3.6A 220 rnA
rnA 20 rnA

350

3.5A

4.4A

4.6A

(4.6A

!

4.6A 220 rnA

VD

=

D

220 rnA

+12V±5%

VSS = -5V±5%

-

-

2.5 rnA

320 rnA

350 rnA

220 rnA 50 rnA

(220 rnA

\,

-

95 rnA

-

-

-

VAA =

-12V±5%
SOmA
SOmA

-

150 rnA

40 rnA

(50

rnA)

50 rnA

PowerforiSSC530

341/0

lines; all

1-7/1-8'

CHAPTER 2

PREPARATION FOR USE

2-1. INTRODUCTION

This chapter provides instructions for preparing the iSBC

Single Board Computer for use in the user-defined

80/30

It

environment.

1 and 3 be fully understood before beginning the con­figuration and installation procedures provided
chapter.

is advisable that the contents

of

Chapters

in

this

2-2. UNPACKING AND INSPECTION

Inspect the shipping carton immediately upon receipt for

of

evidence
carton
the carrier's agent be present when the carton
the carrier's agent

and the contents

carton and packing material for the agent's inspection.

For repairs to a product damaged in shipment, contact the
Intel Technical Support Center (see paragraph 5-4)
obtain a Return Authorization Number and further in­structions. A purchase order will be required to complete
the repair. A copy
ted to the carrier with your claim.

mishandling during transit. .If the shipping

is

severely damaged or waterstained, request that

is

opened.

is

not present when the carton

of

the carton are damaged, keep the

of

the purchase order should be submit-

is

opened

If

to

Important criteria for installing and interfacing the
iSBC 80/30
following paragraphs.

in

the above environments are presented in

2-4. USER-FURNISHED COMPONENTS

Because the iSBC 80/30

applications, the user need purchase and install only those

components required to satisfy his particular configura-

tion. A list
intended applications
2-1. Table 2-2 lists details, types, and vendors
connectors referenced in table 2-1.

of

components required to configure all the

is

designed to satisfy a variety

of

the iSBC 80/30 are listed in table

of

of

those

2-5. POWER REQUIREMENTS

The iSBC 80/30 requires
power supply inputs. The currents required from these
supplies are listed in table 1-1. (The - 5 V supply is

mandatory only

an on-board regulator that operates off the
can otherwise supply the

if

+5V,

-5V,

+ 12V, and

Intel 2708 EPROM chips are installed;

-5V

power.)

-12V

-12V

supply.

2-6. COOLING REQUIREMENT

It is suggested that salvageable shipping cartons and pack­ing material be saved for future use in the event the
product must be reshipped.

2-3. INSTALLATION CONSIDERATIONS

The iSBC 80/30 is designed for use in one
configurations:

a. Standalone (single-board) system.
b. Bus master in a single bus master system.
c. Bus master in a multiple bus master system.

of

the following

The iSBC 80/30 dissipates 401 gram-calories/minute

of

(1.62 Btu/minute) and adequate circulation
provided to prevent a temperature rise above 55°C
(131°F). The System
tem include fans to provide adequate intake and exhaust
ventilating air.

80 enclosures and the Intellec Sys-

air must be

of

2-7. PHYSICAL DIMENSIONS

Physical dimensions

a. Width:
b.

Height:

c. Thickness:

of

the iSBC 80/30 are as follows:

30.48 cm (12.00 inches).

17.15 cm (6.75 inches).

1.25 cm (0.50 inch).

2-1

Preparation for

Use

iSBC

80/30

Item

No.

1

2

3

4

5 Connector

6

7

Item

iSBC 604 Modular Backplane and Cardcage. In-

iSBC 614 Modular Backplane and Cardcage. In-

Connector

{mates with

Connector

{mates with

{mates with J1}

Connector

{mates with J2}

Connector

{mates with J3}

Table 2-1. User-Furnished

Description

four slots with bus terminators.

cludes
{See figure 5-3.}

cludes

four slots without bus terminators.

{See figure 5-4.}

Multibus

P1}

P2}

See

table 2-2.

Auxiliary

See
table 2-2.

See parallel
table 2-2.

See parallel I/O connector details in
table 2-2.

See serial I/O connector details
table 2-2.

I/O

and

Installed Components

connector

connector details

connector details in

details

Use

Provides
signal interface between iSBC 80/30 and

three
system.

Provides four-slot

in

in

in

Power inputs
Not required if
in

Auxiliary backup battery inputs and asso­ciated memory protect functions.

Interfaces parallel I/O ports to Intel 8255A
Programmable Peripheral Interface {PPI}.

Interfaces I/O ports to optional Intel 8041/
8741A
{UPI}.

Interfaces serial I/O port to
Programmable Communications Interface
{USART}.

power input pins and Multibus

additional boards

extension of iSBC 604.

and

Multibus signal interface

an iSBC 604/q14.

iSBC 80/30

Universal

Peripheral

in

a multiple board

is

installed

Interface

Intel.

8251A

in

8

9

10

11

ROM/EPROM Chips One

ROM/EPROM chips:

ROM
8308

-

2316E 2716

2332

Intel 8041/8741 A

Line Drivers

I/O Terminators Intel iSBC

Universal Peripheral Interface {UPI}.

SN74031,OC
SN7400 I
SN7408
SN7409

Types
ing,
collector.

Pull-Up:

or

two

each of the following

EPROM

2708
2758

-

Type

NI
NI,

OC

selected as typical; I = invert-

NI

= noninverting, and OC = open

901

Divider or iSBC 902

iSBC

901

~

330

iSBC 902

0

1K x 8
2K

4K x 8

Current

16 rnA
16 rnA
16 rnA
16 rnA

220

l~~v

0

BITS

1K

Intel

x 8
x 8

On-board UV erasable PROM for program

development and/or dedicated program

Compatible ROM chips can also

use.
employed.
do not mix.

Single
memory,
timer,
faces two 8-bit I/O ports; two additional
input bits
branch and event timer functions.

Used for interface to
optional Intel 8041/8741. Requires two
line driver IC's for each 8-bit parallel
output port. {Exception: refer to para­graph 2-11.}

Used for interface
optional Intel 8041/8741A.
901

input port. {Exception: refer to paragraph
2-11.} Additional
8041/8741
for conditional branch

functions.

Use either ROM or EPROM;

chip microcomputer with program

I/O, and clock oscillator. Inter-

's or two 902's for each 8-bit parallel

memory,

data

{TO

and T1} for conditional

901

if

TO

and

CPU,

Intel 8255A and

to

Intel 8255A and

Requires two

or 902 required for

T1

inputs are used

or

event timer

be

event

12

2-2

Capacitors

Seven capacitors as required.

Rise time/noise capacitors for

port.

serial I/O

iSBC 80/30

Table 2-2. User-Furnished Connector Details

Preparation for

Use

Function

Parallel

I/O 25/50

Connector

Parallel

I/O

Connector

Parallel

I/O

Connector

Serial

I/O

Connector

Serial

I/O 13/26

Connector

Serial

1/0

Connector

Multibus

Connector

No. Of

Palrsl

Pins (Inches) Type

25/50

25/50

13/26

13/26

43/86

Centers

0.1

0.1

0.1

0.1

0.1

0.1

0.156 Soldered

Connector

Flat Crimp

Soldered VIKING

Wirewrap1

Flat Crimp

Soldered

Wirewrap1

MICRO PLASTICS

1

Vendor

3M
3M

AMP

ANSLEY

SAE

AMP

TI
TI

VIKING

COC3

ITICANNON

3M

AMP 88106-1

ANSLEY 609-2615

SAE

TI

AMP

TI

COC3

ARCO

VIKING

3415-0000 WITH EARS

3415-0001 WID EARS

88083-1
609-5015
S06750

2-583485-6
3VH25/1JV5
H312125

H311125
3VH25/1
VPB01 B25000A 1

EC4A050A1A

3462-0001

S06726

H312113

1-583485-5

H311113

VPB01 E43000A 1
MP-0156-43-BW-4
AE443WP1 LESS EARS
2VH43/1AV5

Vendor Part No.

SERIES

JN05

SERIES

Intel

Part No.

iSBC 956

Cable

Set

N/A

N/A

955

iSBC

Cable

Set

N/A

N/A

N/A

Multibus

Connector

AUXiliary

Connector

Auxiliary

Connector

NOTES:

1.

2.

3.

43/86

30/60

30/60

Connector heights are not guaranteed to conform to OEM packaging equipment.
Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment.
CDC VPB01 ... , VPB02 ... , VPB04 ... , etc. are identical connectors with different electroplating thicknesses
surfaces.

0.156

0.1

0.1

Wirewrapl.2

Soldered

Wirewrapl.2

1

2-8. COMPONENT INSTALLATION

Instructions for installing the optional ROM/EPROM,
Intel 8041/8741A Universal Peripheral Interface, line

VO

drivers,
are given in following paragraphs. When installing the
optional chips, be sure to orient pin 1
the white dot located near pin 1
The grid location on figure 5
and figure 5 -2 (schematic diagram) are specified for each
user-installed component. Because the schematic
gram consists

terminators, and rise time/noise capacitors

of

the chip adjacent to

of

the associated IC socket.

-1

(parts location diagram) .

dia-

of

nine sheets, grid references to figure 5

...

COC3
COC3

VIKING

TI H312130

VIKING

COC3

TI

consist

of

VFB01 E43000A 1 or

VPB01

E43AOOA

2VH43/1AV5

3VH30/1JN5
VPB01

B30AOOA2

H311130

1

four alphanumeric characters. For example,

grid reference 6ZD4 signifies sheet 6 Zone D4.

2-9.

ROM/EPROM

cmps

Install the ROM/EPROM chips in IC sockets A25 and

-1

A37. (Refer to figure 5

zone ZC3 and figure 5 -2 zone

3ZA3.) Sockets A25 and A37, respectively,

modate the low order and high-order addresses
ROM/EPROM chip pair. For instance,

if

two Intel 2716
EPROM chips are installed, the chip installed in IC socket
A25 is assigned addresses
IC socket A37 is assigned addresses

2

0000-07FF; the chip installed in

0800-0FFF.

MOS 985

N/A

N/A

or

accom-

metal

of

the

2-3

Preparation for

Use

iSBC 80/30

The default (factory connected) jumpers are configured
for Intel 2316E ROM

or

2716 EPROM.

If

different type
chips are installed, reconfigure the jumpers as described in
paragraph 2 -14.

2-10. UNIVERSAL PERIPHERAL

INTERFACE

Install the optional Inte18041/8741A Universal Peripheral
Interface (UPI) chip in socket A20. (Refer to figure 5-1
zone ZC6 and figure 5-2. zone 5ZC4.)

2-11. LINE DRIVERS AND 110

TERMINATORS

Table 2-3 lists the I/O ports and the location
sockets for installing either line drivers
(Refer

to

table 2

-1

items

10

and 11.) Port
equipped with Intel 8226 Bidirectional Bus Drivers and
requires no additional components. (Refer
2-22 and 2-23.)

of

associated IC

or

I/O terminators.

E8

is

factory

to

paragraphs

2-12. RISE TIME/NOISE CAPACITORS

Eye pads are provided so that rise time/noise capacitors
may be installed
pins. The selection
user and is normally a function
ment. The location

as

required on the individual serial I/O

of

capacitor values

of

these eye pads are

is

at the option

of

the particular environ-

as

follows:

of

the

2-13. JUMPER CONFIGURATION

The iSBC 80/30 includes a variety

options to allow the user

to

parficular applicatio'n. Table

jumper-selectable options and lists

locations

of

the jumpers

as
location diagram) and figure 5-2 (schematic diagram).
Because the schematic consists

to

references

figure 5-2 consists
characters. For example, grid reference 3ZB7 signifies
sheet 3 Zone B7.

Study table 2-5 carefully while making reference to
figures 5-1 and 5-2.

If

the default (factory configured)
jumper wiring is appropriate for a particular function, no
further actions is required for that function.
different configuration
jumper(s) and install

is

required, remove the default

an

optional jumpers(s)

For most options, the information in table 2-4 is suffi-

cient for proper configuration. Additional information,

where necessary for clarity,
paragraphs.

2-14. ROM/EPROM CONFIGURATION

Table 2-5 lists the jumper configurations and associated

address block for the various 'types
ROM/EPROM chips.

of

jumper-selectable

configure the board for his

2-4

summarizes these
the-

grid reference

shown

of

of

is

described

in

figure 5-1 (parts

nine sheets, grid

four alphanumeric

If,

however, a

as

specified.

in

subsequent

of

compatible Intel

Capacitor Fig.

C11
C12
C13
C14
C16
C17
C18

8255A

PPI

Interface

8041/8741

UPI

Interface

(Optional)

Z04

Z04 6Z83
Z03
Z04 6Z04

Z03 6Z06

Z03

Z03

5-1

Fig. 5-2

6Z04
6ZC4

6ZC6
6Z06

Table 2-3. Line Driver

1/0

Port

E8

E9

EA

1

2

Bits

0-7 None Required -

0-3

4-7
0-3

4-7
0-3

4-7
0-3

4-7

2-15. ON-BOARD RAM ADDRESSES

This on-board RAM can be accessed by the on-board
8085A microprocessor (CPU)
masters in the system via the

board 8085A access and for system access are assigned as

and

1/0

described in

Terminator Locations

Driver/

Terminator

A5
A6

A4
A3

A7
A8

A10
A11

paragraph~

Fig. 5·1

as

well as by other bus

~1ultibus.

Addresses for on-

2-16 and 2-17, respectively.

Fig. 5·2

Grid

Ref.

Z06

Z06
Z07

Z07
Z06

Z06

Z05 5Z83

Z05

Grid

4ZA3
4ZA3

4ZC3
4Z83

5Z03
5ZC3

5Z83

Ref

-

-

2-4

TO,

T1

A9

Z05

5ZC3

iSBC 80/30

Preparation for

Use

Function

ROM/EPROM

Configuration

On-Board RAM

(On-Board Access)

On-Board

(System Access)

RA

M

Table 2-4.

5-1

Fig.

Grid Ref.

ZC3 3ZB7
ZC3 3ZC6 157 thru 159
ZC3
ZD2
ZD2
ZD2 3ZA3 102 thru 105

ZD2

ZB7
ZB7

ZB7

ZB7
ZB7

ZB7
ZB7

Fig. 5-2

Grid Ref.

3ZB4
3ZA3 84 thru
3ZA4

3ZD7,3ZD6

5ZC6
5ZB6

5ZB5

5ZC7
5ZC6
5ZB6
5ZB5

Jumper

Selectable Options

Six

jumpers accommodate one of four types of user-installed ROM or
EPROM chips.
the

following six groups of posts:

112

thru

153 thru 156

99

thru

One jumper wire selects

base address for on-board 8085A access of on-board RAM. JumperW1

default position *A-B selects 16K access and default jumper *98-92
selects base address 4000H. Refer
reconfiguration

16-Bit Address System: Three jumper wires

system access:
W5 (one): Must

W4 (one):

171

thru 180 (one): Base address.

Refer

to

20-Bit Address System: Five jumper wires

system access:
W6 (two): Upper or lower 512K space.

W5 (one): 65K page select.
W4 (one):

171

thru 180 (one): Base address.

Refer

to

Description

One

jumper required between two posts

114)

Default jumpers accommodate Intel 2716 EPROM

88

101

8K

paragraphs 2-17 and 2-18.

8K

paragraphs 2-17 and 2-19.

or 2316E ROM chips. Refer
reconfiguration

8K

or 16K access and one jumper wire selects

is

required.

be

set

to

or 16K access.

or 16K access.

position *K-L.

to

is

required.

to

paragraphs 2-15 and 2-16 if

paragraph 2-14

select base address for

select base address for

in

each of

if

Bus

Clock

Constant Clock

Bus

Priority Out

Bus Priority

Resolution

Auxiliary Backup

Batteries

On-Board

-5V

Regulator

ZB7

ZB7

ZB7 8ZD2

ZB7

ZB5

ZB6

5ZA4

5ZA4

8ZD6

1ZC5,1ZB5

1ZB2

Default jumper *165-166 routes Bus Clock signal BCLKI

(Refer

to

supplies this signal.

Default jumper *167-168 routes Constant Clock signal CCLK/ to the

Multibus. (Refer
master supplies this signal.

Default jum per * 169-170 routes Bus Priority Out signal BPRO/

Multibus (Refer to table 2-13.) Remove this jumper only
systems
to paragraph 2-27.)

One jumper defines one of two modes of resolving bus contention

multiple
*162-163:

If auxiliary

power outages, remove

The 80/30 requires a

-5V

is
Intel
supply is available, the

be
battery.

-12V
battery is used, enable the

table 2-13.) Remove this jumper only

to

table 2-13.) Remove this jumper only

employing a parallel priority bus resolution scheme. (Refer

bus master system:

Can

163-164:

AUX

mandatory only

2708 EPROM chips

supplied by the on-board

supply.)

request Multibus

Always requesting Multibus; .should only

iSBC 80/30 has lowest priority.

backup batteries are employed

input for the on-board RAM chips. The system

(The

-5V
if

on-board

If

neither a system

default jumpers *W8, *W9, and *W10.

Intel 2708 EPROM chips are employed. If

-5

as

needed.

to

sustain memory during ac

supply for Intel 2708 EPROM chips and a

are

not employed and

AUX

input

to

-5V

-5V

regulator operates from the system

-5V

regulator by connecting jumper*W10.

the on-board RAM chips can

regulator or by

-5V

supply nor

to

if

the Multibus.

another bus master

if

another bus

to

in

those

be

used when

-5V

supply

no

system

an

auxiliary backup

an

auxiliary backup

the

in

-5V

a

2-5

Preparation for

Use

iSBC 80/30

Function

Failsafe Timer

RAM Refresh

Timer

Input

Frequency

Table 2-4.

5-1

Fig.

Grid Ref.

ZC8

ZC4

ZD5

ZD5

ZD5

Jumper

Fig. 5-2

Grid Ref.

1ZC6 If the on-board 8085A

2ZA3

7ZB3

7ZA4

7ZB5

Selectable Options (Continued)

or

memory
ledge signal, the 8085A will hang up

is triggered during

within 1
allow the 8085A
jumper 115-116.

The 8202 Memory

follows
*110-111: Automatic refresh (normal) mode.

110-106:

In

the automatic refresh mode, a wait state can

on-board 8085A if a memory access occurs while a memory refresh

cycle is

the refresh cycle
works around memory accesses by refreshing memory during the
instruction decode clock cycle which

frequencies

Input

are jumper selectable

Counter 0 (8041/8741 Event Clock)

*47-52:

47-51: 153.6 kHz.

47-48: External Event Clock (from Port EA).
Counter 1 (Count
*46-54: 1.2288 MHz.

46-52:

46-50: Counter 0 output.

46-48: External Event Clock (from Port EA).
Jumper 46-50 effectively connects Counter
the output of Counter

This permits lower clock rates

provides longer time intervals.
Counter 2 (8251A Baud Rate Clock)
*53-54: 1.2288 MHz.

53-49: 2.4576 MHz.

I/O device and that device does not return

0

milli~econds,

to

to

Controller for on-board RAM

select the automatic or invisible refresh mode:

Invisible refresh (on request) mode.

in

progress.

is

to

Same

as

Same

as

Description

CPU

addresses either a system or

in

T1

of every machine cycle and, if not retriggered

the resultant time-out pulse

exit

the

wait state. If this feature

In

this case, the 8085A is forced to wait until

complete.

the 8253 Programmable Interval Timer counters

Counter

Out)

Counter

as

follows:

2.

2.

0 serves

In

to

a wait state. A failsafe timer

is

jumper selectable

the invisible refresh mode, the 8202

follows each instruction fetch.

as

Counter 1 and,

0 and 1

the input clock

an

on-board

an

acknow-

can

be

is

desired, connect

be

in

in

used

imposed

series

in

to

Counter

turn, Counter 1

on

which

to

as

the

1.

Event Clock

ZD5

Interrupt

Priority

ZC6
ZC6
ZB6

8251A

Serial I/O

Port Configuration

8255A

Parallel I/O

Port Configuration

8041·/8741

*Default jumper connected at the factory.

A Universal
Peripheral.
Interface

- Sheet 6 Jumpers are used

- Sheet 4 Jumpers are used

- Sheet 5 Jumpers

2-6

7ZB4

Sheet 7

The Event Clock is a jumper option for Port

PPI. The Event Clock may
sources:

Same

as

48-50:
48-51: 153.6 kHz.
48-52:

Same

A jumper matrix provides a wide selection of interrupts to

to

the on-board 8085A and

following jumpers (refer

117 thru 134
136 thru 152
181

thru 190

clock, ring indicator, carrier detect, etc.,
to

paragraph 2-21.

operating mode. Refer

are

on the application. Refer

PIT

as

PIT

to

input the serial I/O port transmit clock, receive

to

configure Ports

used

to

select various input and/or output signals depending

be

provided by the following optional

Counter 0 (8041/8741 Event Clock).
Counter 2 clock.

,the

to

to.

Multibus. The matrix includes the

paragraph 2-20):

paragraph 2-22.

to

paragraph 2-23.

E8,

C (Port

EA)

from

several sources. Refer

E9,

and

EA

of

the 8255A

be

interfaced

for the desired

iSBC 80/30

Preparation for

Use

Table 2-5.

ROM/EPROM

EPROM

EPROM

EPROM

*2316E

*Default jumpers are connected for type 2716 EPROM or

2316E ROM. Disconnect and reconfigure jumpers as
necessary if

2-16.

tion B-C allows the on-board
16K RAM; jumper
access to all 16K. For
may be configured on
EOOO;
configured on 16K boundaries

ROM/EPROM

Type

2708

or
8308
ROM

2758

*2716

or
ROM

2332
ROM

112-113,158-159,
100-101,104-105,
155-154, 86-84

112-113,158-159,
100-101,104-103,
155-154,86-87

112-113, 157-158,
100-101,104-103,
155-156,86-85

112-114,157-158,
100-99,104-102,
155-153,86-85

installing different type ROM/EPROM.

ON-BOARD808SAACCESS.

WI

SK

Configuration

Jumpers

Jumpers

Address

Block

0000-07FF

0000-07FF

OOOO-OFFF

0000-1 FFF

JumperWl

SOS5A

to access

SK

of

default position A-B allows

access, the RAM address block

SK

boundaries 2000, 4000,

posi-

the

...

for 16K access, the RAM address block may be

4000,

SOOO,

or

COOO.
(Address boundary 0000 is reserved for ROM/EPROM.)
Default jumper
and 16K access.
jumper

WI

B-C. If a different address boundary is desired,

9S

-92 selects boundary 4000 for both

If

only

SK

access is desired remove

from position A-B and install

it

id

position

SK

recon-

figure the jumpers as listed in table 2-6.

SYSTEM ACCESS. The on-board RAM can be

2-17.
shared by other bus masters in the system via the

Multibus.

If

one or more bus masters have a 20-bit

address capability, the extended addressing jumpers

allow the onboard RAM

I-megabyte address space. (The on-board

access memory in the

to

reside anywhere within a

lo~er

65K address space.) If it

SOS5A

can only

not desired to have the on-board RAM s4ared by the
system, leave default jumper

wise~

configure the jumpers for 16-bit addressing or

IS0-179 installed. Other-

20-bIt addressing as described in following paragraphs.

NOTE

Addresses for system access
are completely independent
board

SOS5A

access

of

of

on-board RAM

of

addresses for on-

on-board RAM.

Table 2-6.

Jumper

98-91

*98-92 4000-5FFF

98-93
98-94
98-95
98-96
98-97

NOTES:

1.

2.

3.

Jumper

808SA Access

Address block 0000-1 FFF is reserved for

ROM/EPROM.
Requires jumper
Requires jumper
*Default

is

required.

Configuration

of

On-Board

RAM Address

8KAccess

2000-3FFF

6000-7FFF
8000-9FFF

AOOO-BFFF

COOO-DFFF
EOOO-FFFF

jumper; disconnect if reconfiguration

2

W1

position B-C installed.

W1

position

for

RAM

Block1

16K Access

*A-B

2-18. 16-BIT ADDRESS SYSTEMS. For system access,

~n-board

the

1?~bIt

and Jumper W5 default position K-L restricts the

bIlIty
addresses
(Refer

As

shown

16K

~f

B-A lImIts the system to
B-C allows

RAM

is

divided into eight 65K pages. In

add~ess

to

systems, there

to

Page 0 (the only page in a 16-bit system).

is

no page selection capa-

table 2 -7.)

in

table 2-S, the system can access either

t~e

on-board RAM. Jumper W4 default

SK

access; jumper W4 position

acce!tS

of

all 16K

of

on-board RAM.

One jumper wire places the on-board RAM in the desired
SK

or

16K

segment

SK, for example, the

of

the selected 65K page. To access

SK

segment can be placed
boundary 0000 (1st SK), 2000 (2nd SK), 4000 (3rd
SK),

...

EOOO

(Sth SK). To access 16K, the 16K
segment can be placed on any 16K boundary
16K),

4000 (2nd 16K),

16K). Figure

2-1

SOOO

(3rd 16K), or

illustrates a step-by-step sequence for

establishing RAM addresses for 16-bit address systems.

is

2-19. 20-BIT ADDRESS SYSTEMS. In 20-bit address

systems, the on-board RAM can reside anywhere within a

As

I-megabyte address space.

RAM

is

first placed in the lower

W6. Jumper W5 then selects one

shown in table 2-7 the

or

upper 524K

of

eight 65K pages within

the upper or lower 524K bytes.

Next, referring to table 2-S, the system can access either
SK

or

16K

of

the on-board RAM. Default jumper W4
position B-A limits the system
position B-G allows access

of

all 16K

to

SK

access; jumper W4
of

on-board RAM.

On-Board

3

4000-7FFF

8000-BFFF

COOO-FFFF

installed.

SK

or

posi~ion

on

any

SI<

0000 (1st

COOOO

(4th

by

ju~per

2-7

Preparation for

Use

iSBC 80/30

Table 2-7. 65K Page System Memory Selection

Low/(High)1

System
Memory

N/A

(Note

2)

0-524K

(525-1048K)

W6:

*B-C
*D-E

W6:

(B-E)
(D-A)

NOTES:

1. Notation in parentheses applies to high (upper
524K) bytes

Systems without 20-bit address capability must

2.
use jumper

* Default Jumper; disconnect if reconfiguration is

re~uired.

N/A

= not applicable.

65K

Page No.

0

W5:

*K-L

0

K-A

W5:

1 10000-1 FFFF

K-B

W5:

2 20000-2FFFF

K-C

W5:

3

K-D

W5:

4

K-E

W5:

5 50000-5FFFF

K-F

W5:

6 60000-6FFFF

K-G

W5:

7

K-H

W5:

of

20-bit system address space.

W5

in position

Address

OOOO-FFFF

OOOOO-OFFFF

(80000-8FFFF)

(90000-9FFFF)

(AOOOO-AFFFF)

30000-3FFFF

(BOOOO-BFFFF)

40000-4FFFF

(COOOO-CFFFF)

(DOOOO-DFFFF)

(EOOOO-EFFFF)

70000-7FFFF

(FOOOO-FFFFF)

*K-L.

Range

1

Table 2-8. 8K/16K Block Selection

Within

65K Page

Finally, one jumper wire places the on-board RAM in the

of

desired 8K or 16K segment
access an 8K segment in

the selected 65K page. To

Page 4

of

the lower 524K, for
example, the 8K segment can be placed on any 8K
boundary
(3rd 8K),

Page 4

in
placed on any 16K boundary

(2nd 16K), 48000 (3rd 16K),

40000

...

of

(l

st 8K), 42000 (2nd 8K),

4EOOO

(8th 8K). To access a 16K segment

the lower 524K, the 16K segment can be

40000

Ost

16K), 44000

or4COOO

(4th 16K). Figure

44000

2-2 illustrates a step-by-step sequence for establishing
RAM addresses for a

20-bit address system.

2-20. PRIORITY INTERRUPTS

Table 2-9 lists the source (from) and destination (to)
interrupt matrix shown in figure 5 -2 sheet 7. For example,
note that the 8259A Programmable Interrupt Controller
(PIC) can handle eight positive-true interrupt requests
and, after resolving any priority contention, outputs an

of

interrupt request to the INTR input

the 8085A micro-

processor.

Study table 2-9 carefully while making reference to figure

5-2 sheet 7 before deciding on a definite priority config-

uration for the
require some explanation: the 8085A

iSBC 80/30. There are two areas that

TRAP and RST 7.5

interrupts.

Default jumper 137-145 grounds the
input to prevent the possibility
generated by noise spikes.

of

Since the TRAP interrupt

TRAP interrupt

false interrupts being

maskable, cannot be disabled by the program, and has the
highest priority, it should be used only to detect a cata­strophic event such

as

a power failure or a bus failure.

of

is

the

not

Address Block Within 65K

8K

or

W4:

W4:

16K

8K

*B-A

16K

B-C

System Access

*Default jumper; disconnect if reconfiguration is desired.

Page (Refer
Jumper

180-172 1st 8K

180-173 2nd 8K
180-174 3rd 8K
180-175 4th 8K
180-176 5th 8K
180-177 6th 8K
180-178 7th 8K
180-179

*180-171 No Access

180-173 1st 16K
180-175 2nd 16K
180-177 3rd 16K
180-179 4th 16K

*180-171

2-8

to

Table 2-7)

8th 8K

No Access

Block

The

RST 7.5 interrupt input

default jumpered to the COUNT OUT output

1.

If

it

is

desired to interrupt the 8085A if the Failsafe

Timer times out, remove jumper 123-138

is

edge-sensitive only and

of

(COUNT OUT)

Counter

and connect jumper 122-138 (BUS TIME OUT). (The
BUS TIME OUT signal

Timer

is

retriggered after timing out.)

is

generated when the Failsafe

NOTE

The 8259A PIC can be programmed to respond

or

to either edge-sensitive

If

rupt requests.

the PIC

level-sensitive inter-

is

programmed to re-

spond to edge-sensitive interrupt requests, the

PIC will respond only to a low-to-high transition

on

anyone

of

the individual IR input lines.

is

iSBC 80/30

65K

BYTE

SYST

W4:

B·C

4TH

3RD

2ND

1ST

16K

16K

16K

16K

16K

1 BO-175

1 BO-173

ACCESS

1 BO-179

1BO-177

Preparation for

COOO

BOOO

4000

0000

Use

COOO

-

BOOO

-

4000

0000

PAGE

-

--

L 16.BIT

EXPLANATION:

CD

Jumper W5 must be

SYS~EM

W5
K·L

0

CD

ADDRESS UNES

in

position K-L.

0

6TH

BK

5TH BK

4TH BK

3RDBK

2ND

BK

1ST

BK

ON·BOARD

BASE

AD

7000

6000

5000
4000

DR

----I

_____

BK

ACCESS

160-176

1BO-175

1BO-174

1BO-173

1

BO-172

ON·BOARD

RAM

UPPER BK

LOWER BK

AOOO

BOOO

6000

4000

2000

0000

...a:.LL..I.~

® Jumper W4 position B-A selects

® Jumper lS0-17S selects 7th

(the only page in a 16-bit address system).

Thus, the lower
of

memory has on-board 808SA addresses

Note that for
Sth

SK

bytes access the upper

accessed by the system; addresses for system use are established by jumpers

611-2

Figure 2-1.

SK

of

on-board memory

SK

access, the 1st, 3rd, 5th, and 7th

Jumper

Configuration for Multibus Access of On-Board RAM (16-Bit Address System)

SK

access.

SK

segment

SK

of

of

65K page 0

is

assigned system addresses

AOOO

thru 5FFF.

SK

bytes access the lower

on-board RAM. With jumper W4 in position B-C, all 16K

L

COOO

SK

ON·BOARD

thru DFFF.

of

on-board RAM. The 2nd, 4th, 6th, and

lS0-173 (1st 16K), lS0-175 (2nd 16K), etc.

ADDRESS

LINES

In

this example, this same

of

on-board RAM is

SK

2-9

Preparation for

SYSTEM

BASE

AD

FOOOO

EOOOO

00000

COOOO

BOOOO

AOOOO

90000

80000

70000

60000

50000

40000

30000

20000

10000

00000

DR

0

Use

1M BYTE SYST

W5:K·H

W5:K·G

W5:

K·F

W5:

K·E

W5:K·D

W5:K·C

W5:K·B

W5:K·A

W5:

K·E

W5:K·D

W5:K·C

W5:K·B

W5:K·A

-

L 20·BIT SYSTEM ADDRESS LINES

PAGE

7

6

5

4

3

2

0

4

3

2

0

UPPER 524K
(EIGHT 65K PAGES)
W6:

B·E,

D·A

LOWER 524K

65K PAGES)

(EIGHT
W6:

B·C,

D·E

0)

W4:B·C

4TH 16K

3RD16K

2ND16K

1ST16K

7TH

8K

6TH

8K

5TH

8K

4TH

8K

3RD8K

2ND

8K

1ST8K

16K

180·179

180·177

180·175

180·173

8K

180·179

180·178

180·177

180·176

180·175

180·174

iSBC 80/30

ACCESS

6COOO

68000

64000

60000

ACCESS

6EOOO

6COOO

6AOOO

68000

66000

60000

ON.BOARD ON·BOARD

BASE

ADDR

.....

__

EXPLANATION:

BOOO

CD

Jumper W6 positions B-C and D-E place memory in

lower 524K

of

system address space.

® Jumper W5 position K-G selects page 6

524K.

® Jumper W4 position B-A selects

@Jumper

Thus, the upper 8K
memory has on-board

Note that for

Bth

IBO-173

selects 2nd

of

BK

access, the

BK

bytes access the upper

on-board memory is assigned system addresses 62000 thru 63FFF. In this example, this same

BOB5A

Ist,3rd,

BK

access

of

BK

segment

addresses

of

AOOO

5th, and 7th

BK

of

on-board RAM. With jumper W4

of

lower

page 6.

page 6.

thru BFFF.

BK

bytes access the lower

AOOO

~-----~F-""~V

9000

8000 .....J

______

T

L16.BIT

BK

of

on-board RAM. The 2nd, 4th,

in

position B-C, all 16K

accessed by the system; addresses for system use are established by the jumpers

(2nd 16K), etc.

611·3

Figure 2·2.

Jumper

Configuration for Multibus Access of On-Board RAl\1 (20-Bit Address System)

~A_M

__

UPPER

8K

LOWER

8K

ON·BOARD

IBO-173

-.-:77777'1o.

.....

ADDRESS

UNES

of

on-board RAM is

(lst

16K),

BK

of

6th~

and

IBO-175

2-10

iSBC 80/30

Table 2-9; Priority Interrupt Jumper Matrix

Preparation for

Use

Source

Multibus

External Via J2-50
External Via J1-50
Power

Fail

logic'

P2-19

Via

Failsafe Timer

PPI

8255A

Port A (Port
Port

8251A USART

8253

PIT
Counter
Counter 1

8259A

8041/8741A

8255A

B (Port

0 Out

PIC

PPI

E8)
E9)

Out

UPI

Interrupt

Request (From)

INTO/

(1)

INT1/

(1)

INT2/

(1)

INT3/

(1)

INT4/

(1)

INT5/

(1)

INT6/

(1)

INT7/

(1)

EXT

INTR1/

EXT

INTRO/

PFI/ (1)(2)

BUS

TIME OUT/

55PAI

(1

55PBI

(1

51TXR
51RXR

8041/8741 EVENT
COUNT OUT

INTR

(6)

41INTR(1)

INTROUT (13)

)(4)
)(4)

(1)

(1)

Signal

(1)
(1)

(1

(3)

)(5)

elK

(1)

Post Device

148 8259A PIC
147
152
151
150
149
146
136

144 8085A

125

134

122

117
118

142
143

141
123

None

124
185

Multibus

CPU

119
120

Interrupt

(7)

IRO

'

IR1
IR2
IR3
IR4
IR5
IR6
IR7

TRAP

RST 7.5
RST 6.5
RST 5.5

(1.1)

INTR

INTO/

INT1/
INT2I
INT3/
INT4/
INT5/

INT6/
INT7/
ADR10/

Request (To)

>

(8)

(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)

:=D---o

Signal

All

level sensitive

or 130
all

edge sensitive

(7)

(9)

(10)
(10)

(12)

121

(14)

Post

133
132
131

129
128
127
126

137
138
139
140

None

181
182
183
184
187

188
189
190
186

NOTES:

(1)

(2)
(3)
(4)

(5)
(6)
(7)
(8)

(9)

(10)
(11)

(12)

(13)
(14)

Signal

is

positive-true at associated jumper post.
Disconnect 137-145 and connect 134-137 (8085A TRAP).
Disconnect 123-138
Used

primarily

Default jumper 123-138 connects signal

Applied directly
May

be

programmed for either edge-sensitive or level-sensitive input;

Default jumper 137-145 disables (grounds) input. TRAP

edge sensitive.

Default jumper 123-138 connects input to COUNT OUT. RST 7.5

RST 6.5 and RST

INTR

is

connected directly
To system via Multibus; requires ground-true signal.
Signal

is

ground-true at associated jumper post.

One two-input OR gate

and

connect 122-138 (8085A RST 7.5); jumper 115-116 must also

in

strobed

I/O

applications.

to

8085A RST 7.5.

to

8085A INTR input.

is

highest priority, non-maskable, and

5.5,

respectively, are third and fourth highest priority. Both inputs are level sensitive.

to

INTR output of 8259A

is

provided

in

interrupt matrix.

PIC.

be

connected. See note (5).

IR

lines are not individually programmable.

is

second highest priority and

is

is

both level and

edge sensitive only.

2-11

Preparation for

Use

iSBC 80/30

2-21. 8251A

PORT

CONFIGURATION

Table 2-10 lists the signals, signal functions, and the
jumpers required (if necessary)
ticular signal to or from the serial

to

input

or

output a par-

I/O port (Intel 8251A

Programmable Communication Interface).

2-22. 8255A

PORT

CONFIGURATION

Table 2··/ 1 lists the jumper configuration for three parallel
I/O ports. Note that each
EA) can be configured in a variety

1

Pin

2
3
4

5

6 RECEIVED DATA

7
8

PROTECTIVE GND
TRANS

TRANSMITTED DATA 8251A RXD in or

SEC REC DATA

REC
REQUEST

- (Note

10

-

12
13
14
16
17
19
21
22
23
25
26

CLEAR TO SEND 8251A RTS out (Note

(Note
DATA SET READY
DATA
GND

REG LINE

RING INDICATOR

-12V

TRANS SIG

+12V

+5V

GND

SEC CLEAR TO SEND

of

the three ports (E8, E9, and

of

ways

to

suit the

Table 2-10. Connector

Sigoal Function

SIG

ElE

TIMING (IN) 8251A TXC

SIG

ElE

TIMING

TO SEND

5)

5)

TERMINAL

ROY

SIG

DET

ElETIMING

(OUT)

J3

~in

Protective Ground

8251A TXD out
8255A STXD

8741A
8251A TXD out or *80-81

8251A RXD in
8251A RXC in (Note
8251A
8251A RTS out to CTS in 67-68

8251A RTS out to CTS in
8251A DTR out
8251A DSR in ­Ground
8255A Carrier Detect
8255A Ring Indicator

-12Vout
Same as 8251A TXC

+12Vout

+5Vout
Ground
8255A STXD

Assignments Vs.

individual requirement. Recommended line drivers and
I/O terminators for user applications are listed

2-1.

2-23. 8041/8741A

PORT

CONFIGURATION

The optional Intel 8041/8741A Universal Peripheral
Interface can be programmed and, hence, configured to
perform serial or parallel

I/O functions. Refer

to

sheet 5 for jumper details. Applications for the 8041/8741

are presented in the

Intel UPI-41 User's Manual, Order

No. 9800504.

in

(Note

ouP or

RS232 out

Jumper

2)

4

Configuration

Jumper

69-70
56-57

*82-83

81-82
76-79, 73-71

76-79,

In

73-74

Jumper

-

*55-56

-

*82-83, *80-81

-

-

-

*80-81, *82-83
*58-59

-

CTS in (Note

2)

5)

80-83

59-60

-

-

5)

-

67-68

-

-

-

-

-

-

3

in

3

in

in

-

-

64-65
76-75, 72-73
63-66
61-62

-

3

in

76-77

-

-

-

-

-

-

-

-

-

in

table

figure 5 -2

Out

NOTES:

1.

All odd-numbered pins

component side of the board with the extractors at the top.

2.

Default jumpers
Input Frequency (Counter

3.

Optional jumper-selected output function for Intel 8255 Programmable Peripheral Interface. Refer to figure 5-2 sheet
Optional jumper-selected output function for 8041/8741 Universal Peripheral Interface. Refer to figure 5-2 sheet

4.
Jumper

5.

* Default jumpers connected at the factory.

2-12

67-68

(1,

3,

5,

...

25) are on component side of the board. Pin 1

*55-56

and

*58-59

2)

in

table 2-4.

connects 8251A RTS output back

connect 8253 BAUD RATE

to

CTS input for those applications without CTS capability.

ClK

is

the right-most pin when viewed from the

to

8251

TXC and RXC inputs, respectively. See Timer

4.

5.

iSBC 80/30

Preparation for

Use

Port

E8

E8

E8

Table 2-11. 8255A

Mode

Driver (0)/

Terminator

(T)

Delete Add

o Input 8226: A1,A2 None

o Output

(latched)

1 Input

(strobed)

8226: A1,A2

8226: A1,A2

T:A3

D:A4

*7-8

*15-16

and J1-18.

*17-18

Port

Jumper

*7-8

4-8

*7-8

*21-22

15-17

Configuration

Configuration

Effect

8226 = input enabled.

8226 = output enabled.

8226 = input enabled.

Connects J1-26 to
STBAI input.

Connects

IBF

Jumpers

A output

Port

None;

E9

input or output.
None;

EA

or output,
Mode

E9

EA

None;

E9

input or output.
Port EA bits perform the

EA

following:

to

• Bits 0,1,2 - Control for

• Bit 3 - Port E8 Interrupt

• Bit 4 - Port E8 Strobe

• Bit 5 - Port E8 Input Buffer

• Bits 6,7 - Port

Rest'rictions

can

be

in

Mode 0 or

can

be

in

Mode

unless Port

1.

None; can
input or output.

None;
or output,
Mode

Port

(55PAI)
matrix.

(STB/)

Full (IBF) output.

output (both must be

same direction).

be

can

be

unless Port

1.

can

be

E9

if

in

to

interrupt jumper

input.

in

Mode 0 or

in

Mode

in

Mode 0 or

Mode

EA

0,

input

E9

is

0,

input

E9

is

1.

input or

in

1,

in

1,

in

1,

E8

1 Output
(latched)

8226: A1,A2
T:A3
D:A4

*7-8

*9-10

and

*15-16

4-8

*13-14

9-15

8226: output enabled.

Connects J1-30 to
ACKAI input.

Connects OBF

to

J1-18.

AI

output

None;

can

E9

be

if

to

E9

input or output.

Port EA bits perform the

EA

following:

• Bits 0,1,2 - Control for
Port

• Bit 3 - Port
(55PAI)

matrix.

• Bits 4,5 - Input or output

(both must be

direction).

• Bit 6 - Port E8 Acknowl­edge (ACK/) input.

• Bit 7 - Port

Buffer Full (OBF/) output.

in

Mode 0 or

in

Mode

1.

E8

Interrupt

interrupt ·jumper

in

same

E8

Output

1,

2-13

Preparation for Use

iSBC 80/30

Table 2-11. 8255A Port Configuration Jumpers (Continued)

Port

EB

E9

Mode

2 B226: A1,A2

(bidi

rectional)

o Input

Driver

(D}I

:rerminator

T:A3
D:A4

T: A5,A6

Jumper

Delete

(T)

*7-8

*17-1B

and to J1-24.

*25-26

*9-10

and

*15-16

None

Add

B-13 Allows ACKAI input

*21-22

17-25

*13-14

9-15

None

Configuration

Effect

control B226 in/out
direction.

Connects
STBAI input.

Connects

Connects
ACKA/

Connects OBFA/ output
to

J1-26

IBFA

J1-30

input.

J1-1B.

to

to • Bit 0 -

output

to

Port

E9
EA

EB
EA

Restrictions

None.
Port

EA

following:

• Bits 1

• Bit 3 - Port

• Bit 4 - Port

• Bit 5 - Port

• Bit 6 - Port

• Bit 7 - Port

None.
None; Port EA can

Mode
Port

bits perform the

Can
for jumper option (see
figure

input or output if
is

in

(55PAI)
matrix.

(STB/) input.

Full (IBF) output.

edge (ACK/) input.

Full (OBF/) output.

0,

EB

only

5-2

zone 4ZC4).

,2

- Can

Mode

O.

EB

to

interrupt jumper

EB

EB

EB

EB

Output Buffer

input or output, if

is also

in

be

used

be

used for

Port

E9

Interrupt

Strobe

Input Buffer

Acknowl-

be

in

Mode

O.

E9

E9

o Output

(latched)

1 Input

(strobed)

D:

A5,A6

T: A3,A5,A6

D:A4

None None

*23-24

*19-20

and

*9-10

10-20

Connects IBFs output
to J1-22.

Connects J
STBsI input.

1-32

to

None.

EB

None;

Port

EA

Mode
Port

None.

EB

Port EA bits perform the

EA

following:

• Bit 0 - Port
(55PBI)
matrix.

• Bit 1 - Port
Buffer Full (IBF) output.

• Bit 2 - Port
(STB/) input.

• Bit 3 ­Mode
or output. Otherwise, bit 3
is

• Bits 4,5 -

Port

• Bits 6,7 - Input or output

(both must
direction).

EA

0,

input or output, if

EB

is also

to

If

0,

bit 3 can

reserved. .

EB

mode.

can

be

in

in

Mode

O.

E9

Interrupt

interrupt jumper

E9

Input

E9

Strobe

Port

EB

is

in

be

input

Dep~nds

be

!

in

on

same

2-14

iSBC

80/30

Preparation for

Use

Port

E9

EA

(upper)

Mode

1 Output
(latched)

o Input

Table 2-11.

Driver

Terminator
T:A3

D:

T:A3

(D)/

A4,AS,A6

8.255A

(T)

Port Configuration Jumpers (Continued)

Jumper
Delete Add Effect Port
*25-26 *23-24

*19-20

and

*9-10

None

10-20

*21-22

*17-1B

*13-14

*9-10

Configuration

Connects OBFs/ output
J1-22.

Connects
ACKs/ input.

Connects bit 4 to J 1-26.

Connects bit
Connects bit 6 to J 1-30.
Connects bit 7 to J 1-32.

J1-32

S to J 1-2B.

to

Restrictions

None.

EB

Port EA bits perform the

EA

following:

• Bit 0 - Port
(SSPBI)
jumper matrix.

• Bit 1 - Port

• Bit 2 - Port
edge (ACKI) input.

• Bit 3 - If Port
Mode
or output. Otherwise, bit 3
is reserved.

• Bits 4,5 - Input
direction).

• Bits 6,7 - Depends on

Port

EB

for all four bits to be available.
Port

E9

for all four bits to

to

Buffer Full (OBF/) output.

0,

bit 3 can

(both must be

Port

EB

mode.

EB

must

E9

must be

E9

Interrupt

interrupt

E9

Output

E9

Acknowl-

EB

or

in

be

in

in

be

is

in

be

input

output

same

Mode 0

Mode 0
available.

EA

(lower)

EA

(upper)

EA

(lower)
*Default

o Input

o Output

(latched)

o Output

(latched)

jumper connected

T:A4

D:

A3

D:A4

at

the factory.

None

None Same

None Same

*2S-26
*23-24
*19-20
*1S-16

Mode 0 Input.

Mode

as

as

0 Input.

2-24. MUL TIBUS CONFIGURATION

For systems applications, the iSBC 80/30

installation in a standard Intel

Backplane and Cardcage. (Refer

2.) Alternatively, the

iSBC 80/30 can be interfaced to a

iSBC 604/614 Modular

to

user-designed system backplane by means

to

table 2

-1

connector. (Refer

characteristics and methods

item 3.) Multibus signal

of

implementing a serial

parallel priority resolution scheme for resolving bus

contention in a mUltiple bus master system are described

in the following paragraphs.

is

designed for

table 2-1 items 1 and

of

an 86-pin

or

..

Always tum off the system power supply before

or

installing the board in

removing the board

Connects bit 0 to J 1-24.
Connects bit 1 to J 1-22.
Connects bit 2 to J1-20.

Connects bit 3 to J 1-1B.

for Port EA (upper)

for Port EA (lower)

E9

as

must be

must be

EB

for all four bits to be available.

Port

E9

for all four bits to be available.

Same

EAB

Mode 0 Input.
Same as for Port EA {lower}

E9

Mode 0 Input.

in

in

for Port EA (upper)

Port

EB

from the backplane. Failure to observe this pre-

to'

caution can cause damage

the board.

2-25. SIGNAL CHARACTERISTICS

As

shown in figure 1-1, connector

80/30

to

the Multibus. Connector

listed

in

table 2 -12 and descriptions'

are provided in table 2-13.

dc

The

characteristics

of

theiSBC

signals are provided in table 2-14. The ac
istics of the iSBC 80/30 when operating in the master
mode and slave mode are provided in tables 2-15 and
2-16, respectively. Bus exchange timing diagrams are
provided in figures 2-3 and 2-4.

PI

interfaces the iSBC

PI

pin assignments are

of

the signal functions

80/30 bus interface

Mode 0

Mode 0

chara<;ter-

2-15

Preparation for

Use

iSBC 80/30

Pin*

1
2
3

4

5
6
7
8

9
10
11
12
13
14
15
16

17

18
19
20
21
22
23
24
25
26

27

28
29

30
31

32

33
34
35
36
37

38
39

40

41
42

43

Signal

GND

GND

+5V
+5V
+5V
+5V
+12V
+12V

-5V

-5V
GND
GND
BCLKI
INIT/
BPRN/
BPRO/
BUSY/
BREQ/
MRDC/
MWTC/
10RC/
10WC/
XACKI
INH1/

ADR10/
CBRQ/
ADR11/
CCLKI
ADR12/

ADR13/

INT6/
INT7/
INT4/
INT5/

INT2/
INT3/
INTO/
INT1/

ADRE/

Table 2-12. Multibus Connector

Function

Ground

}

,

Power input

>

J 53 ADR4/

Ground

}

Clock

Bus
System Initialize
Bus Priority
Bus Priority Out
Bus Busy
Bus Request
Memory Read Command
Memory Write Command
I/O

Read Command 64

I/O

Write Command 65
Transfer Acknowledge
Inhibit

Extended Address bus
Common Bus Request 72
Extended Address bus
Constant
Extended Address bus 75 GND

Extended Address bus
Interrupt
Interrupt
Interrupt
Interrupt

Interrupt

Interrupt

Interrupt request on level 0

Interrupt

In

RAM

Clock

request on level 6 78
request on level 7
request on level 4

request on level 5
request on level 2

request on level 3

request on level 1 85 GND

\

PI

Pin Assignments

Pin*

44

46 ADRD/
47

48
49
50 ADR9/
51
52

54 ADR5/
55 ADR2I
56 ADR3/
57
58 ADR1/
59
60
61
62
63

66
67 DAT6/
68 DAT7/
69 DAT4/

70

71

73
74

76 GND
77

79

80
81

82
83
84

86 GND

Signal

ADRF/
ADRC/ 45

ADRN

ADRB/

ADR8/

ADR6/
ADR7/

ADRO/

DAT5/
DAT2I

DAT3/
DATO/
DAT1/

+12V

-12V
+5V

+5V

+5V

+5V

Function

> Address bus

J

,

> Data Bus

J

Ground

I

,

>'

Power input

J

Ground

I

'::AII

odd-numbered pins

component side of the board with the extractors at the top.

2-16

(1,

3, 5

...

85)

are on component side of the board. Pin 1 is the left-most pin when viewed from the

All unassigned pins are reserved.

iSBC 80/30

Table 2-13. Multibus Signal Functions

Preparation for

Use

Signal

ADRO/-ADRF/
ADR10/-ADR13/

BClK!

BPRN/

BPRO/

BREQ/

BUSY/

CBRQ/

CClK!

Functional Description

Address. These 20 lines transmit the address of the memory location or I/O port to

ADRF/ is the most-significant bit except where
ADR13/ are transmitted

In

this case, ADR13/

Bus Clock. Used

iSBC 80/30,

Bus Priority

use of the bus. BPRN/ is synchronized with

Bus Priority

BPRN/ input of the bus master with the next

Bus Request.

requires

Bus Busy. Indicates that the bus

of the bus. BUSY/ is synchronized with

Common Bus Request. Indicates that a bus master wishes control of the bus but does not presently

have control. As soon as control of the bus
CBROI

Constant Clock. Provides a clock signal of constant frequency for use by other system modules.

When generated by the iSBC 80/30,
35-65 percent duty

to

BClK!

In.

Indicates to a particular bus master that no higher priority bus master

Out.

In

In

parallel priority resolution schemes, BREQ/ indicates that a particular bus master

control of the bus 'for one

signal.

only by those bus masters capable of addressing beyond 65K of memory.

is

the most-significant bit.

synchronize the bus contention logic on all bus masters. When generated by the

has a period

serial (daisy chain) priority resolution schemes, BPRO/ must be connected to the

cycle.

of

108 nanoseconds (9.22 MHz) with a 35-65 percent duty cycle.

or

more data transfers. BREQ/

is

in

use and prevents all other bus masters from gaining control

CClK!

ADR10/ through ADR13/ are used. ADR10/ through

BelK!.

lower bus priority.

is

synchronized with

BClK!.

is

obtained, the requesting bus controller raises the

has a period of 108 nanoseconds (9.22 MHz) with a

be

accessed.

is

requesting

BClK!.

DATO/-DAT7/

INH1/

INIT/

INTO/-INT7/

10RC/

10WC/

MRDC/

MWTC/

XACK!

Data. These eight bidirectional data lines transmit and receive data to and from the addressed memory

location or I/O port. DAT7/

Inhibit Ram. Prevents system access to on-board RAM;

RAM for certain applications. This

Initialization. Resets the entire system

Interrupt. These eight

highest priority;

I/O Read Command. Indicates that the address of

that the output of that port is

I/O

Write Command. Indicates that the address of

that the contents on the

Memory Read Command.

lines and that the contents of that location are to

Memory Write Command. Indicates that the address of a memory location

lines and that the contents on the Multibus data lines are to be written into that location.

Transfer Acknowledge. Indicates that the addressed memory location has completed the specified

or

write operation. That is, data has been placed onto or accepted from the Multibus data lines.

read

INT7/ has the lowest priority.

is

the most-significant bit.

signal has no effect on on-board access of on-board RAM.

to

a known internal state.

lines are for inputting interrupt requests to the iSBC 80/30.

to

be

read (placed) onto the Multibus data lines.

Multibus data lines are to be accepted by the addressed port.

Indicates that the address

allows system addresses to overlay on-board

an

I/O port is on the Multibus address lines and

an

I/O port

is

on the Multibus address lines and

of

a memory location is on the Multibus address

be

read (placed) on the Multibus data lines.

is

on the Multibus address

INTO/

has the

2-17