Intel 82543GC User Manual

82543GC Gigabit Ethernet Controller

Specification Update

June 18, 2004

Revision 2.1

The 82543GC Gigabit Ethernet Controller may contain design defects or errors kno wn as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.

82543GC Gigabit Ethernet Controller Specification Update

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future

definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future change s to them. The 82543GC Gigabit Ethernet Controller

specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-

4725 or by visiting Intel’s web site at http://www.Intel.com.

may contain design defects or errors known as errata which may cause the product to deviate from published

82543GC Gigabit Ethernet Controller Specification Update

CONTENTS

CONTENTS .........................................................................................................................................................3

REVISION HISTORY...........................................................................................................................................5

PREFACE............................................................................................................................................................7

NOMENCLATURE ..............................................................................................................................................7

COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE..............................................................7

GENERAL INFORMATION.................................................................................................................................8

82543GC Component Marking Information..................................................................................................8

Summary Table of Changes..............................................................................................................................9

Codes Used in Summary TableS .................................................................................................................9

SPECIFICATION CHANGES ............................................................................................................................11

1. GMII Setup and Hold Times..............................................................................................................11

ERRATA............................................................................................................................................................11

1. MDI Control Register Returns Incorrect Values ................................................................................11

2. Descriptor Queue Maximum Size Limitation .....................................................................................11

3. Late Collision Statistics May Be Incorrect .........................................................................................11

4. Some Registers Cannot Be Accessed During Reset ........................................................................12

5. DAC Accesses May Be Interpreted Incorrectly .................................................................................12

6. Flash Memory Interface Functions Incorrectly in 64-Bit Address Space...........................................12

7. Excessive Errors in 100Mb Half-Duplex Mode..................................................................................12

8. 48 Bit Preambles Sent in 10Mb and 100Mb Operation .....................................................................13

9. CRS Detection Takes Too Long in MII Half-Duplex Mode ................................................................13

10. DMA Early Receive Function Does Not Work ...................................................................................13

11. ILOS Bit Copied Incorrectly from EEPROM to Speed Bits................................................................13

12. Gigabit Half-Duplex Mode Operates Incorrectly................................................................................13

13. Zero-Byte PCI Bus Writes .................................................................................................................14

14. TCP Segmentation Feature Operates Incorrectly .............................................................................14

15. Incorrect Checksum Calculation and Indication ...............................................................................14

16. Transmitter Affected by Discarding Packets......................................................................................14

17. Flash Memory Address Conflicts.......................................................................................................15

18. Packet Buffer Memory Address Conflicts..........................................................................................15

19. Transmit Packet Corruption of Small Packets...................................................................................15

20. Receive Packet Buffer Corruption When Nearly Full.........................................................................15

21. Receive Packet Loss in 100Mb Half-Duplex Operation.....................................................................16

22. TNCRS Statistic Register Has Live Count in Full-Duplex Mode........................................................16

23. Receive IP Checksum Offload Disabled............................................................................................16

24. EEPROM Initializes Software Defined Pins Incorrectly.....................................................................16

25. Continuous XOFFs Transmitted When Receive Buffer Is Full ..........................................................17

26. Default Speed Selection May Depend on EEPROM Presence.........................................................17

82543GC Gigabit Ethernet Controller Specification Update

27. Link Status Change Interrupt Only Occurs If Link is Up ....................................................................17

28. Early Transmit Feature Does Not Operate Correctly.........................................................................17

29. TDO Output Not Floated When JTAG TAP Controller Inactive.........................................................18

30. Initialization Ignores Incorrect EEPROM Signature...........................................................................18

31. Internal Loopback Difficulties.............................................................................................................18

32. Collision Pin Not Ignored in TBI Mode...............................................................................................18

33. Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers..............................19

34. Illegal Oversize Packets Overflow Receive FIFO.............................................................................. 19

35. Transmit Descriptor Writeback Problems with Non-Zero WTHRESH...............................................19

36. Bus Initialization with Some Chipsets................................................................................................20

37. Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups...........................20

38. Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000............................................20

SPECIFICATION CLARIFICATIONS................................................................................................................21

1. 0-70C Ambient Temperature Range .................................................................................................21

2. Receiver Enabling and Disabling.......................................................................................................21

DOCUMENTATION CHANGES........................................................................................................................21

1. TX/RX Descriptor Register Addresses ..............................................................................................21

2. Auto Speed Detect Function Requires CTRL.SLU Bit to Be Set.......................................................22

3. Values Programmed to Some Registers While in Reset Do Not Persist...........................................22

4. JTAG Port Operation.........................................................................................................................22

5. Register Summary Uses Improper Page Reference Format.............................................................23

6. Change O_EN_CDET Output to NO_CONNECT .............................................................................23

7. Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T ......................23

8. Remove Transmit Report Status Sent Function................................................................................23

9. Remove Transmit DMA Pre-fetching and Preemption Functions......................................................23

10. Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (TBT).....................................24

11. Remove Adaptive IFS Throttle Function (AIT)...................................................................................24

82543GC Gigabit Ethernet Controller Specification Update

REVISION HISTORY

82543GC Gigabit Ethernet Controller Specification Update

Date of Revision Revision Description

June 18, 2004 2.1 Initial Public Release

82543GC Gigabit Ethernet Controller Specification Update

Note: This page is intentionally left blank.

82543GC Gigabit Ethernet Controller Specification Update

PREFACE

This document is an update to published specifications. There are two current specification documents:

• 82543GC Gigabit Ethernet Controller Datasheet, Intel Corporation.

• OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual, Intel Corporation.

This document is intended for hardware system manufactures and software developers of applications, operating systems or tools. It contains Specification Changes, Errata, Specification Clarifications, and Documentation Changes.

The changes/errata/clarifications described in this document will be incorporated into the next release of 82543GC Gigabit Ethernet Controller Data Sheet, the 82543GC Gigabit Ethernet Controller Developer’s Manual.

NOMENCLATURE

Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next

release of the specifications. Errata are design defects or errors. Errata may cause 82543GC device behavior to deviate from published specifications. Hardware

and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications.

Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications.

COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE

82543GC steppings can be identified by the following register contents:

82543GC Stepping Vendor ID Device ID Revision Number

A0 8086h 1001h 00h A1 8086h 1001h 01h A2 8086h 1001h 02h

The device also provides an identification number through the Test Access Port.

82543GC Gigabit Ethernet Controller Specification Update

GENERAL INFORMATION

This section covers the 82543GC device.

82543GC COMPONENT MARKING INFORMATION

Stepping QDF

Number

A0 Q415 S L3N8 FW82543GC A1 Q416 S L3N9 FW82543GC A2 Q417 N/A FW82543GC or

N/A N/A TL82543GC

S- Spec Number

Top Marking Notes

TL82543GC

The legend for the manufacturing code is as follows:

YY = Assembly input year WW = Assembly workweek XXnnn = Complete lot traceability code (use for issue reporting) XX = Mask/assembly spec nnn = Lot history code

TL82543GC

M C

'00 JAPAN

YWWXXnnn

Engineering Samples. May be marked with either QDF number or S-spec number. Engineering Samples. May be marked with either QDF number or S-spec number. Engineering Samples. May be marked two ways: with the QDF number and a top mark FW82543GC; or without any QDF or S-spec number, and a top mark TL82543GC. Production Devices. Marked without QDF or S-spec numbers and bear a top mark TL82543GC.

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