Voltage Regulator Module
(VRM) and Enterprise Voltage
Regulator-Down (EVRD) 11.0
Design Guidelines
April 2008
Reference Number: 315889-002
Notice: This document contains information on products in the design phase of development. The information here is subject to change without
notice. Do not finalize a design with this information.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Dual-Core Intel Xeon processor 7000 sequence, the Quad-Core Intel Xeon processor 5300 Series, Dunnington, Tigerton, DualCore Intel® Xeon® 7100 series, and the Intel 5000 Series Chipsets and Intel E8500 chipsets, and the Truland and Caneland
platforms may contain design defects or errors known as errata, which may cause the product to deviate from published
specifications. Current characterized errata are available upon request.
The code names “Clovertown,” “Wolfdale,” “Stoakley,” “Tigerton,” “Caneland”, “Dunnington”, “Aliceton,” ”Paxville MP”, “Truland”, and
“Harpertown” presented in this document are only for use by Intel to identify products, technologies, or services in development,
that have not been made commercially available to the public, i.e., announced, launched or shipped. They are not “commercial”
names for products or services and are not intended to function as trademarks.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained
The requirements in this document will focus primarily on the Enterprise processors
based on Dual-Core Intel
®
Xeon® Processor-based Server and Quad-Core Intel®
Xeon® Processor-based Server/Workstation platforms. Some requirements will vary
according to the needs of different computer systems and processors. The intent of this
document is to define the electrical, thermal and mechanical design specifications for
VRM/EVRD 11.0.
VRM – The voltage regulator module (VRM) designation in this document refers to a
voltage regulator that is plugged into a baseboard via a connector or soldered in with
signal and power leads, where the baseboard is designed to support more than one
processor. VRM output requirements in this document are intended to match the needs
of a set of microprocessors.
EVRD – The enterprise voltage regulator down (EVRD) designation in this document
refers to a voltage regulator that is permanently embedded on a baseboard. The EVRD
output requirements in this document are intended to match the needs of a set of
microprocessors. EVRD designs are only required to meet the specifications of a
specific baseboard and thus must meet the specifications of all the processors
supported by that baseboard.
‘1’ – In this document, refers to a high voltage level (V
‘0’ – In this document, refers to a low voltage level (V
and VIH).
OH
and VIL).
OL
‘X’ – In this document, refers to a high or low voltage level (Don’t Care).
‘#’ – Symbol after a signal name in this document, refers to an active low signal,
indicating that a signal is in the asserted state when driven to a low level.
The specifications in the respective processors’ Electrical, Mechanical, and Thermal Specifications (EMTS) documents always take precedence over the data provided in
this document.
VRM/EVRD 11.0 incorporates functional changes from prior VRM and EVRD design
guidelines:
315889-0029
• New power-on sequence
• Extended VR 10.x VID table with a 7th bit for 6.25 mV resolution and 0.83125 V to
1.6 V range, only 12.5 mV resolution will be used in Dual-Core Intel Xeon
Processor-Based Platform and Intel E8500 platforms.
• Support for a separate additional VR 11.0 VID table with a 8-bit table and 6.25 mV
resolution with a 31.25 mV to 1.6 V VID range, only 12.5 mV resolution will be
used in Dual-Core Intel Xeon Processor-Based Servers and Intel E8500 platforms
with a VID setpoint range of 0.850 V to 1.6 V.
• Tighter DC load line tolerance from ±20 mV to ±15 mV
Table 1-2.Guideline Categories
REQUIRED:
EXPECTED:
PROPOSED:
An essential feature of the design that must be supported to ensure correct processor and
VRM/EVRD functionality.
A feature to ensure correct VRM/EVRD and processor functionality that can be supported
using an alternate solution. The feature is necessary for consistency among system and
power designs and is traditionally modified only for custom configurations. The feature may
be modified or expanded by system OEMs, if the intended functionality is fully supported.
A feature that adds optional functionality to the VRM/EVRD and therefore is included as a
design target. May be specified or expanded by a system OEMs.
Applications
Guideline Categories
§
10315889-002
Output Voltage Requirements
2Output Voltage Requirements
2.1Voltage and Current - REQUIRED
There will be independent selectable voltage identification (VID) codes for the core
voltage regulator. The VID code is provided by the processor to the VRM/EVRDs, which
will determine a reference output voltage, as described in Section 3.2. As previously
mentioned, the VR 11.0 controller will support two VID tables:
1. An extended 7-bit VR 10.x table, ranging from 0.83125 V to 1.6 V
2. An 8-bit VR11.0 linear table ranging from 0.03125 V to 1.6 V (usable range 0.5 V-
1.6 V).
For Dual-Core Intel Xeon Processor 7000/7100/7200/5000/5100/5200 Series -based
servers and Quad-Core Intel Xeon Processor 7300/5300/5400 Series -based servers/
workstations, the VID bits utilization will be as shown in the table below. Section 2.2
and Section 2.3 specify deviations from the VID reference voltage.
Table 2-1.Processor VID signal implementation
VID Signals used
Processor Supported
Dual-Core Intel® Xeon®
Processor 7000/7100 Series
processor
Quad-Core Intel(R) Xeon(R)
Processor 7300 Series &
Dual-Core Intel(R) Xeon(R)
Processor 7200 Series
processors
by Processor and
routed to VR with
Pull-Up resistors
VID[4:0,5]
(VID4=MSB
VID5=LSB)
VID[4:0,5]
(VID4=MSB
VID5=LSB)
VID[6:1]
VID[6:1]
Notes
VR10.2 mode; VID6 is not driven on the processor
package (socket 604), but should be routed on the VR
side with a pullup resistor; VR’s VID7 to be pulled
Low.
VR10.2 mode; Land AM5 (equivalent to platform
signal VID6) is not driven on the processor package,
but still routed to VID6 on VR side with a pullup
resistor; VR’s VID7 to be pulled Low.
VR11.0 mode; Land AM2 (equivalent to platform
signal VID0) is connected to VSS on the processor
package, and routed to VID0 on VR side with a pullup
resistor; VR’s VID7 to be pulled Low.
VR11.0 mode; VID0 is not driven on the processor
package (socket 604P), but should be routed on the
VR side and pulled Low; VR’s VID7 to be pulled Low.
The load line tolerance in Section 2.2 shows the relationship between Vcc and Icc at the
die of the processor.
The VRM/EVRD 11.0 is required to support the following:
• A maximum continuous load current (I
CCTDC) of 130 A.
• A maximum load current (ICCMAX) of 150 A peak.
• A maximum load current step (I
• A maximum current slew rate (dI
CCSTEP), within a 1 µs period, of 100 A.
CC/dt) of 1200 A/µs at the lands of the processor.
315889-00211
Output Voltage Requirements
The continuous load current (ICCTDC) can also be referred to as the Thermal Design
Current (TDC). It is the sustained DC equivalent current that the processor is capable
of drawing indefinitely and defines the current that is used for the voltage regulator
temperature assessment. At TDC, switching FETs may reach maximum allowed
temperatures and may heat the baseboard layers and neighboring components. The
envelope of the system operating conditions, establishes actual component and
baseboard temperatures. This includes voltage regulator layout, processor fan
selection, ambient temperature, chassis configuration, etc. To avoid heat related
failures, baseboards should be validated for thermal compliance under the envelope of
the system’s operating conditions. It is proposed that voltage regulator thermal
protection be implemented for all designs (Section 6.2).
The maximum load current (I
CCMAX) represents the maximum peak current that the
processor is capable of drawing. It is the maximum current the VRM/EVRD must be
electrically designed to support without tripping any protection circuitry.
The maximum step load current (IccStep) is the max dynamic step load that the
processor is expected to impose on its Vcc power rail within the Iccmin and Iccmax
range, where the Iccmin is the processor’s min load, constituted by its leakage current.
The amount of time required by the VR to supply current to the processor is dependent
on the processor’s operational activity. As previously mentioned, the processor is
capable of drawing IccTDC indefinitely; therefore, the VR must be able to supply
CCTDC) indefinitely. Refer to Figure 2-1 for the time durations required by the VR to
(I
supply current for various processor loads.
It is expected that the maximum load current (I
10 ms. Further, it is expected that the load current averaged over a period of
100 seconds or greater, will be equal to or less than the thermal design current
CCTDC).
(I
Figure 2-1. VRM/EVRD 11.0 Load Current vs. Time
Icc MAX
CCMAX) can be drawn for periods up to
Sustained Current (A)
Icc TDC
0.010.101.0010.00100.01000.0
Time Duration (s)
Table 2-2 shows the ICC guidelines for any flexible motherboard (FMB) frequencies
supported by the VRM/EVRD 11.0 in Tabl e 1-1 . For designers who choose to design
their VR thermal solution to the I
regulator thermal protection circuitry be implemented (see Section 6.2).
12315889-002
CCTDC current, it is recommended that voltage
Output Voltage Requirements
Table 2-2.Icc Guidelines
Dual-Core Intel
Dual-Core Intel
Dual-Core Intel
Dual-Core Intel
Dual-Core Intel
Dual-Core Intel
Dual-Core Intel
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Dual-Core Intel
Dual-Core Intel
Dual-Core Intel
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Dual-Core Intel
Quad-Core Intel
®
Xeon® processor 7000 sequence FMB 1301501001, 2
®
Xeon® 7100 series processor FMB 1151351001, 2
®
Xeon® Processor 5000 Series FMB 130150901, 2
®
Xeon® Processor 5000 Series MV/667 FMB 100115761, 2
®
Xeon® Processor X5160 Series Performance FMB 7090401, 2
®
Xeon® Processor E5100 Series FMB 6575301, 2
®
Xeon® Processor L5148/5138/5128 Series FMB 3545251, 2
®
Xeon® processor X5300 Series Performance FMB 110125701, 2
®
Xeon® processor E5300 Series FMB 7090501, 2
®
Xeon® processor L5300 Series-LV FMB 5060351, 2
®
Xeon® Processor X5200 Series 7090371, 2
®
Xeon® Processor E5200 (6075211, 2
®
Xeon® Processor L5200 Series 3850361, 2
®
Xeon® Processor X5482 130150671, 2
®
Xeon® Processor X5400 Series 110125681, 2
®
Xeon® Processor E5400 Series 80102651, 2
®
Xeon® Processor L5400 Series 5060601, 2
®
Xeon® Processor X7300 Series 110130781, 2
®
Xeon® Processor E7300 Series 7590721, 2
®
Xeon® Processor 7200 Series 7590721, 2
®
Xeon® Processor L7300 Series 5060541, 2
Processor
I
CCTDC
(A)
CCMAX
I
(A)
CCSTEP
I
(A)
Notes
Notes:
1.These values are either pre-silicon or the latest known values and are subject to change. See the respective
Processor’s Electrical, Mechanical, and Thermal Specifications (EMTS) for the latest IccTDC and IccMAX
specifications.
2.FMB = Planned Flexible Motherboard guideline for processor end-of-life.
3.Voltage regulator thermal protection circuitry should not trip for load currents greater than ICCTDC
4.For platforms designed to support several processors, the highest current value should be used.
5.For platforms designed to support a single specific processor, only use that processor’s current
requirements.
2.2Load Line Definitions - REQUIRED
To ensure processor reliability and performance, platform DC and AC transient voltage
regulation must be contained within the V
boundaries, except for short burst transients above the V
Section 2.4. Die load line compliance must be guaranteed across 3-sigma component
manufacturing tolerances, thermal variation and age degradation. The following load
line contains static and transient voltage regulation data as well as maximum and
minimum voltage levels. It is required that the regulator’s positive and negative
differential remote sense pins be connected to both the V
CC_DIE_SENSE2 and VSS_DIE_SENSE2 pin pairs of the processor socket, see Figure 3-1.
V
The prefix V
CC is designated for the positive remote sense signal and the VSS prefix for
the negative remote sense signal.
315889-00213
CCMIN and the VCCMAX die load line
CCMAX as specified in
CC_DIE_SENSE, VSS_DIE_SENSE,
The upper and lower load lines represent the allowable range of voltages that must be
presented to the processor. The voltage must always stay within these boundaries for
proper operation of the processor. Operating above the V
in higher processor operating temperature, which may result in damage or a reduced
processor lifespan. Processor temperature rise from higher functional voltages may
lead to dynamic operation to low power states, which directly reduces processor
performance. Operating below the V
CCMIN load line limit will result in minimum voltage
violations, which will result in reduced processor performance, system lock up, “blue
screens” or data corruption.
For load line validation information, please refer to the LGA771-V2 Voltage Test Tool User’s Guide.
Figure 2-2 and Figure 2-2 shows the load line voltage offsets and current levels based
on the VID specifications for the core regulator.
The encoding in Table 2-2 for the load lines is valid for the range of load current from
0 A to 150 A. The VID_Select, load line 1 (LL1), and load line 0 (LL0) control signals
from Section 3.4, form a 3-bit load line selection and will be used to configure the VRM/
EVRD to supply the proper load lines for the platforms in Table 1-1 . Refer to Figure 6-1
for additional encoding requirements for VRMs. For implementation of VID_Select, LL0,
and LL1 on the baseboard refer to the appropriate platform design guidelines. The
VID_Select control signal will select the appropriate VR10 or VR11 table and remap the
external VID [6:0] pins to the appropriate DAC input. This line will be pulled up
externally to the VTT rail (1.1 V/1.2 V ± 5%) via a recommended 4.7 kΩ resistor on the
baseboard and will be programmed by the processor package. The processor does not
support 5 V or 12 V levels and these should not be used. The VID_Select signal should
be logic low or tied to ground for extended VR10 table selection. A logic high will
.
indicate a VR11 table selection. The VID_Select will not toggle during normal operation.
Table 2-3.VID_Select, LL1, LL0 Codes (Sheet 1 of 2)
Output Voltage Requirements
CCMAX load line limit will result
VID
Table
VR10.2
VR11.0
VID
Table
VID_
Select
LL1LL0Load Line / Processors
000
001
010
011
100
101
110
111
VID_
Select
LL1LL0V
1.25 mΩ; Reserved
1.25 mΩ; Dual-Core Intel® Xeon® Processor 5000 Series / MV
processor LGA771 die Load Line
1.25 mΩ; Dual-Core Intel® Xeon® processor 7000 series / Dual-Core
Intel® Xeon® 7100 series processor mPGA604 die Load Line
1.25 mΩ; Quad-Core Intel Xeon processor 5300 Series
CC Tolerance / Die Load LineUnitsNotes
14315889-002
Output Voltage Requirements
Table 2-3.VID_Select, LL1, LL0 Codes (Sheet 2 of 2)
VID
Table
Notes:
1.The Vcc values are the expected voltage measured at the processor die.
2.The Dual-Core Intel® Xeon® 7100 series / Dual-Core Intel® Xeon® processor 7000 sequence entry is
3.For VRM 11.0 mode, VRM_Pres# and VR_ID# should be held LOW for all combinations as described in
VID_
Select
VR10.2 mode
VR11.0 mode
required for backward compatibility for VR ‘modules’ only using the EVRD/VRM 10.2, but the VRM11.0
should be backward compatible with VRM10.2 platforms, as modular VRs can be transferred from one
platform to another.
The voltage ranges shown in Section 2.2 include the following tolerances:
• Initial DC output voltage set-point error.
• Output ripple and noise.
• No-load offset centering error.
• Current sensing and droop errors.
• Component aging affect.
• Full ambient temperature range and warm up.
• Dynamic output changes from minimum-to-maximum and maximum-to-minimum
load should be measured at the point of regulation. When measuring the response
of the die voltage to dynamic loads, use the VCC_DIE_SENSE and VSS_DIE_SENSE
or VCC_DIE_SENSE2 and VSS_DIE_SENSE2 pins on the processor socket with an
oscilloscope set to a DC to 20-100 MHz bandwidth limit and with probes that are
1.5 pF maximum and 1 MW minimum impedance.
• Variations of the input voltage.
315889-00215
Output Voltage Requirements
2.4Processor VCC Overshoot - REQUIRED
The VRM/EVRD 11.0 is permitted short transient overshoot events where Vcc exceeds
the VID voltage when transitioning from a high-to-low current load condition
(Figure 2-2). This overshoot cannot exceed VID + VOS_MAX. The overshoot duration,
which is the time that the overshoot can remain above VID, cannot exceed TOS_MAX.
These specifications apply to the processor die voltage as measured across the remote
sense points and should be taken with the oscilloscope bandwidth setting limited to
20 MHz or 100 MHz, depending what is supported by your particular scope (with
20 MHz preference).
• VOS_MAX = Maximum overshoot voltage above VID = 50 mV
• TOS_MAX = Maximum overshoot time duration above VID = 25 µs
Figure 2-2. Processor Vcc Overshoot Example Waveform
V
VID + 0.050
OS
Voltage [V]
VID - 0.000
T
OS
0510152025
Time [us]
TOS: Overshoot time above VID
: Overshoot voltage above VID
V
OS
2.5Impedance vs. Frequency - EXPECTED
Vcc power delivery designs can be susceptible to resonance phenomena capable of
creating droop amplitudes that violate the load line specification. This is due to the
frequency varied PCB, output decoupling and socket impedances from the power plane
layout structures. Furthermore, these resonances may not be detected through
standard time domain validation and require engineering analysis to identify and
resolve.
Impedance vs. Frequency, Z(f) performance simulations of the power delivery network
is a strongly recommended method to identify and resolve these impedances, in
addition to meeting the time domain load line in Section 2.2 and Section 2.3. The
decoupling selection needs to be analyzed to ensure that the impedance of the
decoupling is below the load line target up to the F
in Figure 2-3. Frequency domain load line and overshoot compliance is expected across
the 0 Hz to FBREAK bandwidth. The power delivery frequency response is largely
BREAK (2 MHz) frequency as defined
16315889-002
Output Voltage Requirements
dependent upon the selection of the bulk capacitors, ceramic capacitors, power plane
routing and the tuning of the PWM controller’s feedback network. This analysis can be
done with LGA771-V2 VTT tool impedance testing or through power delivery simulation
if the designer can extract the parasitic resistance and inductance of the power planes
on the motherboard along with good models for the decoupling capacitors.
Measured power delivery impedance should be within the tolerance band shown in
Figure 2-3. The tolerance band is defined for the VTT impedance measurement only.
For load line compliance, time domain validation is required and the VR tolerance band
must be met at all times. Above 500 kHz, the minimum impedance tolerance is not
defined and is determined by the MLCC capacitors required to get the ESL low enough
to meet the load line impedance target of the F
tolerance drops to the load line target impedance. Any resonance point that is above
the ZMAX line needs to be carefully evaluated with the time domain method by applying
transient loads at that frequency and looking for V
the impedance profile up to FBREAK is important to ensure the package level decoupling
properly matches the motherboard impedance. After FBREAK, the impedance
measurement is permitted to rise at an inductive slope. The motherboard VR designer
does not need to design for frequencies over F
package decoupling takes over in the region above FBREAK.
Each of these design elements should be fully evaluated to create a cost optimized
solution, capable of satisfying the processor requirements. Experimental procedures for
measuring the Z(f) profile will be included (shortly) in the next revision of the
EVRD_VRM11_0_LL_dVID LGA771_775-V2 VTT Tester-UG.pdf Test Methodology User’s Guide using the VTT. Additional background information regarding the theory of
operation is provided in Appendix A.
BREAK frequency. At 700 kHz, the ZMAX
MAX or VMIN violations. Maintaining
BREAK as the Intel Microprocessor
Figure 2-3. Power Distribution Impedance vs. Frequency
Zone 1
PWM Droop control
& compensation BW
Z
LL Max
Z target = Z
Z
LL
LL Min
VR BW
500 kHz
Notes:
1.Zone 1 is defined by the VR closed loop compensation bandwidth (VR BW) of the voltage regulator.
Typically 30-40 kHz for a 300 kHz voltage regulator design
2.Zones 2 & 3 are defined by the output filter capacitors and interconnect parasitic resistance and
inductance. The tolerance is relaxed over 500 kHz allowing the VR designer freedom to select output filter
capacitors. The goal is to keep Z(f) below Z
bulk cap values, type and quantity of MLCC capacitors. The ideal impedance would be between Z
Z
LLMin, but this may not be achieved with standard decoupling capacitors.
LL up to FBREAK (2 MHz) and as flat as practical, by selection of
Zone 2
Output Filter
Bulk & MLCC
700 kHz
F
Zone 3
Inductive effects
MLCC ESL +
Socket
Hz
break
LL and
315889-00217
Loading...
+ 39 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.