Intel 31244 PCI-X User Manual
Intel® 31244 PCI-X to Serial ATA
Controller
Design Guide
April 2004
Order Number: 273651-003
Intel® 31244 PCI-X to Serial ATA Controller
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS
AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS
OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel
published specifications. Current characterized errata are available on request.
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Copyright © 2004, Intel Corporation
31244 PCI-X to Serial ATA Controller may contain design defects or errors known as errata which may cause the product to deviate from
2 Design Guide
Intel® 31244 PCI-X to Serial ATA Controller
Contents
Contents
1 About This Document .................................... .. ..... .. ..... ....... ..... .. ..... .. ..... ....... ..... .. ..... .. ..... ..... ...........9
1.1 Reference Documentatio n........ ............... .............. ............................ ............................. ......9
1.2 Terminolog y and Def in i tions ...................... ............................ ............... ............................ ....9
2 Overview........................................................................................................................................13
2.1 Features..............................................................................................................................13
2.2 Applications ........................................................................................................................ 15
3Intel
4 Routing Guidelines........................................................................................................................ 25
5Intel
®
31244 PCI-X to Serial ATA Controller Package ..................................................................17
3.1 Signal Pin Descriptions................................................................................................ .......18
3.1.1 VA0, VA1 (V
3.2 Package/Marking Info rmation.............................................................................................22
3.3 Ball Map By Function..........................................................................................................23
4.1 General Rout ing Guidelines.... ............................. ............................ .............. .....................25
4.2 Crosstalk.............................................................................................................................26
4.3 EMI Considerations ....... .............. ............................ ............................. ............................ ..27
4.4 Power Distrib ut ion and Decouplin g....... ............................. ............................ .....................28
4.4.1 Decoupling.............................................................................................................28
4.4.1.1 Intel
4.5 Trace Impedance ................................................................................................................29
4.5.1 Differential Impedance........................................................................ ................. ..29
®
31244 PCI-X to Serial ATA Controller Interface Ports.........................................................31
5.1 Serial ROM Interface .......................................................................................................... 31
5.2 JTAG Interface....................................................................................................................31
5.3 PCI-X Interf a c e....... .............. ............................ ............................. ............................ .........32
5.4 Serial ATA Interface............................................................................................................33
5.4.1 Direct Port Access (DPA).......................................................................................33
5.4.2 Extended Voltage Mode ..................................................................... ...................33
5.4.3 LED Inte r face...... ............................ ............... ............................ ............................34
5.4.4 Reference Clock Generation ................................................ ....... ................. .........35
) Pin Requirements.............................. ............................ .........21
CCPLL
®
31244 PCI-X to Serial ATA Controller Decoupling.......................28
6 Printed Circuit Board (PCB) Methodology.....................................................................................37
6.1 Intel
6.2 Extended Voltage Mode ................................................................................................... ..39
7 PCI-X Layout Guide lines .................................................... ............................. ..............................47
7.1 PCI Voltage Levels .............................................................................................................47
7.2 PCI/X Clocki ng Modes............ .............. ............................. ............................ .....................48
Design Guide 3
®
31244 PCI-X to Serial ATA Controller
Normal Mode (standard SATA driver) ................................................................................ 38
6.1.1 Intel
6.2.1 Backplane Topologies ........................................................................................... 40
6.2.2 Motherboard Stackup for Backplane Designs.......................................... ............ ..42
6.2.3 Backplane Stripline Stackup.................................................................................. 44
6.2.4 Cable Intercon nect With Backpl ane.......................................................................45
®
31244 PCI-X to Serial ATA Controller HBA Stackup...................................39
Intel® 31244 PCI-X to Serial ATA Controller
Contents
7.3 PCI General Layout Guidelines.............................................. ............ ....... ....... ............ ......49
7.4 PCI-X Layout Guidelines For Slot Configurations............................................................... 50
7.4.1 Protection Circuitry for Add-in Cards..................................................................... 50
7.4.2 PCI Clock La yo ut Guide lines............................................... ............................ ......51
7.4.3 Connecting Intel
to Single-Slot ......................................................................................................... 52
7.4.4 Embedded Intel
Single PCI-X Load.................................................................................................53
7.4.5 Embedded Intel
®
31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller
Design With Multiple PCI-X Loa ds.........................................................................54
8 Cables and Connectors.................................................................................................................55
8.1 Cabling................................................................................................................................55
8.1.1 Serial ATA Cable....................................... ............................ ............................ ....58
9 Voltage Power Delivery.......................... ............................. .......................................... ................59
®
9.1 Intel
31244 PCI-X to Serial ATA Controller Core
Supply Voltage: Providing 2.5V in 3.3 V System............................................................... 59
10 Test Methodology.... ......................................................................................................................61
10.1 Extended Voltage Mode .. ...................................................................................................63
10.1.1 Extended Voltage Mode Receiver Mode l ..............................................................63
10.1.2 Extended Voltage Mode Driver Model...................................................................64
11 Terminati o n s: Pu ll-down/Pull-ups........... ............... ............................ ............................ ................65
®
12 Intel
IQ31244 PCI-X to Serial ATA Controller Evaluation Platform Board...................................67
12.1 Features..............................................................................................................................68
13 Debug Connectors and Logic Analyzer Connectivity ....................................................................69
13.1 Probing PCI-X Signals........................................................................................................69
14 Design for Manufacturing..............................................................................................................75
15 Thermal Solutions..........................................................................................................................77
15.1 Thermal Recommendations................................................................................................77
16 References....................................................................................................................................79
16.1 Related Documents............................................................................................................79
16.2 Electronic Information.........................................................................................................80
®
A Intel
IQ31244 Controller Evaluation Platform Board Bill of Materials..........................................81
4 Design Guide
Intel® 31244 PCI-X to Serial ATA Controller
Contents
Figures
1Intel® 31244 PCI-X to Serial ATA Controller Block Diagram......................................................14
2 Quad Serial ATA Host Bus Adapter............................................................................................15
3 Pa cka g ing Considerations................................... ............................. ............................ ..............17
4 Package Information: 256-pin PBGA . .........................................................................................22
5 PBG A Ma p ped By Pin Fun c ti o n. ............... .............. ............................ ............................. ...........23
6 Exa mples of Stubless a n d Shor t Stu b Trac e s........................ ............................. .......................25
7 Crosstalk Effects on Trace Distance and Height........................................................................26
8 PCB Ground Layout Around Connectors................................................................. .......... ....... ..26
9 C ro ss Se ction of Differential Trace.................................. ............................. ............................ ..29
10 LED and Serial EEPROM Configurations...................................................................................34
11 Intel
12 Intel
13 Write Backplane Topology..........................................................................................................40
14 Read Backplane Topology................................................................................ ....... ............ .......41
15 Microst r i p St ackup .................................................... ............................. .....................................43
16 Stripl i n e St ackup....................................... ............................ .............. ........................................ 44
17 Single-Slot Topology...................................................................................................................52
18 Embedded Intel
19 Embedded PCI-X Design With Multiple Loads ...........................................................................54
20 Serial ATA Direct Connect..........................................................................................................55
21 Serial ATA Connectors Cable to Host Connections ...................................................................56
22 Serial ATA Host Connectors.......................................................................................................57
23 Serial ATA Cable Signal Connections ........................................................................................58
24 Serial ATA Eye Diagram.............................................................................................................62
25 Extended Mode Receiver Example ............................................... .......... .. ....... ....... .......... ....... ..63
26 Extended Mode Driver Example.................................................................................................64
27 Intel
®
31244 PCI-X to Serial ATA Controller Connection Scheme - Normal Mode....................38
®
31244 PCI-X to Serial ATA Controller HBA Stackup........................................................39
®
31244 PCI-X to Serial ATA Controller
Design with Single PCI-X Load...................................................... ..... ....... ..... .. ....... ..... ....... ..... ..53
®
IQ31244 PCI-X to Serial ATA Controller Evaluation Platform Board
Block Diagram ............................................................................................................................67
Design Guide 5
Intel® 31244 PCI-X to Serial ATA Controller
Contents
Tables
1 Refer e n ce Documents......................... ............................. ............................ .............. ..................9
2 Ter mi n o log y and Def in ition........... ............... ............................ .............. ............................. ..........9
3 Serial ATA Sig nals Pin Descriptions...........................................................................................18
4 PCI-X Bus Pin Descriptions........................................................................................................ 19
5 Configuration Pin Descriptions...................................................................................................20
6 JTAG Pin Descriptions ...............................................................................................................20
7 Serial ROM Interface Pin Descriptions .......................................................................................21
8 Power Su ppl y Pin Descriptio n s.......................... .............. ............................ ............................. .21
9 Normal Voltage Mode ................................................................................................................. 33
10 Extended Voltage Mode .............................................................................................................33
11 Normal Voltage Mode.................................................................................................................38
12 Motherboard Sta cku p , Microstrip......... ............... ............................ ............................ ................42
13 Motherboard Mi cro s trip Parameters............................................... ............................ ............... .42
14 Backplane Stripline Stackup. ......................................................................................................44
16 Backplane Stackup, Offset Stripline ....................................................................................... ....45
15 Backplane Stackup, Microst rip ................................................................................................... 45
17 Cable Specifi ca tion.......................... ............................ ............................. ..................................45
18 PCI/X Voltage Levels........................................................................ ................. ......... ................47
19 PCI-X Clocking Modes........................ ............................. ............................ ..............................48
20 Add-on Card R outing Parameters..............................................................................................49
21 PCI-X Slot Guidelines................................................ .............. ............................ .......................50
22 Wiring Lengths fo r Single Slot..................... .............. ............................ ............................. ........52
23 Wiring Lengths for Embedded Intel
with Single PCI -X Loa d... ............................. .............. ............................ ............................. ........53
24 Wire Lengths For Multiple PCI-X Load Embedded
25 Serial ATA Signal Definitions......................................................................................................55
26 Interface Timing and SI Requirements . ......................................................................................61
27 Timing Require men t....... ............................. ............................ ............................ .......................62
28 Extended Voltage Mode Receiver ..............................................................................................63
29 Extended Mode Driver......................................................................................... ....... ................64
30 Termination s: Pull-up/Pull-down.................................................................................................65
31 Logic Analyzer Pod 1....................................... ....... ............ ....... ....... .......... ....... ....... ....... ...........69
32 Logic Analyzer Pod 2....................................... ....... ............ ....... ....... .......... ....... ....... ....... ...........70
33 Logic Analyzer Pod 3....................................... ....... ............ ....... ....... .......... ....... ....... ....... ...........71
35 Logic Analyzer Pod 5....................................... ....... ............ ....... ....... .......... ....... ....... ....... ...........72
34 Logic Analyzer Pod 4....................................... ....... ............ ....... ....... .......... ....... ....... ....... ...........72
36 Logic Analyzer Pod 6....................................... ....... ............ ....... ....... .......... ....... ....... ....... ...........73
37 Thermal Resistance ....................................................................................................................77
38 544-Lead H-PBGA Package Thermal Characteristics................................................................77
39 Design References.....................................................................................................................79
40 Intel Related Documentation......................................................................................................79
41 Electronic In formation............ .............. ............... ............................ ............................ ................80
®
31244 PCI-X to Serial ATA Controller Design..................................................................54
Intel
®
31244 PCI-X to Serial ATA Controller
6 Design Guide
Revision History
Date Revision # Description
April 2004 003 Removed Section 5.4.5, “Spread Spectrum Clocking” on page 35.
December 2002 002 In Section 2.1, added a new table titled “Serial ROM Interface Pin Descriptions”.
October 2002 001 Initial release of this document.
Intel® 31244 PCI-X to Serial ATA Controller
Contents
Removed SSC pin in Table 2, “Terminology and Definition” on page 9.
Updated SSCEN pin in Table 5, “Configurat i on Pi n De scr ipt i on s ” on p ag e 20 and
T able 30, “Terminations: Pull-up/Pull-down” on page 65.
Removed Section 9.1, “Power Delivery for the Intel® 31244 PCI-X to Serial A TA
Controller (TBD)” on page 59.
In Ap pendix A, “Intel
Materials”, replaced Bill of Materials table with a URL to the Intel
In Sectio n 2.1, adde d no te to Table 2, “Ser ial ATA Signal Pi n Des cr i pt io ns”,
indicating that LED2 and LED3 as dual purpose pins.
Replaced Figure 5, “PBGA Mapped by Pin Function” with a rev ised illustration.
Added cont en t to Sect ion 3.4 .1. 1, “In te l GD31 24 4 PC I-X to Se ria l ATA Co nt rol le r
Decoupling”, regarding the use of at le ast twelve 0.1 µF capacitors to decouple
the VCC 2.5 V signal.
Removed Section 3.4.1.2, “PCI-X Decoupling”.
In Table 30, “Terminations: Pullup/Pulldown”, revised row with si gnal name of
TRST# to include TDI#, TMS#, and TCK as 4.7K pull-ups.
In Appendix A, revised the Bill of Materials.
®
IQ31244 Controller Ev aluation Platform Board Bill of
®
website.
Design Guide 7
Intel® 31244 PCI-X to Serial ATA Controller
Contents
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8 Design Guide
About This Document 1
1.1 Reference Documentation
For the latest revision and documentation number, con tac t your Intel representative.
Table 1. Reference Documents
Document Intel Document Number or Source
®
Intel
Artisea PCI-X to Serial ATA Controller Developer’s Manual 273603
®
Artisea PCI-X to Serial ATA Controller Datasheet 273595
Intel
®
Packaging Databook 240800
Intel
Printed Circuit Board (PCB)Test Methodology User’s Guide,
Revision 1.6
Termina t in g D iff er e nt ial Signal s on PCBs, by St eve Kaufer and
Kelee Crisafulli. Pr inted Circuit Design Magazine, March 1999
1.2 Terminology and Definitions
http://developer.intel.com/design/chipsets/
applnots/298179.htm
298179
http://www.pcdmag.com
T able 2. Terminology and Definition (Sheet 1 of 3)
Term Definition
Stripline
Microstrip
Prepreg
Core
Material used fo r the lam inatio n pro cess of manufact uri ng PCBs. It co ns is t s of a lay er of
epoxy ma terial that is placed between two cores. This layer melts into epoxy when heated
and forms around adjacent traces.
Material used for the lamination process of manufacturing PCBs. This material is two sided
laminate with copper on each side. The core is an internal layer that is etched.
Stripline in a PCB is composed of the
conductor inserted in a dielectric with GND
planes to the top and bottom.
NOTE: An easy way to distinguish stripline
from microstrip is th at you need to
strip a way laye rs of the boa rd to vi ew
the trace on stripline.
Microstrip in a PCB is composed of the
conductor on the top layer above the
dielectric with a ground plane below
Design Guide 9
Intel® 31244 PCI-X to Serial ATA Controller
About This Document
Tab le 2. Term ino logy an d Definition (Sheet 2 of 3)
Term Definition
Layer 1: copper
Prepre g
Layer 2: GND
Core
PCB
Example of a Four-Layer Stack
Layer 3: VCC
Prepreg
Layer 4: copper
JEDEC Provides standards for th e semiconductor industry.
A network that tr ansmits a coup led signal to another network is aggress or network.
Zo
Aggressor
Zo
Victim Network
Aggressor Network
Printe d circuit board.
Example manufacturing process consists of
the following steps:
• Consists of alternat in g lay er s o f cor e and
prepreg stacked
• The finished PCB is heated and cured.
• The via holes are drilled
• Plating cover s holes and outer su rfaces
• Etching removes unwanted copper
• Board is tinned, co ated with solder mask
and silk scre en ed
Zo
Zo
Victim
Network
A networ k t hat rece iv es a co up led cr os s-t a lk si gna l fro m a noth er n etwor k is a c alle d t he vict i m
network
The trace of a PCB that completes an electrical connection between two or more
components.
Stub Branch from a t runk terminat ing at the pad of an agent.
CRB Customer Reference Board
HBA Host Bus Adapte r
TX + / TX -
RX + / RX -
These si gnals are the outbound high-sp eed different ial signals that are connected to the
serial ATA cable.
These signals are the inbound high-speed differential sig nals that are connected to th e serial
ATA cable.
TX This is a transmit port that contains the basic high-spe ed driver electronics.
RX This is a receiver port contains the basic high-speed receiver electronics.
Termination
calibration
PLL
Voltage
Regulator
This bl ock is used to establish the impedance of the RX block in order to properly termi nate
the high-speed serial cable.
This bl ock is used to synchronize an inte rnal clocking reference so that the input high-speed
data stream may be properly decoded.
This bl ock stabilizes the internal voltages used in the other blocks so that reliable operation
may be achieved. This bloc k may or may not be required for proper operation of the balance
of the circuitry . The need for thi s block is impleme ntation specific.
TxData Serially encoded 10b data attached to the high-speed serial differential line driver.
10 Design Guide
T able 2. Terminology and Definition (Sheet 3 of 3)
Term Definition
RxData Serially encoded 10b data attached to the high-speed serial differential line receiver.
10b encoding
Jitter Jitter is a high-frequency, semi-random displacement of a signal from its ideal location.
ISI
Differential
Signal
The 8B/10B encoding scheme transmits eight bits as a 10- bit code group. This encoding is
used with Gigabit Ethernet, Fibre Channel and InfiniBand*.
Inter-symbol interference. Data-dependent deterministic jitt er caused by the ti me differences
required for the signal to arrive at the receiver threshold when starting from different places in
bit sequences (symbols).
For example media attenuates the peak amplitude of the bit sequence [0,1,0,1...], more than
it attenuates the peak amplitude of the bit sequence [0,0,0,0,1,1,1,1...], thus the time required
to reach the receiver threshold with the [0,1,0,1...] sequence is less than required from the
[0,0,0,0,1,1,1,1...] sequence.
The run length of 4 produces a higher amplitude which takes more time to overcome when
changing bit values and therefore produces a time difference compared to the run length of
1-bit sequence. When different run lengths are mixed in the same transmission the different
bit sequences (symbols) therefore interfere with each other.
ISI is expected whenev er any bit sequence has frequency components that are pro pagated
at different rates by the transmission media. This translates into high-high-frequency,
data-dependent, jitter.
A signal derived by t aking the dif fe rence between tw o condu ctors. In this spec a di f ferenti al signal
is comprised of a positive conductor and a negative conductor. The differential signal is the
voltage on the positive conductor minus the voltage on the negative conductor (i.e., TX+ – TX-).
Intel® 31244 PCI-X to Serial ATA Controller
About Th i s Do cum ent
Design Guide 11
Intel® 31244 PCI-X to Serial ATA Controller
About This Document
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12 Design Guide
Intel® 31244 PCI-X to Serial ATA Controller
Overview
Overview 2
This document provides layout infor ma tion and guidelines for designing platform or add-in board
applications with the Intel
that this docu ment be used as a guideline. Intel recommends employing best-known design
practices with board-level simulation, signal integrity testing and validation for a robust design.
Designers should not e that th is guide focu ses upon spec ific de sign consi derat ions for th e GD31244
and is not intend ed to be an all-inclusive list of all good design practices. It is recommended that
this guide is used as a s tarting point and use empirical data to optimize your particular design.
Note: This pre-silicon analysis information is preliminary and subjec t to change. Sections marked with
TBD are to be updated in future revisions.
2.1 Features
The GD31244 is a state-of-the- art, PCI-X to Serial ATA Controller with four Serial ATA ports
running at 1.5 Gbits/s. The device is targeted at embedded applications suc h as PC mothe r boards,
as well as standalone PCI- X Host Bus Adapter (HBA) cards and RAID controllers.
The GD31244 is both a PCI-X Bus Master and Slave, which automatically switches modes as
required.
As a PCI-X Sla ve, the device supports:
• I/O Reads • Configura tion Read
• I/O Wri tes • Configura tion Write
• Memory Read Bus Cycles
®
31244 PCI-X to serial ATA controller (GD312 44). It is recommended
As a PCI-X Bu s Master, this device supports:
• Single Memory Reads • Lin e M emory Reads
• Multiple Memory Reads • Memory Writes
This device is compliant with a PCI-X bus operating at up to 64 bits at 133 MHz, resulting in burst
data rates of 1064 Mbytes/s. The GD31244 provides four Serial ATA ports running at 1.5 Gbits/s
transfe r r ate, which are compliant to the Serial ATA: High speed Serialized AT Attachment
Specificati on, Revision 1.0e. The GD31244 derives its Serial ATA c locks from an internal PLL,
with a reference clock of 37.5 MHz provided externally or from a crystal.
The GD31244 is fully compatible with parallel ATA operating system drivers and software. The
chip may be configured in compatibility mode, mapping the PCI-X configuration space to match
the x86 standa rd Pri mary a nd Se condary IDE port s. To support both o n-boa rd para lle l IDE, plus the
four Serial ATA ports, the chip may be configured for native PCI-X mode, allowing Plug-and-Play
BIOS and operating systems to map the Serial ATA drives to non-conflicting task file and I/O
address space. For higher performance in systems where compatibility is not required, all four
channels may be configured as Direct P ort Acc ess ( DPA).
Design Guide 13
Intel® 31244 PCI-X to Serial ATA Controller
Overview
Feature Highlights:
• Four SATA Channels at 1.5 Gbits/s
• Serial ATA: High speed Serialized AT Att achment Specification, Revision 1.0e Compli ant
• 64-bit/133 MHz PCI-X Bus. Backwards com p atible to 32-bit/33 MHz and 64-bit/66 MHz
• Compatible with existing Operating Sy stems
• Supports native PCI IDE
• Hot-Plug Drives
• Su pports Master/Slav e Mode for Compati bility with existing Operating Systems
• Sup ports SATA Direct Port Access (Master/Master Mode)
• Independent DMA Masters for ea ch SATA Channe l
• 3.3 V and 2.5 V Supply, 2 W maximum
Figure 1. Inte l
®
31244 PCI-X to Serial ATA Controller Block Diagram
LED0
P_AD(63:0)
P_CBE(7:0)
P_PAR
P_PAR64
P_FRAME#
P_TRDY#
P_IRDY#
P_STOP#
P_DEVSEL#
P_REQ#
P_REQ64#
P_ACK64#
P_GNT#
P_CLK
P_RST#
P_PERR#
P_SERR#
P_INTA#
PCI-X
64-bit
133 MHz
Interface
LED1
LED2
LED3
Dual
Port
FIFO
and
Transport
Engine
I/O
Serial ATA
Transport/Link
Layer
Serial ATA
Transport/Link
Layer
Serial ATA
Transport/Link
Layer
Serial ATA
Transport/Link
Layer
PHY
I/F
PHY
I/F
PHY
I/F
PHY
I/F
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
00B
00B
00B
00B
TX0P
TX0N
RX0N
RX0P
TX1P
TX1N
RX1N
RX1P
TX2P
TX2N
RX2N
RX2P
TX3P
TX3N
RX3N
RX3P
A9194-03
14 Design Guide
2.2 Applications
The GD31244 may be used to build a Serial ATA Host Bus Adapter which connects to the PCI-X
bus. Control for external activity LEDs, a 37.5 MHz Crystal, a voltage regulator and some external
resistors and capacitors are needed.
Figure 2. Quad Serial ATA Host Bus Adapter
P_AD[63:0]
P_CBE[7:0]
P_PAR
P_PAR64
P_FRAME#
P_TRDY#
P_IRDY#
P_STOP#
P_DEVSEL#
P_REQ#
P_REQ64#
P_ACK64#
PCI-X Bus
P_GNT#
P_CLK
P_IDSEL
P_RST#
P_PERR#
P_SERR#
P_INTA#
V
CC5REF
JTAG
TRST#
Oscillator
37.5 MHz
1000
+
TDI
TD0
TCK
TMS
18 pF
18 pF
Ω, 1%
VIO VCC
CLKIN
CLKOUT
RBIAS
V18A
0.1 µF10 µF
10 µF
Regulator
®
Intel
31244
PCI-X
to
Serial
ATA
Controller
V18B
+
CAP0
CAP1
CAP2
CAP3
RX0P
RX0N
TX0P
TX0N
RX1P
RX1N
TX1P
TX1N
RX2P
RX2N
TX2P
TX2N
RX3P
RX3N
TX3P
TX3N
0.1 µF
VA1
VA0
2.5V3.3V
22µF,
TANT,
EIA-A,
6.3V
.1µF,
0603,
x7R
10 µH
22µF,
TANT,
EIA-A,
6.3V
.1µF,
0603,
x7R
+
20Ω
0603, 1%
+
2.5V
+
22µF,
TANT,
EIA-A,
6.3V
.1µF,
0603,
x7R
10 µH
22µF,
TANT,
EIA-A,
6.3V
.1µF,
0603,
x7R
20Ω
0603, 1%
+
2.5V
B0418-02
0.1 µF
0.015 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
LED0
LED1
LED2
LED3
Serial
ATA
Port 0
Connector
Serial
ATA
Port 1
Connector
Serial
ATA
Port 2
Connector
Serial
ATA
Port 3
Connector
Design Guide 15
Intel® 31244 PCI-X to Serial ATA Controller
Overview
This page left intentionally blank.
16 Design Guide
Intel® 31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller Package
Intel
Intel® 31244 PCI-X to Seri al ATA
Controller Package 3
The GD31244 signals, are located on a 256-pin Plastic Ball Grid Array (PBGA) package to simplify
signal routin g and s ys tem implementat ion. For detailed signal descripti ons r efer to the Intel
31244 PCI-X to Serial ATA Controller Datasheet. Contact your Intel sales representative to obtain
a copy of this document. The construction of the packages is shown in Figure 3.
Figure 3. Packaging Consideration s
Die Attach Epoxy
Polyimide Dielectic
Die
Wirebond
Eutectic Solder Balls
A9196-02
®
Design Guide 17
Intel® 31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller Package
Intel
3.1 Sig na l Pin Descriptions
The signal pin descriptions for the GD31244 are provided as a reference. A complete list is also
available in the Intel
®
31244 PCI-X to Serial ATA Controller Datasheet.
Tab le 3. Serial ATA Signals Pin Descriptions
Name Description
TX0P, TX0N,
TX1P, TX1N,
TX2P, TX2N,
TX3P, TX3N
RX0P, RX0N,
RX1P, RX1N,
RX2P, RX2N,
RX3P, RX3N
CLKOUT OUTPU T - LVTTL: This is connected to one sid e of the 37.5 MHz crystal.
CLKIN
CLKO Buffered output of the 37.5 MHz clock.
RBIAS
CAP0, CAP1
LED0, LED1,
†
LED2
, LED3
† LED2 and LED3 are dual purpose pins. Refer to Table 7.
OUTPUT - Differential High-Speed Outputs: These are the differential serial outputs for
each channel. When disabled, these outputs are drive n to their DC-Bias point.
INPUT - Differential High-Speed Inputs: These are the differential serial inputs for each
channel.
INPUT - LVTTL: This is the reference clock input for the clock multiplier unit at 37.5 MHz. It
may be connected to either an external clock source or one side of a crystal.
INPUT - ANALOG: This pi n i s p ul l -down t o g rou nd w ith a 10 00Ω, 1% resistor in order to set
the internal termination resistors to 1000 Ω.
Analog: An external 0.1 µF (+/- 10%) capacitor is connected between these pins to set the
Clock Multiplier PLL loop filter response.
OUTPUT - LVTTL: These are the Activity LED outputs for channel 0, channel1, channel 2
†
and chan nel 3 (active LOW with 10 mA maximum sink capability).
18 Design Guide
®
31244 PCI-X to Serial ATA Controller Package
Intel
Table 4. PCI-X Bus Pin Descriptions (Sheet 1 of 2)
Name Description
CAP2, CAP3
P_ACK64#
P_AD[63:0]
P_C/BE[7:0]#
P_CLK All PCI bus signals are referenced to this clock.
P_DEVSEL#
P_FRAME#
P_GNT#
P_IDSEL
P_INTA#
P_IRDY#
P_PAR
P_PAR64
P_PERR#
P_REQ#
Analog: An external 0.015 µF (+/- 10%) capacitor is connected between these pins to set
the PCI PLL loop filter response.
BIDIRECTIONAL - LVTTL: Indicates that the device has positively decoded its address as
the target of the current access and the target is willing to transfer data using the full 64-bit
data bus.
BIDIRECTIONAL - LVTTL PCI Address and Data: The address and data lines are
multiplexed on these pins. A bus transaction consists of an address phase followed by one
or more da ta ph as es . P _AD[ 63 :56] co nt ai ns t he mos t sig ni fic ant by te and P _AD [7: 0] con ta in
the lea s t significant byte.
BIDIRECTIONAL - LVTTL: Com man d and By te E nab le. The bus command and byte enable
signals are multiplexed on these pins. During the address phase, the P_CBE# lines define
the bus comma nd . Dur i ng th e da t a phas e, th e P_C BE # lin es ar e used as Byt e Enabl e s. The
Byte Enables are valid for the entire data phase and det ermine which byt e lanes carry
mean in gfu l da t a.
BIDIRECTIONAL - L V TTL wi th Pull-Up Resistor: Devi ce Sele ct. This signal is asserted by
the target once it has detected its address. As a bus master, the P_DEVSEL# is an input
signa l to th e I n tel
bus has been selected. As a bus slave, the GD31244 asserts P_DEVSEL# to indicate that it
has decoded its address as the target of the current tran saction.
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Cycle Frame. This signal is driven by the
current master to indicate the beginning and duration of a transaction. P_FRAME# is
asserted to indicate the start of a transaction and de-asserted during the final data phase.
INPUT - LVTTL. Grant: This signal is asserted b y the bus arbiter and indicates to t he
GD31244 that access to the bus has been granted. This is a point-to-point signal and every
mast er ha s its ow n GN T# .
INPUT - LVTTL. Initializati on Dev ice Select: This signal is used as a chip select during
PCI-X conf i gur at ion r ea d an d writ e tra ns act i on s. Thi s si gn al is pro vi ded by the ho st in PC I-X
systems.
OUTPUT - Open Drain Interrupt A: This signal is used to request an inter rupt by the
GD31244. This is an active low , level triggered interrupt signal.
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Initiator Ready. This signal indicates the
bus master ability to complete the current data phase and is used in conjunction with the
target ready (P_TRDY#) signal. A data phase is complet ed on any clock cycle where both
P_IRDY# and P_TRDY# are asserted LOW.
BIDIRECTIONAL - L V T TL: Parity. Pa rit y i s e ven ac ross P_ AD[3 1: 0] and P _CB E[ 3: 0]# li ne s.
It is stable and valid one clock after the address phase. For data phases, P_PAR is stable
and vali d one clock after either P_IRDY# is asserted on a write or P_TRDY# is asserted on
a read.Once P_PAR is valid, it remains valid until on e clock after th e completion of th e
current data phase. The master drives P_PAR for address and write data phases; and the
target, for read data phases.
BIDIRECTIONAL - LVTTL: Parity for 64-bit Accesses. Parit y is ev en ac r oss P_A D[ 63 :0 ] an d
P_CBE[7:0]# lines. It is stable and valid one clock after the address phase. For data phases,
P_PAR64 is stable and valid one clock after either P_IRDY# is asserted on a write or
P_TRDY# is asserted on a read.Once P_PAR64 is valid, it remains valid until one clock after
the comple ti on of th e cur re nt dat a ph as e. The mas t er dr i ves P_PAR64 for addr e ss a nd wri te
data ph ases; and the target, for read data phases.
BIDIRECTIONAL - LVTTL with P ull- Up Resistor: Parity Error. This signal is used to report
data p arity errors dur ing all PCI-X t ransactions except a Special Cycle. This signal is
asse rt e d tw o cl oc k cy cles afte r th e err o r was detecte d by th e de vi c e re c ei ving data. Th e
minimum duration of P_PERR# is one clock for each data phase where an error is detected.
A device cannot report a parity error until it has claimed the access by asserting
P_DEVSEL# and completed a data phase.
OUTPUT - LVTTL. Request: This signal indicates to the bus arbiter that the GD31244
desires use of the bus. This is a point-to-point signal and every bus master has its own
P_REQ#.
®
31244 PC I- X to ser ial ATA co nt ro ll er i nd ic at ing w h ethe r any d evi ce on the
Intel® 31244 PCI-X to Serial ATA Controller
Design Guide 19
Intel® 31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller Package
Intel
Tab le 4. PCI-X Bus Pin Descriptions (Sheet 2 of 2)
Name Description
P_REQ64#
P_RST#
P_SERR#
P_STOP#
P_TRDY#
TEST0 INPUT - LVTTL: Test input. Set LOW for normal operation.
TOUT OUTPUT - T est pin. Do not use.
BIDIRECTIONAL - LVTTL: Indicates the attempt of a 64-bit transaction on the PCI bus.
When the target is 64-bit capable, the target acknowledges the attempt with the assertion of
P_ACK64#.
INPUT - LVTTL Reset: This signal is used to place PCI-X registers , sequencers, and
signal s into a consistent state. When P_RST# is asserted, all PCI-X output signals are
tri-stated.
OUTPUT - Open Drain with Pull-Up Resistor: System Error. This signal is used to report
address parity errors. When an error is detected, P_SERR# is driven LOW for a single
PCI-X clock.
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Stop. This signal is driven by the targe t
to indicate to the initiator that it wishes to stop the current transaction. As a bus slave,
P_STOP # is dr i ven by the GD 31 244 t o i n for m t he bu s ma st er t o stop t he curr e nt t r ansac ti o n.
As a bus master, P_ST OP# is received by the GD31244 to stop the current transaction.
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Target Ready. This signal indicates t he
selected device’s ab ility to complete the current data phase and is used in conjunction with
P_IRDY#. A data phase is completed on any clock cycle where both P_IRDY# and
P_TRDY# are asserted LOW.
Tab le 5. Configuration Pin Descriptions
Name Type Description
32BITPCI# INPUT
DPA_MODE# INP UT
SSCEN INPUT Tie this pin to GND.
Tab le 6. JTAG Pin Descriptions
Name Description
TDO
TDI
TCK
TMS
TRST#
TEST DATA OUTPUT: is the serial output pin for the JTAG feature. TDO is dri v en on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. The behavior of TDO is in dependent of P_RST#.
TEST DATA INPUT : is the serial input pin for the JTAG feature. TDI is sampled on the rising
edge of TCK, during the S HI FT-IR and SHIFT-DR states of the Test Ac ce ss Por t. Thi s sig nal
has a weak internal pull -up to ensure proper operation when this signal is unconnected.
TEST CLOCK: is an input which provides the clocking function for the IEEE 1149.1
Boundary Scan T esting (JTAG). State info rmation and data are clocked into the component
on the rising edge and data is clocked out of the component on the falling edge.
TEST MODE SELECT: is an in pu t samp led at th e ri sin g ed ge of TCK to select the operation
of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal
pull-up to ensure proper operation when this signal is unconnected.
TEST RESET: an input that asynchronously resets the Test Access Port (TAP) controller
function of IEEE 1149.1 Boundary Scan Testing (JTAG). This signal has a weak internal
pull-up.
Pin number A2. This pin control s the state of the “64 bit device” status
bit 16, in the PCI-X Status Regi ster. When pulled down, reports a 0, a
32-bit bus. When pulled up, reports 1, a 64-bit device.
INPUT - LVTTL: When HIGH or open, selects Master/Slave Mode for
software compatibility. When LOW, selects Master-Master mode for
high performance.
20 Design Guide
®
Intel
Table 7. Serial ROM Interface Pin Descriptio ns
Name Description
Intel® 31244 PCI-X to Serial ATA Controller
31244 PCI-X to Serial ATA Controller Package
SDI
SDO (LED3)
SCLK (LED2)
SCS#
INPUT - LVTTL with Pull Up: Connects to the serial data output (SDO) of the Serial ROM.
Customers are recommended to add pads for both a pull-up and a pull-down resistor for
possible use in the future.
OUTPUT - LVTTL: Connects to the serial data input (SDI) of the Serial ROM. This is also
the ac tivity LED output for Channel 3 when all four LEDs are activated (active LOW).
OUTPUT - LVTTL: Connects to the clock input (SCLK) of the serial ROM. This is also the
acti vity LED output for Channel 2 when all four LEDs are activated (active LOW) .
OUTPUT - LVTTL with Pull Up: Connects to the chip select input (SCS#) of the Serial
ROM.
Table 8. Power Supply Pin Descriptions
Name Description
OUTPUT: This is the reg ul at ed 1 . 8V supply ge ner at ed i nt ern al ly. Bypa ss wit h 0.1 a nd 1 0µF
capacitors.
V18A, V18B
V
CC5REF
VA0 , VA1
V
SS
V
CC
V
IO
, V
V
CC0
V
, V
CC2
V18A and V18B are each outputs of internal voltage regulators. They need to be separately
bypassed to ground with 0.1 and 10 µF capacitors separately, they must not be connected
together.
Voltage Clamp I/O: In 5 V tolerant systems, this is connected to a 5 V supply. In 3.3 V
powere d systems this is connected to 3.3 V. In PCI add-in cards, this is normally connected
to I/O Power (10 A, 16 A, 19 B, 59 A and 59 B). The user must ensure that the value of
V
the GD31244 not just PCI inputs. For example, when the Serial ROM device is 5 V I/O this
pin must be 5 V regardless of the PCI bus.
2.5 V Analog Power Supply: Separate filtering is recommended. VA0 supplies the PCI
PLL. VA1 supplies the CMU.
Ground.
2.5 V Digital Logic Power Supply.
3.3 V PCI I/O Power Supply.
,
CC1
2.5 V High-Speed I/O Power Supply for each channel.
CC3
is hig h enou gh t o ensu r e c ompli an ce to t he V
CC5REF
speci fic ati o n on ev ery i n put to
IH(MAX)
3.1.1 VA0, VA1 (V
CCPLL
) Pin Requirements
To reduce clock skew, the VA0 and VA1 balls for the Phase Lock Loop (PLL) circuit are each
isolat ed o n the pac kag e. The lowpa s s fi lter, as shown in Figure 2, reduces noise induced clock ji tt er
and its effects on timing relationships in system designs. The 22 µF bulk capacitors must be low
ESR solid tantalum and the 0.1 µF ceramic capacitor must be of the type X7R. The node
connecting VA0 and VA1, must be as short as possible.
Design Guide 21
Intel® 31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller Package
Intel
3.2 Package/Marking Information
The package is marked wit h three lines of text as shown in Figure 4. (The figure is not to scale.)
Figure 4. Package Information: 256-pin PBGA
12
1416
10
8
11
13
15
This page left intentionally blank.
3x 0.50 R
1.0 mm, Typ
BOTTOM VIEW TOP VIEW
13254769
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Pin A1
Indicator
17mm
17mm
2.06 ± 0.3
SIDE VIEW
Pin A1 Identifier
Part Number Package Suffix
Date Code
Intel® 31244 XX
#### AAAA
Lot Tracking Code
A9626-02
22 Design Guide
3.3 Ball Map By Function
Figure 5 shows the 544 BGA pins mapped by pin function. This diagram is helpful in placing
components aroun d the GD31244 for the layout of a PCB. To simplify routing and minimize the
number of cross traces, keep this layout in mind when placing components on your board. Name
signals, by desig n, are located on the PBGA package to simpl ify signal routing and s ys tem
implementation.
Figure 5. PB GA M apped By Pin Func ti on
1 2 3 4 5 6 7 8 9 101112 131415 16
32BIT
VSS
A A
B B
VCCREF VSS VSS TXOP RX0N TX1P RX1N VSS TX2P RX2N TX3P RX3N VSS VSS VCCREFVA1
LED3 TX0N RX0P TX1N RX1P CAP0 CAP1 TX2N RX2P TX3N RX3P CLKIN CLKOUT VSS
PCI#
LED2 P_AD32VCC
C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R
T T
SCS# VSS VCC0 VCC1 VSS VSS VSS VSS TDO
VSS P_RST# P_INTA# VSS LED0 MS_DA SSCEN VSSVCC TRST# TCK VSS P_AD33
P_REQ# P_AD31 P_GNT# CLKO SDI LED1 TOUT TEST0 RBIAS TDI TMS P_AD36 P_AD35 VI0 P_AD34VIO
VIO
VSS
P_AD28 VIO P_AD29 P_AD30
P_AD25 VSS P_AD26 P_AD27
P_AD23 P_IDSEL P_CBE3 P_AD24 P_AD46 P_AD45 VIO P_AD44
P_AD19 P_AD20 P_AD21 P_AD22
P_AD18 VSS VCC VCC
V18A VIO
P_
TRDY#
P_
SERR#
P_
PERR#
P_PAR VSS P_AD15 VIO
VSS P_CBE1 P_AD14 VSS
12345678910111213141516
P_
IRDY#
P_
P_AD16
DEVSEL#
VSS
P_CBE2 VCCREF
P_
VSS P_AD13
STOP#
PCI-X Interface Pins
SERDES section
VIO
VIO
VIO
VIO
VIO
P_AD17
P_
VIO
FRAME#
P_AD12
P_AD11 P_CBE0 VSS P_CLK VSS VSS
P_AD10
P_AD9
VIO 3.3V
VSS
VSS VSS VSS VIO
VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS
VIO
VIO VIOVIO
VCCREF
P_AD8
VIO P_AD6 VA0 VSS P_AD3 VIO P_CBE6
P_AD7 P_AD5 CAP3 CAP2 P_AD2
VCC is 2.5V
JTAG Section
VCC2VSS VCC3VSS
VCC
VSS VSS
VSS P_AD4
VIO
VCCREF
VSS VIO
VSS
VSSVSS
VIO
P_AD1
P_
REQ64#
P_
ACK64#
P_AD39 P_AD38 VSS P_AD37
P_AD43 P_AD42 P_AD41 P_AD40
VIO
P_AD49 P_AD48 VSS P_AD47
VIO
VCC VCC P_AD51 P_AD50
VIO
P_AD53 P_AD52 VSS V18B
VIO
VIO
P_AD0
P_CBE7
P_CBE5
VSS VIO VCCREF
P_AD54
VCCREF P_AD57
P_CBE4 VSS P_AD59
P_AD63 VSS
VIO
VSS P_AD62 P_AD61
P_
VSS
PAR64
P_AD56 P_AD55
P_AD58
P_AD60
VSS
B0419-02
C
R
Design Guide 23
Intel® 31244 PCI-X to Serial ATA Controller
®
31244 PCI-X to Serial ATA Controller Package
Intel
This page left intentionally blank.
24 Design Guide
Intel® 31244 PCI-X to Serial ATA Controller
Rout ing Gu idelines
Routing Guidelines 4
This chapter provi des routing guidelines for layout and design of a printed circuit board using the
GD31244. The high-speed clocking required when de s igning with the GD31244 requires special
attention to signal integrity. In fact, it is highly recommended that the board design be simulated to
determine optimum layout for signal integrity. The information in this chapter provides guidelines
to aid the designer with board layout. S everal factors influe nce the signal integrity of a GD31244
design. These factors include:
• power distribution • decoupling
• minimizing cros st alk • layout conside r ations when routing the SATA bus
4.1 General Routing Guidelines
This section deta ils general routing guidelines for connecting the GD31244. The order in which
signals are routed varies from desi gner to designer. Some designers prefer to route a ll clock signals
first, while others prefer to route all high-speed bus signals first. Either order may be used,
provided the guidelines listed here are followed.
Route the GD31244 address/data and control si gnals using a da isy chain topology. This topology
assumes that no stubs are used to connect any devices on the net. Figure 6, shows two possible
techniques to achieve a stubless trace. When it is not possible to apply one of the se two techniques
due to congestion, a very short stub is allowed - do not exceed 250 mils.
Note: A rule of the thumb for stub trace length is to make sure that the stub length is less than or equal to
the one-quarter of the signal transition.
Example:
• Nominal trace velocity To = 190 ps/in
• Typical signal slew rate = 2 V/ns
• Low-to- H ig h Voltage differential (0.3V
• Rise Ti me T
=.66 V *(1 ns/2 V) = 330 ps
R
to 0.5 VCC) =0.66 V
CC
• Equivalent Distance = 330 ps/T o = 1. 74in
• Stub length less than 1/4 of the length =0 .44 in
Figure 6. Examples of Stubless and Short Stub Traces
Stubless Short Stub
<250 Mils
A7690-01
Design Guide 25
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