INFINEON IPB50R140CP User Manual
IPB50R140CP
CoolMOSTM Power Transistor
Features
• Lowest figure of merit R
• Ultra low gate charge
• Extreme dv/dt rated
• High peak current capability
• Pb-free lead plating; RoHS compliant
• Quailfied according to JEDEC
CoolMOS CP is designed for:
• Hard & soft switching SMPS topologies
• CCM PFC for ATX Notebook adapter, PDP and LCD TV
• PWM for ATX, Notebook adapter, PDP and LCD TV
Type Package Marking
ON
x Q
g
1)
for target applications
Product Summary
V
DS @Tjmax
R
DS(on),max
Q
g,typ
PG-TO263
550 V
0.140
48 nC
Ω
IPB50R140CP PG-TO263 5R140P
Maximum ratings, at T
Parameter Symbol Conditions Unit
Continuous drain current
Pulsed drain current
Avalanche energy, single pulse
Avalanche energy, repetitive t
Avalanche current, repetitive t
MOSFET dv /dt ruggedness dv /dt
Gate source voltage
Power dissipation
Operating and storage temperature
=25 °C, unless otherwise specified
j
I
D
TC=25 °C
T
2)
AR
AR
2),3)
2),3)
I
D,pulse
E
AS
E
AR
I
AR
TC=25 °C
ID=9.3 A, VDD=50 V
ID=9.3 A, VDD=50 V
V
V
GS
static V
AC (f>1 Hz)
P
tot
, T
T
j
TC=25 °C
stg
=100 °C
C
=0...400 V
DS
Value
23
15
56
616 mJ
0.93
9
50
±20
±30
192
-55 ... 150
A
A
V/ns
W
°C
Mounting torque M3 and M3.5 screws 60 Ncm
Rev. 2.0 page 1 2007-11-20
Maximum ratings, at Tj=25 °C, unless otherwise specified
p
IPB50R140CP
Parameter Symbol Conditions Unit
Continuous diode forward current
Diode pulse current
Reverse diode dv /dt
2)
4)
I
S
I
S,pulse
T
C
=25 °C
dv /dt 15 V/ns
Parameter Symbol Conditions Unit
Value
14
56
Values
A
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case
R
thJC
- - 0.65 K/W
SMD version, device
Thermal resistance, junction ambient
Soldering temperature, wave & reflow
soldering allowed
R
thJA
T
sold
on PCB, minimal
foot
rint
--62
SMD version, device
on PCB, 6 cm
5)
area
cooling
-35-
2
reflow MSL 1 - - 260 °C
Electrical characteristics, at T
Static characteristics
Drain-source breakdown voltage
Gate threshold voltage
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
Gate resistance
=25 °C, unless otherwise specified
j
V
(BR)DSSVGS
V
GS(th)
I
DSS
I
GSS
R
DS(on)
R
G
=0 V, ID=250 µA
VDS=VGS, ID=0.93 mA
VDS=500 V, VGS=0 V,
T
=25 °C
j
V
=500 V, VGS=0 V,
DS
T
=150 °C
j
VGS=20 V, VDS=0 V
VGS=10 V, ID=14 A,
T
=25 °C
j
V
=10 V, ID=14 A,
GS
T
=150 °C
j
f =1 MHz, open drain - 2.2 -
500 - - V
2.5 3 3.5
--2µA
-20-
- - 100 nA
- 0.13 0.14
Ω
- 0.32 -
Ω
Rev. 2.0 page 2 2007-11-20
IPB50R140CP
r
Parameter Symbol Conditions Unit
Values
min. typ. max.
Dynamic characteristics
Input capacitance
Output capacitance
Effective output capacitance, energy
6)
related
Effective output capacitance, time
7)
related
Turn-on delay time
Rise time
Turn-off delay time
Fall time
C
C
C
C
t
t
t
t
iss
oss
o(er)
o(tr)
d(on)
r
d(off)
f
V
=0 V, VDS=100 V,
GS
f =1 MHz
V
=0 V, VDS=0 V
GS
to 400 V
V
=400 V,
DD
V
=10 V, ID=14 A,
GS
=12.2 Ω
R
G
- 2540 - pF
- 110 -
- 110 -
- 230 -
-35-ns
-14-
-80-
- 8.0 -
Gate Charge Characteristics
Gate to source charge
Q
gs
-11-nC
Gate to drain charge
Gate charge total
Gate plateau voltage
Q
Q
V
gd
g
plateau
=400 V, ID=14 A,
V
DD
V
=0 to 10 V
GS
-15-
-4864
- 5.2 - V
Reverse Diode
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Peak reverse recovery current
1)
J-STD20 and JESD22
2)
Pulse width tp limited by T
3)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f.
4)
ISD≤ID, di /dt ≤200A/µs, V
5)
Device on 40mm*40mm*1.5 epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for drain connection. PCB
j,max
DClink
=400V, V
V
SD
t
rr
Q
rr
I
rrm
peak<V(BR)DSS
is vertical without blown ai
6)
C
is a fixed capacitance that gives the same stored energy as C
o(er)
7)
C
is a fixed capacitance that gives the same charging time as C
o(tr)
VGS=0 V, IF=14 A,
T
=25 °C
j
VR=400 V, IF=IS,
di
/dt =100 A/µs
F
, Tj<T
, identical low and high side switch
jmax
while VDS is rising from 0 to 80% V
oss
while VDS is rising from 0 to 80% V
oss
- 0.9 1.2 V
- 400 - ns
- 5.6 - µC
-26-A
DSS.
DSS.
Rev. 2.0 page 3 2007-11-20
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