IDT IDT54FCT16652T, IDT54FCT16652AT, IDT54FCT16652CT, IDT54FCT16652ET, IDT54FCT162652T User Manual
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查询IDT54FCT162652ATEB供应商
FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical t
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%
• Features for FCT16652T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162652T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
DESCRIPTION:
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET
16-bit registered transceivers are built using advanced dual
metal CMOS technology. These high-speed, low-power de-
SK(o) (Output Skew) < 250ps
±16mA (military)
IDT54/74FCT16652T/AT/CT/ET
IDT54/74FCT162652T/AT/CT/ET
vices are organized as two independent 8-bit bus transceivers
with 3-state D-type registers. For example, the xOEAB and
x
OEBA
signals control the transceiver functions.
The xSAB and xSBA control pins are provided to select
either real time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that
occurs in a multiplexer during the transition between stored
and real time data. A LOW input level selects real-time data
and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The FCT16652T/AT/CT/ET are ideally suited for driving
high capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162652T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162652T/AT/CT/ET are plug-in replacements for the
FCT16652T/AT/CT/ET and ABT16652 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
OEAB
1B1
2
2OEBA
2CLKBA
CLKAB
2
1
2SBA
2SAB
2A1
A REG
D
C
TO 7 OTHER CHANNELS
B REG
D
C
2B1
2549 drw 02
1
OEAB
OEBA
1
1
CLKBA
1
SBA
1
CLKAB
1
SAB
B REG
D
C
1A1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
A REG
D
C
TO 7 OTHER CHANNELS
2549 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-2549/8
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
OEAB
1
CLKAB
1
SAB
GND
V
GND
GND
V
GND
2
SAB
2
CLKAB
2OEAB
1A1
1
A
CC
A
1
1
A
1A5
1
A
1
A
A
1
2A1
2
A
A
2
A
2
2A5
2A6
CC
2
A
2A8
1
2
3
4
5
6
2
7
8
3
9
4
10
11
6
12
7
13
8
14
SO56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
OEBA
1
1
CLKBA
1
SBA
GND
1B1
1
B
2
V
CC
1B3
1
B
4
1
B
5
GND
1
B
6
1B7
B
8
1
SO56-2
15
SO56-3
2
16
3
17
18
4
19
20
21
22
7
23
24
42
41
40
39
38
37
36
35
34
33
3225
26
27
28
31
30
29
B
1
2
2
B
2
2B3
GND
2
B
4
B
5
2
B
6
2
V
CC
2B7
2
B
8
GND
2
SBA
2
CLKBA
2
OEBA
1OEAB
1CLKAB
1SAB
GND
1A1
1
A2
VCC
1
A3
1
A4
1A5
GND
1
A6
1
A7
1
A8
2A1
2
A2
2
A3
GND
A4
2
2A5
2A6
VCC
A7
2
2A8
GND
SAB
2
2
CLKAB
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1
OEBA
1CLKBA
1SBA
GND
1
B1
1
B2
VCC
1B3
1
B4
1
B5
GND
1
B6
1B7
1
B8
2
B1
2
B2
2B3
GND
2
B4
B5
2
B6
2
VCC
2B7
2
B8
GND
2SBA
2CLKBA
2OEBA
SSOP/
TSSOP/TVSOP
TOP VIEW
2549 drw 03
CERPACK
2549 drw 04
TOP VIEW
2
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
xAx Data Register A Inputs
Data Register B Outputs
xBx Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA Output Data Source Select Inputs
xOEAB, x
FUNCTION TABLE
xOEAB x
OEBA
Output Enable Inputs
(2)
Inputs Data I/O
OEBA
OEBA
L
L
X
H
L
L
L
L
H
H
xCLKAB xCLKBA xSAB xSBA xAx xBx
H
H
H
H
X
L
L
L
H
H
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
2549 tbl 01
X
X
X
(2)
X
X
X
X
X
L
H
X
X
X
X
X
X
L
H
X
X
CAPACITANCE (TA = +25°C, f = 1.0MHz)
(1)
Output
Input
Input
(1)
Conditions Typ. Max. Unit
VIN = 0V 4.5 6.0 pF
VOUT = 0V 5.5 8.0 pF
Operation or Function
Store A and B Data
(1)
Store A, Hold B
Store A in Both Registers
Hold A, Store B
Store B in both Registers
Stored B Data to A Bus
Stored A Data to B Bus
Symbol Parameter
CIN Input
Capacitance
CI/O I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
Input Input Isolation
Input
Unspecified
Input
(1)
(2)
Unspecified
Output
Output Input Real Time B Data to A Bus
Input Output Real Time A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or x
Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH
transition on the clocks inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't care
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
VTERM
VTERM
OEBA
inputs.
(2)
Terminal Voltage with Respect to
GND
(3)
Terminal Voltage with Respect to
GND
(1)
–0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
–0.5 to
CC +0.5
V
2549 lnk 02
2549 tbl 03
V
2549 lnk 04
3
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
xOEAB xOEBA
xCLKAB
xCLKBA xSAB xSBA
BUS
B
2549 drw 05
LL X X XL
REAL-TIME TRANSFER
BUS B TO A
BUS
A
x
OEABxOEBAxCLKAB
H
H
X
REAL-TIME TRANSFER
BUS A TO B
BUS
B
2549 drw 06
x
CLKBA
x
SAB
x
SBA
XLX
BUS
A
xOEAB xOEBA xCLKAB xCLKBA xSAB xSBA
X
LXX
LH XX
H
STORAGE FROM
↑
X
↑
A AND/OR B
BUS
B
2549 drw 07
XX
↑
X
X
X
↑
BUS
A
x
OEABxOEBAxCLKABxCLKBA
HL
TRANSFER STORED
DATA TO A AND/OR B
H or L
H or L
BUS
B
2549 drw 08
x
SABxSBA
H
H
4
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
Symbol Parameter Test Conditions
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)
II L Input LOW Current (Input pins)
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND
VH Input Hysteresis — — 100 — mV
ICCL
ICCH
ICCZ
A = –40°C to +85°C, VCC = 5.0V ±10%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Input HIGH Current (I/O pins)
Input LOW Current (I/O pins)
(5)
(1)
(5)
VCC = Max. VI = VCC — — ±1 µA
(5)
(5)
VI = GND — — ±1
(5)
Min. Typ.
— — ±1
— — ±1
VO = 0.5V — — ±1
(3)
–80 –140 –225 mA
(2)
Max. Unit
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
2549 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16652T
Symbol Parameter Test Conditions
IO Output Drive Current VCC = Max., VO = 2.5V
(3)
(1)
Min. Typ.
–50 —–180 mA
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V
VIN = VIH or VIL IOH = –12mA MIL.
VOL Output LOW Voltage VCC = Min.
IN = VIH or VIL
V
IOFF Input/Output Power Off Leakage
(5)
VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA
OH = –15mA COM'L.
I
IOH = –24mA MIL.
OH = –32mA COM'L.
I
IOL = 48mA MIL.
OL = 64mA COM'L.
I
2.4 3.5 — V
2.0 3.0 — V
(4)
— 0.2 0.55 V
(2)
OUTPUT DRIVE CHARACTERISTICS FOR FCT162652T
Symbol Parameter Test Conditions
IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
IODH Output HIGH Current VCC = 5V, VIN = VIH or V IL,
VOH Output HIGH Voltage VCC = Min.
V
IN = VIH or VIL
VOL Output LOW Voltage VCC = Min.
V
IN = VIH or VIL
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at T
A = –55°C.
(1)
(3)
VOUT = 1.5V
(3)
IOH = –16mA MIL.
I
OH = –24mA COM'L.
IOL = 16mA MIL.
I
OL = 24mA COM'L.
Min. Typ.
60 115 200 mA
–60 –115 –200 mA
2.4 3.3 — V
— 0.3 0.55 V
(2)
Max. Unit
2549 lnk 06
Max. Unit
2549 lnk 07
5
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
(1)
V
IN
= V
CC
VIN = GND
Min. Typ.
— 0.5 1.5 mA
— 75 120
∆I
I
CCD
CC
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
Parameter Test Conditions
VCC = Max.
= 3.4V
(3)
(4)
V
IN
VCC = Max.
Outputs Open
xOEAB = x
OEBA
=GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
VCC = Max.
Outputs Open
f
CP
= 10MHz (xCLKBA)
V
IN
= V
CC
VIN = GND
— 0.8 1.7 mA
50% Duty Cycle
xOEAB = x
OEBA
One Bit Toggling
=GND
V
IN
V
IN
= 3.4V
= GND
— 1.3 3.2
fi = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
f
CP
= 10MHz (xCLKBA)
V
IN
= V
CC
VIN = GND
— 3.8 6.5
50% Duty Cycle
xOEAB = x
OEBA
=GND
Sixteen Bits Toggling
V
IN
V
IN
= 3.4V
= GND
— 8.3 20.0
fi = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C = IQUIESCENT + IINPUTS + IDYNAMIC
6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
∆I
H = Duty Cycle for TTL Inputs High
D
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
CP = Number of Clock Inputs at fCP
N
fi = Input Frequency
N
i = Number of Inputs at fi
CC = 5.0V, +25°C ambient.
IN = 3.4V). All other inputs at VCC or GND.
CC formula. These limits are guaranteed but not tested.
(2)
Max. Unit
(5)
(5)
µ
A/
MHz
2549 tbl 08
6
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16652T/162652T FCT16652AT/162652AT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition
tPLH
Propagation Delay
tPHL
Bus to Bus
tPZH
Output Enable Time
tPZL
xOEAB or x
tPHZ
Output Disable Time
tPLZ
xOEAB or x
tPLH
Propagation Delay
tPHL
Clock to Bus
tPLH
Propagation Delay xSBA or
tPHL
xSAB to Bus
OEBA
OEBA
to Bus
to Bus
CL = 50pF
L = 500Ω
R
tSU Set-up Time HIGH or LOW
Bus to Clock
tH Hold Time HIGH or LOW
Bus to Clock
tW Clock Pulse Width
HIGH or LOW
tSK(o) Output Skew
(3)
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns
2.0 14.0 2.0 15.0 2.0 9.8 2.0 10.5 ns
2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns
2.0 9.0 2.0 10.0 2.0 6.3 2.0 7.0 ns
2.0 11.0 2.0 12.0 2.0 7.7 2.0 8.4 ns
4.0 — 4.5 — 2.0 — 2.0 — ns
2.0 — 2.0 — 1.5 — 1.5 — ns
6.0 — 6.0 — 5.0 — 5.0 — ns
— 0.5 — 0.5 — 0.5 — 0.5 ns
2549 tbl 09
FCT16652CT/162652CT FCT16652ET/162652ET
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition
tPLH
Propagation Delay
tPHL
Bus to Bus
tPZH
Output Enable Time
tPZL
xOEAB or x
tPHZ
Output Disable Time
tPLZ
xOEAB or x
tPLH
Propagation Delay
tPHL
Clock to Bus
tPLH
Propagation Delay xSBA or
tPHL
xSAB to Bus
OEBA
OEBA
to Bus
to Bus
CL = 50pF
L = 500Ω
R
tSU Set-up Time HIGH or LOW
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
1.5 5.4 1.5 6.0 1.5 3.8 — — ns
1.5 7.8 1.5 8.9 1.5 4.8 — — ns
1.5 6.3 1.5 7.7 1.5 4.0 — — ns
1.5 5.7 1.5 6.3 1.5 3.8 — — ns
1.5 6.2 1.5 7.0 1.5 4.2 — — ns
2.0 — 2.0 — 2.0 — — — ns
Bus to Clock
tH Hold Time HIGH or LOW
1.5 — 1.5 — 0.0 — — — ns
Bus to Clock
tW Clock Pulse Width
5.0 — 5.0 — 3.0
(4)
———ns
HIGH or LOW
tSK(o) Output Skew
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
(3)
— 0.5 — 0.5 — 0.5 — — ns
(2)
Max. Unit
2549 tbl 10
7
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
V
OUT
50pF
C
L
Pulse
Generator
V
IN
D.U.T.
T
R
500
500
7.0V
Ω
Ω
2549 drw 05
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
DEFINITIONS:
L= Load capacitance: includes jig and probe capacitance.
C
R
T = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Switch
Closed
Open
2549 lnk 07
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
t
SU
t
H
INPUT
ASYNCHRONOUS CONTROL
PRESET
t
REM
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLOCK ENABLE
CLEAR
t
SU
t
H
ETC.
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
t
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
PLH
t
PLH
t
PHL
t
PHL
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2549 drw 06
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
2549 drw 08
PULSE WIDTH
LOW-HIGH-LOW
HIGH-LOW-HIGH
PULSE
PULSE
t
W
2549 drw 07
ENABLE AND DISABLE TIMES
ENABLE DISABLE
3V
CONTROL
INPUT
t
t
PLZ
PHZ
F ≤ 2.5ns; tR ≤ 2.5ns
t
PZL
OUTPUT
NORMALLY
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
LOW
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
1.5V
0V
0.3V
0.3V
1.5V
0V
3.5V
V
V
0V
1.5V
1.5V
OL
OH
2549 drw 09
8
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX FCT XXXX
Temperature
Range
Device TypeXPackage
X
Process
Blank
B
PV
PA
PF
E
16652T
16652AT
16652CT
16652ET
162652T
162652AT
162652CT
162652ET
54
74
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
Non-Inverting 16-Bit Bus Transceiver/Register
–55°C to +125°C
–40°C to +85°C
2549 drw 14
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 FAX 408-492-8674
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