AIR BAND FM TRANSCEIVER
iC-a23
iC-a5
INTRODUCTION
This service manual describes the latest service information for
the IC-A23/IC-A5 FM TRANSCEIVER at the time of
publication.
MODEL VERSION SYMBOL
IC-A23
IC-A5
To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation.
#01
#11
#21
#31
A23-USA
USA-1
A5-USA
USA-1
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. Such a connection
could cause a fire hazard and/or electric shock.
DO NOT expose the transceiver to rain, snow or any liq-
uids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100
mW) to the antenna connector. This could damage the
transceiver s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110003490 S.IC TA31136FN IC-A23 RF UNIT 1 piece
8810008990 Screw FH BT 2 × 10 ZK IC-A5 CHASSIS 6 pieces
Addresses are provided on the inside back cover for your
convenience.
IC-A5 IC-A23
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 40 dB or 50 dB attenuator between the transceiver and a deviation meter or spectrum analyser when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4 – 1 RECEIVER CIRCUITS ................................................................................................................... 4 – 1
4 – 2 TRANSMITTER CIRCUITS ............................................................................................................ 4 – 2
4 – 3 PLL CIRCUIT ................................................................................................................................. 4 – 3
4 – 4 POWER SUPPLY CIRCUITS ......................................................................................................... 4 – 4
4 – 5 CPU PORT ALLOCATIONS ........................................................................................................... 4 – 5
SECTION 5 ADJUSTMENT PROCEDURES
5 – 1 PREPARATION ............................................................................................................................... 5 – 1
5 – 2 PLL ADJUSTMENT......................................................................................................................... 5 – 2
5 – 3 TRIMMER ADJUSTMENT.............................................................................................................. 5 – 3
5 – 4 RECEIVER ADJUSTMENT............................................................................................................. 5 – 7
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9 – 1 LOGIC UNIT ................................................................................................................................... 9 – 1
9 – 2 RF UNIT ......................................................................................................................................... 9 – 3
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
11 – 1 LOGIC UNIT ................................................................................................................................. 11 – 1
11 – 2 RF UNIT ....................................................................................................................................... 11 – 2
1 - 1
SECTION 1 SPECIFICATIONS
‘‘
GENERAL
• Frequency coverage : TX 118.000–136.975 MHz
RX 108.000–136.975 MHz *
1
WX 161.650–163.275 MHz *
1
*1: IC-A23 only, IC-A5; 118.000–136.975 MHz
*2: U.S.A version only
• Type of emission : 6K00A3E, 16K0G3E (Weather channel; [USA] version only)
• Channel spacing : 25 kHz
• Memory channels : 20 channels × 10 banks
• Power supply requirement : 9.6 V DC (supplied battery pack)
• External power supply requirement : 9.6 V–12.0 V DC (negative ground)
• Current drain (at 9.6 V DC) : Transmit 1.8 A max.
1.1 A typical
Receive 500 mAmax. (AF max.)
70 mA typical (stand-by)
• Operating temperature range : –10˚C to +60˚C; +14˚F to +140˚F
• Frequency stability : ±17 ppm (–10˚C to +60˚C)
• Antenna connector : BNC type (50 Ω nominal)
• Dimensions (projections not included) : 58(W) × 107(H) × 28.5(D) mm; 2
5
⁄16(W) × 4 7⁄32(H) × 1 1⁄8(D) in.
• Weight (with ant., BP-200L) : 340 g; 12 oz.
‘‘
TRANSMITTER
• RF output power (at 9.6 V DC) : 5.0 W (PEP) typical, 1.5 W (CW) typical.
(with supplied battery pack)
• Modulation system : Low level modulation
• Modulation limiting : 70–100% of max. deviation
• Audio harmonic distortion : Less than 10 % (at 60 % modulation)
• Hum and noise ratio : More than 35 dB
• Spurious emissions : More than 60 dB
• Microphone impedance (MIC) : 150 Ω
‘‘
RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st 30.05 MHz
2nd 450 kHz
• Sensitivity : Less than 1.0 µV at 6 dB S/N (AM)
Less than 1.0 µV at 12 dB S/N (FM)
• Threshold squelch sensitivity : Less than 0.71 µV (AM)
Less than 0.22 µV (FM)
• Selectivity : More than 7.5 kHz/–6 dB
Less than 25 kHz/–60 dB
• Spurious response rejection ratio : More than 60 dB
• Audio power output (at 9.6 V DC) : More than 500 mW at 10 % distortion with an 8 Ω load
• Hum and noise : More than 25 dB
• Audio output impedance : 8 Ω
• Ext. speaker connector : 3-conductor 3.5(d) mm (
1
⁄8”)/8 Ω
Specifications are measured in accordance with FCC Part87.
All stated specifications are subject to change without notice or obligation.
Clock oscillator
(X1: CR-534,
5.039 MHz)
EEPROM
(IC7: HN58X2432)
RESET
(IC2: S-80945ALMP)
PTT detector
(Q10: 2SB1462)
Microphone
mute
(Q12: UN9211)
CPU
(IC1: M38267M6L)
VOR circuit
(IC-A23 only)
Microphone
amplifier
(IC9: BA3308F)
AF amplifier
(IC6: TA7368F)
YGR amplifier
(Q3: 2SK2973)
VCO circuit
Reference
oscillator
(X2: CR-683,
29.600 MHz)
Power amplifier
(Q2: 2SK2994)
RF amplifier
(Q11: 3SK230)
ALC detector
(D2, D3: MA728)
Antenna switching
circuit
AF amplifier/
Low-pass filter
(IC510: TC75W51F)
ALC CTRL
(Q1: UMS1)
VOR switching
(Q19: UN9210)
[IC-A23] only
1st mixer
(Q12: 3SK151
30.05 MHz)
ALC amplifier
(Q5: 2SC4211)
Lo switching diode
(D6, D17: MA77)
Electric volume
(IC505: M52429FP)
IF amplifier
(Q13, Q15, Q16,
Q17: 2SC4215)
2nd mixer,
IF amplifier,
Noise detector
(IC1: TA31136FN)
PLL IC
(IC3: TB31207FN)
Q16
Q15
Q13
IF discreminator
crystal
(X1: CDBCA450CX24
450 kHz)
• RF UNIT
SECTION 2 INSIDE VIEWS
BOTTOM VIEW
TOP VIEW
• LOGIC UNIT
BOTTOM VIEW
2 - 1
SECTION 3 DISASSEMBLY INSTRUCTIONS
A
C
B
Chassis panel
F
F
G
F
Shield plate
RF unit
H
I
I
RF unit
[ANT] plug
I
E
E
E
Sealing rubber
J1
LOGIC unit
RF unit
Chassis panel
D
1 REMOVING THE CHASSIS PANEL
q Remove 1 knob, B, and unscrew 1 nut, A.
w Unscrew 2 screws
e Remove the chassis panel in the direction of the arrow.
2 × 10 mm, black).
(
C
3 REMOVING THE SHIELD PLATE
q Unsolder 3 points, F, to separate the shield plate
and RF unit.
w Unscrew 1 screw
(2 × 4 mm, silver).
G
2 REMOVING THE LOGIC UNIT
q Remove the sealing rubber.
w Unsolder 1 point,
e Unscrew 4 screws
r Unplug J1 to separate LOGIC unit and RF unit.
t Remove the LOGIC unit in the direction of the arrow.
, to separate a SENSOR control.
D
(2 × 4 mm, silver).
E
4 REMOVING THE RF UNIT
q Unsolder 1 point, H, to separate the [ANT] plug.
w Unscrew 5 screws
the RF unit.
e Remove the RF unit in the direction of the arrow.
(2 × 4 mm, silver), to separate
I
3 - 1
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (RF UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving. However, its impedance becomes very high
while D8 and D9 are turned ON. Thus transmit signals are
blocked from entering the receiver circuits. The antenna
switching circuit employs a λ⁄4 type diode switching system.
Received signals are passed through the low-pass filter
(L1–L3, C3–C7). The filtered signals are applied to the λ⁄4
type antenna switching circuit (D8, D9).
The passed signals are then applied to the RF amplifier circuit.
4-1-2 RF CIRCUIT (RF UNIT)
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the antenna switching circuit are amplified
at the RF amplifier (Q11) after passing through the tunable
bandpass filter (D13, L18, C58, C60). The amplified signals
are applied to the 1st mixer circuit (Q12) after out-of-band
signals are suppressed at the tunable bandpass filter
(D14–D16, L22, L23, C70–C79).
Varactor diodes are employed at the bandpass filters
(D13–D16) that track the filters and are controlled by the
CPU (LOGIC unit; IC1) via the expander IC (IC4) using
bandpass filter control voltage. These diodes tune the center frequency of an RF passband for wide bandwidth receiving and good image response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS (RF UNIT)
The 1st mixer circuit converts the received signal into a fixed
frequency of the 1st IF signal with a PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a crystal filter at the next stage of the 1st
mixer.
The signals from the RF circuit are mixed at the 1st mixer
(Q12) with a 1st LO signal (AM; 78.85–107.825 MHz, FM;
132.45–134.125 MHz) coming from the VCO circuit to produce a 30.05 MHz 1st IF signal.
The 1st IF signal is applied to a crystal filter (FI1) to suppress out-of-band signals. The filtered 1st IF signal is
applied to the 1st IF amplifier (Q13), then applied to the 2nd
mixer circuit (IC1, pin 16).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(RF UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF
signal. Adouble conversion superheterodyne system (which
converts receive signals twice) improves the image rejection
ratio and obtains stable receiver gain.
The IF IC contains the 2nd local oscillator, 2nd mixer, limiter
amplifier, guadrature detector and s-meter detector circuit,
etc.
The 1st IF signal from the 1st IF amplifier is applied to the
2nd mixer section of the IF IC (IC1, pin 16), and is mixed
with a 29.6 MHz 2nd LO signal generated at the PLL circuit
using the reference frequency (29.6 MHz) to produce a 450
kHz 2nd IF signal.
The 2nd IF signal from the 2nd mixer (IC2, pin 3) passes
through a ceramic filter (FI2) to remove unwanted heterodyned frequencies. The filtered signal is amplified at the IF
amplifier (Q15), and is then applied to the AM detector circuit or FM detector circuit respectively.
(1) AM DETECTOR CIRCUIT
The amplified signal is then amplified at the 2nd IF amplifiers
(Q16, Q17) and applied to the AM detector (Q18) to demodulate the 2nd IF signal into AF signals.
The demodulated AF signals are applied to the AM/FM
switch (IC2, pin 6) via the ANL circuit (D18).
(2) FM DETECTOR CIRCUIT
The amplified signal is then amplified at the limiter amplifier
(IC1, pin 5) and applied to the quadrature detector (IC1, pins
10, 11) to demodulate the 2nd IF signal into AF signals.
The demodulated AF signals are output from pin 9 of the IC1
and are applied to the AM/FM switch (IC2, pin 7).
ANT
LPF
ANT
SW
BPF
BPF
XTAL
BPF
BPF
FM
DET
1st IF
AMP
RF
AMP
AF signal
to the AF circuit
2nd IF
AMP
2nd IF
AMP
2nd IF
AMP
AM
DET
ANL
AM/FM
Switch
Q11 Q12
Q13
IC1
IC1
FI1
FI2
Q15
D8, D9 D14, D15, D16D13
1st Mixer 2nd Mixer
Q16, Q17
Q18D18
AM signal
FM signal
IC1
IC2
• RF CIRCUIT
4 - 2
4-1-5 AF CIRCUIT (RF UNIT)
The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker.
AF signals from the AM detector (Q18; While in AM mode)
or IF IC (IC1, pin 9; While in FM mode) are applied to the
AM/FM switch (IC2, pin 6 or 7). The output signals from pin
1 are applied to the AF amplifier (IC510, pin 6), and then
pass through the low-pass filter (IC510, pins 2, 1). The filtered signals are amplified at the OP-amplifier (IC14), and
are then applied to the power amplifier (IC6, pin 4) to obtain
the specified audio level after being passed through the
electric volume (IC505, pins 1, 2). The amplified AF signals
are applied to the internal speaker (SP1) via the [EXT SP]
jack (J2) when no plug is connected to the jack.
4-1-6 SQUELCH CIRCUIT (RF AND LOGIC UNITS)
Asquelch circuit cuts out AF signals when no RF signals are
received. By detecting noise components in the AF signals,
the squelch switches the AF mute switch.
Aportion of the 2nd IF signal from the 2nd IF amplifier (Q15)
is fed back to the IF IC (IC1, pin 5). The IF signal is amplified at the IF amplifier section in the IC, which then detects
the receiver signal strength at the RSSI section for conversion into DC voltage.
The DC voltage is applied to the CPU (LOGIC unit; IC1, pin
3) via the “RSSI” signal after being amplified at the RSSI
amplifier (IC13).
The CPU analyzes the noise condition and outputs the control signal to the shift resistor (IC5). The shift resistor (IC5,
pin 14) outputs the squelch control signal via “AFC” line. The
signal is applied to the AF out control circuit (Q36, Q35) to
control the power amplifier (IC6) and cut the AF signal line.
4-1-7 AGC CIRCUIT (RF UNIT)
The AGC (Automatic Gain Control) circuit reduce signal fading and keeps the audio output level constant.
AF signals from the AM detector circuit (Q18) are converted
into DC voltage at the AGC amplifier circuits (Q14; for
1st/2nd IF amplifiers, Q10; for RF amplifier) by detecting the
driving current at the AM detector. The DC voltage from the
AGC amplifiers is applied to the 1st/2nd IF amplifiers (Q13,
Q15, Q16) and RF amplifier (Q11) to reduce the amplifier
gain when strong signals are received.
R87 C104
Mixer
16
IF amp.
2nd IF filter
450 kHz
PLL IC
IC3
X2
29.6 MHz
X1
(29.6 MHz)
RSSI
IC2 TA31136F
12
1st IF (30.05 MHz) from
the IF amplifier (Q13)
S-meter signal to the RSSI
amplifier (IC13, pin 1)
11109
853
FM AF signal to the
AM/FM switch (IC2, pin 7)
AM AF signal to the
AM/FM switch (IC2, pin 6)
R5
2
12
14
Active
filter
FI2
Noise
detector
FM
detector
C93C95 C92
R72
R71
C91
Q15
C103R86C101
Q16
C109
R91
R92 C108
R89
Q17
C112
R94
C111
Q18
R97 R96
R5
R5
R73 C94
C201
R74
R5
AGC
AMP
AGC
AMP
AF signal to the AM/FM Switch (IC2)
AM
DET
Q15
to the RF amplifier (Q11)
to the 1st IF amplifier (Q13)
2nd IF signal from
the 2nd mixer (IC1)
Q16
Q17
Q18
Q14
Q10
2nd IF
AMP
2nd IF
AMP
2nd IF
AMP
• 2ND IF AND DEMODULATOR CIRCUITS
• AGC CIRCUIT
4 - 3
4-1-8 ANL CIRCUIT (RF UNIT)
The ANL (Automatic Noise Limiter) circuit (Q21, D18)
reduces pulse noises.
The AM detector output signal from the Q18 is applied to the
cathode of D18 passing through R99 where it is divided by
R99 and R100. The signal is also applied to the anode of
D18, passing through R101 and R102.
When the ANL function is activated (Q21 is ON), C115 is
grounded. The detector output, including pulse noise, is
applied to the cathode of D18 only. If pulse noises are
received, the cathode voltage of D18 becomes higher than
the anode voltage and D18 turns OFF. Thus, while pulse
noises are received, the detected signal is not applied to
IC2.
4-1-9 VOR NAVIGATION CIRCUIT (LOGIC UNIT)
(IC-A23 ONLY)
From the AF signal, the VOR circuit detects a variable signal
(VORC) and reference signal (VORS) from a VOR station.
The VOR circuit sends these signals to the CPU (IC1).
When the transceiver is set in the navigation band
(108.000–117.975 MHz), the VORON port of shift resistor
(IC8, pin 4) becomes “HIGH” turning the VOR circuit ON via
Q15. Q15 controls a 5 V power source for the VOR circuit.
The signal from the AM detector (VORDET) is buffer amplified at the OP-AMP IC (IC12).
The “VORDET” signal includes 30 Hz variable phase components and 9960 Hz reference phase components.
The 30 Hz component passes through the 30 Hz bandpass
filter (IC12, R83, R85–R88, C112, C113), and is converted
to a square-wave signal at the VORC comparator (IC14).
The square-wave signal is then applied to the CPU (IC1, pin
22) as variable signal (VORC).
The 9960 Hz component passes through the 10 kHz bandpass filter (IC12, R79–R81, C108, C109). These components are FM modulated with 480 Hz deviation and 30 Hz
modulation.
Signals are then amplified at a limiter amplifier (IC11), and
detected at an FM detector (IC11) to obtain a 30 Hz reference signal.
The 30 Hz signal is compensated on phase at IC12. This
signal is passed through the 30 Hz bandpass filter (IC12)
and is converted to a square-wave signal at the VORS comparator (IC14). This signal is applied to the CPU (IC1, pin 1 1)
as a reference signal (VORS).
A portion of output from the buffer amplifier (IC12) is applied
to the amplifier (Q13). When VOR level is low or receiving
the signal except VOR signal, output from Q13 is reduced.
Q13 cannot be turned ON, then IC1 (pin 2) receives “HIGH”
to indicate “OFF FLAG” indicator.
Buff.
IC12
BPF
30 Hz
BPF
10 kHz
LPF
FM
DET
FI2
BIAS
Phase
shift
Limit.
IC1
IC11
Comp.
Amp.
Comp.
IC14
1
3
2
5
67 7 2 8
1
"VOR" signal from VOR
controller (Q15, pin 3)
"VORDET" signal from
the AM detector (Q18)
35
14
3
7
"VORC" signal to the
CPU (IC1, pin 22)
"VORS" signal to the
CPU (IC1, pin 11)
"VORD" signal to the
CPU (IC1, pin 2)
IC13
C115 R101
D18
R102
To IC2, pin 6
R99
AM AF signal
from Q18
R100
Q21
"ANLC" signal
from IC5, pin 12
• ANL CIRCUIT
• VOR NAVIGATION CIRCUIT
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(LOGIC AND RF UNITS)
The microphone amplifier circuit amplifies audio signals with
+6 dB/octave pre-emphasis characteristics from the microphone to a level needed for the modulation circuit.
AF signal from the internal/external microphone are applied
to the microhone amplifier (LOGIC unit; IC9, pin 9) via the
modulation depth adjustment pot (LOGIC unit; R41). The
amplified signals are applied to the AF amplifier (RF unit;
IC510, pin 6) and low-pass filter (RF unit; IC510, pin 3) after
being passed through the voice rec/play IC (LOGIC unit;
IC15). The filtered signals are applied to the modulation circuit.
4-2-2 MODULATION CIRCUIT (RF UNIT)
The modulation circuit modulates the TX LO signal from the
VCO (RF signal) using the microphone audio signal.
While in transmission, the LO signal from the VCO circuit
(Q31, Q32, D24) is amplified at the buffer amplifiers (Q30,
Q27, Q28) and passed through the LO switch (D17). This
signal is then applied to the AM modulator (D5).
The buffer amplifier (q6) amplifies the LO signal with a gain
controlled by an AF signal to make low level modulation.
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
(RF UNIT)
The drive amplifier circuit amplifies the transmit signal to a
level needed for the power amplifier circuit. The power
amplifier circuit amplifies this to obtain a specified transmit
output power.
The modulated RF signal from the buffer amplifier (Q6) is
applied to the pre-drive amplifier (Q4) after being passed
through the ALC attenuator (D4). The signal is amplified at
the YGR (Q3) and power amplifier (Q2) to obtain 5 W of RF
power (at 9.6 V DC). The amplified signal passes through
the low-pass filter (L5, C11–C16). The filtered signal is
applied to the antenna connector (CHASSIS unit; J1) via the
antenna swtich (D1) and low-pass filter (L1–L3, C3–C7).
4-2-4 ALC CIRCUIT (RF UNIT)
The ALC (Automatic Level Control) circuit protects the drive
and power amplifiers from mismatched output loads, and
selects HIGH or LOW output power.
The power detector circuit (D2, D3) detects forward and
reflection signals respectively. The combined voltage is at a
minimum level when the antenna is matched at 50 Ω and is
increased when it is mismatched.
The detected voltage is amplified at the ALC amplifier (Q5)
after being passed through the ALC controller (Q1). The
amplified signal is applied to the ALC attenuator (D4) to
obtain stabilized output power.
When the antenna impedance is mismatched, the detected
voltage exceeds the reference voltage. Thus, the bias voltage of the pre-driver is decreased.
4 - 4
R11
T+5
PWR
DET
D2, D3
"RFDET" signal to the CPU
(LOGIC unit; IC1, pin 4)
LPF
Q2
Power
amplifier
VCC
Q3Q4
YGR
amplifier
VCCT+5
Pre-drive
D4
ALC
ATT
ALC
amplifier
R25
R26
C38
Q5
C38
TX signal from the
buffer amplifier (Q6)
To the antenna
Q1
From the D/A converter
(IC4, pin 6)
C37
R24
R23
• ALC CIRCUIT
4 - 5
4-3 PLL CIRCUIT (RF UNIT)
A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the VCO circuit (Q31, Q32, D27).
The oscillated signal is amplified at the buffer-amplifiers (RF
unit; Q30, Q29) and then applied to the PLL IC (IC1, pin 2).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the reference frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
A portion of the VCO signal is amplified at the buffer-amplifier (Q27, Q28) and is then applied to the receive 1st mixer
(Q12) or transmit buffer-amplifier circuit (Q6) via the T/R
switching diode (D6, D17).
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
Cont.
16/17
PLL
Loop
filter
OSC Tr
VCO
Buffer
Buffer
Buffer
Q27
Buffer
Q28
Q29
Q30
R134, R135,
C168, C169
3
4
5
PCK
IC3 (PLL IC)
PDATA
PSTB
to 1st mixer circuit
D17
D6
9
12
13
14
11
8
Q31, Q32, D24
C198C177
From IC4, pin 14
C175
"2ndLO" signal to the
IF IC (IC1, pin 2)
X2
R158
to transmitter circuit
"UNLK" signal to the CPU
(LOGIC unit; IC1, pin 48)
LINE
HV
VCC
+5V
T+5
R5
DESCRIPTION
The voltage from the external power supply.
The same voltage as the HV line or battery volt-
age through the power switch (RF unit; Q24).
Common 5 V converted from the VCC line by the
+5 V regulator circuit (LOGIC unit; IC16 or IC3,
D9). The output voltage is applied to the CPU
(LOGIC unit; IC1), reset circuit (LOGIC unit;
IC2), and etc.
5 V for transmitter circuits regulated by the TX
control circuit (RF unit; Q7, Q8, D7). The output
voltage is applied to the LO switch (RF unit; D6),
buffer amplifier (RF unit; Q6), pre-driver (RF unit;
Q4) and etc.
5 V for receiver circuits regulated by the RX control circuit (RF unit; Q20). The output voltage is
applied to the LO switch (RF unit; D17), AM
detector (RF unit; Q18), IF amplifiers (RF unit;
Q17, Q16, Q15), IF IC (RF unit; IC1, pin 4) and
etc.
• PLL CIRCUIT
4 - 6
Pin
number
5
7
11
12
13
14
Port
name
DETMITE
R5C
WXC
ANLC
EMBI
AFC
Description
Outputs detector mute signal to the
AM/FM select switch (IC2, pin 2).
Outputs receiver 5V control signal to
the RX controller (Q20).
Outputs AM/FM (WX ch) select signal
to the RX shift circuit (Q34, D25) and
AM/FM select switch (IC2, pin 5).
Outputs control sigal to the ANLswitch
(Q21).
Outputs control signal to the external
microphone controller (Q25, Q26,
D23, D27).
Outputs control signal to the AF out
cotnroller (Q35, Q36) for the AF power
amplifier (IC6).
4-5-2 SHIFT RESISTOR (RF UNIT; IC5)
Pin
number
4
5
6
7
11
12
13
Port
name
VORON
PLAYC
RECC
LIGHTC
BLEDC
MMUTE
ALCC
Description
Outputs control signal to the VOR
controller (Q15).
Outputs playback control signal to the
voice rec/play IC (IC15, pin 23).
Outputs recording control signal to the
voice rec/play IC (IC15, pin 27).
Outputs LCD backlight control signal.
Outputs BUSY LED control signal.
Outputs control signal to the Mic mute
switch (Q12) for internal microphone.
Outputs control signal to the ALC con-
troller (Q11).
4-5-3 SHIFT RESISTOR (LOGIC UNIT; IC8)
4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC UNIT; IC1)
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12,
21
17
18
19
20
22
23
24
25
32
33
47
48
54
55
Port
name
VIN
VORD
RSSI
RFDETV
THRMC
SBATT
PDATA
PCK
PSTB
BEEP
VORS
DICK,
DIUD
LIGHT
BPCPI
CLOUT
CLIN
VORC
POWER
PTT
JACKDET
DCC
RESET
EDATA
UNLK
PCON
ECK
Description
Input port for the battely voltage
detection.
Input port for the VOR signal detection.
Input port for the receive signal level.
Input port for the power detection of
power amplifier (RF unit; Q2).
Input port for the transceiver’s internal
temperature.
Input port for the battely type detec-
tion.
Outputs data signals to the PLLIC (RF
unit; IC3).
Outputs clock signal to the PLL IC.
Outputs strobe signals to the PLL IC.
Outputs beep audio signals.
Input port for the 30 Hz phase signal.
Input port for [DIAL].
Input port for [LIGHT] switch.
Outputs the bias control signal for a
type of battery.
Outputs the cloning signal.
Input port for the cloning signal.
Input port for the VOR 30 Hz standard
signal.
Input port for [POWER] swtich.
Input port for the [PTT] swtich.
High:While [PTT] switch is pushed.
Input port for the external SP jack connection detection.
High: While the external SP jack is
connected.
Input port for the external DC connection detection.
Input port for the CPU reset signal.
• Input port for the data signals from
the EEPROM (LOGIC unit; IC7).
• Outputs data signals to the EEPROM IC.
Input port for the PLL unlock signal.
Low: PLL is unlocked.
Outputs control signal for the 5V regulator.
Outputs clock signal to the EEPROM
IC (LOGIC unit; IC7).
Loading...