IBM DS-2000 User Manual

WARRANTY INFORMATION

Qua Tech Inc. warrants the DS-2000 free of defects for one purchase. Qua Tech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee the accuracy of this manual, Qua Tech Inc. assumes no liability for damages resulting from errors in this document. Qua Tech Inc. reserves the right to edit or append to this document at any time without notice.

Please complete the following information and retain for your records. Have this information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: DS-2000

PRODUCT DESCRIPTION: DUAL

(1) year from the date of

CHANNEL RS-422 ASYNC.

to be

COMMUNICATIONS

SERIAL NUMBER:

IBM PC/XT/ATTM, PS/2TM, and MicroChannelTM are trademarks of International Business Machines.

ADAPTER

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TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

LIST OF FIGURES . . . . . . . . . . . . . iii

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16550 FUNCTIONAL DESCRIPTION . . . . . . . . 3

A. INTERRUPT ENABLE REGISTER . . . . . . . . 4

B. INTERRUPT IDENTIFICATION REGISTER . . . . 5

C. FIFO CONTROL REGISTER . . . . . . . . . . 7

D. LINE CONTROL REGISTER . . . . . . . . . . 8

E. MODEM CONTROL REGISTER . . . . . . . . . 10

F. LINE STATUS REGISTER . . . . . . . . . . 11

G. MODEM STATUS REGISTER . . . . . . . . . . 13

H. SCRATCHPAD REGISTER . . . . . . . . . . . 14

IV. FIFO INTERRUPT MODE OPERATION . . . . . . . 14

V. BAUD RATE SELECTIONS . . . . . . . . . . . . 14

VI. ADDRESSING . . . . . . . . . . . . . . . . . 16

VII. INTERRUPTS . . . . . . . . . . . . . . . . . 16

VIII. PROGRAMMABLE OPTION SELECT . . . . . . . . . 16

IX. OUTPUT CONFIGURATIONS . . . . . . . . . . . 19

X. EXTERNAL CONNECTIONS . . . . . . . . . . . . 23

XI. INSTALLATION . . . . . . . . . . . . . . . . 24

XII. SPECIFICATIONS . . . . . . . . . . . . . . . 24

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LIST OF FIGURES

Figure 1. DS-2000 board layout . . . . . . . . . 2

Figure 2. 16550 internal registers . . . . . . . 3

Figure 3. Interrupt enable register . . . . . . 4

Figure 4. Interrupt identification register . . 5 Figure 5. Interrupt source identification . . . 6

Figure 6. FIFO control register . . . . . . . . 7

Figure 7. FIFO receiver trigger levels . . . . . 7

Figure 8. Line control register . . . . . . . . 8

Figure 9. Parity options . . . . . . . . . . . . 9

Figure 10. Word length and stop bit options . . . 9

Figure 11. MODEM control register . . . . . . . . 10

Figure 12. Line status register . . . . . . . . . 11

Figure 13. MODEM status register . . . . . . . . 13

Figure 14. Input clock frequency options . . . . 15

Figure 15. Divisor latch options . . . . . . . . 15

Figure 16. POS implementation . . . . . . . . . . 17

Figure 17. Base address locations . . . . . . . . 18

Figure 18. Interrupt request levels . . . . . . . 18

Figure 19. Output control block diagram . . . . . 21

Figure 20. J2/J3 layout and settings . . . . . . 21

Figure 21. Auxiliary channel configuration

(handshake mode) . . . . . . . . . 22

Figure 22. Auxiliary channel configuration

(external clock mode) . . . . . . . 22

Figure 23. Auxiliary channel configuration

(loopback mode) . . . . . . . . . . 22

Figure 24. Output connections . . . . . . . . . . 23

Figure 25. Output signal definitions . . . . . . 23

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I. INTRODUCTION

The DS-2000 is a dual channel asynchronous serial communication adapter which utilizes balanced differential drivers and receivers to provide RS-422-A communications. It is capable of reliable communications over long distances (4000 feet) within noisy industrial environment. Data is communicated through two D-9 connectors which provide shielding from environmental noise. Optional high speed transient suppressers may also be installed on the DS-2000 to further reduce the effects of environmental signal transients and surges.

The serial interface is accomplished through a pair of 16550 Asynchronous Communication Elements (ACEs). The 16550 is compatible with the 8250 and 16450 ACEs used in the IBM PC/XT/AT models. The 16550 also has an additional FIFO mode that reduces CPU overhead at higher data rates.

The DS-2000 supports sixteen base addresses for each ACE through the Programmable Option Select (POS) including the eight addresses designated SERIAL 1 through SERIAL 8. The addresses are independent for each channel. CPU interrupt level selections are also handled through the POS. Each channel may select a separate interrupt or share an interrupt level with other devices.

II. BOARD

DESCRIPTION

A component diagram of the DS-2000 showing the locations of the 16550 ACEs, configuration jumpers, and D-9 connectors is shown in figure 1. The first communication channel is controlled by the 16550 labeled U9, jumper J2, and is accessed through the connector labeled CN1. The second channel uses the 16550 labeled U10, jumper J3, and is accessed through the connector labeled CN2. The clock rate divider for both channels is controlled by jumper J1.

iii

FUNCTIONAL DESCRIPTION

Figure 1. DS-2000 board layout.

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FUNCTIONAL DESCRIPTION

III. 16550 FUNCTIONAL DESCRIPTION

The 16550 is an upgrade of the standard 16450 Asynchronous Communications Element (ACE). Designed to be compatible with the 16450, the 16550 enters the character mode on reset and in this mode will appear as a 16450 to user software. An additional mode, FIFO mode, can be selected to reduce CPU overhead at high data rates. The FIFO mode increases performance by providing two internal 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.

Other features of the 16550 include: Programmable baud rate, character length, parity, and number of stop bits Automatic addition and removal of start, stop, and parity bits Independent and prioritized transmit, receive and status interrupts Transmitter clock output to drive receiver logic External receiver clock input

The following pages provide a brief summary of the internal registers available within the 16550 ACE. The registers are addressed as shown in figure 2 below.

+---------------+-----------------------------------+ | DLAB A2 A1 A0 | REGISTER DESCRIPTION | +---------------+-----------------------------------+ | 0 0 0 0 | Receive buffer (read) | | | Transmit holding register (write) | | 0 0 0 1 | Interrupt enable | | x 0 1 0 | Interrupt identification (read) | | | FIFO control (write) | | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (least significant) | | 1 0 0 1 | Divisor latch (most significant) | +---------------+-----------------------------------+

Figure 2. Internal register map for 16550 ACE. DLAB is accessed through the Line Control Register.

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FUNCTIONAL DESCRIPTION

A. INTERRUPT

ENABLE REGISTER

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmitter holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+

Figure 3. Interrupt enable register bit definitions.

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and data carrier detect.

ELSI - Receiver Line Status Interrupt:

When set (logic 1), enables interrupt on overrun, parity, and framing errors, and break indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupt on transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupt on received data available or FIFO trigger level.

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FUNCTIONAL DESCRIPTION

B. INTERRUPT

IDENTIFICATION REGISTER

+------+ D7 | FFE |----- FIFO enable (FIFO only) +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+

Figure 4. Interrupt identification register bit

definitions.

FFE - FIFO Enable:

When logic 1, indicates FIFO mode enabled.

IIDx - Interrupt Identification:

Indicates highest priority interrupt pending if any. See IP and figure 5. NOTE: IID2 is always a logic 0 in character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See IIDx and figure 5.

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FUNC TIONAL DESCRIPTION

Figure 5. Interrupt identification bit definitions.

Receiver Line Status:

Indicates overrun, parity, or framing errors or break interrupts. The interrupt is cleared by reading the line status register.

Received Data Ready:

Indicates receive data available. The interrupt is cleared by reading the receiver buffer register.

FIFO mode:

Indicates the receiver FIFO trigger level has been reached. The interrupt is reset when the FIFO drops below the the trigger level.

Character Timeout: (FIFO mode only)

Indicates no characters have been removed from or input to the receiver FIFO for the last four character times and there is at least one character in the FIFO during this time. The interrupt is cleared by reading the receiver FIFO.

Transmitter Holding Register Empty:

Indicates the transmitter holding register is empty. The interrupt is cleared by reading the interrupt identification register or writing to the transmitter holding register.

MODEM Status:

Indicates clear to send, data set ready, ring indicator, or data carrier detect have changed state. The interrupt is cleared by reading the MODEM status register.

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IBM DS-2000 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual