HYUNDAI GMS81508B, GMS81516B, GMS81524B User Guide

GMS81508B K

HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81508B

GMS81516B

GMS81524B

User’s Manual (Ver. 1.04)

+ < 8 1 ' $ ,

MicroElectronics

Semiconductor Group of Hyundai Electronics Industrial Co., Ltd.

Version 1.04

Published by

MCU Application Team

©1999 HYUNDAI Micro Electronics All right reserved.

Additional information of this manual may be served by HYUNDAI Micro Electronics offices in Korea or Distributors and Representatives listed at address directory.

HYUNDAI Micro Electronics reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, HYUNDAI Micro Electronics is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

HYUNDAI MicroElectronics

GMS81508B/16B/24B

Table of Contents
1. OVERVIEW............................................	1
Description .........................................................	1
Features .............................................................	1
Development Tools ............................................	2
Ordering Information ..........................................	2
2. BLOCK DIAGRAM .................................	3
3. PIN ASSIGNMENT ................................	4
4. PACKAGE DIAGRAM ............................	6
5. PIN FUNCTION......................................	8
6. PORT STRUCTURES..........................	10
7. ELECTRICAL CHARACTERISTICS ....	12
Absolute Maximum Ratings .............................	12
Recommended Operating Conditions ..............	12
A/D Converter Characteristics .........................	12
DC Electrical Characteristics ...........................	13
AC Characteristics ...........................................	14
Serial Interface Timing Characteristics ............	15
Typical Characteristic Curves ..........................	16
8. MEMORY ORGANIZATION.................	18
Registers ..........................................................	18
Program Memory .............................................	21
Data Memory ...................................................	24
Addressing Mode .............................................	27
9. I/O PORTS ...........................................	31
10. BASIC INTERVAL TIMER..................	34
11. TIMER/EVENT COUNTER ................	36
8-bit Timer / Counter Mode ..............................	38
16-bit Timer / Counter Mode ............................	42
8-bit Capture Mode ..........................................	43
16-bit Capture Mode ........................................	44
12. ANALOG DIGITAL CONVERTER......	46
13. SERIAL COMMUNICATION ..............	48

Transmission/Receiving Timing ......................	50
The Serial I/O operation by SRDY pin ............	50
The method of Serial I/O .................................	51
The Method to Test Correct Transmission ......	51
14. PWM OUTPUT ..................................	52
15. BUZZER FUNCTION .........................	55
16. INTERRUPTS ....................................	57
Interrupt Sequence ..........................................	59
BRK Interrupt ..................................................	60
Multi Interrupt ..................................................	61
External Interrupt .............................................	61
17. WATCHDOG TIMER .........................	64
18. POWER DOWN OPERATION...........	66
STOP Mode ....................................................	66
Minimizing Current Consumption ....................	67
19. OSCILLATOR CIRCUIT.....................	69
20. RESET ...............................................	70
External Reset Input ........................................	70
Watchdog Timer Reset ...................................	70
21. POWER FAIL PROCESSOR.............	71
22. OTP PROGRAMMING.......................	73
How to Program ..............................................	73
Pin Function ....................................................	73
Programming Specification .............................	76
A. CONTROL REGISTER LIST ..................	i
B. SOFTWARE EXAMPLE .......................	iii
7-segment LED display ....................................	iii
C. INSTRUCTION....................................	viii
Terminology List ..............................................	viii
Instruction Map ..................................................	ix
Instruction Set ....................................................	x
D. MASK ORDER SHEET ......................	xvi

DEC. 1999 Ver 1.04

HYUNDAI MicroElectronics

GMS81508B/16B/24B

GMS81508B/16B/24B

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH A/D CONVERTER

1. OVERVIEW

1.1 Description

The GMS81508B/16B/24B are advanced CMOS 8-bit microcontrollers with 8K/16K/24K bytes of ROM. The device is one of GMS800 family. This device using the GMS800 family CPU includes several peripheral functions such as Timer, A/D converter, Programmable buzzer driver, Serial I/O communication, Pulse Width Modulation function, etc. The RAM, ROM, and I/O are placed on the same memory map in addition to simple instruction set.

The GMS815xxB is functionally 100% compatible with earier GMS81508/16 or GMS81508A/16A, however better characteristics have such as strong EMS, wide operating voltage, temperature, frequency and fast programming time for the OTP.

	Device name	ROM Size	RAM Size	OTP	Package
	GMS81508B	8K bytes	448 bytes	GMS81516BT
					64SDIP, 64MQFP,
	GMS81516B	16K bytes	448 bytes	GMS81516BT
					64LQFP
	GMS81524B	24K bytes	448 bytes	GMS81524BT

1.2 Features

•8K/16K/24K Bytes On-chip Program Memory

•448 Bytes of On-chip Data RAM (Included stack memory)

•Minimum Instruction Execution Time 0.5μs at 8MHz

•One 8-bit Basic Interval Timer

•Four 8-bit Timer/Event counter

or Two 16-bit Timer/Event counter

•One 6-bit Watchdog timer

•Eight channel 8-bit A/D converter

•Two channel 8-bit PWM

•One 8-bit Serial Communication Interface

•Four External Interrupt input ports

•Buzzer Driving port

-500Hz ~ 250kHz@8MHz

•52 I/O Ports, 4 Input Ports

•Twelve Interrupt sources

-Basic Interval Timer: 1

-External input: 4

-Timer/Event counter: 4

-ADC: 1

-Serial Interface: 1

-WDT: 1

•Built in Noise Immunity Circuit

-Noise filter

-Power fail processor

•Power Down Mode

-STOP mode

•2.2V to 5.5V Wide Operating Range

•1~10MHz Wide Operating Frequency

•64SDIP, 64MQFP, 64LQFP package types

•Available 16K, 24K bytes OTP version

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1.3 Development Tools

The GMS815xxB are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Jr.TM and OTP programmers. There are third different type programmers such as emulator add-on board type, single type, gang type. For mode detail, Refer to “22. OTP PROGRAMMING” on page 73. Macro assembler operates under the MS-Windows 95/98TM.

Please contact sales part of Hyundai MicroElectronics.

1.4 Ordering Information

		Device name	ROM Size	RAM size	Package
		GMS81508B K	8K bytes	448 bytes	64SDIP
		GMS81508B Q	8K bytes	448 bytes	64MQFP
		GMS81508B LQ	8K bytes	448 bytes	64LQFP
		GMS81516B K	16K bytes	448 bytes	64SDIP
	Mask version	GMS81516B Q	16K bytes	448 bytes	64MQFP
		GMS81516B LQ	16K bytes	448 bytes	64LQFP
		GMS81524B K	24K bytes	448 bytes	64SDIP
		GMS81524B Q	24K bytes	448 bytes	64MQFP
		GMS81524B LQ	24K bytes	448 bytes	64LQFP
		GMS81516BT K	16K bytes OTP	448 bytes	64SDIP
		GMS81516BT Q	16K bytes OTP	448 bytes	64MQFP
	OTP version	GMS81516BT LQ	16K bytes OTP	448 bytes	64LQFP
		GMS81524BT K	24K bytes OTP	448 bytes	64SDIP
		GMS81524BT Q	24K bytes OTP	448 bytes	64MQFP
		GMS81524BT LQ	24K bytes OTP	448 bytes	64LQFP

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GMS81508B/16B/24B

2. BLOCK DIAGRAM

ADC Power

Supply

DD	SS
AV	AV

R00~R07

R10~R17

R20~R27

R30~R37

R0

R1

R2

R3

PSW

ALU

A

X

Y

Stack Pointer

Data Memory

PC

(448 bytes)

	Program
Interrupt Controller	Memory
	Data Table

System controller

8-bit Basic

Interval

System

Timer

Clock Controller

8-bit

8-bit serial

8-bit PWM

8-bit

PC

Timing generator

Watchdog

Timer/

Interface

ADC

Timer

Counter

ClockGenerator

RESET		TEST	IN	OUT	DD		SS
			X	X	V		V

Power

Supply

Buzzer

R4

R5

R6

Driver

R40

/ INT0

R50

/ SIN

R60 / AN0

R41

/ INT1

R51

/ SOUT

R61 / AN1

R42

/ INT2

R52

/ SCLK

R62 / AN2

R43

/ INT3

R53

/ SRDY

R63 / AN3

R44

/ EC0

R54

/ WDTO

R64 / AN4

R45

/ EC2

R55

/ BUZ

R65 / AN5

R46

/ T1O

R56

/ PWM0

R66 / AN6

R47

/ T3O

R57

/ PWM1

R67 / AN7

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3. PIN ASSIGNMENT

64SDIP (Top View)

		VDD							1
		TEST							2
		AVSS							3
		AVDD							4
AN7		R67							5
AN6		R66							6
AN5		R65							7
AN4		R64							8
AN3		R63							9
AN2		R62							10
AN1		R61							11
AN0		R60							12
PWM1		R57							13
PWM0		R56							14
BUZ		R55							15
WDTO		R54							16
SRDY		R53							17
SCLK		R52							18
SOUT		R51							19
SIN		R50							20
T3O		R47							21
T1O		R46							22
EC2		R45							23
EC0		R44							24
INT3		R43							25
INT2		R42							26
INT1		R41							27
INT0		R40							28
	RESET								29
		XIN							30
	XOUT								31
		VSS							32

GMS81508B/16B/24B

64 R30 63 R31 62 R32 61 R33 60 R34 59 R35 58 R36 57 R37 56 R00 55 R01 54 R02 53 R03 52 R04 51 R05 50 R06 49 R07 48 R10 47 R11 46 R12 45 R13 44 R14 43 R15 42 R16 41 R17 40 R20 39 R21 38 R22 37 R23 36 R24 35 R25 34 R26 33 R27

64MQFP (Top View)

R36

R35

R34

R33

R32

R31

R30

VDD

TEST

AVSS

AVDD

AN7 R67

AN6 R66

R37

51 52

53

54

55

56

57

58

59

60

61

62

63 64 1

R65

AN5

R00		R01		R02
50		49		48

2 3 4
R64		R63			R62
AN4		AN3			AN2

47 R03

AN1 R61 5

R04		R05		R06		R07		R10		R11		R12		R13		R14		R15
46		45		44		43		42		41		40		39		38		37

GMS81508B/16B/24B

6 7 8 9

10 11

12 13 14 15

R60

R57

R56

R55

R54

R53

R52

R51

R50

R47

AN0

PWM1

PWM0

BUZ

WDTO

SRDY

SCLK

SOUT

SIN

T3O

R16		R17
36		35

16		17
R46			R45
T1O			EC2

34 R20

EC0 R44 18

33 R21

INT3 R43 19

32

31

30

29

28

27

26

25

24

23

22

21

20

R22

R23

R24

R25

R26

R27

VSS

XOUT

XIN

RESET

R40 INT0

R41 INT1

R42 INT2

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GMS81508B/16B/24B

64LQFP (Top View)

R00

R01

R02

R03

R04

R05

R06

R07

R10

R11

R12

R13

R14

R15

R16

R17

48

47 46 45

44 43 42 41

40 39

38

37 36 35

34

33

R37

49

32

R20

R36

50

31

R21

R35

51

30

R22

R34

52

29

R23

R33

53

28

R24

R32

54

27

R25

R31

55

26

R26

R30

56

GMS81508B/16B/24B

25

R27

VDD

57

24

VSS

TEST

58

23

XOUT

AVSS

59

22

XIN

AVDD

60

21

RESET

AN7

R67

61

20

R40

INT0

AN6

R66

62

19

R41

INT1

AN5

R65

63

18

R42

INT2

AN4

R64

64

17

R43

INT3

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16

R63

R62

R61

R60

R57

R56

R55

R54

R53

R52

R51

R50

R47

R46

R45

R44

AN3

AN2

AN1

AN0

PWM1

PWM0

BUZ

WDTO

SRDY

SCLK

SOUT SIN

T3O

T1O

EC2

EC0

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4. PACKAGE DIAGRAM

64SDIP

				2.280
					2.260
0.205 max.																																				min. 0.015

0.022	0.050	0.070 Typ.	0.140	0.120
0.016	0.030

UNIT: INCH

0.750 Typ.

0.680

0.660

		2
		0.01
		8
0-15°		0.00

64MQFP

							24.15																																								UNIT: MM
							23.65
							20.10
							19.90

18.15

17.65

14.10

13.90

		0-7°
SEE DETAIL “A”	0.10	0.73	0.23	0.13
0.36
		1.03
3.18 max.		1.95
		REF

0.501.00 Typ.

0.35

DETAIL “A”

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GMS81508B/16B/24B

64LQFP

12.00 Typ.

10.00 Typ.

UNIT: MM

12.00 Typ.

10.00 Typ.

1.45	1.35
		0-7°
SEE DETAIL “A”
0.15	0.05	0.75
		0.45
1.60 max.		1.00
		REF

0.380.50 Typ.

0.22	DETAIL “A”

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5. PIN FUNCTION

VDD: Supply voltage.

VSS: Circuit ground.

TEST: Used for Test Mode. For normal operation, it should be connected to VDD.

RESET: Reset the MCU.

XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit.

XOUT: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R20~R27: R2 is an 8-bit CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R30~R37: R3 is an 8-bit CMOS bidirectional I/O port. R3 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

In addition, R4 serves the functions of the various following special features.

Port pin	Alternate function
R40	INT0 (External interrupt 0)
R41	INT1 (External interrupt 1)
R42	INT2 (External interrupt 2)
R43	INT3 (External interrupt 3)
R44	EC0 (Event counter input 0)
R45	EC2 (Event counter input 2)
R46	T1O (Timer/Counter 1 output)
R47	T3O (Timer/Counter 3 output)

R50~R57: R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

In addition, R5 serves the functions of the various following special features.

Port pin

Alternate function

R50 SIN (Serial data input)

R51 SOUT (Serial data output)

R52 SCLK (Serial clock)

R53 SRDY (Serial ready)

R54 WDTO (Watchdog Timer output)

R55 BUZ (Buzzer driver output)

R56 PWM0 (PWM output 0)

R57 PWM1 (PWM output 1)

R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

In addition, R6 is shared with the ADC input.

Port pin	Alternate function
R60	AN0 (Analog Input 0)
R61	AN1 (Analog Input 1)
R62	AN2 (Analog Input 2)
R63	AN3 (Analog Input 3)
R64	AN4 (Analog Input 4)
R66	AN5 (Analog Input 5)
R66	AN6 (Analog Input 6)
R67	AN7 (Analog Input 7)

Note: On the MDS Choice, when the MCU is RESET, R60 can not be used digital input port. For more detail, refer to "9. I/O PORTS" on page 31.

AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source.

AVSS: ADC circuit ground.

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GMS81508B/16B/24B

			PIN NAME					In/Out		Function
									Basic		Alternate
	VDD							-	Supply voltage
	VSS							-	Circuit ground
									Controls test mode of the chip,
	TEST							I
									For normal operation, it should be connected at VDD.
								I	Reset signal input
	RESET
	XIN							I	Oscillation input
	XOUT							O	Oscillation output
	R00~R07							I/O	8-bit general I/O ports
	R10~R17							I/O	8-bit general I/O ports
	R20~R27							I/O	8-bit general I/O ports
	R30~R37							I/O	8-bit general I/O ports
	R40	(INT0)						I/O (I)			External interrupt 0 input
	R41	(INT1)						I/O (I)			External interrupt 1 input
	R42	(INT2)						I/O (I)			External interrupt 2 input
	R43	(INT3)						I/O (I)	8-bit general I/O ports		External interrupt 3 input
	R44							I/O (I)			Timer/Counter 0 external input
			(EC0)
	R45							I/O (I)			Timer/Counter 2 external input
			(EC2)
	R46	(T1O)						I/O (O)			Timer/Counter 1 output
	R47	(T3O)						I/O (O)			Timer/Counter 3 output
	R50	(SIN)						I/O (I)			Serial data input
	R51	(SOUT)						I/O (O)			Serial data output
	R52	(SCLK)						I/O (I/O)			Serial clock I/O
	R53							I/O (I/O)			Receive enable I/O
			(SRDY)						8-bit general I/O ports
	R54	(WDTO)						I/O (O)			Watchdog timer overflow output
	R55	(BUZ)						I/O (O)			Buzzer driving output
	R56	(PWM0)						I/O (O)			PWM pulse output
	R57	(PWM1)						I/O (O)
	R60~R63 (AN0~AN3)							I (I)	General input ports		Analog voltage input
	R64~R67 (AN4~AN7)							I/O (I)	General I/O ports
	AVSS							-	Ground level input pin for ADC
	AVDD							-	Supply voltage input pin for ADC

Table 5-1 Port Function Description

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6. PORT STRUCTURES

R00~R07, R10~R17, R20~R27, R30~37
	VDD
	Data Reg.
Bus	Dir.	Pin
	Reg.
Data
	VSS
	MUX
	Rd
R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/
EC0, R45/EC2, R50/SIN

		PMR Selection
			VDD
		Data Reg.
	Bus	Direction	Pin
	Data
		Reg.
		M UX	VSS
		Rd
	EX) INT0
	Alternate Function
	R46/T1O, R47/T3O, R51/SOUT, R54/WDTO
	R55BUZ, R56/PWM0, R57/PWM1

	Selection
		VDD
Secondary function
	M UX
	Data Reg.	Pin
Data Bus	Direction	VSS
	Reg.
	M UX
	Rd
10

R52/SCLK
	Selection
			VDD
SCK Output
		M UX
	Data Reg.		Pin
Bus	Direction		VSS
	Reg.
			M UX
Data		exck
		M U X
		Rd
SCK Input
S53/SRDY
Selection
SRDY

VDD

SRDY Output

M UX

Pin

Data Reg.

Direction

VSS

BusData

Reg.

M UX

Rd

SRDY Input

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GMS81508B/16B/24B

R60/AN0 ~ R63/AN3

RESET

VDD

VDD

Data bus

RESET

Rd

VSS

To A/D converter

VSS

R64/AN7 ~ R67/AN7
		VDD
	Data Reg.
Bus	Dir.	Pin
	Reg.
Data
		VSS
	M U X
	Rd
	To A/D converter
XIN, XOUT

	VDD
XIN
	VSS
XOUT	VSS
	Stop

TEST

				VDD
								OTP version: disconnected
								Mask version: connected
TEST

VSS

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7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage .............................................	-0.3 to +7.0 V
Storage Temperature ..................................	-40 to +125 °C
Voltage on any pin with respect to Ground (VSS)
..................................................................	-0.3 to VDD+0.3
Maximum current out of VSS pin ..........................		150 mA
Maximum current into VDD pin ..............................		80 mA
Maximum current sunk by (IOL per I/O Pin) ..........		20 mA

Maximum output current sourced by (IOH per I/O Pin)

................................................................................... 8 mA

7.2 Recommended Operating Conditions

Maximum current (ΣIOL) ......................................	100 mA
Maximum current (ΣIOH)........................................	50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

	Parameter	Symbol	Condition	Specifications		Unit
				Min.	Max.
			fXIN=1 ~ 10 MHz	4.5	5.5
	Supply Voltage	VDD	fXIN=1 ~ 8 MHz	2.7	5.5	V
			fXIN=1 ~ 4 MHz	2.2	5.5
			VDD=4.5~5.5V	1	10
	Operating Frequency	fXIN	VDD=2.7~5.5V	1	8	MHz
			VDD=2.2~5.5V	1	4
	Operating Temperature	TOPR	Normal Version	-20	85	°C
			Temperature Extention Version	-40	85

7.3 A/D Converter Characteristics

(TA=25°C, VSS=0V, VDD=5.12V@fXIN=8MHz, VDD=3.072V@fXIN=4MHz)

				Specifications
Parameter	Symbol		Min.	Typ.1	Max.		Unit
					fXIN=4MHz	fXIN=8MHz
Analog Input Voltage Range	VAIN		VSS	-	AVDD	AVDD	V
Non-linearity Error	NNLE		-	±1.0	±1.5	±1.5	LSB
Differential Non-linearity Error	NDNLE		-	±1.0	±1.5	±1.5	LSB
Zero Offset Error	NZOE		-	±0.5	±1.5	±1.5	LSB
Full Scale Error	NFSE		-	±0.35	±0.5	±0.5	LSB
Gain Error	NGE		-	±1.0	±1.5	±1.5	LSB
Overall Accuracy	NACC		-	±1.0	±1.5	±1.5	LSB
AVDD Input Current	IREF		-	0.5	1.0	1.0	mA
Conversion Time	TCONV		-	-	40	20	μs

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GMS81508B/16B/24B

				Specifications
Parameter	Symbol		Min.	Typ.1		Max.		Unit
						fXIN=4MHz	fXIN=8MHz
Analog Power Supply Input Range	AVDD		0.9VDD	VDD		1.1VDD		V

1. Data in “Typ” column is at 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested.

7.4 DC Electrical Characteristics

(TA=-20~85°C, VDD=2.7~5.5V, Ta= -20~85°C, fXIN=8MHz, VSS=0V),

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.1

Max.

VIH1

V

=4.5

XIN,

RESET,

0.8VDD

-

VDD+0.3

V

Input High Voltage

DD

R4, R5, R6

VDD=2.7

VIH2

R0, R1, R2, R3

0.7VDD

-

VDD+0.3

XIN,

VIL1

V

=4.5

RESET,

-

0.2VDD

V

Input Low Voltage

DD

R4, R5, R6

VDD=2.7

VIL2

R0, R1, R2, R3

-

0.3VDD

VDD=4.5

R0,R1,R2,R3,R4,R5

Output High Voltage

VOH

VDD=2.7

VDD-1.0

-

-

V

R6

I

=-2mA

OH1

VDD=4.5

R0,R1,R2,R3,R4,R5

Output Low Voltage

VOL

VDD=2.7

-

-

1.0

V

R6

IOL1=5mA

Power Fail Detect

VPFD

VPFD=3.0V

@ TA=25°C

0.9VPFD

1.1VPFD

V

Voltage

VPFD=2.4V

Input High

IIH1

VIN=VDD

All input pins

-5.0

-

5.0

μA

Leakage Current

Input Low

IIL

VIN=VSS

All input pins

-5.0

-

5.0

μA

Leakage Current

Hysteresis

VT+, VT-

RESET,

EC0,

EC2,

0.3

0.8

V

SIN, SCLK, INT0~INT3

IDD1

fXIN=8M Hz

All input = VSS

-

8

20

mA

Crystal O scillator,

Power Current

IDD2

fXIN=4M Hz

4

10

mA

CL1=CL2=30pF

ISTOP

All input = VSS

-

1

10

μA

1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

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7.5 AC Characteristics

(TA=-20~+85°C, VDD=5V±10%, VSS=0V)

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

Operating Frequency

fXIN

XIN

1.0

-

10.0

MHz

Oscillation Stabilizing

tST

XIN, XOUT

-

-

20

ms

Time

External Clock Pulse

tCPW

XIN

40

-

-

ns

Width

External Clock Transi-

tRCP,tFCP

XIN

-

-

20

ns

tion Time

Interrupt Pulse Width

tIW

INT0, INT1, INT2, INT3

2

-

-

tSYS

Input Width

tRST

8

-

-

tSYS

RESET

RESET

Event Counter Input

tECW

tSYS

EC0, EC2

2

-

-

Pulse Width

Event Counter Transi-

tREC,tFEC

EC0, EC2

-

-

20

ns

tion Time

t

SYS = 1/fXIN

tCPW

tCPW

VDD-0.5V

XIN

0.5V

t

RCP

t

FCP

tIW

tIW

0.8VDD

INT0~INT3

0.2VDD

tRST

RESET

0.2VDD

tECW tECW

0.8VDD

EC1, EC2

0.2VDD

tREC	t
	FEC

Figure 7-1 Timing Chart

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GMS81508B/16B/24B

7.6 Serial Interface Timing Characteristics

(TA=-20~+85°C, VDD=5V±10%, VSS=0V, fXIN=8MHz)

Parameter	Symbol	Pins		Specifications				Unit
			Min.		Typ.		Max.
Serial Input Clock Pulse	tSCYC	SCLK	2tSYS+200		-		8	ns
Serial Input Clock Pulse Width	tSCKW	SCLK	tSYS+70		-		8	ns
Serial Input Clock Pulse Transition	tFSCK	SCLK	-		-		30	ns
Time	tRSCK
SIN Input Pulse Transition Time	tFSIN	SIN	-		-		30	ns
	tRSIN
SIN Input Setup Time (External SCLK)	tSUS	SIN	100		-		-	ns
SIN Input Setup Time (Internal SCLK)	tSUS	SIN	200		-			ns
SIN Input Hold Time	tHS	SIN	tSYS+70		-			ns
Serial Output Clock Cycle Time	tSCYC	SCLK	4tSYS		-		16tSYS	ns
Serial Output Clock Pulse Width	tSCKW	SCLK	tSYS-30					ns
Serial Output Clock Pulse Transition	tFSCK	SCLK					30	ns
Time	tRSCK
Serial Output Delay Time	sOUT	SOUT					100	ns

tSCYC

tFSCK

t

RSCK

tSCKW

tSCKW

SCLK

0.8VDD

0.2VDD

tSUS

tHS

SIN

0.8VDD

0.2VDD

tDS

tFSIN

tRSIN

SOUT

0.8VDD

0.2VDD

Figure 7-2 Serial I/O Timing Chart

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7.7 Typical Characteristic Curves

This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.

In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3 σ) and (mean − 3σ) respectively where σ is standard deviation

IOH	IOH−VOH		R0~R6 pins
	VDD=4.5V
(mA)
-12	Ta=25°C
-9
-6
-3
0
	0.3	0.6	0.9	1.2	1.5	(V)
				VDD-VOH
	IOL−VOL1			R0~R6 pins

IOL

(mA)	VDD=4.5V
20	Ta=25°C
15
10
5
0						VOL
	0.2	0.4	0.6	0.8	1.0	(V)
	VDD−VIH1		XIN, RESET,
VIH1			R4, R5, R6 pins
	fXIN=8MHz
(V)
4	Ta=25°C
3
2
1
0						VDD
	2	3	4	5	6 (V)
16

IOH−VOH

R0~R6 pins

IOH

(mA)	VDD=3.0V
-12	Ta=25°C
-9
-6
-3
0
	0.3	0.6	0.9	1.2	1.5	(V)
				VDD-VOH
	IOL−VOL2			R0~R6 pins

IOL

(mA)	VDD=3.0V
20	Ta=25°C
15
10
5
0						VOL
	0.2	0.4	0.6	0.8	1.0	(V)
VDD−VIH2 R0, R1, R2, R3 pins
VIH2	fXIN=8MHz
(V)
4	Ta=25°C
3
2
1
0						VDD
1	2	3	4	5	6	(V)

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GMS81508B/16B/24B

− XIN, RESET, VDD VIL1 R4, R5, R6 pins

VIL2	fXIN=8MHz
(V)
4	Ta=25°C
3
2
1
0						VDD
	2	3	4	5	6	(V)

IDD−VDD Normal Operation

IDD	Ta=25°C
(mA)
20
15
10
5	fXIN = 8MHz
0				4MHz	VDD
	2	3	4	5	6 (V)

VDD−VIL2 R0, R1, R2, R3 pins
VIL2	fXIN=8MHz
(V)
4	Ta=25°C
3
2
1
0						VDD
1	2	3	4	5	6	(V)
ISTOP−VDD				Stop Mode
IDD
(μA)
0.4
0.3
0.2						85°C
						25°C
0.1						-20°C
0						VDD
	2	3	4	5	6 (V)

Operating Area

fXIN

(MHz) Ta= -20~85°C
10
8
6
4
2
0					VDD
2	3	4	5	6	(V)

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8. MEMORY ORGANIZATION

The GMS81508B/16B/24B has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 24K bytes

8.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.

A ACCUMULATOR

XX REGISTER

YY REGISTER

	SP	STACK POINTER
		PROGRAM COUNTER
PCH	PCL
		PROGRAM STATUS
	PSW
		WORD

Figure 8-1 Configuration of Registers

Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y Register as shown below.

Y
Y	A
A
Two 8-bit Registers can be used as a “YA” 16-bit Register

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.

Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore).

Generally, SP is automatically updated when a subroutine

of Program memory. Data memory can be read and written to up to 448 bytes including the stack area.

call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost.

The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FE H” is used.

		Stack Address (100H ~ 1FEH)
Bit 15		8 7	Bit 0
		01H	SP

00H~FEH

Hardware fixed

Note: The Stack Pointer must be initialized by software because its value is undefined after RESET.

Example: To initialize the SP

LDX	#0FEH
TXSP	; SP ← FEH

Address 01FFH can not be used as stack. Don not use 1FFH, or malfunction would be occurred.

Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).

Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.

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[Zero flag Z]

or data transfer is “0” and is cleared by any other result.

This flag is set when the result of an arithmetic operation

MSB

LSB

PSW

N

V

G

B

H

I

Z

C

RESET VALUE: 00H

NEGATIVE FLAG

CARRY FLAG RECEIVES

OVERFLOW FLAG

CARRY OUT

ZERO FLAG

SELECT DIRECT PAGE

INTERRUPT ENABLE FLAG

when G=1, page is selected to “page 1”

BRK FLAG

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF

ADDITION OPERLANDS

Figure 8-3 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG.

[Overflow flag V]

This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.

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At execution of

At acceptance

At execution

At execution

a CALL/TCALL/PCALL

of interrupt

of RET instruction

of RET instruction

01FE

PCH

Push

01FE

PCH

01FE

PCH

01FE

PCH

down

Push

Pop

Pop

01FD

PCL

01FD

PCL

01FD

PCL

01FD

PCL

down

up

up

01FC

01FC

PSW

01FC

01FC

PSW

01FB

01FB

01FB

01FB

SP before

execution

01FE

01FE

01FC

01FB

SP after

execution

01FC

01FB

01FE

01FE

At execution

At execution

of PUSH instruction

of POP instruction

PUSH A (X,Y,PSW)

POP A (X,Y,PSW)

01FE

A

Push

01FE

A

Pop

0100H

down

up

Stack

01FD

01FD

depth

01FC

01FC

01FB

01FB

01FEH

SP before

execution

01FE

01FD

SP after

execution

01FD

01FE

Figure 8-4 Stack Operation

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GMS81508B/16B/24B

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 24K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H.

Figure 8-5, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.

A000H

C000H

24K ROM

ROM

E000H

areaPCALL

GMS815016B,16K

GMS815024B,

FEFFH

8KGMS81508B,ROM

FF00H

FFC0H

TCALL area

FFDFH

FFE0H

Interrupt

FFFFH

Vector Area

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,

it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7.

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc.

Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.

Address	Vector Area Memory
0FFE0H
	-
E2	-
E4	Serial Communication Interface
E6	Basic Interval Timer
E8	Watchdog Timer Interrupt
EA	A/D Converter-
EC	Timer/Counter-	3 Interrupt
EE	Timer/Counter-	2 Interrupt
F0	Timer/Counter 1 Interrupt
F2	Timer/Counter 0 Interrupt
F4	External Interrupt 3
F6	External Interrupt 2
F8	External Interrupt 1
FA	External Interrupt 0
FC	-
FE	RESET Vector Area

NOTE:

“-” means reserved area.

Figure 8-6 Interrupt Vector Area

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Address	PCALL Area Memory	Address
0FF00		0FFC0H
H		C1
		C2
		C3
		C4
		C5
		C6
		C7
		C8
		C9
		CA
		CB
		CC
		CD
	PCALL Area	CE
		CF
	(256 Bytes)
		D0
		D1
		D2
		D3
		D4
		D5
		D6
		D7
		D8
		D9
		DA
		DB
		DC
		DD
0FFFFH		DE
		DF

Program Memory

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

NOTE:

* means that the BRK software interrupt is using same address with TCALL0.

Figure 8-7 PCALL and TCALL Memory Area

PCALL→ rel		TCALL→ n
4F35	PCALL 35H	4A	TCALL 4

4A

4F

01001010

Reverse

35

~

~

~

~

~

~

~

~

0D125H

NEXT

PC: 11111111

11010110

0FF00H

FH

FH

DH 6H

0FF35H

NEXT

0FF00H

0FFD6H

25

0FFD7H

D1

0FFFFH

0FFFFH

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GMS81508B/16B/24B

Example: The usage software example of Vector address for GMS81524B.

	ORG	0FFE0H
	DW	NOT_USED
	DW	NOT_USED
	DW	SIO		; Serial Interface
	DW	BIT_TIMER		; Basic Interval Timer
	DW	WD_TIMER		; Watchdog Timer
	DW	ADC		; ADC
	DW	TIMER3		; Timer-3
	DW	TIMER2		; Timer-2
	DW	TIMER1		; Timer-1
	DW	TIMER0		; Timer-0
	DW	INT3		; Int.3
	DW	INT2		; Int.2
	DW	INT1		; Int.1
	DW	INT0		; Int.0
	DW	NOT_USED		; -
	DW	RESET		; Reset
	ORG	0A000H		; 24K ROM Start address
;	ORG	0C000H		; 16K ROM Start address
;	ORG	0E000H		; 8K ROM Start address
;*******************************************
;		MAIN	PROGRAM		*
;*******************************************
;
RESET:	DI			;Disable All Interrupts
	CLRG
	LDX	#0
RAM_CLR: LDA		#0		;RAM Clear(!0000H->!00BFH)
	STA	{X}+
	CMPX	#0C0H
;	BNE	RAM_CLR
	LDX	#0FEH		;Stack Pointer Initialize
;	TXSP
	LDM	R0, #0		;Normal Port 0
	LDM	R0DD,#82H		;Normal Port Direction
	:
	:
	:
	LDM	TDR0,#250		;8us x 250 = 2000us
	LDM	TM0,#1FH		;Start Timer0, 8us at 8MHz
	LDM	IRQH,#0
	LDM	IRQL,#0
	LDM	IENH,#0C8H		;Enable Timer0, INT0, INT1
	LDM	IENL,#0
	LDM	IEDS,#55H		;Select falling edge detect on INT pin
	LDM	PMR4,#3H		;Set external interrupt pin(INT0, INT1)
	EI			;Enable master interrupt
	:
	:
	:

:

:

NOT_USED:NOP RETI

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8.3 Data Memory

Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and LCD memory.

0000H

User Memory

PAGE0 When “G-flag=0”,

this page is selected

00BFH

00C0H Control

00FFH Registers

0100H

	User Memory	PAGE1 When “G-flag=1”
	or Stack Area

01FFH

Figure 8-8 Data Memory Map

User Memory

The GMS815xxB has 448 × 8 bits for the user memory (RAM).

Control Registers

The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH.

Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

More detailed informations of each register are explained in each peripheral section.

Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”.

Example; To write at CKCTLR

LDM	CLCTLR,#09H ;Divide ratio(÷32)

Stack Area

The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt.

When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags.

The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 20.

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GMS81508B/16B/24B

Address

Register Name

Symbol

R/W

Initial Value

Page

7

6

5

4

3

2

1

0

00C0

R0 port data register

R0

R/W

Undefined

page 31

00C1

R0 port I/O direction register

R0DD

W

0

0

0

0

0

0

0

0

page 31

00C2

R1 port data register

R1

R/W

Undefined

page 31

00C3

R1 port I/O direction register

R1DD

W

0

0

0

0

0

0

0

0

page 31

00C4

R2 port data register

R2

R/W

Undefined

page 31

00C5

R2 port I/O direction register

R2DD

W

0

0

0

0

0

0

0

0

page 31

00C6

R3 port data register

R3

R/W

Undefined

page 32

00C7

R3 port I/O direction register

R3DD

W

0

0

0

0

0

0

0

0

page 32

00C8

R4 port data register

R4

R/W

Undefined

page 32

00C9

R4 port I/O direction register

R4DD

W

0

0

0

0

0

0

0

0

page 32

00CA

R5 port data register

R5

R/W

Undefined

page 33

00CB

R5 port I/O direction register

R5DD

W

0

0

0

0

0

0

0

0

page 33

00CC

R6 port data register

R6

R/W

Undefined

page 33

00CD

R6 port I/O direction register

R6DD

W

0

0

0

0

-

-

-

-

page 33

00D0

R4 port mode register

PMR4

W

0

0

0

0

0

0

0

0

page 32, page 63

00D1

R5 port mode register

PMR5

W

-

-

0

0

-

-

-

-

page 33, page 55

00D3

Basic interval timer mode register

BITR

R

Undefined

page 35

Clock control register

CKCTLR

W

-

-

0

1

0

1

1

1

page 35

00E0

Watchdog Timer Register

WDTR

W

-

0

1

1

1

1

1

1

page 64

00E2

Timer mode register 0

TM0

R/W

0

0

0

0

0

0

0

0

page 37

00E3

Timer mode register 2

TM2

R/W

0

0

0

0

0

0

0

0

page 37

00E4

Timer 0 data register

TDR0

W

Undefined

page 37

Timer 0 counter register

T0

R

Undefined

page 37

00E5

Timer 1 data register

TDR1

W

Undefined

page 37

Timer 1 counter register

T1

R

Undefined

page 37

00E6

Timer 2 data register

TDR2

W

Undefined

page 37

Timer 2 counter register

T2

R

Undefined

page 37

00E7

Timer 3 data register

TDR3

W

Undefined

page 37

Timer 3 counter register

T3

R

Undefined

page 37

00E8

A/D converter mode register

ADCM

R/W

-

-

0

0

0

0

0

1

page 47

00E9

A/D converter data register

ADR

R

Undefined

page 47

00EA

Serial I/O mode register

SIOM

R/W

-

0

0

0

0

0

0

1

page 49

00EB

Serial I/O register

SIOR

R/W

Undefined

page 49

00EC

Buzzer driver register

BUR

W

Undefined

page 55

00F0

PWM0 duty register

PWMR0

W

Undefined

page 53

Table 8-1 Control Registers

DEC. 1999 Ver 1.04

25

	GMS81508B/16B/24B				HYUNDAI MicroElectronics
	Address	Register Name	Symbol	R/W		Initial Value							Page
					7	6	5	4	3	2	1	0
	00F1	PWM1 duty register	PWMR1	W		Undefined							page 53
	00F2	PWM control register	PWMCR	W	0	0	0	0	0	0	0	0	page 53
	00F4	Interrupt enable register low	IENL	R/W	0	0	0	0	-	-	-	-	page 58
	00F5	Interrupt request flag register low	IRQL	R/W	0	0	0	0	-	-	-	-	page 57
	00F6	Interrupt enable register high	IENH	R/W	0	0	0	0	0	0	0	0	page 58
	00F7	Interrupt request flag register high	IRQH	R/W	0	0	0	0	0	0	0	0	page 57
	00F8	External interrupt edge selection register	IEDS	W	0	0	0	0	0	0	0	0	page 63
	00F9	Power fail detection register	PFDR	R/W	-	-	-	-	1	1	0	0	page 71

Table 8-1 Control Registers

W

Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,

content of other seven bits are may varied to unwanted value.

R/W	Registers are controlled by both bit and byte manipulation instruction.

- : this bit location is reserved.

26	DEC. 1999 Ver 1.04

HYUNDAI MicroElectronics

GMS81508B/16B/24B

8.4 Addressing Mode

The GMS800 series MCU uses six addressing modes;

•Register addressing

•Immediate addressing

•Direct page addressing

•Absolute addressing

•Indexed addressing

•Register-indirect addressing

(1) Register Addressing

Register addressing accesses the A, X, Y, C and PSW.

(2) Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data immediately.

Example:

0435 ADC #35H

MEMORY
04	→ A
A+35H+C
35

When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data.

Example: G=1

E45535 LDM 35H,#55H

0135H	data	data ¨ 55H
~		~
~		~
0F100H	E4
0F101H	55
0F102H	35

(3) Direct Page Addressing → dp

In this mode, a address is specified within direct page.

Example; G=0

C535

LDA

35H

;A ←RAM[35H]

35H	data
~	~		data → A
~	~
0E550H	C5
0E551H	35

DEC. 1999 Ver 1.04

27