HP Spectre XT 13-2000 Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Hadid M/B LA8554P Schematics Document

Intel Ivy Bridge ULV Processor with DDRIIIL memory down+ Panther Point

Date : 2012/5/23

3 3

Version 3.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

4019HW

146Thursday, May 09, 2013

E

C

of

A

B

C

D

E

Compal Confidential

Model Name : QCU00 Hadid

1 1

File Name : LA8554P

2011/12/12

Intel

IVY Bridge

ULV Processor

FCBGA 1023

31mm*24mm

Page 4~10

DMI x4FDI x8

100MHz 5GT/s

LVDS Conn.

100MHz

2.7GT/s

Page 24

HDMI Conn.

2 2

X1

LAN(Gbe) RTL8111E-VL

Page 22

RJ45

Page 22

3 3

Page 21

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

X1

WLAN&BT (MINI card)

Page 23 Page 25

X1

LVDS

HDMI

SATAx6

X1

m-SATA (MINI card)

(GEN1 1.5Gb/S GEN2 3Gb/S GEN3 6Gb/S)

USB 2.0 Bus

100MHz 100MHz

Intel

Panther Point

PCH

989pin BGA

25mm*25mm

Page 12~19

LPC BUS

33MHz

DDR3 1333/1600MHz 1.5V DDR3L 1333MHz 1.35V

Dual Channel

USB3.0 x2

USB 3.0 x1 USB 2.0 x2 HD Audio

3.3V 48MHz

3.3V 24MHz

SPI

BIOS SPI ROM x1, 8MB

Page 12

DDR3L-1600 Memory down

BANK 0, 1, 2, 3

Page 12

FAN conn.

USB 2.0 x1

PCI-Express x1

X2

X1

HD webcam

Page 23

HD Audio

USB charger

HDA Codec

IDT 92HD99

SPK conn HP Amp

Rear SPK Amp

Card Reader RTS5229

SD socketUSB 2.0 X1

Digital MIC

Page 30

Rear SPK conn HP&MIC

jack

IO board

LED

RTC CKT.

Power On/Off CKT.

DC/DC interface CKT.

Touch pad daughter board

BATT LED daughter board

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

E

24

C

of

6Thursday, May 09, 2013

PS2

Page 29

ENE KB932

Int.KBD

B

Page 28

Page 29

SPI

EC ROM 256K Byte

Page 28

EC SMBus

Accelerometer

HP3DC2

Page 30

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/29 2011/06/29

TPM1.2 SLB9635TT

Page 30

SMBus (PCH)

4 4

A

Touch Pad

A

B

C

D

E

QCU00 (LA-8554P Ver:0.1)

Voltage Rails

S1

Power Plane Description VIN BATT+ Battery power supply (12.6V) N/A N/A N/A B+

1 1

2 2

3 3

+CPU_CORE

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator

+1.05VS_VCCP +VCCP +1.5V +1.5VS

+1.8VS (+5VALW ) to 1.8V switched power rail to PCH +3VALW +3VALW always on power rail +3VALW_EC +3VALW always to KBC ON ON ON* +LAN_IO +3V_PCH +3VS +5VALW +5V_PCH +5VS +5VALW to +5VS switched power rail OFFON OFF +VSB B+ to +VSB always on power rail for sequence control ON ON* +RTCVCC RTC power Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMBCLK PCH_SMBDATA

PCH_SML1CLK PCH_SML1DATA

Adapter power supply (19V)

AC or battery power rail for power circuit. Core voltage for CPU

+V1.05SP to +1.05VS_VCCP switched power rail for CPU +VCCP (1.05V ) power for PCH +1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V) +1.5VS switched power rail

+3VALW to +LAN_IO power rail for LAN +3VALW to +3V_PCH power rail for PCH (Short Jumper) +3VALW to +3VS power rail +5VALWP to +5VALW power rail +5VALW to +5V_PCH power rail for PCH (Short resister)

BATT

SOURCE

KB932

PCH

Charger

V

HP Amp

MINI3

V

DESTINATIONDIFFERENTIAL CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2

CLK

CLKOUT_PCIE3 CLKOUT_PCIE4

4 4

CLKOUT_PCIE5

10/100/1G LAN

WLAN None CARD READER None None

NoneCLKOUT_PCIE6 CLKOUT_PCIE7 CLKOUT_PEG_B

A

None

N/A N/A N/A

ON

ON OFF OFF ON OFF OFF ON ON OFF ON

ON ON

ON ON ON ON ON ON ON ON

ON ON

SODIMM

FLEX CLOCKS CLKOUTFLEX0 CLKOUTFLEX1 CLKOUTFLEX2 CLKOUTFLEX3

B

S3 S5

N/AN/AN/A

OFF

OFF OFF

OFF

OFF ON*

ON

ON* ON*

OFF

ON ON*

ON*

ONON

EC_SMB_CK2 EC_SMB_DA2

V

EC_SMB_CK1 EC_SMB_DA1

DESTINATION

Symbol Note :

: means Digital Ground

: means Analog Ground

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

EC SM Bus1 address

Device

Smart Battery

PCH SM Bus address

Device Address

DDR DIMM0 Mini Card2 Mini Card3 TP module

G-Sensor

V

None None None None

SIGNAL

Address

0001 011X b

TP

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

SLP_S1#

ON

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ONONON

ON

OFF

ON

OFF

EC SM Bus2 address

Device

PCH (Reserve)

G-sensor

CLKOUT PCI0 PCI1 PCI2 PCI3 PCI4

Address

1010 0110b 0101001b

DESTINATION PCH_LPBACK PCI_LPC

None None None

ON

OFF

V

SATA SATA0 SATA1 SATA2 SATA3 SATA4 SATA5

UMA VX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

DESTINATION

m-SATA,JMINI2

CONN@@Option

X

Compal Secret Data

None

None None None None

Deciphered Date

D

ON

LOW

OFF

USB Port Table

USB 2.0

EHCI1

EHCI2

USB 3.0 Port

USB 1.1 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

0 1 2 3 4 5 6 7 8

9 10 11 12 13

1 2 3 4

Title

Size

Document Number Rev

C

4019HW

Date: Sheet of

1 External USB Port

USB2.0 (left side) USB2.0 (Right side)

Camera BT

1 External USB Port

USB3.0 (left)

Compal Electronics, Inc.

SCHEMATICS,MB A8554

E

C

6Thursday, May 09, 2013

34

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2011/06/30 2013/06/30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/30 2013/06/30

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A8554

4019HW

1

C

446Thursday, May 09, 2013

5

UCPU1

QBP8@

1.5G R1

UCPU1

QC52@

2.0G R1

UCPU1

QC9B@

2.0G R1

D D

C C

eDP_COMPIO and ICOMPO signals should be shorted near balls

B B

and routed with typical impedance <25 mohms

NOTE:eDP_COMPIO and eDP_ICOMPO should not be left floating even if Internal Graphic is disabled since they are shared with other interfaces

UCPU1

2.0G R3

L18@

+VCCP

1.5G R3

UCPU1

1.9G R1

UCPU1

1.9G R1

UCPU1

1.9G R3

12

RC2

24.9_0402_1%

QBTP@

QC53@

QC9C@

L17@

DMI_CRX_PTX_N015 DMI_CRX_PTX_N115 DMI_CRX_PTX_N215 DMI_CRX_PTX_N315

DMI_CRX_PTX_P015 DMI_CRX_PTX_P115 DMI_CRX_PTX_P215 DMI_CRX_PTX_P315

DMI_CTX_PRX_N015 DMI_CTX_PRX_N115 DMI_CTX_PRX_N215 DMI_CTX_PRX_N315

DMI_CTX_PRX_P015 DMI_CTX_PRX_P115 DMI_CTX_PRX_P215 DMI_CTX_PRX_P315

FDI_CTX_PRX_N015 FDI_CTX_PRX_N115 FDI_CTX_PRX_N215 FDI_CTX_PRX_N315 FDI_CTX_PRX_N415 FDI_CTX_PRX_N515 FDI_CTX_PRX_N615 FDI_CTX_PRX_N715

FDI_CTX_PRX_P015 FDI_CTX_PRX_P115 FDI_CTX_PRX_P215 FDI_CTX_PRX_P315 FDI_CTX_PRX_P415 FDI_CTX_PRX_P515 FDI_CTX_PRX_P615 FDI_CTX_PRX_P715

FDI_FSYNC015 FDI_FSYNC115

FDI_INT15 FDI_LSYNC015

FDI_LSYNC115

UCPU1

1.7G R1

UCPU1

1.8G R1

UCPU1

1.7G R1

UCPU1

1.7G R3

4

QBP7@

QC55@

QC9E@

L16@

EDP_COMP

UCPU1

QBTQ@

1.7G R1

UCPU1

QC56@

1.7G R1

UCPU1A

@

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

SANDY-BRIDGE_BGA1023~D

3

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI Intel(R) FDI DP

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS -- GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_COMP

RC1

24.9_0402_1%

+VCCP

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms

12

PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Title

Size

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

1

546Thursday, May 09, 2013

of

C

5

4

3

Buffered reset to CPU

+3VS

2

1

CC1

0.1U_0402_16V4Z

2

D D

BE45

UCPU1B

@

F49

C57

C49

A48

C45

D45

C48

B46

D44

PLT_RST#

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

PLT_RST#16,22,23,26,28,30

+VCCP

C C

B B

Processor Pullups

RC8 62_0402_5%

RC11 10K_0402_5%

12

H_PROCHOT#

H_CPUPWRGD_R

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present

H_PROCHOT#28,35

This pin is for compability with future platforms. A pull up resistor to VCCIO is required if connected to the DF_TVS strap on the PCH.

H_SNB_IVB#17

1 2

RC7 10K_0402_5%@

CRB use 0ohm PD

T5

PAD

@

56_0402_5%

H_THRMTRIP#

RC13

0_0402_5%

RC16

0_0402_5%

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

130_0402_5%

H_PECI_ISO

H_PROCHOT#_R

H_PM_SYNC_R

H_CPUPWRGD_R

BUF_CPU_RST#

H_PECI17,28 H_DRAMRST#

1 2

RC10

H_THRMTRIP#17

1 2

H_PM_SYNC15

H_CPUPWRGD17

@

1 2

@

1 2

RC18

1

NC

2

A

R956

@

0_0402_5%

1 2

5

P

G

3

UC1

4

BUFO_CPU_RST#

Y

SN74LVC1G07DCKR_SC70-5

MISC

THERMAL PWR MANAGEMENT

+VCCP

12

RC3 75_0402_5%

RC4

12

BUF_CPU_RST#

12

BCLK

BCLK#

DPLL_REF_CLK

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ#

TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

@

TCK

TDI

43_0402_1%

DPLL_REF_CLK#

CLOCKS

DDR3

MISC

JTAG & BPM

RC6 750_0402_1%

J3 H2

AG3 AG1

N59 N58

AT30

H_DRAMRST#

BF44 BE43 BG43

PAD PAD

@

N53

@

N55 L56

XDP_TCK

L55

XDP_TMS

J58

XDP_TRST#

M60

XDP_TDI

L59

XDP_TDO

K58

G58 E55 E59 G55 G59 H60 J59 J61

CLK_CPU_DMI CLK_CPU_DMI# 14

1 2

RC82 1K_0402_5%

1 2

RC83 1K_0402_5%

CLK_RES_ITP CLK_RES_ITP#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

T35 T39

XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R

SM_RCOMP Trace Width=15mils

1 2

RC17

14

0_0402_5%

XDP_DBRESET#

7

XDP_DBRESET#XDP_DBRESET#_R

1 2

RC19 0_0402_5%@

1 2

RC20 0_0402_5%@

1 2

RC21 0_0402_5%@

1 2

RC22 0_0402_5%@

+3VS

RC5 1K_0402_5%

circuit check 10k

Connect DPLL_REF_SSCLK on Processor to GND through 1K ± 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP

+VCCP

through 1K ± 5% resistor

XDP_DBRESET#

12

15

CFG12 CFG13 CFG14 CFG15 8

8 8 8

SANDY-BRIDGE_BGA1023~D

+3VS

RC81 10K_0402_5%

1 2

@

0_0402_5%

+3V_PCH

1 2

200_0402_5%

SYS_PWROK15

PM_DRAM_PWRGD15

A A

0.1U_0402_16V4Z

RC27

RC28

1 2

5

CC2

+3V_PCH

1

2

UC2 74AHC1G09GW_TSSOP5

5

1

P

B

4

PM_SYS_PWRGD_BUF

O

2

A

G

3

Part Number = SA00003Y000

SUSP31,41

SUSP

2

G

+1.5V_CPU_VDDQ

12

@

RC29 39_0402_5%

13

D

@

QC1 2N7002_SOT23

S

12

RC25 200_0402_5%

4

DDR3 Compensation Signals

SM_RCOMP0

RC23 140_0402_1%

SM_RCOMP1

RC24 25.5_0402_1%

SM_RCOMP2

RC26 200_0402_1%

12 12 12

PU/PD for JTAG signals

XDP_TMS

RC30 51_0402_5%

XDP_TDI

RC31 51_0402_5%

XDP_TDO

RC32 51_0402_5%

XDP_TCK

RC33 51_0402_5%

XDP_TRST#

RC34 51_0402_5%

12 12

@

12

@

12

@

12

@ @

Place close to CPU

XDP_DBRESET#_R

H_CPUPWRGD_R

+VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XDP_TRST#

PM_SYS_PWRGD_BUF

BUF_CPU_RST#

3

12

CC4 0.1U_0402_16V7K

1 2

C118 220P_0402_50V7K

C263

0.1U_0402_16V7K

1 2

100P_0402_50V8J@

C265

1 2

220P_0402_50V7K

C266

1 2

Compal Secret Data

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SCHEMATICS,MB A8554

Document Number Rev

Size

Custom

Date: Sheet

4019HW

646Thursday, May 09, 2013

1

646Thursday, May 09, 2013

C

of

5

4

3

2

1

DDR_A_D[0..63]12

D D

C C

DDR_A_BS012

B B

A A

DDR_A_BS112 DDR_A_BS212

DDR_A_CAS#12 DDR_A_RAS#12 DDR_A_WE#12

H_DRAMRST#6

DRAMRST_CNTRL_PCH14,28,8

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DRAMRST_CNTRL_PCH

AG6

AJ6

AP11

AL6

AJ10

AJ8 AL8 AL7

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

4.99K_0402_1%

UCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SANDY-BRIDGE_BGA1023~D

@

RC35

@

0_0402_5%

1 2

D

S

13

QC2 BSS138_NL_SOT23-3

G

RC38

2

1 2

AU36

SA_CLK[0]

AV36

SA_CLK#[0]

AY26

SA_CKE[0]

AT40

SA_CLK[1]

AU40

SA_CLK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

BG35

12

BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

RC37 1K_0402_5%

1 2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

+1.5V

RC36

1K_0402_5%

DDR3_DRAMRST#_RH_DRAMRST#

M_CLK_A_DDR0 M_CLK_A_DDR#0 DDR_A_CKE0

DDR_A_CS0#

M_A_ODT0

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR3_DRAMRST#

12

DDR_B_D[0..63]12

DDR_B_BS012 DDR_B_BS112 DDR_B_BS212

DDR_B_CAS#12 DDR_B_RAS#12 DDR_B_WE#12

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

SANDY-BRIDGE_BGA1023~D

@

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

M_CLK_B_DDR0 M_CLK_B_DDR#0 DDR_B_CKE0

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

M_CLK_B_DDR0 M_CLK_B_DDR#0 DDR_B_CKE0

12

DDR_B_CS0#

M_B_ODT0 12

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15] 12

12

1

CC3

0.047U_0402_16V4Z

2

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

2

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

1

74

C

of

6Thursday, May 09, 2013

5

4

3

2

1

CFG Straps for Processor

CFG2

12

RC40 1K_0402_1%@

1: Normal Operation; Lane # definition matches

*

socket pin map definition

13

D

2

+V_DDR_REFA_DQ

D D

QC9A

RC15

1 2

0_0402_5%@

DRAMRST_CNTRL_PCH

G

BSS138W-7-F_SOT323-3

S

12

RC14

@

1K_0402_1%

+V_DDR_REFA_R

+V_DDR_REFB_DQ

1 2

QC9B

RC86 0_0402_5%@

13

D

2

G

BSS138W-7-F_SOT323-3

S

12

RC87

@

1K_0402_1%

DRAMRST_CNTRL_PCH

+V_DDR_REFB_R

14,28,7

PEG Static Lane Reversal - CFG2 is for the 16x

For Chief River only

0:Lane Reversed

CFG4

12

RC41 1K_0402_1%

UCPU1E

@

CFG0

T9

CFG1

T6

CFG2

@

T10

CFG3

@

T11

CFG4

@

CFG5

@

CFG126 CFG13

6 6

CFG14 CFG15

6

12

49.9_0402_1%

12

T12 T13

@

T7

@

T8

@

T14

@

T15

@

T16

@ @

T17 T18

@ @

VAXG_VAL_SENSE

VSSAXG_VAL_SENSE

CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

VCC_VAL_SENSE VSS_VAL_SENSE

C C

1 2

+CPU_CORE

+VGFX_CORE

TBC

RC46

B B

1K_0402_1%

@

RC42 49.9_0402_1%

RC43

1 2

RC44 49.9_0402_1%

RC45 49.9_0402_1%

CPU_RSVD6 CPU_RSVD7

12

RC47 1K_0402_1%

@

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61

DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

RSVD28 RSVD29

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

+V_DDR_REFA_R +V_DDR_REFB_R

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port

*

attached to Embedded Display Port 0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

CFG6 CFG5

1K_0402_1%

PCIE Port Bifurcation Straps

00 = 1 x 8, 2 x 4 PCI Express

CFG[6:5]

01 = reserved 10 = 2 x 8 PCI Express

*

11 = 1 x 16 PCI Express

CFG7

@

12

RC49

12

@

1K_0402_1%

RC50 1K_0402_1%

RC48

@

SANDY-BRIDGE_BGA1023~D

PEG DEFER TRAINING

CFG7

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

1: (Default) PEG Train immediately following xxRESETB de assertion

*

0: PEG Wait for BIOS for training

Title

Size

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

C

846Thursday, May 09, 2013

1

846Thursday, May 09, 2013

C

of

5

D D

C C

B B

A A

5

4

+CPU_CORE

4

Ultra-DC 33A

UCPU1F

@

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

SANDY-BRIDGE_BGA1023~D

3

8.5A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

CORE SUPPLY

POWER

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

PEG AND DDRSENSE LINES

VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

QUIET RAILS

VIDALERT#

VIDSCLK

VIDSOUT

SVID

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

choose low or high

+1.05VS_VCCPQ

AM25 AN22

A44

H_CPU_SVIDALRT#

B43

H_CPU_SVIDCLK

C44

H_CPU_SVIDDAT

10/31 change RC55, RC56, RC57, RC58, RC59, RC60 , RC61, RC62, RC64 to 0201 package for space issue

F43

VCCSENSE

G43

VSSSENSE

AN16

VCCIO_SENSE

AN17

VSS_SENSE_VCCIO

2011/06/29 2011/06/29

+VCCP

RC51

1 2

0_0805_5%

VCCP_PWRCTRL_R

RC54

1 2

0_0805_5%

1 2

CC73 1U_0402_6.3V6K

1 2

RC63

12

RC66 10_0402_1%

Compal Secret Data

Deciphered Date

+VCCP

10K_0402_5%

1 2

RC53

@

+VCCP

10_0402_1%

2

+3VS

12

RC52

@

75_0402_5%

+VCCP

12

RC55 130_0201_5%

1 2

RC57 43_0201_5%

+VCCP

VCCIO_SENSE 40 VSS_SENSE_VCCIO

2

VR_SVID_ALRT# 44 VR_SVID_CLK VR_SVID_DAT

1 2

RC60 100_0201_1%

12

RC64 100_0201_1%

40

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

1

44 44

+CPU_CORE

Place the PU resistors close to CPU

VCCSENSE

44

VSSSENSE

Place the PU resistors close to VR

4019HW

1

C

946Thursday, May 09, 2013

C

of

5

4

3

2

1

+1.5V_CPU_VDDQ +1.5V

CC74 0.1U_0402_10V7K

CC75 0.1U_0402_10V7K

D D

+VGFX_CORE

12

Ultra-DC (GT2)29A Ultra-DC (GT1)18A

C C

12/6 Base on Intel review result, change to 100 ohm

B B

+1.8VS

+VCCSA

A A

5

0_0805_5%

1 2

10U_0603_6.3V

CC23

6M

1U_0402_6.3V

CC129

1

2

6K

RC77

1

2

1

2

CC130

VCC_AXG_SENSE44

VSS_AXG_SENSE44

Delete CC120

10U_0603_6.3V

CC26

6M

10U_0603_6.3V6M

1

CC20

2

1U_0402_6.3V

CC131

1

2

6K

1

2

10U_0603_6.3V

1

CC22

2

6M

1U_0402_6.3V

CC132

1

2

6K

1U_0402_6.3V6K

Can connect to GND if motherboard only‧ supports external graphics and if GFX VR is not stuffed in a common motherboard design,

XG can be left floating in a common‧

VA motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed

+VGFX_CORE

12

RC84 100_0201_1%

12

RC85

100_0201_1%

+1.8VS_VCCPLL

CC121

1U_0402_6.3V6K

1U_0402_6.3V

1

2

6K

+VCCSA

10U_0603_6.3V

CC21

6M

CC133

1

2

1

CC24

2

6M

1U_0402_6.3V

6K

Delete CC25

1

2

4

CC122

1.2A

4A

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

W50 W51 W52 W53 W55 W56 W61

W20

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59

Y48 Y61

F45

G45

BB3 BC1 BC4

L17

L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21

UCPU1G

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

VAXG_SENSE VSSAXG_SENSE

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

SANDY-BRIDGE_BGA1023~D

@

GRAPHICS

SENSE

LINES

1.8V RAIL

SA RAIL

+V_SM_VREF should have 20 mil trace width

AY43

3

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

5A

CPU1.5V_S3_GATE28

+V_SM_VREF_CNT

1U_0402_6.3V

CC101

1

2

6K

1

2

+1.5V_CPU_VDDQ

1U_0402_6.3V

CC85

CC86

1

2

6K

1 2

RC74

@

0_0402_5%

RC75

@

0_0402_5%

1 2

12

RC76 0_0603_5%

VCCSA_VID0 42 VCCSA_VID1

Compal Secret Data

1U_0402_6.3V

CC102

1

2

6K

SUSP#28,31,38,39,40

1U_0402_6.3V6K

1 2

CC119

T1 PAD

PAD

T2

@ @

1 2

RC78 0_0402_5%@

VCCSA_VID0 VCCSA_VID1

2011/06/29 2011/06/29

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22]

DDR3 - 1.5V RAILS

POWER

VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC67

0_0402_5%

12

0.1U_0402_16V4Z

1U_0402_6.3V

CC87

1

2

6K

CC88

2

1U_0402_6.3V6K

1U_0402_6.3V

CC89

1

2

6K

+3VALW

12

RC72 100K_0402_5%

RUN_ON_CPU1.5VS3#

61

2N7002DWH_SOT363-6 QC5A

1U_0402_6.3V

CC90

6K

Follow PDDG 0.71 page 6

VCCSA_SENSE

Deciphered Date

42

2

1

2

1U_0402_6.3V6K

CC91

+V_SM_VREF

CC79

1U_0402_6.3V

CC92

1

2

6K

5

+1.5V_CPU_VDDQ

12

RC68 1K_0402_1%

1

2

1

2

+VSB

12

RC69 1K_0402_1%

+1.5V_CPU_VDDQ

10U_0603_6.3V

1

CC100

CC93

2

6M

2

6M

+1.5V +1.5V_CPU_VDDQ

12

RC70 100K_0402_5%

RUN_ON_CPU1.5VS3

34

2N7002DWH_SOT363-6 QC5B

330K_0402_5%

10U_0603_6.3V

1

CC96

CC94

CC95

CC97

2

6M

+1.5V_CPU_VDDQ Source

SI7326DN-T1-E3_PAK1212-8

QC4

4

12

1

RC73

2

VCCSA

Vout

VID1VID0

0

0 01 10

1

0.9V

0.725V

0.675V X V1

V V0.8V X

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

Follow CRV board Delete CC100 add 10uF*1 1uF*2

10U_0603_6.3V

1

CC98

CC99

2

6M

1 2 35

@

CC118

0.1U_0402_25V6

12

R78

_0402_5% 20K

D

S

RC71 470_0603_5%

1 2

Q10

SB000002X00

13

BSS138W-7-F_SOT323-3

2

RUN_ON_CPU1.5VS3#

G

IvySandy

V V V

4019HW

1

10 46Thursday, May 09, 2013

C

of

5

4

UCPU1H

3

2

1

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

AA1

AA8

AC6

AD4

AE8 AF1

AG7 AH4

AJ7 AK1

VSS[10]

A53

VSS[11]

A9

VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

D D

C C

B B

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G48

VSS[221]

G51

VSS[222]

G6

VSS[223]

G61

VSS[224]

H10

VSS[225]

H14

VSS[226]

H17

VSS[227]

H21

VSS[228]

H4

VSS[229]

H53

VSS[230]

H58

VSS[231]

J1

VSS[232]

J49

VSS[233]

J55

VSS[234]

K11

VSS[235]

K21

VSS[236]

K51

VSS[237]

K8

VSS[238]

L16

VSS[239]

L20

VSS[240]

L22

VSS[241]

L26

VSS[242]

L30

VSS[243]

L34

VSS[244]

L38

VSS[245]

L43

VSS[246]

L48

VSS[247]

L61

VSS[248]

M11

VSS[249]

M15

VSS[250]

SANDY-BRIDGE_BGA1023~D

@

VSS

VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_NCTF_10

NCTF

VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

SANDY-BRIDGE_BGA1023~D

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Title

Size

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

11 46Thursday, May 09, 2013

of

1

of

C

5

4

3

2

1

UDDRA1

+VREF_CA_A +VREF_CA_A +VREF_CA_A

+V_DDR_REFA_DQ +V_DDR_REFA_DQ +V_DDR_REFA_DQ

D D

DDR_A_MA[0..14]7 DDR_A_DQS#[0..7]7 DDR_A_DQS[0..7]7

DDR_A_D[0..63]7

C C

DDR_B_MA[0..14]7 DDR_B_DQS#[0..7]7 DDR_B_DQS[0..7]7

DDR_B_D[0..63]7

+V_DDR_REFB_DQ

B B

A A

+VREF_CA_B

M_CLK_B_DDR07

M_CLK_B_DDR#07

2

70.1U_0402_16V7K

80.1U_0402_16V7K CD2

CD2

1

DDR_A_BS07 DDR_A_BS17 DDR_A_BS27

M_CLK_A_DDR07 M_CLK_A_DDR#07

DDR_A_CKE07

M_A_ODT07

DDR_A_CS0#7

DDR_A_RAS#7 DDR_A_CAS#7 DDR_A_WE#7

DDR3_DRAMRST#7

DDR_B_MA0 DDR_B_MA1

2

30.1U_0402_16V7K

40.1U_0402_16V7K

DDR_B_MA2 DDR_B_MA3

CD4

DDR_B_MA4

1

DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS07 DDR_B_BS17 DDR_B_BS27

DDR_B_CKE07

M_B_ODT07 DDR_B_CS0#7 DDR_B_RAS#7

DDR_B_CAS#7 DDR_B_WE#7

240_0402_1%

DDR_A_MA0 DDR_A_MA1

2

DDR_A_MA2 DDR_A_MA3 DDR_A_MA4

1

DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0 DDR_A_CKE0

M_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS0 DDR_A_DQS1

DDR_A_DQS#0 DDR_A_DQS#1

DDR3_DRAMRST#

RD1

240_0402_1%

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

M_CLK_B_DDR0 M_CLK_B_DDR#0 DDR_B_CKE0

M_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS0 DDR_B_DQS1

DDR_B_DQS#0 DDR_B_DQS#1

DDR3_DRAMRST#

12

RD9

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M2 N8 M3

J7 K7 K9

K1 L2

J3

K3

L3

F3 C7

E7 D3

G3 B7

T2 L8

12

J1 L1 J9 L9

M7

EDJ4216BBBG-GN-F_FBGA96

@

UDDRB1

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC

L1

NC

J9

NC

L9

NC

M7

NC

96-BALL SDRAM DDR3L

EDJ4216BBBG-GN-F_FBGA96

@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC NC NC NC

NC

96-BALL SDRAM DDR3L

E3

DDR_A_D2

DQL0

F7

DDR_A_D1

DQL1

F2

DDR_A_D7

DQL2

F8

DDR_A_D4

DQL3

H3

DDR_A_D6

DQL4

H8

DDR_A_D0

DQL5

G2

DDR_A_D3

DQL6

H7

DDR_A_D5

DQL7

D7

DDR_A_D12

DQU0

C3

DDR_A_D15

DQU1

C8

DDR_A_D8

DQU2

C2

DDR_A_D11

DQU3

A7

DDR_A_D9

DQU4

A2

DDR_A_D10

DQU5

B8

DDR_A_D13

DQU6

A3

DDR_A_D14

DQU7

+1.5V

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

E3

DDR_B_D6

DQL0

F7

DDR_B_D3

DQL1

F2

DDR_B_D1

+1.5V

DDR_B_D7 DDR_B_D4 DDR_B_D2 DDR_B_D5 DDR_B_D0

DDR_B_D11 DDR_B_D8 DDR_B_D10 DDR_B_D12 DDR_B_D14 DDR_B_D13 DDR_B_D15 DDR_B_D9

+V_DDR_REFB_DQ

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

+VREF_CA_B

2

90.1U_0402_16V7K

00.1U_0402_16V7K CD2

CD3

1

2

50.1U_0402_16V7K

60.1U_0402_16V7K CD4

CD4

1

UDDRA2

M8 H1

N3

DDR_A_MA0

P7

DDR_A_MA1

P3

DDR_A_MA2

N2

DDR_A_MA3

P8

DDR_A_MA4

P2

DDR_A_MA5

R8

DDR_A_MA6

R2

DDR_A_MA7

T8

DDR_A_MA8

R3

DDR_A_MA9

L7

DDR_A_MA10

R7

DDR_A_MA11

N7

DDR_A_MA12

T3

DDR_A_MA13

T7

DDR_A_MA14

M2

DDR_A_BS0

N8

DDR_A_BS1

M3

DDR_A_BS2

J7

M_CLK_A_DDR0

K7

M_CLK_A_DDR#0

K9

DDR_A_CKE0

K1

M_A_ODT0

L2

DDR_A_CS0#

J3

DDR_A_RAS#

K3

DDR_A_CAS#

L3

DDR_A_WE#

F3

DDR_A_DQS2

C7

DDR_A_DQS3

E7 D3

G3

DDR_A_DQS#2

B7

DDR_A_DQS#3 DDR_A_DQS#5

T2

DDR3_DRAMRST# DDR3_DRAMRST#

L8

12

RD2

240_0402_1%

J1 L1 J9 L9

M7

EDJ4216BBBG-GN-F_FBGA96

@

UDDRB2

M8 H1

N3

DDR_B_MA0

P7

DDR_B_MA1

P3

DDR_B_MA2

N2

DDR_B_MA3

P8

DDR_B_MA4

P2

DDR_B_MA5

R8

DDR_B_MA6

R2

DDR_B_MA7

T8

DDR_B_MA8

R3

DDR_B_MA9

L7

DDR_B_MA10

R7

DDR_B_MA11

N7

DDR_B_MA12

T3

DDR_B_MA13

T7

DDR_B_MA14

M2

DDR_B_BS0

N8

DDR_B_BS1

M3

DDR_B_BS2

J7

M_CLK_B_DDR0

K7

M_CLK_B_DDR#0

K9

DDR_B_CKE0

K1

M_B_ODT0

L2

DDR_B_CS0#

J3

DDR_B_RAS# DDR_B_CS0#

K3

DDR_B_CAS#

L3

DDR_B_WE#

F3

DDR_B_DQS2

C7

DDR_B_DQS3

E7 D3

G3

DDR_B_DQS#2

B7

DDR_B_DQS#3

T2

DDR3_DRAMRST#

L8

12

RD10

240_0402_1%

J1 L1 J9 L9

M7

EDJ4216BBBG-GN-F_FBGA96

@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC NC NC NC

NC

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC NC NC NC

NC

96-BALL SDRAM DDR3L

E3

DDR_A_D19

DQL0

F7

DDR_A_D20

DQL1

F2

DDR_A_D18

DQL2

F8

DDR_A_D21

DQL3

H3

DDR_A_D22

DQL4

H8

DDR_A_D16

DQL5

G2

DDR_A_D23

DQL6

H7

DDR_A_D17

DQL7

D7

DDR_A_D28

DQU0

C3

DDR_A_D31

DQU1

C8

DDR_A_D29

DQU2

C2

DDR_A_D25

DQU3

A7

DDR_A_D30

DQU4

A2

DDR_A_D27

DQU5

B8

DDR_A_D24

DQU6

A3

DDR_A_D26

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

E3

DDR_B_D19

DQL0

F7

DDR_B_D18

+1.5V

DDR_B_D21 DDR_B_D22 DDR_B_D17 DDR_B_D23 DDR_B_D20 DDR_B_D16

DDR_B_D27 DDR_B_D25 DDR_B_D31 DDR_B_D28 DDR_B_D30 DDR_B_D29 DDR_B_D26 DDR_B_D24

+VREF_CA_B

+V_DDR_REFB_DQ

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

DDR_A_MA0 DDR_A_MA1

2

90.1U_0402_16V7K

00.1U_0402_16V7K

DDR_A_MA2 DDR_A_MA3

CD3

CD4

DDR_A_MA4

1

DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0 DDR_A_CKE0

M_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6

DDR_A_DQS#4

RD3

240_0402_1%

DDR_B_MA0 DDR_B_MA1

2

80.1U_0402_16V7K

70.1U_0402_16V7K

DDR_B_MA2 DDR_B_MA3

CD4

DDR_B_MA4

1

DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

M_CLK_B_DDR0 M_CLK_B_DDR#0 M_CLK_B_DDR#0 DDR_B_CKE0

M_B_ODT0 DDR_B_RAS#

DDR_B_CAS# DDR_B_WE#

DDR_B_DQS4 DDR_B_DQS7 DDR_B_DQS5

DDR_B_DQS#4 DDR_B_DQS#5

DDR3_DRAMRST#

RD12

240_0402_1%

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M2

N8

M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

12

J1 L1 J9 L9

M7

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M2

N8

M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

12

J1 L1 J9 L9

M7

UDDRA3

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0 A8

DQU1 A9

DQU2 A10/AP

DQU3 A11

DQU4 A12/BC

DQU5

DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ RAS

VDDQ CAS

VDDQ WE

VDDQ

VDDQ DQSL

VDDQ DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ NC

VSSQ

NC

VSSQ

NC

VSSQ

NC

VSSQ

96-BALL SDRAM DDR3L

EDJ4216BBBG-GN-F_FBGA96

@

UDDRB3

DQL0

VREFCA

DQL1

VREFDQ

DQL2

DQL3

A0

DQL4

A1 A2

DQL5 A3

DQL6 A4

DQL7 A5 A6 A7

DQU0 A8

DQU1 A9

DQU2 A10/AP

DQU3 A11

DQU4 A12/BC

DQU5

DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ RAS

VDDQ CAS

VDDQ WE

VDDQ

VDDQ DQSL

VDDQ DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ NC

VSSQ

NC

VSSQ

NC

VSSQ

NC

VSSQ

96-BALL SDRAM DDR3L

EDJ4216BBBG-GN-F_FBGA96

@

DDR_A_MA0 DDR_A_MA1

2

DDR_A_MA2 DDR_A_MA3 DDR_A_MA4

1

DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0 DDR_A_CKE0

M_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS7

DDR_A_DQS#6 DDR_A_DQS#7

DDR3_DRAMRST#

RD4

240_0402_1%

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

M_CLK_B_DDR0 DDR_B_CKE0

M_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS6

DDR_B_DQS#6 DDR_B_DQS#7

DDR3_DRAMRST#

RD11

240_0402_1%

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M2 N8 M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

12

J1 L1 J9 L9

M7

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M2 N8 M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

12

J1 L1 J9 L9

M7

UDDRA4

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0 A8

DQU1 A9

DQU2 A10/AP

DQU3 A11

DQU4 A12/BC

DQU5

DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ RAS

VDDQ CAS

VDDQ WE

VDDQ

VDDQ DQSL

VDDQ DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ NC

VSSQ

NC

VSSQ

NC

VSSQ

NC

VSSQ

96-BALL SDRAM DDR3L

EDJ4216BBBG-GN-F_FBGA96

@

UDDRB4

DQL0

VREFCA

DQL1

VREFDQ

DQL2

DQL3

A0

DQL4

A1 A2

DQL5 A3

DQL6 A4

DQL7 A5 A6 A7

DQU0 A8

DQU1 A9

DQU2 A10/AP

DQU3 A11

DQU4 A12/BC

DQU5

DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ RAS

VDDQ CAS

VDDQ WE

VDDQ

VDDQ DQSL

VDDQ DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ NC

VSSQ

NC

VSSQ

NC

VSSQ

NC

VSSQ

96-BALL SDRAM DDR3L

EDJ4216BBBG-GN-F_FBGA96

@

E3

DDR_A_D54

F7

DDR_A_D53

F2

DDR_A_D50

F8

DDR_A_D49

H3

DDR_A_D55

H8

DDR_A_D48

G2

DDR_A_D51

H7

DDR_A_D52

D7

DDR_A_D57

C3

DDR_A_D59

C8

DDR_A_D60

C2

DDR_A_D62

A7

DDR_A_D61

A2

DDR_A_D58

B8

DDR_A_D56

A3

DDR_A_D63

+1.5V

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

DDR_A_RAS# DDR_A_CAS# M_A_ODT0 DDR_A_CKE0

DDR_A_WE# DDR_A_MA10 DDR_A_CS0# DDR_A_BS2

DDR_A_BS0 DDR_A_MA12 DDR_A_MA0 DDR_A_BS1

DDR_A_MA3

1K_0402_1%

RD7

DDR_A_MA1 DDR_A_MA2 DDR_A_MA4

DDR_A_MA5 DDR_A_MA11 DDR_A_MA9 DDR_A_MA14

DDR_A_MA13 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8

+1.5V

12

RD5 1K_0402_1%

CD3

12

1

1U_0402_6.3V6K

E3

DDR_B_D55

F7

DDR_B_D50

F2

DDR_B_D52

F8

DDR_B_D54

H3

DDR_B_D48

H8

DDR_B_D51

G2

DDR_B_D49

H7

DDR_B_D53

D7

DDR_B_D58

C3

DDR_B_D56

C8

DDR_B_D62

C2

DDR_B_D61

A7

DDR_B_D63

A2

DDR_B_D60

B8

DDR_B_D59

A3

DDR_B_D57

+1.5V

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Layout Note: Place near memory group

+0.75VS

CD8

CD6

1U

CD7

CD5

1U_0402_6.3V6K

_0402_6.3V6K

1

2

@

+1.5V

10U_0603_6.3V6M

CD12

CD13

1

2

1 2

RD17 36_0201_1%

1 2

RD18 36_0201_1%

1 2

RD19 36_0201_1% RD20 36_0201_1%

1 2 1 2

RD21 36_0201_1%

1 2

RD22 36_0201_1%

1 2

RD23 36_0201_1% RD24 36_0201_1%

1 2 1 2

RD26 36_0201_1%

1 2

RD27 36_0201_1%

1 2

RD28 36_0201_1% RD25 36_0201_1%

1 2 1 2

RD30 36_0201_1%

1 2

RD31 36_0201_1%

1 2

RD32 36_0201_1%

1 2

RD29 36_0201_1%

1 2

RD34 36_0201_1%

1 2

RD35 36_0201_1%

1 2

RD36 36_0201_1% RD33 36_0201_1%

1 2 1 2

RD38 36_0201_1%

1 2

RD39 36_0201_1%

1 2

RD40 36_0201_1% RD37 36_0201_1%

1 2

+VREF_CA_A

+VREF_CA_A +VREF_CA_B

1

2

1K_0402_1%

Enter RAM

M_CLK_A_DDR0

1

2

M_CLK_A_DDR#0

CD35

1.5P_0402_50V8

10U_0603_6.3V6M

1

2

RD8

30.1_0402_1%

+1.5V

RD13

2

CD1 4

12

2

1

2

+0.75VS

RD6 1K_0402_1%

CD3

1U_0402_6.3V6K

2

1

2

12

END topology

10U_0603_6.3V6M

CD1 5

1

2

CD33

0.1U_0402_16V4Z

12

2

1

2

CD9

1U _0402_6.3V6K

10U_0603_6.3V6M

CD1 6

+VREF_CA_B

Tacoma

RD14

30.1_0402_1%

10U_0603_6.3V6M

CD1

10U _0603_6.3V6M

0

1

2

10U_0603_6.3V6M

CD1

1

7

2

DDR_B_RAS#

RD42 36_0201_1%

DDR_B_CAS#

RD43 36_0201_1%

M_B_ODT0

RD44 36_0201_1% RD41 36_0201_1%

DDR_B_CKE0 DDR_B_WE#

RD46 36_0201_1%

DDR_B_MA10

RD47 36_0201_1%

DDR_B_CS0#

RD48 36_0201_1% RD45 36_0201_1%

DDR_B_BS2 DDR_B_BS0

RD50 36_0201_1%

DDR_B_MA12

RD51 36_0201_1%

DDR_B_MA0

RD52 36_0201_1% RD49 36_0201_1%

DDR_B_BS1 DDR_B_MA3

RD54 36_0201_1%

DDR_B_MA1

RD55 36_0201_1%

DDR_B_MA2

RD56 36_0201_1% RD53 36_0201_1%

DDR_B_MA4 DDR_B_MA5

RD58 36_0201_1%

DDR_B_MA11

RD59 36_0201_1%

DDR_B_MA9

RD60 36_0201_1% RD57 36_0201_1%

DDR_B_MA14 DDR_B_MA13

RD62 36_0201_1%

DDR_B_MA6

RD63 36_0201_1%

DDR_B_MA7

RD64 36_0201_1% RD61 36_0201_1%

DDR_B_MA8

1K_0402_1%

10U_0603_6.3V6M

CD1 1

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K CD2

CD19

CD1

CD2

1

+

8

2

1 2 1 2 1 2 1 2

12

RD67 1K_0402_1%

CD38

12

RD68

1

0

CD22 330U_B2_2.5VM_R15M

2

SGA00004400

+0.75VS

1U_0402_6.3V6K

1

2

+1.5V+1.5V

+V_DDR_REFA_DQ +V_DDR_REFB_DQ

1U_0402_6.3V6K

1

2

Enter RAM

M_CLK_B_DDR0

1

CD36

1.5P_0402_50V8

2

M_CLK_B_DDR#0

30.1_0402_1%

RD15

1K_0402_1%

1

CD34

0.1U_0402_16V4Z

2

12

END topology

12

RD65

Tacoma

RD16

30.1_0402_1%

CD2 3

12

1

2

RD66 1K_0402_1%

+V_DDR_REFB_DQ+V_DDR_REFA_DQ

CD3

1U_0402_6.3V6K

7

1U_0402_6.3V6K

CD2

CD25

CD2

4

6

1

2

1

2

E3

DDR_A_D39

F7

DDR_A_D38

F2

DDR_A_D36

F8

DDR_A_D34

H3

DDR_A_D32

H8

DDR_A_D33

G2

DDR_A_D35

H7

DDR_A_D37

D7

DDR_A_D45

C3

DDR_A_D46

C8

DDR_A_D40

C2

DDR_A_D47

A7

DDR_A_D41

A2

DDR_A_D43

B8

DDR_A_D44

A3

DDR_A_D42

+1.5V+1.5V

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

E3

DDR_B_D35

F7

DDR_B_D34

F2

DDR_B_D32

F8

DDR_B_D38

H3

DDR_B_D36

H8

DDR_B_D39

G2

DDR_B_D33

H7

DDR_B_D37

D7

DDR_B_D47

C3

DDR_B_D41

C8

DDR_B_D43

C2

DDR_B_D44

A7

DDR_B_D42

A2

DDR_B_D45

B8

DDR_B_D46

A3

DDR_B_D40

+1.5V

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+VREF_CA_A

+V_DDR_REFA_DQ

+VREF_CA_B

+V_DDR_REFB_DQ

2

10.1U_0402_16V7K

20.1U_0402_16V7K CD4

CD4

1

2

CD490.1U_0402_16V7K

CD500.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2011/7/12 2012/7/12

Deciphered Date

Compal Electronics, Inc.

Title

Size

D

Date: Sheet

SCHEMATICS,MB A8554

Document Number Rev

4019HW

1

12

C

of

46Thursday, May 09, 2013

5

1 2

RH115

10M_0402_5%

YH1

1 2

15P

32.768KHZ_12.5PF_9H03200019

_0402_50V8J

1

CH2

2

D D

PCH_RTCX1 PCH_RTCX2

1

CH3 15P_0402_50V8J

2

+RTCVCC

1 2

RH117

1 2

RH118

1U_0603_10V4Z 20K_0402_5% 20K_0402_5%

1U_0603_10V4Z

1

12

CH4

SHORT PADS

2

1

12

CH5

SHORT PADS

2

1/13 Change dimension to stardard part

1 2

RH116

+RTCVCC

RH119

HDA_BITCLK_AUDIO26

HDA_RST_AUDIO#26

HDA_SYNC_AUDIO26

C C

HDA_SDO28

HDA_SDOUT_AUDIO26

+3V_PCH +3V_PCH+3V_PCH

12

RH127

@

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH133

@

100_0402_1%

1 2

CH46 22P_0402_50V8J@

1 2

RH120

1 2

RH121

1 2

1M_0402_5%

1 2

@

1 2

RH125 33_0402_5%

12

RH128

@

200_0402_5%

12

RH134

@

100_0402_1%

SM_INTRUDER#

1M_0402_5%

FBMA-10-100505-301T_2P

HDA_BIT_CLK

HDA_RST#

33_0402_5%

HDA_SYNC_R HDA_SYNC

33_0402_5%

RH158

RH123

0_0402_5%

12

RH129

@

200_0402_5%

12

RH135

@

100_0402_1%

QH1

SB000002X00

BSS138W-7-F_SOT323-3

RH122 0_0402_5%@

HDA_SDOUT

+5VS

G

2

S

1 2

13

D

Reserve for EMI please close to U48

B B

SPI ROM FOR BIOS&ME ( 8MByte )

+3VS

1 2

RH141

1 2

RH145

1 2

RH144

22P_0402_50V8J

11/01 add CH8 for RF request

@

CH8

PCH_SPI_CS0#

3.3K_0402_5%

PCH_SPI_WP#

3.3K_0402_5%

PCH_SPI_HOLD#

3.3K_0402_5%

1

2

2/29 change power rail to 3VS follow QAU30,50

+3V_SPI

1

CH6

0.1U_0402_16V4Z

2

20mils

+3VS +3V_SPI

1 2

R211 0_0402_5%

PCH_SPI_WP#

PCH_SPI_HOLD# PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO

HDA_SDIN026

@

CH1

12

22P_0402_50V8J

8MByte SPI ROM PN SA000039A00

4

PCH_RTCX1

CLRP1

CLRP2

HDA_SPKR26

PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI PCH_SPI_SO

12

PCH_JTAG_TCK

RH15051_0402_5%

@

RH151

1 2

PCH_SPI_CLK

33_0402_5%

UH2

CONN@

8 3 7 1 6 5

32M W25Q32BVSSIG SOIC 8P SPI ROM

VCC W HOLD S C D

4

VSS

2

Q

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

UH2

RTCIHDA

JTAG

SPI

32M W25Q32BVSSIG SOIC 8P SPI ROM

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14

HDDHALT_LED#

P1

3

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED#

BBS_BIT0_R

R60 10K_0402_5%

23,28,30

LPC_AD0

23,28,30

LPC_AD1 LPC_AD2 23,28,30

23,28,30

LPC_AD3

LPC_FRAME#

SERIRQ

28,30

T19

PAD~D@

T20

PAD~D@

T21 PAD~D@

PAD~D@

T22

37.4_0402_1%

750_0402_1%

SATA_LED#

+1.05VS_VCC_SATA

+1.05VS_SATA3

26

1 2

RH130

1 2

RH132 49.9_0402_1%

1 2

RH137

1 2

R67 10K_0402_5%

1 2

23,28,30

SATA_PRX_DTX_N1 25 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 25

+3VS

2

25

JSATA1 SSD

25

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

HDA_SYNC

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low Needs to be pulled High for Huron River platfrom

HDA_SYNC

RTC Battery

+RTCVCC

W=20mils

1

CH7 1U_0603_10V4Z

2

1

BAV70W 3P C/C_SOT-323

1/5 Modify PIN define

1K_0402_5%

DH1

2 3

10/7 change +3VLP to +3VL

1

PCH_INTVRMEN

RH124 330K_0402_5%

PCH_INTVRMEN

RH126 330K_0402_5%@

INTVRMEN

：

Integrated VRM enable

H

*

：

Integrated VRM disable

L

SERIRQ

SATA_LED#

HDA_SPKR

RH131 10K_0402_5% RH136 10K_0402_5%@ RH138 10K_0402_5%

RH139 1K_0402_5%@

HDDHALT_LED#

*

HDA_SDOUT

RH140 1K_0402_5%@

Low = Disabled

*

High = Enabled

RH149 1K_0402_5%

+RTCBATT

10mils

12

20mils

RH148

+3VL

W=20mils

12 12

12 12 12

12

LOW=Default HIGH=No Reboot

12

+3V_PCH

12

4 3

2 1

ACES_50271-0020N-001

CONN@

+3V_PCH

JRTC1

GND GND

2 1

+RTCVCC

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

1

13 46Thursday, May 09, 2013

C

of

5

PCIE_PRX_DTX_N122

PCIE LAN

MiniWLAN --->

D D

PCIE Card Reader

Giga Lan--->

C C

WLAN--->

PCIE_PRX_DTX_P122 PCIE_PTX_C_DRX_N122 PCIE_PTX_C_DRX_P122

PCIE_PRX_DTX_N323 PCIE_PRX_DTX_P323

PCIE_PTX_C_DRX_N323

PCIE_PTX_C_DRX_P323

PCIE_PRX_DTX_N426

PCIE_PRX_DTX_P426 PCIE_PTX_C_DRX_N426 PCIE_PTX_C_DRX_P426

CLK_PCIE_LAN#22 CLK_PCIE_LAN22

LAN_CLKREQ#22

CLK_PCIE_MINI1#23 CLK_PCIE_MINI123

MINI1_CLKREQ#23

Card Reader--->

1/19 WL_OFF# Change to GPIO45

B B

XTAL25_IN

12

XTAL25_OUT

CLK_RES_ITP#6

3

4

1

CH13

2

CLK_RES_ITP6

12P _0402_50V8J

CH12

YH2

25MHZ 10PF +-20PPM 7V25000014

1

12P

1

GND

_0402_50V8J

1

2

RH1871M_0402_5%

GND

2

CH10 0.1U_0402_10V7K CH11 0.1U_0402_10V7K

CH83 0.1U_0402_10V7K CH82 0.1U_0402_10V7K

+3V_PCH

+3VS

CLK_PCIE_CD#26 CLK_PCIE_CD26

+3V_PCH

CLK_PCH_14M

CH37 0.1U_0402_10V7K CH9 0.1U_0402_10V7K

1 2 1 2

RH182 10K_0402_5%

RH180 10K_0402_5%

RH177 10K_0402_5%

RH320 10K_0402_5%

RH183 10K_0402_5%

RH185 10K_0402_5%

RH189 10K_0402_5%

RH190 0_0402_5%@ RH191 0_0402_5%@

1 2 1 2

RH171

1 2

RH316 10K_0402_5%

1 2

WL_OFF#23

1 2

12 12

@

RH193

33_0402_5%

4

CLK_PCIE_LAN# CLK_PCIE_LAN

10K_0402_5%

CLK_PCIE_MINI1# CLK_PCIE_MINI1

12

22P_0402_50V8J

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

CLK_PCIE_CD# CLK_PCIE_CD

CLK_BCLK_ITP# CLK_BCLK_ITP

@

CH14

1 2

PCIECLKREQ0#

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

SMBALERT#

H14

SMBCLK

C9

SMBDATA

A12

DRAMRST_CNTRL_PCH

C8

SML0CLK

G12

SML0DATA

C13

GPIO74

E14

SML1CLK

M16

SML1DATA

M7

T11

P10

M10

PCH_GPIO47

AB37 AB38

AV22 AU22

AM12 AM13

BF18

CLKIN_DMI#

BE18

CLKIN_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLKIN_DOT96#

E24

CLKIN_DOT96

AK7

CLKIN_SATA#

AK5

CLKIN_SATA

K45

CLK_PCH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47 H47 K49

DGPU_PRSNT#

RH155

1 2

Memory

10K_0402_5%

CLK_PCI_LPBACK

1 2

RH184 90.9_0402_1%

2

PV# 9/13 change power rail form +3VALW->+3V_PCH

+3V_PCH

10K_0402_5%

DRAMRST_CNTRL_PCH

RH8

T42

T43 T44

12

+3V_PCH

16

+1.05VS_VCCDIFFCLKN

PAD~D@

PAD~D@ PAD~D@

28,7,8

CLK_CPU_DMI# CLK_CPU_DMI

+3VS

12

RH322 10K_0402_5%

12

RH321 10K_0402_5%

@

CLK_CPU_DMI# CLK_CPU_DMI

2N7002DWH_SOT363-6

SMBCLK

SMBDATA

10/18 check to intel

6

2

6 1

QH2A

RH192

@

1 2

0_0402_5%

3 4

2N7002DWH_SOT363-6

1

SMBDATA SMBCLK SML0CLK SML0DATA SML1CLK SML1DATA

GPIO74

DRAMRST_CNTRL_PCH

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please place close to PCH

+3VS

2.2K_0402_5%

5

QH2B

RH194

1 2

0_0402_5%

@

+3VS

1 2

RH152

2.2K_0402_5%

1 2

RH153

2.2K_0402_5%

1 2

RH156

2.2K_0402_5%

1 2

RH157

2.2K_0402_5%

1 2

RH159

2.2K_0402_5%

1 2

RH160

2.2K_0402_5%

1 2

RH263 10K_0402_5%

1 2

RH161 1K_0402_5%

1 2

RH176

@

1 2

RH162 10K_0402_5%

1 2

RH163 10K_0402_5%

1 2

RH164 10K_0402_5%

1 2

RH165 10K_0402_5%

1 2

RH166 10K_0402_5%

1 2

RH167 10K_0402_5%

1 2

RH168 10K_0402_5%

1 2

RH169 10K_0402_5%

1 2

RH170 10K_0402_5%

+3VS

RH186

1 2

RH188

2.2K_0402_5%

1 2

1M_0402_5%~D

PCH_SMBCLK 23,29

PCH_SMBDATA

+3V_PCH

23,29

Reserve for EMI please close to UH1

1/13 YH2 Change dimension to stardard part

CLK_PCI_LPBACK

Reserve for EMI please close to UH1

A A

@

RH195

33_0402_5%

12

1 2

22P_0402_50V8J

@

CH15

2N7002DWH_SOT363-6

SML1CLK

SML1DATA

6 1

2

QH6A

3 4

2N7002DWH_SOT363-6

QH6B

26,28

EC_SMB_CK2

5

EC_SMB_DA2

26,28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A8554

Document Number Rev

4019HW

1

14 46Thursday, May 09, 2013

C

of

HP Spectre XT 13-2000 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual