HP PRO X2 410G Schematics

www.schematic-x.blogspot.com

Nobel UMA (11.6")

DDR3L Memory Down *8pcs FBGA96 10*14mm REV:E Maxima 8GBs

PAGE 12,13,14,15 Intel Shark Bay ULT

D D

System BIOS SPI ROM

PAGE 7

Digital MIC

SPK0415HM4H & STMP34DTE01

PAGE 27

Daughter Board

Speaker

C C

Combo Jack

PAGE 21

PAGE 22

DDR3L

SPI Interface

HeadPhone AMP

TPA6133A2RTJR

Touch Screen

Port5

PAGE 15

Audio Codec

92HD95 40_QFN

Package : QFN

Size : 6 x 6 (mm)

PAGE 22

USB To I2C For Touch PA(reserve)

Port3

PAGE 21

PAGE 29

USB2.0

EnE KB9010QF A1

Embedded Controller

Combo Jack

11.6” slate 299.3mm x 194.27mm x 11.6mm

Azalia

Package : LQPF128 Size : 14 x 14 (mm)

PAGE 21

Intel Shark Bay ULT Platform Block DiagramUltra

Y-serious Processor

Power : 4.5 (Watt)

Package : BGA1168

Size : 40 X 24 (mm)

PAGE 2~10

LPC

USB3.0 Interface

USB2.0

SMBUS

Docking Connector

PCB 10L STACK UP

Slate

eDP

SATA1 6GB/s

USB2.0 Interface

USB HUB

GL850G-OHG31

Port6

PAGE 28

Front Camera

SPCA2095A SPCA2095A

Port2

PAGE 18

Rear Camera

Port7

PAGE 18

11.6" eDP 1980x1080 Full HD

PAGE 16

NGFF SLOT-B SSD 22*42 and 22*80 (mm)

PAGE 17

Base Card reader

USB HUB Port1

LAYER 1 : TOP LAYER 2 : SGND LAYER 3 : IN1(High) LAYER 4 : IN2(Low) LAYER 5 : GND LAYER 6 : SVCC LAYER 7 : IN3(Low) LAYER 8 : IN4(High) LAYER 9 : GND LAYER 10 : BOT

Mini Card WLAN / BT Combo

Acceleometer + Magentometer HP303DLHCTR

I2C

PCIE3

USB HUB Port2

PAGE 20

Gyrometer HP3GD20HTR

PAGE 24 PAGE 24

ALS-Sensor

Capella CM32181

PAGE 24

PCIE Gen 1 x 1 Lane

Touch Screen

I2C

I2C1

PAGE 15

DDI

BASE TOUCH PAD

I2C1

PAGE 26

I2C

Card Reader

RTS5237-GR

Support CPPM Package : LQPF48 Size : 7 x 7 (mm)

PCIE2

PAGE 19

SENSOR HUB STM32F103RBH6

I2C0

PAGE 24

PAGE 26

Base

B B

I2C

I2C1

Touch Pad

DDI

Combo Jack

USB3.0 Interface

Embedded Controller

ENE IO3730B

Keyboard

A A

Package : LQFP-64

SMBUS

USB2.0 Interface USB 2.0 Port 0, 1

Size : 7 x 7 x 1.4

DDI1

USB 3.0 Port 1, 2

USB HUB Port1

HDMI Conn

USB3.0 Port x 2

CardReader IC Micro SD card slot

NB5/RD4

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Block Diagram

Date: Sheet of

Intel Shark Bay ULT

1 36Thursday, September 12, 2013

<6,7,8,9,10,11,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35>

U26A

IN_D2#<26> IN_D1#<26> IN_D0#<26> IN_CLK#<26> IN_D2<26> IN_D1<26> IN_D0<26>

D D

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

C C

IN_CLK<26>

EDP_DISP_UTIL<6>

INT_eDP_AUXP<16>

INT_eDP_AUXN<16>

INT_eDP_TXP0<16> INT_eDP_TXP1<16>

INT_eDP_TXN0<16> INT_eDP_TXN1<16>

DPB_LANE0_N DPB_LANE1_N DPB_LANE2_N DPB_LANE3_N DPB_LANE0_P DPB_LANE1_P DPB_LANE2_P DPB_LANE3_P

eDP_RCOMP EDP_DISP_UTIL

INT_eDP_AUXP INT_eDP_AUXN

INT_eDP_TXP0 INT_eDP_TXP1

INT_eDP_TXN0 INT_eDP_TXN1

+VCCIOA_OUT

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

C54

DDI1_TXN0

B58

DDI1_TXN1

B55

DDI1_TXN2

A57

DDI1_TXN3

C55

DDI1_TXP0

C58

DDI1_TXP1

A55

DDI1_TXP2

B57

DDI1_TXP3

C51

DDI2_TXN0

C53

DDI2_TXN1

C49

DDI2_TXN2

A53

DDI2_TXN3

C50

DDI2_TXP0

B54

DDI2_TXP1

B50

DDI2_TXP2

B53

DDI2_TXP3

D20

EDP_RCOMP

A43

EDP_DISP_UTIL

B45

EDP_AUXP

A45

EDP_AUXN

B46

eDP_TXP0

B47

eDP_TXP1

C46

eDP_TXP2

B49

eDP_TXP3

C45

eDP_TXN0

A47

eDP_TXN1

C47

eDP_TXN2

A49

eDP_TXN3

*HSW_ULT_DDR3L

R264 24.9/F_2

eDP_RCOMP

EC_PECI<23>

H_PROCHOT#<23,34>

eDP

R485 56.2/F_2

TP70

PCI EXPRESS* - GRAPHICS

TP65

TP41

R270 10K/F_2

PROC_DETECT# CATERR# EC_PECI

PROCHOT#

PROCPWRGD

U26B

D61

PROC_DETECT#

K61

CATERR#

N62

PECI

K63

PROCHOT#

C61

PROCPWRGD

*HSW_ULT_DDR3L

MISCTHERMALPWR MANAGEMENT

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3JTAG & BPM

SM_PG_CNTL1

PRDY# PREQ#

PROC_TCK

PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

AV15 AU60

AV60 AU61

AV61

J62 K62

E60 E61 E59

F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

SM_DRAMRST# SM_RCOMP_0

SM_RCOMP_1 SM_RCOMP_2

DDR_PG_CNTL

XDP_TCK0 XDP_TMS_CPU XDP_TRST#_CPU

XDP_TDI_CPU XDP_TDO_CPU

BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

R112 *0_4/S R175 200/F_4

R155 121/F_4 R172 100/F_2

TP73

XDP_PRDY#_CPU <11>

XDP_PREQ#_CPU <11>

TP42

XDP_TCK0 <11> XDP_TMS_CPU <11> XDP_TRST#_CPU <7,11>

XDP_TDI_CPU <11>

XDP_TDO_CPU <11>

XDP_BPM0 <11>

XDP_BPM1 <11>

TP51 TP44 TP43 TP56 TP40 TP50

+1.35VSUS

R113 470_4

DDR3_DRAMRST# <12,13,14,15>

Processor pull-up (CPU)

H_PROCHOT#

XDP_TDO_CPU

B B

XDP_TMS_CPU XDP_TDI_CPU

R490 62_4

+V1.05S_VCCST

R494 51_2 R504 *51_2 R495 *51_2

+V1.05S_VCCST

Local Thermal Sensor

C394 *0.01U/25V_4

U29

MBCLK2<8,16,23>

MBDATA2<8,16,23>

A A

MBCLK2 MBDATA2 IO_THERMDA_L

+3V

Place under CPU heat pipe

R474 *0_4 R473 *0_4

R502 10K_2

8 7 6 4

*G781-1P8

SCLK SDA ALERT# OVERT#

VCC

DXP

IO_THERMDC_L

DXN

GND

G781-1P8(9Ah)

lace under CPU heat pipe

CPUOVERT <23>

IO_THERMDA_IO

C406 *2200P/50V_4

IO_THERMDC_IO

+3V

Q21

1 3

*METR3904-G

XDP_TRST#_CPU XDP_TCK0

R521 *51_2 R500 51_2

+1.35VSUS <4,12,13,14,15,25,33> +V1.05S_VCCST <4,9,11,34> +3V

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 1/9(eDP/DDI)

NB5/RD4

ULT 1/9(eDP/DDI)

Date: Sheet of

Date: Sheet

Intel Shark Bay ULT

2 36Thursday, September 12, 2013

U26C

AH63

M_A_DQ0<12> M_A_DQ1<12> M_A_DQ2<12> M_A_DQ3<12> M_A_DQ4<12> M_A_DQ5<12> M_A_DQ6<12> M_A_DQ7<12>

D D

C C

B B

M_A_DQ8<12>

M_A_DQ9<12> M_A_DQ10<12> M_A_DQ11<12> M_A_DQ12<12> M_A_DQ13<12> M_A_DQ14<12> M_A_DQ15<12> M_A_DQ16<12> M_A_DQ17<12> M_A_DQ18<12> M_A_DQ19<12> M_A_DQ20<12> M_A_DQ21<12> M_A_DQ22<12> M_A_DQ23<12> M_A_DQ24<12> M_A_DQ25<12> M_A_DQ26<12> M_A_DQ27<12> M_A_DQ28<12> M_A_DQ29<12> M_A_DQ30<12> M_A_DQ31<12> M_A_DQ32<13> M_A_DQ33<13> M_A_DQ34<13> M_A_DQ35<13> M_A_DQ36<13> M_A_DQ37<13> M_A_DQ38<13> M_A_DQ39<13> M_A_DQ40<13> M_A_DQ41<13> M_A_DQ42<13> M_A_DQ43<13> M_A_DQ44<13> M_A_DQ45<13> M_A_DQ46<13> M_A_DQ47<13> M_A_DQ48<13> M_A_DQ49<13> M_A_DQ50<13> M_A_DQ51<13> M_A_DQ52<13> M_A_DQ53<13> M_A_DQ54<13> M_A_DQ55<13> M_A_DQ56<13> M_A_DQ57<13> M_A_DQ58<13> M_A_DQ59<13> M_A_DQ60<13> M_A_DQ61<13> M_A_DQ62<13> M_A_DQ63<13>

M_A_BS0<12,13> M_A_BS1<12,13> M_A_BS2<12,13>

M_A_CAS_N<12,13> M_A_RAS_N<12,13>

M_A_WE_N<12,13>

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_BS0 M_A_BS1 M_A_BS2

M_A_CAS_N M_A_RAS_N M_A_WE_N

AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57

AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

AU35 AV35 AY41

AU34 AY34

AW34

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BA0 SA_BA1 SA_BA2

SA_CAS# SA_RAS# SA_WE#

*HSW_ULT_DDR3L

DDR SYSTEM MEMORY A

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CKE2

SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

Haswell ULT Processor (DDR3L)

AV37

M_A_DIM0_CLK_DDR0_DP

AU37

M_A_DIM0_CLK_DDR0_DN

AU43

M_A_DIM0_CKE0

AY36 AW36 AW43

M_A_DIM0_CKE1

AY42

AY43

AP33

M_A_DIM0_CS0_N

AR32

M_A_DIM0_CS1_N

AP32

AJ61

M_A_DQS_DN0

AN62

M_A_DQS_DN1

AM58

M_A_DQS_DN2

AM55

M_A_DQS_DN3

AV57

M_A_DQS_DN4

AV53

M_A_DQS_DN5

AL43

M_A_DQS_DN6

AL48

M_A_DQS_DN7

AJ62

M_A_DQS_DP0

AN61

M_A_DQS_DP1

AN58

M_A_DQS_DP2

AN55

M_A_DQS_DP3

AW57

M_A_DQS_DP4

AW53

M_A_DQS_DP5

AL42

M_A_DQS_DP6

AL49

M_A_DQS_DP7

AU36

M_A_A0

AY37

M_A_A1

AR38

M_A_A2

AP36

M_A_A3

AU39

M_A_A4

AR36

M_A_A5

AV40

M_A_A6

AW39

M_A_A7

AY39

M_A_A8

AU40

M_A_A9

AP35

M_A_A10

AW41

M_A_A11

AU41

M_A_A12

AR35

M_A_A13

AV42

M_A_A14

AU42

M_A_A15

AP49

SM_VREF

AR51

SMDDR_VREF_DQ0_M3

AP51

SMDDR_VREF_DQ1_M3

20mils width

R623 *0_2

M_A_DIM0_CLK_DDR0_DP <12,13> M_A_DIM0_CLK_DDR0_DN <12,13> M_A_DIM0_CKE0 <12,13>

M_A_DIM0_CKE1 <12,13>

M_A_DIM0_CS0_N <12,13> M_A_DIM0_CS1_N <12,13>

M_A_ODT_2M_A_ODT_1

M_A_DQS_DN0 <12> M_A_DQS_DN1 <12> M_A_DQS_DN2 <12> M_A_DQS_DN3 <12> M_A_DQS_DN4 <13> M_A_DQS_DN5 <13> M_A_DQS_DN6 <13> M_A_DQS_DN7 <13>

M_A_DQS_DP0 <12> M_A_DQS_DP1 <12> M_A_DQS_DP2 <12> M_A_DQS_DP3 <12> M_A_DQS_DP4 <13> M_A_DQS_DP5 <13> M_A_DQS_DP6 <13> M_A_DQS_DP7 <13>

M_A_A0 <12,13> M_A_A1 <12,13> M_A_A2 <12,13> M_A_A3 <12,13> M_A_A4 <12,13> M_A_A5 <12,13> M_A_A6 <12,13> M_A_A7 <12,13> M_A_A8 <12,13> M_A_A9 <12,13> M_A_A10 <12,13> M_A_A11 <12,13> M_A_A12 <12,13> M_A_A13 <12,13> M_A_A14 <12,13> M_A_A15 <12,13>

SM_VREF <12> SMDDR_VREF_DQ0_M3 <12> SMDDR_VREF_DQ1_M3 <14>

M_A_ODT_2 <12>

U26D

AY31

M_B_DQ0<14> M_B_DQ1<14> M_B_DQ2<14> M_B_DQ3<14> M_B_DQ4<14> M_B_DQ5<14> M_B_DQ6<14> M_B_DQ7<14> M_B_DQ8<14>

M_B_DQ9<14> M_B_DQ10<14> M_B_DQ11<14> M_B_DQ12<14> M_B_DQ13<14> M_B_DQ14<14> M_B_DQ15<14> M_B_DQ16<14> M_B_DQ17<14> M_B_DQ18<14> M_B_DQ19<14> M_B_DQ20<14> M_B_DQ21<14> M_B_DQ22<14> M_B_DQ23<14> M_B_DQ24<14> M_B_DQ25<14> M_B_DQ26<14> M_B_DQ27<14> M_B_DQ28<14> M_B_DQ29<14> M_B_DQ30<14> M_B_DQ31<14> M_B_DQ32<15> M_B_DQ33<15> M_B_DQ34<15> M_B_DQ35<15> M_B_DQ36<15> M_B_DQ37<15> M_B_DQ38<15> M_B_DQ39<15> M_B_DQ40<15> M_B_DQ41<15> M_B_DQ42<15> M_B_DQ43<15> M_B_DQ44<15> M_B_DQ45<15> M_B_DQ46<15> M_B_DQ47<15> M_B_DQ48<15> M_B_DQ49<15> M_B_DQ50<15> M_B_DQ51<15> M_B_DQ52<15> M_B_DQ53<15> M_B_DQ54<15> M_B_DQ55<15> M_B_DQ56<15> M_B_DQ57<15> M_B_DQ58<15> M_B_DQ59<15> M_B_DQ60<15> M_B_DQ61<15> M_B_DQ62<15> M_B_DQ63<15>

M_B_BS0<14,15> M_B_BS1<14,15> M_B_BS2<14,15>

M_B_CAS_N<14,15> M_B_RAS_N<14,15>

M_B_WE_N<14,15>

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_BS0 M_B_BS1 M_B_BS2

M_B_CAS_N M_B_RAS_N M_B_WE_N

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23

AW23

AY21

AW21

AV23 AU23

AV21 AU21

AY19

AW19

AY17

AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

AL35 AM36 AU49

AM33 AM35

AK35

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BA0 SB_BA1 SB_BA2

SB_CAS# SB_RAS# SB_WE#

AN38

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CKE2

SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

SB_MA0 SB_MA1 SB_MA2 SB_MA3

DDR SYSTEM MEMORY B

SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

M_B_DIM0_CLK_DDR0_DP

AM38

M_B_DIM0_CLK_DDR0_DN

AY49

M_B_DIM0_CKE0

AL38 AK38 AU50

M_B_DIM0_CKE1

AW49

AV50

AM32

M_B_DIM0_CS0_N

AK32

M_B_DIM0_CS1_N

AL32

M_B_ODT_1

AW30

M_B_DQS_DN0

AV26

M_B_DQS_DN1

AN28

M_B_DQS_DN2

AN25

M_B_DQS_DN3

AW22

M_B_DQS_DN4

AV18

M_B_DQS_DN5

AN21

M_B_DQS_DN6

AN18

M_B_DQS_DN7

AV30

M_B_DQS_DP0

AW26

M_B_DQS_DP1

AM28

M_B_DQS_DP2

AM25

M_B_DQS_DP3

AV22

M_B_DQS_DP4

AW18

M_B_DQS_DP5

AM21

M_B_DQS_DP6

AM18

M_B_DQS_DP7

AP40

M_B_A0

AR40

M_B_A1

AP42

M_B_A2

AR42

M_B_A3

AR45

M_B_A4

AP45

M_B_A5

AW46

M_B_A6

AY46

M_B_A7

AY47

M_B_A8

AU46

M_B_A9

AK36

M_B_A10

AV47

M_B_A11

AU47

M_B_A12

AK33

M_B_A13

AR46

M_B_A14

AP46

M_B_A15

R624 *0_2

M_B_DIM0_CLK_DDR0_DP <14,15> M_B_DIM0_CLK_DDR0_DN <14,15> M_B_DIM0_CKE0 <14,15>

M_B_DIM0_CKE1 <14,15>

M_B_DIM0_CS0_N <14,15> M_B_DIM0_CS1_N <14,15>

M_B_DQS_DN0 <14> M_B_DQS_DN1 <14> M_B_DQS_DN2 <14> M_B_DQS_DN3 <14> M_B_DQS_DN4 <15> M_B_DQS_DN5 <15> M_B_DQS_DN6 <15> M_B_DQS_DN7 <15>

M_B_DQS_DP0 <14> M_B_DQS_DP1 <14> M_B_DQS_DP2 <14> M_B_DQS_DP3 <14> M_B_DQS_DP4 <15> M_B_DQS_DP5 <15> M_B_DQS_DP6 <15> M_B_DQS_DP7 <15>

M_B_A0 <14,15> M_B_A1 <14,15> M_B_A2 <14,15> M_B_A3 <14,15> M_B_A4 <14,15> M_B_A5 <14,15> M_B_A6 <14,15> M_B_A7 <14,15> M_B_A8 <14,15> M_B_A9 <14,15> M_B_A10 <14,15> M_B_A11 <14,15> M_B_A12 <14,15> M_B_A13 <14,15> M_B_A14 <14,15> M_B_A15 <14,15>

M_B_ODT_2 <14>

A A

*HSW_ULT_DDR3L

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 2/9 (DDR3 I/F)

NB5/RD4

ULT 2/9 (DDR3 I/F)

Date: Sheet of

Date: Sheet

Intel Shark Bay ULT

3 36Thursday, September 12, 2013

32A

+VCC_CORE

C188

C240

C196

C238

C250

C249

C194

C186

22U/6.3VT_8

C247 22U/6.3VT_8

C213

22U/6.3VT_8

C228

22U/6.3VT_8

C241

22U/6.3VT_8

C211

22U/6.3VT_8

C195

22U/6.3VT_8

C184

22U/6.3VT_8

C242 22U/6.3VT_8

C198 22U/6.3VT_8

C251

22U/6.3VT_8

C154

22U/6.3VT_8

C185

22U/6.3VT_8

D D

C187

22U/6.3VT_8

C197

22U/6.3VT_8

C239

22U/6.3VT_8

C248

22U/6.3VT_8

C169

22U/6.3VT_8

C210

22U/6.3VT_8

C C

C227

C209 22U/6.3VS_8

C208 22U/6.3VS_8

22U/6.3VS_8

C212 22U/6.3VS_8

B B

A A

+VCCIOA_OUT <2> +VCCIO_OUT <6> +1.35VSUS <2,12,13,14,15,25,33> +1.05V <7,10,11,23,32,35> +VCC_CORE <25,34>

U26F

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23

J23 K23 K57 L22 M23 M57 P57 U57

W57 AB57 AD57 AG57

C24 C28 C32

F59

L59

J58

N58 AC58 AB23 AD23 AA23 AE59

AT2 AU44 AV44

D15

F22

H22

J21 N23 R23 T23 U10 AL1

AM11

AP7

AU10 AU15

*HSW_ULT_DDR3L

+3V_DEEP_SUS <6,7,8,9,10,11> +3VPCU <20,23,26,27,35>

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

POWER

HSW ULT POWER

PWR_DEBUG#

VCCST_PWRGD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCIO_OUT

VCCIOA_OUT

VIDALERT#

VIDSCLK VIDSOUT

VR_EN

VR_READY

VCCST VCCST VCCST

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

VCC_SENSE VSS_SENSE

RSVD RSVD

VSS VSS

1.4A

+1.35VSUS

AH26 AJ31 AJ33 AJ37

C161

AN33

10U/6.3V_6

AP43 AR48 AY35 AY40 AY44

Direct tie to CPU VCC/VSS-Ball

AY50

C166

2.2U/6.3V_4

D63 P62 T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59

A59 E20

L62

H_CPU_SVIDALRT#

N63

VR_SVID_CLK

L63

H_CPU_SVIDDAT

H59

PWR_DEBUG

F60 C59

R520 10K_2

AC22 AE22 AE23

B59

P60 P61 N59 N61

E63 E62

AW14 AY14

+V1.05S_VCCST

H_VCCST_PWRGD_R

TP94 TP37 TP39 TP96

R503 100/F_2

R501 100/F_2

TP77 TP79

100- ±1% pull-up to VCC near processor.

Close to CPU

C162

C160

10U/6.3V_6

C148

2.2U/6.3V_4

R271 *0_8

IMVP_PWRGD_R

R519 0_4

R531 *0_4/S

+VCC_CORE VCC_SENSE <34> VSS_SENSE <34>

Processor Strapping

CFG3 (Physcial Debug Enable) DFX Privacy

CFG4

(DP Presence Strap)

CFG0-19 need Reserve TP

C163

C159 10U/6.3V_6

C150

C147

2.2U/6.3V_4

+VCCIO_OUT+1.05V

C230

4.7U/6.3V_6

+VCCIO_OUT +VCCIOA_OUT

TP99

D16 *RB501V-40

2 1

H_VCCST_PWRGD

The CFG signals have a default value of '1' if not terminated on the board.

Disable: Enable: Set DFX Enable in DFX interface MSR

Disable; No physical DP attached to eDP

C164

10U/6.3V_6

+V1.05S_VCCST

Layout note: need routing together and ALERT need between CLK and DATA.

H_CPU_SVIDALRT#

PWR_DEBUG <11>

H_VR_ENABLE_MCP <34>

IMVP_PWRGD_R <23> IMVP_PWRGD <6,34>

HWPG<11,23,30,32,33> H_VCCST_PWRGD <11>

VR_SVID_CLK

H_CPU_SVIDDAT

U33

GND

*74AUP1G07GW

D17 RB501V-40

R466 43_4

R478 *0_4/S

VCC

5 4

R477 75/F_4

+V1.05S_VCCST

R483 130/F_4

+3V_DEEP_SUS

C431 *0.1U/10V_4

C390 *0.1U/10V_4

Place PU resistor close to VR

1 0

Enable; An ext DP device is connected to eDP

CFG0<11> CFG1<11> CFG2<11> CFG3<11> CFG4<11> CFG5<11> CFG6<11> CFG7<11> CFG8<11> CFG9<11> CFG10<11> CFG11<11> CFG12<11> CFG13<11> CFG14<11> CFG15<11> CFG16<11> CFG17<11> CFG18<11> CFG19<11>

SVID ALERT

VR_SVID_ALERT# <34>

SVID CLK

VR_SVID_CLK <34>

D DATA

SVI

VR_SVID_DATA <34>

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19

+V1.05S_VCCST

R534 10K_2

C430 *10P/50V_4

CFG3

CFG4

TP22 TP26 TP19 TP91 TP30 TP20 TP18 TP25 TP55 TP47 TP52 TP60 TP54 TP49 TP62 TP61 TP58 TP45 TP36 TP32

TP63 TP64

TP78 TP76

R449

CFG_RCOMP

49.9/F_4

TD_IREF

R526

8.2K/F_4

Circuit

R431 *1K_2

R222 1K_2

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19

U26E

AC60 AC62 AC63 AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61

T60 AA62 AA61

U63

U62

V63

D1 J20 H18

B12

AV63 AU63

C63 C62 B43

*HSW_ULT_DDR3L

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19

CFG_RCOMP

RSVD RSVD

RSVD RSVD RSVD

TD_IREF

RSVD_TP RSVD_TP

RSVD_TP RSVD_TP RSVD

PROC_OPI_RCOMP

RESERVED

IO Thrm Protect

+3VPCU

For 65 degree, 1.8v limit, (SW)

R152

16.5K/F_4

R156

3.3K/F_4

For 75 degree, 1.2v limit, (HW)

R169 0_4

THER_CPU

R215 100K_4 NTC

+V1.05S_VCCST+1.05V

R218 *0_8/S

+V1.05S_VCCST

NB5/RD4

A51

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD RSVD

RSVD RSVD

C108

0.1U/10V_4

1 2

C118

0.1U/10V_4

1 2

C144 *1U/6.3V_4

R491 150/F_4

PWR_DEBUG

R493 *10K_2

PROJECT : Nobel

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

Date: Sheet

TP104

B51

TP103

L60

TP38

N60 W23 Y22

AY15

PROC_OPI_RCOMP

AV62

R359

D58

49.9/F_4

P22

VSS

N21

VSS

P20 R20

THRM_MOINTOR <23>

THRM_MOINTOR1 <23>

C165 *22U/6.3V_8

Quanta Computer Inc.

ULT 3/9 (POWER-1)

Intel Shark Bay ULT

4 36Thursday, September 12, 2013

U26G

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

D D

C C

B B

A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5 AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

*HSW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

U26H

AP22

VSS

AP23

VSS

AP26

VSS

AP29

VSS

AP3

VSS

AP31

VSS

AP38

VSS

AP39

VSS

AP48

VSS

AP52

VSS

AP54

VSS

AP57

VSS

AR11

VSS

AR15

VSS

AR17

VSS

AR23

VSS

AR31

VSS

AR33

VSS

AR39

VSS

AR43

VSS

AR49

VSS

AR5

VSS

AR52

VSS

AT13

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT42

VSS

AT43

VSS

AT46

VSS

AT49

VSS

AT61

VSS

AT62

VSS

AT63

VSS

AU1

VSS

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

*HSW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

TEST_AY60

TP75 TP69

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

TEST_B2

DC_TEST_A3_B3

TP67

DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

U26I

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

H13

VSS

AY2

DAISY_CHAIN_NTCF_AY2

AY3

DAISY_CHAIN_NTCF_AY3

AY60

DAISY_CHAIN_NTCF_AY60

AY61

DAISY_CHAIN_NTCF_AY61

AY62

DAISY_CHAIN_NTCF_AY62

DAISY_CHAIN_NTCF_B2

DAISY_CHAIN_NTCF_B3

B61

DAISY_CHAIN_NTCF_B61

B62

DAISY_CHAIN_NTCF_B62

B63

DAISY_CHAIN_NTCF_B63

DAISY_CHAIN_NTCF_C1

DAISY_CHAIN_NTCF_C2

*HSW_ULT_DDR3L

VSS

DAISY_CHAIN_NTCF_A3

DAISY_CHAIN_NTCF_A4 DAISY_CHAIN_NTCF_A60 DAISY_CHAIN_NTCF_A61 DAISY_CHAIN_NTCF_A62 DAISY_CHAIN_NTCF_AV1

DAISY_CHAIN_NTCF_AW 1 DAISY_CHAIN_NTCF_AW 2

DAISY_CHAIN_NTCF_AW 3 DAISY_CHAIN_NTCF_AW 61 DAISY_CHAIN_NTCF_AW 62 DAISY_CHAIN_NTCF_AW 63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63 V58 AH46 V23 AH16

DC_TEST_A3_B3

TEST_A4

A60

TEST_A60

A61

DC_TEST_A61_B61

A62

TEST_A62

AV1

TEST_AV1

AW1

TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

TEST_AW63

TP66

TP68 TP8 TP10

TP74

A A

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 4/9 (RSV,GND)

NB5/RD4

ULT 4/9 (RSV,GND)

Date: Sheet of

Intel Shark Bay ULT

5 36Thursday, September 12, 2013

Lynx Point-LP Platform Controller Hub (LVDS,DDI)

U26M

PCH_eDP_BLON<16> PCH_DISP_ON<16>

D D

SUSACK#SUSWARN#

SUSACK#

SYS_RESET#

C364 *0.1U/10V_2

TP13

EC_PWROK

PLTRST#

RSMRST# SUSWARN#

DNBSWON#_R

AC_PRESENT_R

PM_BATLOW# PCH_SLP_S0_N PCH_SLP_WLAN_N

SYS_RESET#<11>

R183 *0_4

R187 0_4

RSMRST#<23>

R178 0_4

R163 0_4

R403 0_4

PCH_SLP_S0_N<11,23>

for DS3

SUSACK#_EC<23>

SYS_PWROK<11>

C C

EC_PWROK<23>

for DS3

SUSWARN#_EC<23>

DNBSWON#<11,23>

U26L

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK/GPIO30(SUS)

AL7

PWRBTN#

AJ8

ACPRESENT / GPIO31(DSW)

AN4

BATLOW# / GPIO72(DSW )

AF3

SLP_S0#

AM5

SLP_WLAN#/ GPIO29(DSW )

*HSW_ULT_DDR3L

System Power Management

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/ GPIO32

SUS_STAT# / GPIO61 (SUS)

SUSCLK / GPIO62 (SUS)

SLP_S5# / GPIO63 ( DSW)

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

SLP_LAN#

AW7

DSWVRMEN

AV5

DPWROK RSMRST#

AJ5

PCIE_WAKE#

CLKRUN#

AG4

SUS_STAT#

AE6

PCH_SUSCLK_L

AP5

AJ6

AT4

AL5

AP4

SLP_SUS#

AJ7

SLP_LAN#

DSWVRMEN <7>

R361 0_4 R366 *0_4

PCIE_WAKE# <19,20,23>

CLKRUN# <23>

R214 *0_4/S

SLP_S5# <11>

SUSC# <11,23>

SUSB# <11,23>

TP14

SLP_A# <11>

R374 0_4

TP24

For DS3 -->Ra Non-DS3 -->Rb

DPWROK_EC

TP15

for DS3

SLP_SUS#_EC

PCH_DPST_PWM<16>

EDP_DISP_UTIL<2>

DPWROK_EC <23>

PCH_SUSCLK <17,23>

TP21

SLP_SUS#_EC <23>AC_PRESENT_EC<23>

PCH_eDP_BLON PCH_DISP_ON PCH_DPST_PWM

R530 *0_4

EDP_BKLEN

EDP_VDDEN

EDP_BKLCTL

*HSW_ULT_DDR3L

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP SIDEBAND

DDPB_AUXN DDPB_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DISPLAY

DDPB_HPD

DDPC_HPD

EDP_HPD

B9 C9

C5 B5 C8

D9 D11

B6 A6 A8

SDVO_CLK SDVO_DATA

HDMI_HPD_DC

INT_eDP_HPD_Q

SDVO_CLK <26> SDVO_DATA <26>

HDMI_HPD_DC <26>

INT. HDMI

B B

PCH Pull-high/low(CLG)

PM_BATLOW# PCIE_WAKE#

SUSACK# SUSWARN#

Check SUSWARN# need PU?

PWRBTN# internally PU in PCH to 3.3V_DSW

DNBSWON#_R AC_PRESENT_R

A A

SYS_PWROK CLKRUN# SYS_RESET#

RSMRST# DPWROK_EC

R378 10K_2 R174 1K_2

R188 10K_2 R179 10K_2

R170 *10K_2 R401 *10K_2

R408 *1K_2

R465 8.2K/F_4 R213 10K_2 R212 *1K_2 R367 10K_2

R358 100K_2

+3VS5

+3V_DEEP_SUS

+3V

for DS3

+3VS5

PLTRST#(CLG)

R196 100K_2

INT_eDP_HPD_Q

PLTRST#

R277 0_4

Q12 *2N7002

R280 *100K_2

Check Q11 Rise/Fall time less than 100ns

PLTRST# <11,19,20,23,25,28>

Reserve EDP_HPD opposites circuit!

+VCCIO_OUT

R522

DG V0.7 -> 10K

*10K/F_2

SCH V0.7 -> 1K

INT_eDP_HPD

+5V

R523 100K_2

Q11

*2N7002

R278 1K/F_4

R281 *100K_2

7/22:follow reference design,mount R523,unmount R281

EDP_HPD_L <16>

System PWR_OK(CLG)

+3VS5

C379 *0.1U/10V_2

SYS_PWROK

U27 *TC7SH08FU

2 1

3 5

R443 0_4

EC_PWROK

R444 10K_2

IMVP_PWRGD <4,34>

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 5/9(Power Manger)

NB5/RD4

ULT 5/9(Power Manger)

Date: Sheet of

Date: Sheet

Intel Shark Bay ULT

+3V<2,7,8,9,10,11,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35>

+3VS5<9,10,11,20,26,27,29,30,35>

+5V<20,21,22,29,35>

6 36Thursday, September 12, 2013

Lynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)

U26J

TP7

PCH_SPI1_CLK PCH_SPI_CS0#

PCH_SPI1_SI PCH_SPI1_SO PCH_SPI_IO2

PCH_SPI_IO3

AW5

RTCX1

AY5

RTCX2

AU7

RTCRST#

AV6

SRTCRST#

AU6

INTRUDER#

AV7

INTVRMEN

AW8

HDA_BCLK / I2S0_SCLK

AV11

HDA_SYNC/ I2S0_SFRM

AU8

HDA_RST#/ I2S_MCLK

AY10

HDA_SDIN0/ I2S0_RXD

AU12

HDA_SDIN1/ I2S1_RXD

AU11

HDA_SDO/ I2S0_TXD

AW10

HDA_DOCK_EN# / I2S1_TXD

AV10

HDA_DOCK_RST/ I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST#

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

AA3

SPI_CLK

SPI_CS0#

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

SPI_IO2

AF1

SPI_IO3

*HSW_ULT_DDR3L

RTC

SPI JTAG

PWROK

ALWAYS Should be always pull-up

RTC_X1 RTC_X2

RTC_RST#<11>

D D

C C

B B

+3V_RTC

PCH Strap Table

R139 1M_2

ACZ_SDIN0<21>

XDP_TRST#_CPU<2,11>

JTAG_TCK_PCH<11> JTAG_TDI_PCH<11>

JTAG_TDO_PCH<11>

JTAG_TMS_PCH<11>

JTAGX_PCH<11>

Pin Name Strap description Sampled Configuration

SPKR

RTC_RST# SRTC_RST# SRTC_RST# SM_INTRUDER# PCH_INVRMEN

ACZ_BCLK ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

XDP_TRST#_CPU JTAG_TCK_PCH JTAG_TDI_PCH JTAG_TDO_PCH JTAG_TMS_PCH

JTAGX_PCH

No reboot mode setting PWROK

SDIO_D0 /GPIO66 Top-Block Swap INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up HDA_SDO /I2S0_TXD

GSPI0_MOSI /GPIO86 PWROK

GPIO15

DSWVRMEN

A A

Flash Descriptor Security

Only for Interposer

Boot BIOS Selection

TLS Confidentiality PWROK

Deep Sx Well On-Die Voltage Regulator Enable

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

LPC

GNT0#

1 0

H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

C12

A12

L11 K10

SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0

SATA0GP SATA1GP PCI_SERR# SIO_EXT_SMI#

SATA_RCOMP

SATA_IREF

Boot Location

LPC

SPI(Default)

SATA_RN0/ PERN6_L3 SATA_RP0/ PERP6_L3 SATA_TN0/ PETN6_L3

SATA_TP0/ PETP6_L3

SATA_RN1/ PERN6_L2 SATA_RP1/ PERP6_L2 SATA_TN1/ PETN6_L2

SATA_TP1/ PETP6_L2

SATA_RN2/ PERN6_L1 SATA_RP2/ PERP6_L1 SATA_TN2/ PETN6_L1

SATA_TP2/ PETP6_L1

SATA_RN3/ PERN6_L0

AUDIO

SATA_RP3/ PERP6_L0 SATA_TN3/ PETN6_L0

SATA_TP3/ PETP6_L0

SATA0GP/ GPIO34 SATA1GP/ GPIO35 SATA2GP/ GPIO36 SATA3GP/ GPIO37

SATA_RCOMP

SATA

SATA_IREF

SATALED#

RSVD RSVD

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode

0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

0 = Default (weak pull-down 20K)

1 = Can be Overridden

0 = ME Crypto Transport Layer Security cipher suite with no confidentiality(Default)

1 = Intel ME Crypto TLS cipher suite with confidentiality

LAD0 <20,23,25> LAD1 <20,23,25> LAD2 <20,23,25> LAD3 <20,23,25>

LFRAME# <20,23,25>

SATA_RXN0 <17> SATA_RXP0 <17> SATA_TXN0 <17> SATA_TXP0 <17>

TP93

SATA0GP <23>

TP95

PCI_SERR# <23>

TP31

SIO_EXT_SMI# <23>

R514 3.01K/F_2

R536 *0_6/S

R462 10K_2

+1.05V

R416 *0_4

+1.05VS5

R415 *51_2 R414 51_2 R417 51_2 R402 51_2 R418 *51_2

Close to Chipset

JTAGX_PCH JTAG_TMS_PCH JTAG_TDI_PCH JTAG_TDO_PCH JTAG_TCK_PCH

MSATA0 (SATA3 6.0Gb/s)

+V1.05S_ASATA3PLL

DG recommended that SATA AC coupling capacitors should be close to the connector (<100 mils) for optimal signal quality.

+3V

Circuit

SPKR

PCH_INVRMEN

ACZ_SDOUT

SPKR <9>

GPIO66_ULT <9>

GPIO15_ULT <9>

DSWVRMEN <6>

PCH_SPI_CS0#_R PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R

GPIO33_EC<23>

+3V_DEEP_SUS

+3V

+3V_RTC

R437 *1K_2 R517 *1K_2

R518 *1K_2

R142 330K_4

R362 1K_2

R221 1K_2

R115 330K_4

PCH_SPI_CS0#_R<23> PCH_SPI1_CLK_R<23> PCH_SPI1_SI_R<23> PCH_SPI1_SO_R<23>

RTC Circuitry(RTC)

+3V_RTC_0

CN18 BAT_CONN

DFHD02MR045

RTC Power trace width 20mils.

RTC_RST#

EC_RTC_RST#<23>

ACZ_SYNC_AUDIO<21>

ACZ_SDOUT_AUDIO<21>

Vender

EC_RTC_RST#

ACZ_RST#_AUDIO<21>

BIT_CLK_AUDIO<21>

+3V_DEEP_SUS

Size

Winbond

GigaDevice AKE3EGN0Q01

Socket

TP place to TOP

C398 1U/6.3V_2

+3V <2,6,8,9,10,11,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35>

+1.05V <4,10,11,23,32,35>

+3VS5 <6,9,10,11,20,26,27,29,30,35> +3VREG <16,23,27,30,31,35> +3V_RTC <10>

+V1.05S_ASATA3PLL <10>

RTC Power trace width 20mils.

+3VREG

+3V_RTC_1

R4201K_2

D14 BAT54CW

Q32 *2N7002

R731

*100K/F_4

HDA Bus(CLG)

PCH_SPI_CS0#_R PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R BIOS_WP# HOLD#

R455 15/F_2 R460 15/F_2 R497 15/F_2 R459 15/F_2

R492 15/F_2

NB5/RD4

ACZ_SYNC ACZ_RST# ACZ_SDOUT ACZ_BCLK

ACZ_SYNC

PCH_SPI_CS0#_R PCH_SPI1_CLK_RPCH_SPI1_CLK

C395 22P/50V_4

R356 33_2 R369 33_2 R363 33_2 R365 33_2

C349

*10P/50V_4

R357 *1K_2

P/N AKE3EFP0N07

DFHS08FS023

TP57 TP48 TP59 TP46 TP100

TP23

PCH_SPI_CS0# PCH_SPI1_SI PCH_SPI1_SI_R

PCH_SPI1_SO PCH_SPI1_SO_R

+3VSPI

R489 3.3K/F_2

PCH_SPI_IO2

30mils

+3V_RTC

C365 1U/6.3V_2

R119

20K/F_2

R117 20K/F_2

R125 *0_6

RTC_RST#

C94 1U/6.3V_2

C96 1U/6.3V_2

SRTC_RST#RTC_RST#

RTC Clock 32.768KHz

C35610P/25V_2

32.768KHz

C35210P/25V_2

GPIO Pull UP

SATA0GP SIO_EXT_SMI# PCI_SERR# SATA1GP SATA1GP

RTC_X1

R563 10M_4

RTC_X2

R436 10K_2 R423 10K_2 R237 10K_2 R464 10K_2 R454 *10K_2

+3V

PCH SPI ROM(CLG)

+3VREG

+3V_DEEP_SUS

U28

CE#

SCK

WP#

BIOS ROM

AKE3EFP0N07

BIOS_WP#

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 6/9(SATA/HDA)

Date: Sheet of

R430 *0_6

R425 0_6

+3VSPI

VDD

HOLD#

VSS

Intel Shark Bay ULT

HOLD#

PCH_SPI_IO3

R448 3.3K/F_2 R442 15/F_2

C378

0.1U/10V_2

7 36Thursday, September 12, 2013

PCI/USBOC# Pull-up(CLG)

PCH_Power_Button# TS_INTB#

PIRQC# PIRQD#

GPIO77_ULT TOUCHPANEL_INTR#_PCH PCH_VOL_UP# PCH_VOL_DOWN# PCH_ROTATE#_R

D D

SMBALERT# USB_OC1# USB_OC2# USB_OC3# USB_OC4#

R251 10K_2 R244 10K_2

R247 10K_2 R480 10K_2

R239 10K_2 R487 10K_2 R252 10K_2 R246 10K_2 R245 10K_2

R377 10K_2 R387 10K_2 R371 10K_2 R393 10K_2 R123 10K_2

+3V_DEEP_SUS

Lynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)

+3V

for DS3

U26N

USB3.0 PORT1,2 SWAP

Docking

C C

B B

USB30_RX2-<26> USB30_RX2+<26> USB30_TX2-<26> USB30_TX2+<26>

USB3.0

USB30_RX1-<26> USB30_RX1+<26> USB30_TX1-<26> USB30_TX1+<26>

TOUCH_PANEL_RST#<27>

PIRQD#_L<23>

PCH_ROTATE#<9,23>

R484 0_2

TOUCHPANEL_INTR#_PCH<27>

PCH_Power_Button#<23>

PCH_ROTATE# PCH_ROTATE#_R

PCH_VOL_UP#<23>

PCH_VOL_DOWN#<23>

TP28

GPIO77_ULT TS_INTB# PIRQC# PIRQD#

TOUCHPANEL_INTR#_PCH

PCH_Power_Button#

R611 0_2

PCH_VOL_UP# PCH_VOL_DOWN#

PCI_PME#

G20 H20 C33 B34

E18

F18 B33 A33

U6 P4 N4 N2

L1 L3

R5 L4 U7

AD4

USB3RN1 USB3RP1 USB3TN1 USB3TP1

USB3RN2 USB3RP2 USB3TN2 USB3TP2

PIRQA#/ GPIO77 PIRQB#/ GPIO78 PIRQC#/ GPIO79 PIRQD#/ GPIO80

GPIO52 GPIO54

GPIO51 GPIO53 GPIO55

PME#

PCI

C- Link

USBRBIAS#

USB

OC0# / GPIO40(SUS) OC1# / GPIO41(SUS) OC2# / GPIO42(SUS) OC3# / GPIO43(SUS)

CL_CLK CL_DATA CL_RST#

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USBRBIAS

RSVD RSVD

Cardreader

AF2 AD2 AF4

USB2.0 PORT0,1 SWAP

AN8 AM8 AR7 AT7 AR8 AP8 AR10 AT10 AM15 AL15 AM13 AN13 AP11 AN11 AR13 AP13

AJ10 AJ11

AN10 AM10

AL3 AT1 AH2 AV3

USBP1- <26> USBP1+ <26> USBP0- <26> USBP0+ <26> USBP2- <18> USBP2+ <18> USBP3- <29> USBP3+ <29> USBP4- <24> USBP4+ <24> USBP5- <27> USBP5+ <27> USBP6- <28> USBP6+ <28> USBP7- <18> USBP7+ <18>

TIE TRACES TOGETHER CLOSE TO PINS WITH LENGTH TO RESISTOR

USB_BIAS

R181

22.6/F_4

USB_OC1# USB_OC2# USB_OC3# USB_OC4#

PCIE_RXN2_CARD<19> PCIE_RXP2_CARD<19>

PCIE_TXN2_CARD<19>

WLAN

PCIE_TXP2_CARD<19>

PCIE_RXN3_WLAN<20> PCIE_RXP3_WLAN<20>

PCIE_TXN3_WLAN<20> PCIE_TXP3_WLAN<20>

USB2.0/USB3.0 COMBO 1st

Front Camera

Touch pad

Sensor HUB

B Hub

Rear Camera

+V1.05S_AUSB3PLL<10>

Card reader

Cardreader

TP87 TP80 TP90 TP5

WLAN

SBP2)

(USBP3) (USBP4) (USBP5)

(USBP6)

(USBP7)

CLK_PCIE_CRN<19>

CLK_PCIE_CRP<19>

PCIE_CLKREQ_CR#<19>

PCIE_CLKREQ_WLAN#<20>

C425 0.1U/10V_2 C426 0.1U/10V_2

C428 0.1U/10V_2 C427 0.1U/10V_2

(USBP0) (USBP1)

CLK_PCIE_WLANN<20> CLK_PCIE_WLANP<20>

Docking Docking

R537 *0_4/S R515 3.01K/F_2

PCIE_TXN2_CARD_C PCIE_TXP2_CARD_C

PCIE_TXN3_WLAN_C PCIE_TXP3_WLAN_C

PCIE_IREF

PCIE_RCOMP

PCIE_CLKREQ0#

CLK_PCIE_CRN CLK_PCIE_CRP

PCIE_CLKREQ_CR#

CLK_PCIE_WLANN CLK_PCIE_WLANP

PCIE_CLKREQ_WLAN#

PCIE_CLKREQ3#

PCIE_CLKREQ4#

PCIE_CLKREQ5#

U26K

G17

PERN1 / USB3RN3

F17

PERP1 / USB3RP3

C30

PETN1 / USB3TN3

C31

PETP1 / USB3TP3

F15

PERN2/ USB3RN4

G15

PERP2/ USB3RP4

B31

PETN2/ USB3TN4

A31

PETP2/ USB3TP4

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

PERN5_L1

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

PERN5_L3

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

B27

PCIE_IREF

A27

PCIE_RCOMP

E15

RSVD

E13

RSVD

C43

CLKOUT_PCIE0N

C42

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

PCIECLKRQ1# / GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2# / GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCI_P3

PCIECLKRQ3# / GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

PCIECLKRQ4# / GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

PCIECLKRQ5# / GPIO23

*HSW_ULT_DDR3L

SMBALERT# / GPIO11(SUS)

SMBUS

SML0ALERT# / GPIO60(SUS)

SML1ALERT# / PCHHOT# / GPIO73(SUS)

SML1DATA / GPIO74(SUS)

PCI-E*

CLOCK SIGNALS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO75(SUS)

XTAL24_IN

XTAL24_OUT

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_LPC_0 CLKOUT_LPC_1

DIFFCLK_BIASREF

RSVD

RSVD TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

AN2

SMBALERT#

AP2

SMB_PCH_CLK

AH1

SMB_PCH_DAT

AL2

SML0ALERT#

AN1

SMB_ME0_CLK

AK1

SMB_ME0_DAT

AU4

SML1ALERT#

AU3

SMB_ME1_CLK

AH3

SMB_ME1_DAT

A25

XTAL24_IN

B25

XTAL24_OUT

B35

CK_XDP_N_R

A35

CK_XDP_P_R

AN15

CLK_PCI_EC_R

AP15

CLK_PCI_LPC_R

C26

XCLK_BIASREF

K21 M21 C35

R527 10K_2

C34

R528 10K/F_2

AK8

R173 10K/F_2

AL8

R182 10K/F_2

R513 1M_2

R643 *0_2 R644 *0_2

R128 22_4 R130 22_4 R129 22_4

R512

3.01K/F_2

TP3

TP101

C432 12P/50V_4

24MHZ +-30PPM Y3

C433 12P/50V_4

TP102

CK_XDP_N <11>

EC1 18P/50V_4

CLK_24M_DEBUG CLK_24M_TPM

EMI(near PCH)

EC3 18P/50V_4

CK_XDP_P <11>

CLK_24M_KBC <23> CLK_24M_DEBUG <20>

CLK_24M_TPM <25>

+V1.05S_AXCK_LCPLL <10>

EC2 18P/50V_4

*HSW_ULT_DDR3L

SMBus/Pull-up(CLG) CLK_REQ/Strap Pin(CLG)

Q18

MBCLK2<2,16,23>

MBDATA2<2,16,23>

A A

R413 4.7K_2

+3V

SMB_RUN_DAT<11,16>

R429 4.7K_2

+3V

SMB_RUN_CLK<11,16>

4 3

*2N7002DW

Q19

4 3

2N7002DW

+3V

SMB_ME1_CLK

2 6

SMB_ME1_DAT

+3V

SMB_PCH_DAT

2 6

SMB_PCH_CLK

PCIE_CLKREQ0# PCIE_CLKREQ5# PCIE_CLKREQ_WLAN# PCIE_CLKREQ3# PCIE_CLKREQ_CR# PCIE_CLKREQ4#

R463 10K_2 R461 10K_2 R201 10K_2 R481 10K_2 R235 10K_2 R240 10K_2

+3V

r DS3

+3V_DEEP_SUS

+3V<2,6,7,9,10,11,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35>

+3V_DEEP_SUS<4,6,7,9,10,11>

NB5/RD4

SMBus/Pull-up(CLG)

R412 2.2K_2 R411 2.2K_2

R379 2.2K_2 R391 2.2K_2

R410 2.2K_2 R409 2.2K_2

R122 10K_2 R389 1K_2

PROJECT : Nobel

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

Date: Sheet

SMB_PCH_CLK SMB_PCH_DAT

SMB_ME0_CLK SMB_ME0_DAT

SMB_ME1_CLK SMB_ME1_DAT

SML1ALERT# SML0ALERT#

Intel Shark Bay ULT

Quanta Computer Inc.

ULT 7/9 (PCIE/USB/CLK)

Intel Shark Bay ULT

8 36Thursday, September 12, 2013

GPIO15_ULT<7>

MPHY_PWREN<35>

ACZ_SPKR<21>

SPKR<7>

TP4

TP86 TP85

R610 *0_2 R476 *0_2 R736 0_2

TP92

R385 *0_4

R398 0_4

SIO_EXT_SCI#<23>

BT_OFF<20>

RF_OFF<20>

D D

DOCK_IN_DET#<26,27,29>

C C

BT_COMBO_EN#<20>

B B

PCH_ROTATE#<8,23> VIBRATOR_OUT<23,27>

TOUCH_PAD_INT<26,29>

GPIO27_EC<23>

DEVSLP1<17>

TP for DG

TP33

PCH_Home_Button#<23>

SENSOR_HUB_INT_LS<24>

SENSOR_HUB_WAKE_LS<24>

GPIO14_ULT

TP9

TP98

SIO_EXT_SCI# BT_OFF RF_OFF

LAN_DISABLE#

GPIO13_ULT

GPIO16_ULT

DGPU_PWROK GPIO24_ULT GPIO25_ULT GPIO26_ULT GPIO27_ULT GPIO28_ULT DEVSLP0 DEVSLP1 DEVSLP2 GPIO44_ULT BOARD_ID4

ACCEL_INTA# BOARD_ID5 BT_COMBO_EN#

PCH_Home_Button#

GPIO50_ULT BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 GPIO70_ULT

MPHY_PWREN

GPIO76_ULT

R450 *0_4/S

Lynx Point-LP Platform Controller Hub

Lynx Point-LP Platform Controller HubLynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)

(HDA,JTAG,SATA)

(HDA,JTAG,SATA)(HDA,JTAG,SATA)

U26O

AU2 AM3 AM2 AM7

AT3 AH4 AD6

T3 AD5 AM4 AN3 AN5 AD7

N5 AK4 AG5 AG3 AB6

P3 AG6 AP1

AL4 AT5

SPKR

*HSW_ULT_DDR3L

GPIO8(SUS) GPIO9(SUS) GPIO10(SUS) LAN_PHY_PWR_CTRL / GPIO12(DSW) GPIO13(SUS) GPIO14(SUS) GPIO15(SUS) GPIO16 GPIO17 GPIO24 (SUS) GPIO25(DSW) GPIO26(SUS) GPIO27(DSW) GPIO28(SUS) DEVSLP0/ GPIO33 DEVSLP1/ GPIO38 DEVSLP2/ GPIO39 GPIO44(SUS) GPIO45(SUS) GPIO46(SUS) GPIO47(SUS) GPIO48 GPIO49 GPIO50 GPIO56(SUS) GPIO57(SUS) GPIO58(SUS) GPIO59(SUS) SDIO_POWER_EN/ GPIO70 HSIOPC/ GPIO71

BMBUSY# / GPIO76

SPKR/ GPIO81

GPIO

Haswell (GPIO)

D60

THRMTRIP#

RCIN#/ GPIO82

SERIRQ

PCH_OPI_RCOMP

CPU/MISC

GSPI0_CS/ GPIO83

GSPI0_CLK/ GPIO84 GSPI0_MISO/ GPIO85 GSPI0_MOSI/ GPIO86

GSPI1_CS/ GPIO87

GSPI1_CLK/ GPIO88 GSPI1_MISO/ GPIO89 GSPI1_MOSI/ GPIO90

UART0_RXD/ GPIO91

UART0_TXD/ GPIO92 UART0_RTS/ GPIO93 UART0_CTS/ GPIO94

UART1_RXD/ GPIO0

SERIAL IO

UART1_TXD/ GPIO1

UART1_RST/ GPIO2

UART1_CTS/ GPIO3

I2C0_SDA/ GPIO4 I2C0_SCL/ GPIO5 I2C1_SDA/ GPIO6 I2C1_SCL/ GPIO7

SDIO_CLK/ GPIO64

SDIO_CMD/ GPIO65

SDIO_D0/ GPIO66 SDIO_D1/ GPIO67 SDIO_D2/ GPIO68 SDIO_D3/ GPIO69

RSVD RSVD

PCH_THRMTRIP#

EC_RCIN#

AW15

PCH_OPI_RCOMP

AF20 AB21

R6 L6 N6 L8

R7 L5 N7 K2

J1 K3 J2 G1

K4 G2 J3 J4

F2 F3 G4

I2C1_SDA_PCH_TS

I2C1_SCL_PCH_TS

E3 F4 D3 E4 C3 E2

SERIRQ

GSPI0_CS GSPI0_CLK GSPI0_MISO GPIO86_ULT

GSPI1_CS GSPI1_CLK GSPI1_MISO GSPI1_MOSI

UART0_RXD UART0_TXD UART0_RTS UART0_CTS

UART1_RXD UART1_TXD UART1_RST UART1_CTS

I2C0_SDA_SENSOR I2C0_SCL_SENSOR

SDIO_CLK SDIO_CMD

SDIO_D1 SDIO_D2 SDIO_D3

R510 *0_4/S

R241 10K_2

R360

49.9/F_4

TP53

I2C0_SDA_SENSOR <24> I2C0_SCL_SENSOR <24>

I2C1_SDA_PCH_TS <26,27> I2C1_SCL_PCH_TS <26,27>

GPIO66_ULT <7>

PM_THRMTRIP# <23>

EC_RCIN# <23>

+3V SERIRQ <23,25>

GSPI1_MOSI UART0_RTS UART1_RST UART0_RXD

UART0_TXD SDIO_D3

GSPI0_MISO

RP1

9 8 7 4

10K_10P8R_6

RP3

9 8 7 4

10K_10P8R_6

1 2 3

GSPI1_CS GSPI0_CS GSPI1_MISO UART1_CTS

1 2 3

+3V

SDIO_D1 SDIO_CMD SDIO_CLK GSPI0_CLK

I2C1_SDA_PCH_TS I2C1_SCL_PCH_TS GSPI1_CLK

+3V

9 8 7 4

GPIO Pull-up/Pull-down(CLG)

GPIO70 SENSOR_HUB_I2C_WAKE

Close to EC

PM_THRMTRIP#

RP2

1 2 3

10K_10P8R_6

SIO_EXT_SCI# BT_OFF RF_OFF GPIO13_ULT GPIO14_ULT

GPIO24_ULT GPIO26_ULT GPIO28_ULT GPIO44_ULT ACCEL_INTA#

PCH_Home_Button# GPIO50_ULT GPIO16_ULT DGPU_PWROK DEVSLP0 DEVSLP1 DEVSLP2 BT_COMBO_EN# GPIO70_ULT EC_RCIN#

GPIO76_ULT MPHY_PWREN MPHY_PWREN

GPIO25_ULT GPIO27_ULT LAN_DISABLE#

UART0_CTS SDIO_D2 UART1_TXD UART1_RXD

+3V

R383 10K_2 R397 10K_2 R134 10K_2

R506 1K_2

for DS3

+3V_DEEP_SUS

R132 10K_2 R384 10K_2 R382 10K_2 R144 10K_2 R192 10K_2

R227 10K_2 R376 10K_2 R228 10K_2 R159 10K_2 R395 10K_2

R435 10K_2 R475 10K_2 R434 10K_2 R470 10K_2 R472 10K_2 R488 10K_2 R248 10K_2 R238 10K_2 R516 *10K_2 R236 10K_2

R471 10K_2 R433 100K_2 R432 *10K_2

+V1.05S_VCCST

+3V

+3VS5

R195 10K_2

R375 10K_2

R164 10K_2

A A

R165 10K_2

R177 *10K_2

R230 *10K_2

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

BOARD_ID5

R197 *10K_2

R372 *10K_2

R153 *10K_2

R140 *10K_2

R176 10K_2

R229 10K_2

+3V_DEEP_SUS

RAM SIZE

2G 4G

Hynix (TG) H5TC4G63AFR-PBA HUMA, A

Micron (TF) MT41K256M16HA-125:E V80A/E Elpida (TN) EDJ4216EFBG-GN-F F

Hynix (TG) H5TC4G63MFR-PBA GEMMA, M

Samsung (TH) K4B4G1646B-HYK0 B

BOARD_ID5

TPM support 0 1

BOARD_ID0 BOARD_ID1 BOARD_ID2

0 0 0 0 0 1 0 0

1 1 0 01

BOARD_ID4 NO 0 YES

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 8/9 (GPIO/MISC)

NB5/RD4

ULT 8/9 (GPIO/MISC)

Date: Sheet of

Date: Sheet

+3V_DEEP_SUS<4,6,7,8,10,11>

+V1.05S_VCCST<2,4,11,34>

+3V<2,6,7,8,10,11,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35>

+3VS5<6,10,11,20,26,27,29,30,35>

Intel Shark Bay ULT

9 36Thursday, September 12, 2013

+1.05V

D D

+1.05V

TP17 C130

1U/6.3V_2

VCCASW=658mA

TP27

+1.05V

C C

TP34

+V3.3DX_1.5DX_ADO

B B

+3V_DEEP_SUS

+3VS5

+3V

VCC1_05=1.741A

+3VS5

DcpSus1=109mA

C199 1U/6.3V_2 C200 1U/6.3V_2 C201 *1U/6.3V_2

C193 *1U/6.3V_2

C225 1U/6.3V_2 C235 22U/6.3VS_8

C237 22U/6.3VS_8 C233 1U/6.3V_2 C226 22U/6.3VST_8

C218 22U/6.3VS_8

SI Change to 22uF for Intel recommend

DcpSus3=10mA

+V3.3DX_1.5DX_PAZSUS_PCH

DcpSus2=25mA

TP16

VCCSUS3_3=63mA

+V1.05S_CORE_PCH

C2071U/6.3V_2 C1401U/6.3V_2 C20210U/6.3VS_6

+PCH_VCCDSW

C139 1U/6.3V_2 C158 *22U/6.3VS_8

+V1.05S_AIDLE

C126 1U/6.3V_2

C176 22U/6.3VST_8

+V1.05M_ASW

+V1.05M_FHV0 +V1.05M_FHV1

+V1.05A_SUS_PCH +V1.05DX_MODPHY_PCH

VCCHSIO=1.838A

+V1.05S_AUSB3PLL

VCCSATA3PLL=42mA

+V1.05S_ASATA3PLL

+V1.05A_VCCUSB3SUS

+V1.05A_USB2SUS

+V3.3A_PSUS

VCCDSW3_3=114mA

C127 *1U/6.3V_2

C190 22U/6.3VST_8

+V3.3S_PCORE

U26P

J11

VCC1_05

H11

VCC1_05

H15

VCC1_05

AE8

VCC1_05

AF22

VCC1_05

C131 0.1U/10V_2 L12 2.2uH/500mA_6

AG19 AG20

AG14 AG13

AD10

VCCHDA=11mA

AH14

AH13

AH10

+V3.3DX_1.5DX_ADO

DCPSUSBYP DCPSUSBYP

AE9

VCCASW

AF9

VCCASW

AG8

VCCASW

VCCASW VCCASW

DCPSUS1

AD8

DCPSUS1

VCCHSIO

L10

VCCHSIO

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

J13

DCPSUS3

VCCHDA

DCPSUS2

AC9

VCCSUS3_3

AA9

VCCSUS3_3

VCCDSW3_3

VCC3_3

*HSW_ULT_DDR3L

POWER

CORE

VCCMPHY

USB3

HDA

VRM

GPIO/ LCC

RTC

SPI

ICC

THERMAL SENSOR

OPI

SERIAL IO

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC

DCPRTC

VCCSPI

VCCCLK VCCCLK

VCCACLKPLL

VCCCLK

VCCCLK VCCCLK

RSVD RSVD RSVD

VCCSUS3_3 VCCSUS3_3

VCCTS1_5

VCC3_3 VCC3_3

RSVD VCCAPLL VCCAPLL

VCCSDIO VCCSDIO

DCPSUS4

RSVD

VCC1_05 VCC1_05

Lynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)(POWER)

+V3.3A_DSW_PRTCSUS

AH11

VCCRTC < 1mA

AG10

AE7

+VCCRTCEXT

VCCSPI=18mA

+V3.3M_PSPI

+V1.05S_AXCK_DCB

J18 K19

A20

+V1.05S_AXCK_LCPLL

J17

+V1.05S_SSCF100

R21 T21

+V1.05S_SSCFF

K18 M20 V21

AE20

+V3.3A_PSUS

AE21

VCCTS1_5=3mA

J15

+V1.5S_ATS +V3.3S_PTS

K14

VCC3_3=41mA

K16

CAPLL=57mA

Y20 AA21 W21

+V1.05S_APLLOPI

VCCSDIO=17mA

U8 T9

+V3.3S_1.8S_SDIO_PCH

AB8

+V1.05A_AOSCSUS

AC20

AG16

+V1.05S_DUSB

AG17

C128 1U/6.3V_2

C146 0.1U/10V_2

C175 *0.1U/10V_2

2.2uH/500mA_6 L11

C203 1U/6.3V_2 C224 47U/6.3VST_8 C205 47U/6.3VST_8

L13 2.2uH/500mA_6

C229 1U/6.3V_2 C234 47U/6.3VST_8

C220 47U/6.3VS_8

C204 1U/6.3V_2

C191 1U/6.3V_2

C183 0.1U/10V_2

C173 1U/6.3V_2

C192 1U/6.3V_2

DcpSus4=1mA

C156 1U/6.3V_2

C129 1U/6.3V_2

R421 0_4 R424 *0_4

R242 *0_6/S

R243 *0_6/S

2.2uH PN CV-2205JZ00

L9 0_6

C182 *47U/6.3VST_8 C177 *47U/6.3VST_8

+3V_DEEP_SUS

+3V_RTC

C141 1U/6.3V_2 C142 0.1U/10V_2 C143 0.1U/10V_2

+3V_DEEP_SUS +3V +1.05V

+1.05V

+V3.3A_PSUS

+1.5V +3V

+1.05V

+3V

TP29

+1.05V

+1.05V_MODPHY

VCCACLKPLL=31mA

VCCCLK=200mA

SLP_SUS_ON<23>

for DS3

R216 100K_2

R426 *0_4/S

C362 1U/6.3V_2

C363 *10P/50V_4

L15 2.2uH/500mA_6

R406 *0_6

U25

ON/OFF

IC(5P) G5243AT11U

R217 *100K_2

OUT

GND

20mil

+V1.05S_ASATA3PLL

20mil

+V1.05S_AUSB3PLL

+V1.05DX_MODPHY_PCH

+3V_DEEP_SUS+3VS5

1 2

C372

0.1U/10V_2

A A

+1.5V<20,21,32>

+1.05V<4,7,11,23,32,35>

+3VS5<6,9,11,20,26,27,29,30,35>

R106 0_4

R110 *0_4

+5V<6,20,21,22,29,35>

+3V

+1.5V

PROJECT : Nobel

+V1.05S_AUSB3PLL<8> +V1.05S_ASATA3PLL<7> +V1.05S_AXCK_LCPLL<8>

+3V<2,6,7,8,9,11,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35>

+3V_RTC<7>

+1.35VSUS<2,4,12,13,14,15,25,33>

NB5/RD4

PROJECT : Nobel

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

ULT 9/9(POWER-2)

Date: Sheet of

Date: Sheet

Intel Shark Bay ULT

10 36Thursday, September 12, 2013

D D

H_VCCST_PWRGD<4>

+1.05V

C C

H_VCCST_PWRGD VCCST_PWRGD_XDP

C137 *0.1U/10V_2

XDP_PREQ#_CPU<2>

XDP_PRDY#_CPU<2>

CFG0<4> CFG1<4>

CFG2<4> CFG3<4>

XDP_BPM0<2> XDP_BPM1<2>

CFG4<4> CFG5<4>

CFG6<4>

R208 *1K_2

CFG7<4>

PWR_DEBUG<4>

SMB_RUN_DAT<8,16> SMB_RUN_CLK<8,16>

XDP_TCK0<2>

R202 *1K_2

CFG1 CFG2

CFG3 OBSFN_B0

OBSFN_B1 CFG4

CFG5 CFG6

CFG7

DNBSWON#

H_SYS_PWROK_XDP

XDP_TCK1 XDP_TCK0

CN4

31 323229 333328 343427 353526 363625 373724 383823 393922 404021 414120 424219 434318 444417 454516 464615 474714 484813 494912 505011 515110 52529 53538 54547 55556 56565 57574 58583 59592 60601

*SEC_BSH-030-01-L-D-A-TR

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

OBSFN_C0 OBSFN_C1

CFG8 CFG9

CFG10 CFG11

OBSFN_D0 OBSFN_D1

CFG12 CFG13

CFG14 CFG15

XDP_RST

XDP_DBRESET_N

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

R254 *1K_2

CFG17 <4> CFG16 <4>

CFG8 <4> CFG9 <4>

CFG10 <4> CFG11 <4>

CFG19 <4> CFG18 <4>

CFG12 <4> CFG13 <4>

CFG14 <4> CFG15 <4>

CK_XDP_P <8> CK_XDP_N <8>

CFG3

C216 *0.1U/10V_2

+1.05V

XDP_DBRESET_N

B B

A A

+3V_DEEP_SUS <4,6,7,8,9,10> +3VS5 <6,9,10,20,26,27,29,30,35> +V1.05S_VCCST <2,4,9,34> +3V <2,6,7,8,9,10,16,17,18,19,20,21,23,24,25,26,27,28,31,34,35> +1.05V <4,7,10,23,32,35>

APS

+3V_DEEP_SUS

CN2

*ACES_88511-180N

+3VS5

R124 *0_2 R88 *0_2

R95 *0_2 R96 *0_2

R103 *0_2 R207 *0_2 R108 *0_2 R111 *0_2

R114 *0_2

SUSB# <6,11,23> SLP_S5# <6>

SUSC# <6,23> SLP_A# <6>

RTC_RST# <7> DNBSWON# <6,23> SYS_RESET# <6> PCH_SLP_S0_N <6,23>

SUSB# <6,11,23>

R86 *0_4 R87 *0_4

+3V_DEEP_SUS +3VS5

R258 *1K_2

C215 *0.1U/10V_2

+V1.05S_VCCST

JTAGX_PCH<7> JTAG_TMS_PCH<7> JTAG_TDI_PCH<7>

JTAG_TDO_PCH<7>

XDP_TDI_R

JTAG_TCK_PCH<7>

HWPG<4,23,30,32,33>

R276 *0_2

+3V

XDP_TDO

XDP_TDI_R

XDP_TMS

XDP_TRST#

H_SYS_PWROK_XDP

+3V

R273 *0_2 R262 *51_2 R259 *0_2 R260 *0_2 R256 *0_2 R257 *0_2 R275 *0_2 R203 *0_2 R204 *0_2

R205 *1K_2

C136 *0.1U/10V_2

C232 *0.1U/10V_2

U13

VCC

1OE

2OE

3OE

4OE

*SN74CBTLV3126RGYR

XDP_TDI_RXDP_TDI

XDP_TDO XDP_TCK0 XDP_TMS XDP_TDI XDP_TDO XDP_TCK0 XDP_TCK1

+3V_DEEP_SUS

DPAD

GND

SYS_PWROK<6>

PLTRST#<6,19,20,23,25,28>

NB5/RD4

R206 *0_2

R255 *1K_2

PROJECT : Nobel

Size Document Number Rev

HSW XDP & APS

Date: Sheet of

Date: Sheet

XDP_TDO_CPU <2>

XDP_TDI_CPU <2>

XDP_TMS_CPU <2>

XDP_TRST#_CPU <2,7>

H_SYS_PWROK_XDP

XDP_RST

Intel Shark Bay ULT

Quanta Computer Inc.

11 36Thursday, September 12, 2013

+ 25 hidden pages

HP PRO X2 410G Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual