HP la4902p Schematics

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

INTEL AUBURNDALE with IBEX core logic

Cartier UMA

3 3

LA-4902P

2009-12-07

4 4

A

B

REV:1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

D

Title

Size Docume nt Number Re v

Cust om

Date : Sheet o f

Compal Electronics, Inc.

Cover Sheet

LA-4902P

E

1 47Monda y, December 1 4, 2009

0.3

A

Compal Confidential

B

C

Cartier UMA

D

XDP Conn.

Page 4

E

Accelerometer

LIS30 2DLTR

File Name : LA-4902P

1 1

2 2

Express Card 54

EM C 21 13

DP Panel

VGA

Display Port

PCIE X1 + USB X1

Audio Board

Page 4

Page 20

Page 18

Page 19

WWAN Card

PCIE X1

Thermal Sensor

Fan Con trol

Page 24

Page 4

USB2.0

eDP

DP-D

FDI

Intel Ibex Peak M

PCI-E BUS

10/1 00/1000 LAN
Intel Hansville GbE

PHY

Page 21

RJ45 CONN

3 3

Page 22

WLAN Card

WLAN + PCIE X1

Page 23

1394 port

Rico R5C835

PCI BUS

Controller

Page 27

Page 27 Audio Board

Smart Card

SD/MMC Slot

LPC BUS

RTC CKT.

Page 12

LE D

Audio Board

Mobile

CPU Dual Core

Socket-rPGA989

37.5mm*37. 5mm

Page 4,5,6,7,8

10 71p i ns

25mm*27mm

Page 12,13,14,15,16,17

ONFI Interface

Braidwood

NAND Flash Card

DMI X4

Page 24

Page 24

Dual Channel

DP-C ; DP-B

USB2.0

Azalia

SATA0

SATA1

DDR3 -SO-DIMM X 2DDR3 1066/1333M Hz 1.5V

BAN K 0, 1, 2, 3

DP X 2(Docking)

USB x2(Docking)

Page 28

Page 28

FingerPrinter VFM451
USBx1

Page 31

USB conn x 3(For I/O)
BT Conn USB x 1

USB x1(Camara)

MDC V1.5

Audio CKT

IDT 92HD75

Audio Board

SATA ODD Connector

Page 26

Page 20

Page 25

Page 12

2.5" SATA HDD Connector

Page 12

Page 9,10

Clock Generator
IC S9L PRS397

daughte r board

RJ1 1

TPA6047A

AMP & Audio Jack

Page 36

(2) PS/2 In terfaces
(2) USB 2.channels
(2) SATA Channels
(2) Display Port Channels
(1) Seria l Port
(1) Parall el Port
(1) Li ne In

Docking CONN.

(1) Lin e Out

Power OK CKT.

Page 32

4 4

Power On/Off CKT.

Page 25

DC/DC Interface CKT.

Page 33

A

TPM1.2

SLB9635TT

Page 31 page 29

Touch Pad CONN.

TrackPoint CONN.

SPI ROM
8 M B

B

SMSC KBC 1098

Page 25

Page 25

Page 31

Int.KBD

Page 25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SMSC Super I/O

SMCS47N217N

COM1 LPT
( Docking ) ( Docking )

Page 30 Page 30

2008/09/15 2009/12/31

Page 30

Compal Secret Data

Deciphered Date

D

Title

Size Docume nt Number Re v

Cust om

Date : Sheet o f

(1) RJ45 (10/100/1000)
(1) VGA
(1) 2 LAN indicator LED's
(1) Power Button
(1) I2C interface

Compal Electronics, Inc.

Block Diagram

LA-4902P

E

Page 26

CK505

Page 11

Page 25

Audio Board

0.3

2 47Wedn esday, De cember 09, 200 9

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

( O MEANS ON X MEANS OFF )

+RTCVCC

power
plane

O

O

O

O

O

O

+B

+3VL +0.75V

O

O

O

O

O

X

+5VALW

+3VALW

O

O

O

O

X

X X X

+3VM

+1.05VM

O

O

O

O

X

X

+1.5V

O

X X

X

+5VS

+3VS

+1.5VS

+VCCP

+CPU_CORE

+1.05V S

+1.8VS

OO

OO

X

X

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
CONN@ : means ME part.

Install below 45 level BOM structure for ver. 0.1

45@ : means just put it in the BOM of 45 level.

Install below 43 level BOM structure for ver. 0.1

DEBUG@ : means just build when PCIE port 80 CARD function enable.

N10M@ : Install for N10M Graphic controller

1098@ : Install for 1098 KBC controller

Remove before MP

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMBCLK
SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

SMSC1098

Calpella

Calpella

Calpella

BATT

V

X
X
X

THERMAL

SODIMM CLK CHIP

XDP G-SENSOR

X

X X

V V

X

X

X X

MINI CARD

X

V V

X

X

X X

DOCK

X

V

X
X

SENSOR

NIC

X X
X

V

X

X
X

V

X

V

X

V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Reserve below BOM structure for ver. 0.1

1091@ : Install for 1091 KBC controller

2008/09/15 2009/12/31

A

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

Cust om

Date : Sheet o f

Compal Electronics, Inc.

Notes List

LA-4902P

3 47Wedn esday, De cember 09, 200 9

0.3

Layout rule 1 0mil w i：dth trace
length < 0.5 ", spa cing 20mil

A A

H_PE CI15

to power; PU to VCCP at power side also

H_PRO CHOT#41

H_THER MTRIP#15

H_CPU RST#

H_PM _SYNC14

H_CP UPWR GD

H_CP UPWR GD15

B B

PM_DRA M_PWRGD14

from power

VTTPWR GOOD32

BUF_PLT_R ST#15

Processor P ullups

H_CAT ERR#

H_PRO CHOT#_D

C C

H_CPU RST#_R

DDR3 Compen sation Signals

SM_RCOMP0

R52 100_0402_1%

SM_RCOMP1

R53 24.9_0402_1%

SM_RCOMP2

R54 130_0402_1%

Layout Note :Please these
resistors n ear Processor

1

1 2

1 2

1 2

1 2

TP_SKTOCC#

T1TPC12

H_CAT ERR#

H_P ECI_ISO

R16

1 2

0_0402_5%

H_PRO CHOT#_D

R17

1 2

0_0402_5%

H_THE RMTRIP#_R

R19

1 2

0_0402_5%

R20

1 2

0_0402_5%

R21

1 2

0_0402_5%

SYS_AG ENT_PWR OK

R22

1 2

0_0402_5%

VCCPW RGOOD _0

R24

1 2

0_0402_5%

VDD PWRGO OD_R

R26

1 2

0_0402_5%

H_PW RGD_XDP_RH_PW RGD_XDP

R30

1 2

0_0402_5%

PLT_RST#_R

R31

1 2

1.5K_0402 _5%

R39 49.9_0402_1%

1 2

1 2

R42 68_0402_5%

1 2

R45 68_0402_5%@

1 2

1 2

1 2

COMP3

R220 _0402_1%

COMP2

R520 _0402_1%

COMP1

R74 9.9_0402_1%

COMP0

R94 9.9_0402_1%

H_CPU RST#_R

H_PM _SYNC_ R

12

R33
750_0402_1%

+VCCP

JCPU 1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,A UB_CFD _rPGA,R 1P0

CON N@

JTAG MAPPING

XDP_TRST#

MISC THERMAL

PWR MANAGEMENT

09/2/5 HP

Close to XDP

1 2

R55 51_0402_5%

REMOTE thermal sensor

D D

REMOTE2+

C4

2200P_0402_ 50V7K

REMOTE2-

1

2

1

C

Q1

2

B

MMBT3904WH_SOT323-3

E

3 1

Layout Note:

place near t he hot test s pot area fo r
NB & t op SODI MM.

CLOCKS

DDR3

JTAG & BPM

2

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

MISC

2

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

3

PM_EXTTS#0

CLK_C PU_BCLK

A16

CLK_C PU_BCLK#

B16

CLK_CP U_XDP

AR30

CLK_CP U_XDP#

AT30

CLK_EXP

E16

CLK_EXP#

D16

A18
A17

F6

SM_RCOMP0

AL1

SM_RCOMP1

AM1

SM_RCOMP2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1

AP15

XDP_ PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

TCK

XDP_TMS

AP28

TMS

XDP_TRST#

AT27

XDP_TDI

AT29

TDI

XDP_TDO

AR27

TDO

XDP_TDI_M

AR29

XDP_TDO_M

AP29

XDP_DBRESET #

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

T2 TPC12

1 2

R18 0_0402_5%

+VCCP

09/2/5 HP

CFG1 25

CFG1 35

CFG1 45

CFG1 55

C1

0.1U_0 402_16V4Z

@

R846
1K_0402_5%

1 2

+VCCP

1

2

CLK_C PU_BCLK 15
CLK_C PU_BCLK# 15

CLK_EXP 13
CLK_EXP# 13

CLK_D P 13
CLK_D P# 13

PM_EXTTS#1_R 9,10

10/09 HP

@

PM_PWR BTN#_R

XDP_BPM#0

R1013 0_0402_5%
R1010 0_0402_5%@

XDP_BPM#1

R1014 0_0402_5%
R1009 0_0402_5%@

XDP_BPM#2

R1015 0_0402_5%
R1011 0_0402_5%@
R1016 0_0402_5%
R1012 0_0402_5%@

PM_PWR BTN#_R12,14

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG1 75 CFG1 0 5
CFG1 65

H_CP UPWR GD

H_PW RGD_XDP

T110TPC12
T111TPC12

C3

0.1U_0 402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PM_EXTTS#1

VDD PWRGO OD_R

09/07/02 HP

from DDR

12

XDP_PREQ#
XDP_ PRDY#

R25
1K_0402_5%

1 2

1 2

R27 0_0402_5%

Thermal Sensor EMC2113 with CPU PWM FAN

+3VS

R35
68_0402_5%

1 2

+3VS_THER

1

SI1 NO1 5

09/2/5 HP

2

THERM_ SCI#15

+3VS

H_THER MTRIP#

1 2

R1 10K_0402_5%

1 2

R3 10K_0402_5%

SI1 NO3 0

R14

1.5K_0402_ 1%

1 2

750_0402_1%

1 2

R15

+1.5V

Q88
SSM3K7002F _SC59-3

D

S

13

G

2

R1989
100K_0402_5%@

2

C1035

0.1U_0 402_16V4Z

1

09/07/02 HP

CPU XDP Connector

JP1

1
3
5

XDP_BPM#0_R
XDP_BPM#1_R

XDP_BPM#2_R
XDP_BPM#3_RXDP_BPM#3

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CP UPW RGD_R
PM_PWR BTN#_R

XDP_TCK

1 2

C2 2200P_04 02_50V7K

FAN_P WM-R

R1082

1 2

@

1 2

R48 10K_0402_5%

1 2

R51 0_0402_5%

SI1 NO2 5

09/2/5 HP

2008/09/15 2009/12/31

7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

SAMTE_BSH -030-01-L-D-A CON N@

H_THE RMDC

H_TH ERMDA

ADDR _SEL

10K_0402_5%

Add 0ohm a nd 0.1u

Compal Secret Data

4

+VCCP

VCCP_ 1.5VSPW RGD 32

R1133
1K_0402_5%

1 2

GPIO50 from PCH

S3 CPU Pow er Rail Change

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

U54

1

DN

2

DP

3

VDD

4

PWM_IN

5

ADDR_SEL

6

ALERT#

7

SYS_SHDN#

8

SMDATA

Deciphered Date

4

XDP_TDO

DRAMRST # 9,10

PCH_ DDR_RS T 15

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

DP2/DN3

DN2/DP3

TRIP_SET

SHDN_SEL

GND

PWM

TACH

SMCLK

GND

EMC2113-2-AX_QFN 16_4X4

17

1 2

R10 51_0402_5%

This shall place near XDP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

CLK_CP U_XDP

40

CLK_CP U_XDP#

42
44

XDP_RST#_R

46

XDP_DBRE SET#_R

48
50

XDP_TDO

52

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58
60

XDP_RST#_R

REMOTE2+

16

REMOTE2-

15

R38

R43

FAN_PW M_OUT

TACH

2.05K_0402_1%

10K_0402_5%

14

13

12

11

10

9

5

+VCCP

CFG8 5
CFG9 5

CFG0 5
CFG1 5

CFG2 5
CFG3 5

CFG1 1 5

CFG4 5
CFG5 5

CFG6 5
CFG7 5

+VCCP

1K_0402_5%

R28

1 2
1 2

R29 0_0402_5%

@

1 2

R32 0_0402_5%

FAN_P WM-R

09/2/5 HP

R44

10K_0402_5%

@

R9980_04 02_5%

10K_0402_5%

SMB_CLK_S3 9,10, 11,13,26SMB_DATA_S39,10,1 1,13,26

1 2

R47

SI1 NO3

09/3/9 HP

H_CPU RST#
XDP_DBRESET #

PLT_RST#

1 2

R910 0_0402_5%

2

C884

0.1U_0 402_16V4Z

1

@

10/16 HP Add

+3VS

+3VS

2

@

C1047

0.1U_0 402_16V4Z

1

+5VS

+3VS

1 2

HP 10/21

R23
1K_0402_5%

1 2

XDP_DBRESET # 12,14

PLT_RST# 1 2,15,21,2 3,25,31

FAN_PW M 29

09/2/5 HP

R997
10K_0402_5%

ACES_85205 -04001

CON N@

1
2
3
4
5
6

JP2

1
2
3
4
G5
G6

DB1 No8 2

SI1 NO3 9

R997 : i nsta ll
R44: un inst all

09/4/10 HP

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

LA-4902P

5

4 47Wed nesda y, Decem ber 09, 2 009

0.3

1

JCP U1A

DMI_CRX_PTX_N014
DMI_CRX_PTX_N114
DMI_CRX_PTX_N214
DMI_CRX_PTX_N314

DMI_CRX_PTX_P014
DMI_CRX_PTX_P114

A A

DMI_CRX_PTX_P214
DMI_CRX_PTX_P314

DMI_CTX_PRX_N014
DMI_CTX_PRX_N114
DMI_CTX_PRX_N214
DMI_CTX_PRX_N314

DMI_CTX_PRX_P014
DMI_CTX_PRX_P114
DMI_CTX_PRX_P214
DMI_CTX_PRX_P314

FDI_CTX_ PRX_N014
FDI_CTX_ PRX_N114
FDI_CTX_ PRX_N214
FDI_CTX_ PRX_N314
FDI_CTX_ PRX_N414
FDI_CTX_ PRX_N514
FDI_CTX_ PRX_N614
FDI_CTX_ PRX_N714

FDI_CTX_ PRX_P014
FDI_CTX_ PRX_P114
FDI_CTX_ PRX_P214
FDI_CTX_ PRX_P314
FDI_CTX_ PRX_P414
FDI_CTX_ PRX_P514

B B

FDI_CTX_ PRX_P614
FDI_CTX_ PRX_P714

FDI _FSY NC014
FDI _FSY NC114

FDI_ INT14

FDI _LSYN C014
FDI _LSYN C114

FDI_CTX_ PRX_N0
FDI_CTX_ PRX_N1
FDI_CTX_ PRX_N2
FDI_CTX_ PRX_N3
FDI_CTX_ PRX_N4
FDI_CTX_ PRX_N5
FDI_CTX_ PRX_N6
FDI_CTX_ PRX_N7

FDI_CTX_ PRX_P0
FDI_CTX_ PRX_P1
FDI_CTX_ PRX_P2
FDI_CTX_ PRX_P3
FDI_CTX_ PRX_P4
FDI_CTX_ PRX_P5
FDI_CTX_ PRX_P6
FDI_CTX_ PRX_P7

FDI _FSY NC0
FDI _FSY NC1

FDI_ INT

FDI _LSY NC0
FDI _LSY NC1

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17

F18
D17

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_ICOMPO

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

C C

IC,A UB_CFD _rPGA,R1 P0

CON N@

PEG_ICOMPI

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

2

EXP_ICOMPI

EXP_RBIAS

C903 0.1U_04 02_10V7K

C904 0.1U_04 02_10V7K

1 2

1 2

R56 49.9_0402_1 %

1 2

R57 750_0402_1%

1 2

DB2: No . 69

MB_C_DP _DATA0_N

MB_C_DP_D ATA0_P

C905 0.1U_0402 _10V7K

C858 0.1U_0402 _10V7K

Layout rule：trace
length < 0.5"

MB_DP_AUXN 20

MB_DP_AUXP 20

1 2

1 2

Q65

SSM3K7002F _SC59-3

MB_DP_DAT A0_N 20

MB_DP_DAT A0_P 20

+VCCP

D

S

3

12

R801

7.5K_0402 _1%

13

2

G

12

R800
100K_0402_5%

MB_DP _HPD 20

+V_D DR_CPU_ REF0
+V_D DR_CPU_ REF1

CFG04
CFG14
CFG24
CFG34
CFG44
CFG54
CFG64
CFG74
CFG84
CFG94
CFG1 04
CFG1 14
CFG1 24
CFG1 34
CFG1 44
CFG1 54
CFG1 64
CFG1 74

T21 T PC12

R65

0_0402_5%@

1 2
1 2

0_0402_5%@

R66

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG 10
CFG 11
CFG 12
CFG 13
CFG 14
CFG 15
CFG 16
CFG 17
CFG 18

AP25

AL25
AL24
AL22
AJ33

AM30
AM28
AP31

AL32

AL30
AM31
AN29
AM32
AK32
AK31
AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30
AK30

AG9
M27
L28

J17
H17
G25
G17
E31
E30

H16

B19
A19

A20
B20

U9
T9

AC9
AB9

C1
A3

J29

J28

A34
A33

C35
B35

4

JCPU 1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD26
RSVD27

RSVD_NCTF_28
RSVD_NCTF_29

RSVD_NCTF_30
RSVD_NCTF_31

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCTF_37

RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD58

RSVD_TP_59
RSVD_TP_60

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

5

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2

KEY

D15
C15
AJ15
AH15

R60

0_0402_5%

1 2
1 2

0_0402_5%

R61

@

@

09/2/16 HP

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

VSS

T128TPC12

T129TPC12

6/30 HP

Deciphered Date

4

IC,A UB_CFD _rPGA,R 1P0

CON N@

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

LA-4902P

5

5 47Wed nesda y, Decem ber 09, 2 009

0.3

CFG Straps for PROCESSOR

CFG7CFG0

R67 3.01K_0402_ 1%@

1 2

PCI-Express Configurat ion Select

1: Single PEG
0: Bifurcat ion enabled

CFG0

Not applica ble for Cla rksfield Processor

CFG3

CFG3-PCI Ex press Stati c Lane Reversal

CFG3

D D

1

CFG4

CFG4-Displa y Port Presence

CFG4

@

R69 3.01K_0402_ 1%

1 2

1: Normal O peration
0: Lane Num bers Reversed

15 -> 0, 14 ->1, .....

R70 3.01K_0402_ 1%

1 2

1: Disabled ; No Physic al Display Port
attached to Embedded D isplay Port

0: Enabled; An externa l Display Port
device is c onnected to the Embedded
Display Port

2

-240mV for Pre-ES1

R68 3.01K_0402_ 1%

1 2

Only tempor ary for ear ly CFD samp les (rPGA/BGA)

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

1

2

3

4

5

AR10
AT10

JCP U1D

W8

SB_CK[0]

W9

SB_CK#[0]

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B _DM0
DDR_B _DM1
DDR_B _DM2
DDR_B _DM3
DDR_B _DM4
DDR_B _DM5
DDR_B _DM6
DDR_B _DM7

DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7

DDR _B_DQS0
DDR _B_DQS1
DDR _B_DQS2
DDR _B_DQS3
DDR _B_DQS4
DDR _B_DQS5
DDR _B_DQS6
DDR _B_DQS7

DDR_B _MA0
DDR_B _MA1
DDR_B _MA2
DDR_B _MA3
DDR_B _MA4
DDR_B _MA5
DDR_B _MA6
DDR_B _MA7
DDR_B _MA8
DDR_B _MA9
DDR_B _MA10
DDR_B _MA11
DDR_B _MA12
DDR_B _MA13
DDR_B _MA14
DDR_B _MA15

M_CLK _DDR2 10
M_CLK _DDR#2 10
DDR_C KE2_DIMMB 10

M_CLK _DDR3 10
M_CLK _DDR#3 10
DDR_C KE3_DIMMB 10

DDR_C S2_DIMMB# 10
DDR_C S3_DIMMB# 10

M_ODT2 10
M_ODT3 10

DDR _B_DM[ 0..7] 10

DDR _B_DQS #[0..7] 10

DDR _B_DQ S[0..7] 10

DDR _B_MA[0.. 15] 10

JCP U1C

A A

DDR _A_D[0 ..63]9

B B

C C

DDR_A _BS09
DDR_A _BS19
DDR_A _BS29

DDR _A_CAS#9
DDR _A_RAS#9
DDR_A _WE#9

DDR _A_D0
DDR _A_D1
DDR _A_D2
DDR _A_D3
DDR _A_D4
DDR _A_D5
DDR _A_D6
DDR _A_D7
DDR _A_D8
DDR _A_D9
DDR _A_D10
DDR _A_D11
DDR _A_D12
DDR _A_D13
DDR _A_D14
DDR _A_D15
DDR _A_D16
DDR _A_D17
DDR _A_D18
DDR _A_D19
DDR _A_D20
DDR _A_D21
DDR _A_D22
DDR _A_D23
DDR _A_D24
DDR _A_D25
DDR _A_D26
DDR _A_D27
DDR _A_D28
DDR _A_D29
DDR _A_D30
DDR _A_D31
DDR _A_D32
DDR _A_D33
DDR _A_D34
DDR _A_D35
DDR _A_D36
DDR _A_D37
DDR _A_D38
DDR _A_D39
DDR _A_D40
DDR _A_D41
DDR _A_D42
DDR _A_D43
DDR _A_D44
DDR _A_D45
DDR _A_D46
DDR _A_D47
DDR _A_D48
DDR _A_D49
DDR _A_D50
DDR _A_D51
DDR _A_D52
DDR _A_D53
DDR _A_D54
DDR _A_D55
DDR _A_D56
DDR _A_D57
DDR _A_D58
DDR _A_D59
DDR _A_D60
DDR _A_D61
DDR _A_D62
DDR _A_D63

AJ10

AL10
AK12

AK11

AM10
AR11

AL11

AT11
AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14
AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A _DM0
DDR_A _DM1
DDR_A _DM2
DDR_A _DM3
DDR_A _DM4
DDR_A _DM5
DDR_A _DM6
DDR_A _DM7

DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2
DDR_A _DQS#3
DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7

DDR _A_DQS0
DDR _A_DQS1
DDR _A_DQS2
DDR _A_DQS3
DDR _A_DQS4
DDR _A_DQS5
DDR _A_DQS6
DDR _A_DQS7

DDR_A _MA0
DDR_A _MA1
DDR_A _MA2
DDR_A _MA3
DDR_A _MA4
DDR_A _MA5
DDR_A _MA6
DDR_A _MA7
DDR_A _MA8
DDR_A _MA9
DDR_A _MA10
DDR_A _MA11
DDR_A _MA12
DDR_A _MA13
DDR_A _MA14
DDR_A _MA15

M_CLK _DDR0 9
M_CLK _DDR#0 9
DDR_C KE0_DIMMA 9

M_CLK _DDR1 9
M_CLK _DDR#1 9
DDR_C KE1_DIMMA 9

DDR_C S0_DIMMA# 9
DDR_C S1_DIMMA# 9

M_ODT0 9
M_ODT1 9

DDR _A_DM[ 0..7] 9

DDR _A_DQS #[0..7] 9

DDR _A_DQ S[0..7] 9

DDR _A_MA[0.. 15] 9

DDR _B_D[0 ..63]10

DDR_B _BS010
DDR_B _BS110
DDR_B _BS210

DDR_ B_CAS#10
DDR_ B_RAS#10
DDR_B _WE#10

DDR _B_D0
DDR _B_D1
DDR _B_D2
DDR _B_D3
DDR _B_D4
DDR _B_D5
DDR _B_D6
DDR _B_D7
DDR _B_D8
DDR _B_D9
DDR _B_D10
DDR _B_D11
DDR _B_D12
DDR _B_D13
DDR _B_D14
DDR _B_D15
DDR _B_D16
DDR _B_D17
DDR _B_D18
DDR _B_D19
DDR _B_D20
DDR _B_D21
DDR _B_D22
DDR _B_D23
DDR _B_D24
DDR _B_D25
DDR _B_D26
DDR _B_D27
DDR _B_D28
DDR _B_D29
DDR _B_D30
DDR _B_D31
DDR _B_D32
DDR _B_D33
DDR _B_D34
DDR _B_D35
DDR _B_D36
DDR _B_D37
DDR _B_D38
DDR _B_D39
DDR _B_D40
DDR _B_D41
DDR _B_D42
DDR _B_D43
DDR _B_D44
DDR _B_D45
DDR _B_D46
DDR _B_D47
DDR _B_D48
DDR _B_D49
DDR _B_D50
DDR _B_D51
DDR _B_D52
DDR _B_D53
DDR _B_D54
DDR _B_D55
DDR _B_D56
DDR _B_D57
DDR _B_D58
DDR _B_D59
DDR _B_D60
DDR _B_D61
DDR _B_D62
DDR _B_D63

IC,A UB_CFD _rPGA,R1 P0

CON N@

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

IC,A UB_CFD _rPGA,R1 P0

CON N@

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Docum ent Num ber R ev

Cus tom

4

Dat e: Sheet o f

Compal Electronics, Inc.

Auburndale(3/5)-DDR3

LA-4902P

5

6 47Wed nesda y, Decem ber 09, 2 009

0.3

1

+CPU _CORE

JCP U1F

A A

B B

C C

D D

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,A UB_CFD _rPGA,R1 P0

CON N@

CPU CORE SUPPLY

1

POWER

SENSE LINES

1.1V RAIL POWER

PROC_DPRSLPVR

CPU VIDS

VSS_SENSE_VTT

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

PSI#

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

10U_0805_6 .3V6M

1

2

H_VI D0
H_VI D1
H_VI D2
H_VI D3
H_VI D4
H_VI D5
H_VI D6
PM_DP RSLPVR_R

C66

H_VTTVID1 = Low, 1.1V

H_VTTVID1 = High, 1.05V

AN35

R75 0_0402_5%

AJ34

1 2
1 2

AJ35

R76 0_0402_5%

B15
A15

Close to CPU

VCCS ENSE

VSSSENS E

10U_0805_6 .3V6M

C58

1

1

2

2

22U_0805_6 .3V6M

C45

1

1

2

2

+VCCP

22U_0805_6 .3V6M

C67

1

2

PSI# 41

H_VI D[0.. 6] 41

1 2

R74 0_0402_5%

H_VTTVID 1 38

IMVP_IMON 41

VCCS ENSE
VSSSENS E

VTT_SENSE 38
VSS_SENSE_VTT 38

1 2

R77 100_0402_1%

1 2

R78 100_0402_1%

2

+VCCP

10U_0805_6 .3V6M

10U_0805_6 .3V6M

C39

C40

1

2

10U_0805_6 .3V6M

22U_0805_6 .3V6M

C57

C49

1

2

+CPU _CORE

C59

1

@

2

47P_0402_5 0V8J

47P_0402_5 0V8J

C61

C60

1

@

@

2

11/6 add to follow des ign guide.

CPU

PROC _DPRSLP VR 41

VCCS ENSE 41
VSSSENS E 41

+CPU _CORE

2

3

+GFX_CORE

10U_0805_6 .3V6M

10U_0805_6 .3V6M

C879

C878

1

1

2

2

1

1

+

+

C974

C973

2

2

330U_X_2VM_R6M

47P_0402_5 0V8J

47P_0402_5 0V8J

C62

1

1

@

2

2

10U_0805_6 .3V6M

1

2

10U_0805_6 .3V6M

1

2

SI1 NO3 6

C972

330U_X_2VM_R6M

+VCCP

C72

1

2

10U_0805_6 .3V6M

C881

C880

1

2

1

+

2

330U_X_2VM_R6M

+VCCP

1

2

22U_0805_6 .3V6M

C73

10U_0805_6 .3V6M

C75

JCPU 1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,A UB_CFD _rPGA,R 1P0

CON N@

GRAPHICS

FDI PEG & DMI

+1.5V to +1.5V_CPU_VDDQ Transfer

SI7326DN- T1-E3_PAK1212-8

Q89

0.1U_04 02_10V6K

C1023

1

R1984

1 2

0_0402_5%

2

RUN ON

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

+1.5V_ CPU_VDD Q+1.5V

1
2
35

0.1U_04 02_10V6K

C1024

4

1

2

RUNON 33

Compal Secret Data

4

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAP HIC S VI Ds

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

4

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

DDR3 - 1.5V RAILS

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65

1.1V1.8V

VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

C1020

1 2

0.1U_04 02_10V6K

C1021

1 2

0.1U_04 02_10V6K

C1022

1 2

0.1U_04 02_10V6K

C1025

1 2

0.1U_04 02_10V6K

3A

POWER

0.6A

Stich CAP b etween 1.5V and 1.5V-CPU_VDDQ

Deciphered Date

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

1

2

1

@

+

2

1U_060 3_10V4Z

C78

1

2

+1.5V_ CPU_VDD Q+1.5V

5

VCC_AXG_S ENSE 43
VSS_AXG_SENSE 43

GFXVR_ VID_0 43
GFXVR_ VID_1 43
GFXVR_ VID_2 43
GFXVR_ VID_3 43
GFXVR_ VID_4 43
GFXVR_ VID_5 43
GFXVR_ VID_6 43

GFXVR_EN 43
GFXVR _DPRSLPVR 43
GFXVR_IMO N 43

1U_060 3_10V4Z

1U_060 3_10V4Z

C51

C50

1

2

10U_0805_6. 3V6M

330U_D 2_2VY_R7M

C63

C64

1

2

1U_060 3_10V4Z

C79

1

1

2

2

SLP_S333

1U_060 3_10V4Z

1

2

10U_0805_6. 3V6M

1

2

22U_0805_6 .3V6M

1

2

22U_0805_6 .3V6M

1

2

2.2U_0 603_6.3V4Z
C80

+1.5V_ CPU_VDD Q

1U_060 3_10V4Z

C52

C53

1

2

C65

+VCCP

10U_0805_6 .3V6M

C71

C70

1

2

+VCCP

22U_0805_6 .3V6M

C77

C76

1

2

+1.8VS

10U_0805_6 .3V6M

C81

1

1

2

2

+1.5V_ CPU_VDD Q

SLP_S3

11/10 for Auburndal e pre-ES1

GFXVR_E N

1U_060 3_10V4Z

C54

1

2

4.7U_0 603_6.3V6K
C82

R1135
220_0402_1%

1 2

13

D

Q90

2

SSM3K7002F _SC59-3

G

S

R967

4.7K_0402 _5%

1 2

7/2/2009 HP

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

Auburndale(4/5)-PWR

LA-4902P

5

06/30HP

0.3

7 47Wed nesda y, Decem ber 09, 2 009

1

JCP U1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

A A

B B

C C

D D

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

IC,A UB_CFD _rPGA,R1 P0

CON N@

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

2

JCP U1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

IC,A UB_CFD _rPGA,R1 P0

CON N@

VSS

3

+CPU _CORE

10U_0805_6 .3V6M

22U_0805_6 .3V6M

C83

1

2

1

2

C84

1

2

@

10U_0805_6 .3V6M

22U_0805_6 .3V6M

C993

C96

1

2

10U_0805_6. 3V6M

C85

1

2

22U_0805_6 .3V6M

10U_0805_6 .3V6M

C113

C111

1

1

2

2

@

22U_0805_6 .3V6M

22U_0805_6 .3V6M

C97

1

2

1

2

C98

1

2

10U_0805_6. 3V6M

22U_0805_6. 3V6M

C112

C86

1

2

@

CPU CORE

10U_0805_6 .3V6M

C116

1

1

2

2

@

22U_0805_6 .3V6M

C99

1

1

2

2

10U_0805_6. 3V6M

C114

1

1

2

2

22U_0805_6 .3V6M

C88

22U_0805_6 .3V6M

C100

22U_0805_6. 3V6M

C115

@

Under cavity

SI1 NO3 0

VSS_N CTF1_R

AT35

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

NCTF

AT1
AR34
B34
B2
B1
A35

VSS_N CTF2_R
VSS_N CTF3_R
VSS_N CTF4_R
VSS_N CTF5_R
VSS_N CTF6_R
VSS_N CTF7_R

T98 TPC12
T99 TPC12
T100 TPC12

22U_0805_6 .3V6M

1

2

@

10U_0805_6 .3V6M

1

2

22U_0805_6 .3V6M

22U_0805_6 .3V6M

C989

C93

C987

1

1

2

C991

1

2

1

2

2

@

@

10U_0805_6 .3V6M

10U_0805_6 .3V6M

C992

C95

1

1

2

2

4

10U_0805_6 .3V6M

22U_0805_6 .3V6M

C90

C89

1

1

2

2

@

22U_0805_6 .3V6M

22U_0805_6 .3V6M

C101

1

2

1

2

@

C102

1

2

10U_0805_6. 3V6M

C87

22U_0805_6 .3V6M

C990

10U_0805_6 .3V6M

C104

22U_0805_6 .3V6M

1

2

10U_0805_6 .3V6M

1

2

330U_X_2VM_R6M

1

+

2

22U_0805_6 .3V6M

C91

1

2

22U_0805_6 .3V6M

C994

C103

1

2

330U_X_2VM_R6M

C105

1

+

2

VSS_N CTF2_R

VSS_N CTF1_R

VSS_N CTF6_R

0.1U_0 402_16V4Z

VSS_N CTF7_R

10U_0805_6 .3V6M

22U_0805_6 .3V6M

C92

C988

1

2

C94

1

2

Inside cavity

05/ 20
chan ge MLCC par t r efer enc es fo r
powe r t eam requ est

10u F: C10 3 C 993 
C94 C97 C1 16 C 11

、、、、 、、、、 、、、、

C89 C98 C9 9 C1 00

、、、、 、、、、 、、、、

C10 2 C 91 C 84 C96 

、、、、 、、、、 、、、、

C11 1

、、、、

C88

22uF : t he o ther s

between Inductor and socket

330U_X_2VM_R6M

330U_X_2VM_R6M

C106

1

+

2

R79

100K_0402_5%

R80

100K_0402_5%

R81

100K_0402_5%

R82

100K_0402_5%

C107

+3VS

12

+3VS

12

+3VS

12

2

1

+3VS

12

470U_D 2_2VM_R4.5M

1

+

2

C1048

C108

@

2

5

2

5

470U_D 2_2VM_R4.5M

C109

1

2

61

34

61

34

C110

1

+

+

@

2

05/ 20
chan ge C105 ~ C 108 to SGA 00001 Q80

Q2A
2N7002DW H_SOT363-6

CRACK _BGA

Q2B
2N7002DW H_SOT363-6

CRACK _BGA

Q3A
2N7002DW H_SOT363-6

CRACK _BGA

Q3B
2N7002DW H_SOT363-6

@

、、、、

22U_0805_6. 3V6M

C117

1

1

2

2

5

BC99 4 C9 88 C 92

、、、、 、、、、

3 C9 0

、、、、

C101

、、、、

BC83

22U_0805_6. 3V6M

22U_0805_6. 3V6M

CRACK _BGA 17 ,29

10U_0805_6. 3V6M

C119

C118

C120

1

1

2

2

@

BGA Ball Cracking Prevention and Detection

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

LA-4902P

5

8 47Wed nesda y, Decem ber 09, 2 009

0.3

+3VS

1

+1.5V +1.5V

DDR3 SO-DIMM A

3 A

3 A @1 . 5 V

@ 1 . 5 V

3 A3 A

@ 1 . 5 V@ 1 . 5 V

JDIMA 1

CON N@

VREF_DQ1VSS1

0.1U_0 402_16V4Z

2.2U_0 805_16V4Z

C121

1

1

2

2

1

2

DDR _A_D0

C122

DDR _A_D1

DDR_A _DM0

DDR _A_D2
DDR _A_D3

DDR _A_D8
DDR _A_D9

DDR_A _DQS#1
DDR _A_DQS1

DDR _A_D10
DDR _A_D11

DDR _A_D16
DDR _A_D17

DDR_A _DQS#2
DDR _A_DQS2

DDR _A_D18
DDR _A_D19

DDR _A_D24
DDR _A_D25

DDR_A _DM3

DDR _A_D26
DDR _A_D27

DDR_C KE0_DIMM A

DDR_A _BS2

DDR_A _MA12
DDR_A _MA9

DDR_A_ MA8
DDR_A _MA5

DDR_A _MA3
DDR_A _MA1

M_CLK _DDR0
M_CLK _DDR#0

DDR_A _MA10
DDR_A _BS0

DDR_A _WE#
DDR _A_CAS# M_ODT0

DDR_A _MA13
DDR_C S1_DIMMA #

DDR _A_D32
DDR _A_D33

DDR_A _DQS#4
DDR _A_DQS4

DDR _A_D34
DDR _A_D35

DDR _A_D40
DDR _A_D41

DDR_A _DM5

DDR _A_D42
DDR _A_D43

DDR _A_D48
DDR _A_D49

DDR_A _DQS#6
DDR _A_DQS6

DDR _A_D50
DDR _A_D51

DDR _A_D56
DDR _A_D57

DDR_A _DM7

DDR _A_D58
DDR _A_D59

R87

1 2

10K_0402_5%

0.1U_0 402_16V4Z

2.2U_040 2_6.3V6M
C144

C143

1

2

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18
DQ1953VSS19

55

VSS20

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

10K_0402_5%

R88

12

VTT1

205

G1

FOX_AS0A 626-U2RN-7F

DQ4
DQ5

VSS3

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

SCL

G2

SI1: No 44

+V_DD R_REF_D IMMA_DQ

A A

B B

C C

D D

09/2/16 HP

DDR_C KE0_DIMMA6

DDR_A _BS26

M_CLK _DDR06
M_CLK _DDR#06

DDR_A _BS06

DDR_A _WE#6
DDR _A_CAS#6

DDR_C S1_DIMMA#6

Reserved

TOP

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

2

DDR _A_D4
DDR _A_D5

DDR_A _DQS#0
DDR _A_DQS0

DDR _A_D6
DDR _A_D7

DDR _A_D12
DDR _A_D13

DDR_A _DM1
DRAMRST #

DDR _A_D14
DDR _A_D15

DDR _A_D20
DDR _A_D21

DDR_A _DM2

DDR _A_D22
DDR _A_D23

DDR _A_D28
DDR _A_D29

DDR_A _DQS#3
DDR _A_DQS3

DDR _A_D30
DDR _A_D31

DDR_C KE1_DIMM A

DDR_A _MA15
DDR_A _MA14

DDR_A_ MA11
DDR_A _MA7

DDR_A_ MA6
DDR_A _MA4

DDR_A _MA2
DDR_A _MA0

M_CLK _DDR1
M_CLK _DDR#1

DDR_A _BS1
DDR _A_RAS#

DDR_C S0_DIMMA #

M_ODT1

DDR _A_D36
DDR _A_D37

DDR_A _DM4

DDR _A_D38
DDR _A_D39

DDR _A_D44
DDR _A_D45

DDR_A _DQS#5
DDR _A_DQS5

DDR _A_D46
DDR _A_D47

DDR _A_D52
DDR _A_D53

DDR_A _DM6

DDR _A_D54
DDR _A_D55

DDR _A_D60
DDR _A_D61

DDR_A _DQS#7
DDR _A_DQS7

DDR _A_D62
DDR _A_D63

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

+0.75V

2

+0.75VS

0 . 6 5 A @ 0

0 . 6 5 A @ 0 .7 5 V

. 75 V

0 . 6 5 A @ 00 . 6 5 A @ 0

. 75 V. 75 V

DDR _A_D[0 ..63]6

DDR _A_DM[ 0..7]6

DDR _A_DQ S[0..7]6

DDR _A_DQS #[0..7]6

DDR _A_MA[0.. 15]6

DRAMRST # 4,10

DDR_C KE1_DIMMA 6

M_CLK _DDR1 6
M_CLK _DDR#1 6

DDR_A _BS1 6
DDR _A_RAS# 6

DDR_C S0_DIMMA# 6
M_ODT0 6

M_ODT1 6

0.1U_0 402_16V4Z

C141

1

1

2

2

SMB_DATA_S3
SMB_CLK_S3

2.2U_0 805_16V4Z

C142

SI1: No 44

+V_DD R_REF_D IMMA_CA

JP20

3

3

2

2

1

1

ACES_85204 -03001

CON N@

For ME/AMT debug

PM_EXTTS#1_R 4,10
SMB_DATA_S3 4,10,11 ,13,26

SMB_CLK_S3 4,10,1 1,13,26

3

+1.5V

12

R83
1K_0402_1%

R84
1K_0402_1%

SI1: No 21
SI1: No 27

5

G2

4

G1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

09/4/10 HP

Layo ut N ote:
Pla ce n ea r D IMMA

10U_0603_6 .3V6M

1

2

+V_DD R_REF_D IMMA_DQ

SI1: No 44

09/4/27 HP

+1.5V

10U_0603_6 .3V6M

10U_0603_6 .3V6M

C127

C126

1

1

2

2

2008/09/15 2009/12/31

R1100
1K_0402_1%

R1101
1K_0402_1%

10U_0603_6 .3V6M

10U_0603_6 .3V6M

C129

C128

1

2

C130

1

2

Compal Secret Data

4

+1.5V

12

+V_DD R_REF_D IMMA_CA

12

10U_0603_6 .3V6M

C131

1

1

2

2

Deciphered Date

4

5

Layo ut N ote:
Sha red bet ween t he tw o
SO-D IMMs.
Pla ce two cap aci tors clo se
to the VR and o ne
be twe en the two SOD IMM s

Layo ut N ote:
Pla ce n ea r D IMMA

SI1: No 48

0.1U_0 402_16V4Z

0.1U_0 402_16V4Z

C132

C133

1

@

@

2

09/4/28 HP

SI2 NO9

0.1U_0 402_16V4Z

0.1U_0 402_16V4Z

C134

C135

1

@

2

1

1

+

@

2

2

+0.75VS

330U_D 2_2VY_R7M

C123

C136

1

2

Title

Size Docum ent Num ber R ev

Cus tom

LA-4902P

Dat e: Sheet

C138

C137

1U_0402 _6.3V6K

C139

1U_0402 _6.3V6K

C140

10U_0603_6 .3V6M

1U_0402 _6.3V6K

1

1

2

2

1U_0402 _6.3V6K

1

2

C124

1

1

2

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

5

9 47Wed nesda y, Decem ber 09, 2 009

10U_0603_6 .3V6M

of

C125

10U_0603_6 .3V6M

1

2

0.3

1

2

3

4

5

SI1: No 44

+V_DD R_REF_D IMMB_DQ

2.2U_0 805_16V4Z

0.1U_0 402_16V4Z

1

+3VS

C145

2

DDR_C KE2_DIMMB6

DDR_B _BS26

M_CLK _DDR26
M_CLK _DDR#26

DDR_B _BS06

DDR_B _WE#6
DDR_ B_CAS#6

DDR_C S3_DIMMB#6

2.2U_04 02_6.3V6M

1

2

1

A A

B B

C C

D D

09/2/16 HP

+VREF _DQ_DIMMB

DDR _B_D0
DDR _B_D1

1

C146

DDR_B _DM0

2

DDR _B_D2
DDR _B_D3

DDR _B_D8
DDR _B_D9

DDR_B _DQS#1
DDR _B_DQS1

DDR _B_D10
DDR _B_D11

DDR _B_D16
DDR _B_D17

DDR_B _DQS#2
DDR _B_DQS2

DDR _B_D18
DDR _B_D19

DDR _B_D24
DDR _B_D25

DDR_B _DM3

DDR _B_D26
DDR _B_D27

DDR_C KE2_DIMM B

DDR_B _BS2

DDR_B _MA12
DDR_B _MA9

DDR_B_ MA8
DDR_B _MA5

DDR_B _MA3
DDR_B _MA1

M_CLK _DDR2
M_CLK _DDR#2

DDR_B _MA10
DDR_B _BS0

DDR_B _WE#
DDR _B_CAS# M_ODT2

DDR_B _MA13
DDR_C S3_DIMMB #

DDR _B_D32
DDR _B_D33

DDR_B _DQS#4
DDR _B_DQS4

DDR _B_D34
DDR _B_D35

DDR _B_D40
DDR _B_D41

DDR_B _DM5

DDR _B_D42
DDR _B_D43

DDR _B_D48
DDR _B_D49

DDR_B _DQS#6
DDR _B_DQS6

DDR _B_D50
DDR _B_D51

DDR _B_D56
DDR _B_D57

DDR_B _DM7

DDR _B_D58
DDR _B_D59

1 2

10K_0402_5%

0.1U_0 402_16V4Z

C165

C166

1

2

+1.5V +1.5V

DDR3 SO-DIMM B

3 A

3 A @1 . 5 V

@ 1 . 5 V

3 A3 A

@ 1 . 5 V@ 1 . 5 V

JDIMB 1 CON N@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18
DQ1953VSS19

55

VSS20

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R91

1 2

R92 10K_0402 _5%

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

+0.75V

BOT

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5

VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7

VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DDR _B_DQS #[0..7]6

DDR _B_D[0 ..63]6

2.2U_0 805_16V4Z

C160

1

2

DDR _B_DM[ 0..7]6

DDR _B_DQS [0..7]6

DDR_ B_MA[0.. 15]6

SI1: No 44

+V_DD R_REF_D IMMB_CA

3

Layo ut N ote:
Pla ce n ea r D IMMB

10U_0603_6 .3V6M

C149

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/12/31

2

DDR _B_D4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

2

DDR _B_D5

DDR_B _DQS#0
DDR _B_DQS0

DDR _B_D6
DDR _B_D7

DDR _B_D12
DDR _B_D13

DDR_B _DM1
DRAMRST #

DDR _B_D14
DDR _B_D15

DDR _B_D20
DDR _B_D21

DDR_B _DM2

DDR _B_D22
DDR _B_D23

DDR _B_D28
DDR _B_D29

DDR_B _DQS#3
DDR _B_DQS3

DDR _B_D30
DDR _B_D31

DDR_C KE3_DIMM B

DDR_B _MA15
DDR_B _MA14

DDR_B_ MA11
DDR_B _MA7

DDR_B_ MA6
DDR_B _MA4

DDR_B _MA2
DDR_B _MA0

M_CLK _DDR3
M_CLK _DDR#3

DDR_B _BS1
DDR _B_RAS#

DDR_C S2_DIMMB #

M_ODT3

+VREF _CA

DDR _B_D36
DDR _B_D37

DDR_B _DM4

DDR _B_D38
DDR _B_D39

DDR _B_D44
DDR _B_D45

DDR_B _DQS#5
DDR _B_DQS5

DDR _B_D46
DDR _B_D47

DDR _B_D52
DDR _B_D53

DDR_B _DM6

DDR _B_D54
DDR _B_D55

DDR _B_D60
DDR _B_D61

DDR_B _DQS#7
DDR _B_DQS7

DDR _B_D62
DDR _B_D63

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

0 . 6 5 A @ 0

0 . 6 5 A @ 0 .7 5 V

. 75 V

0 . 6 5 A @ 00 . 6 5 A @ 0

. 75 V. 75 V

DRAMRST # 4,9

DDR_C KE3_DIMMB 6

M_CLK _DDR3 6
M_CLK _DDR#3 6

DDR_B _BS1 6
DDR _B_RAS# 6

DDR_C S2_DIMMB# 6
M_ODT2 6

M_ODT3 6

0.1U_0 402_16V4Z

C159

1

2

PM_EXTTS#1_R 4,9
SMB_DATA_S3 4,9,11 ,13,26

SMB_CLK_S3 4,9,1 1,13,26

+0.75VS

+1.5V

1

2

R1102
1K_0402_1%

R1103
1K_0402_1%

10U_0603_6 .3V6M

C150

+1.5V

12

+V_DD R_REF_D IMMB_DQ

12

SI1: No 44

09/4/27 HP

10U_0603_6 .3V6M

10U_0603_6 .3V6M

C152

C151

1

1

2

2

Compal Secret Data

Deciphered Date

10U_0603_6 .3V6M

10U_0603_6 .3V6M

C154

C153

1

1

2

2

4

R1104
1K_0402_1%

R1105
1K_0402_1%

0.1U_0 402_16V4Z
C155

1

@

2

+1.5V

12

+V_DD R_REF_D IMMB_CA

12

SI1: No 48

0.1U_0 402_16V4Z
C156

1

1

@

2

2

Layo ut N ote:
Pla ce n ea r D IMM

09/4/28 HP

+0.75VS

0.1U_0 402_16V4Z
C157

1

@

2

C977

C158

1

+

@

2

Title

Size Docum ent Num ber R ev

Dat e: Sheet

330U_D 2_2VY_R7M

0.1U_0 402_16V4Z

1U_040 2_6.3V6K

1U_040 2_6.3V6K

1U_040 2_6.3V6K

C161

C162

1

2

C163

1

1

2

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

LA-4902P

5

1U_040 2_6.3V6K

C164

1

2

0.3

of

10 47Wedn esday, Decembe r 09, 20 09

1

A A

2

3

3VS_1.5V S

4

5

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0T
CPU_0C

VSS_CPU

CPU_1T
CPU_1C

VDD_CPU_IO

VDD_SRC

TGND

+3VS_CK505 + 1.05VS_CK505+3VS_CK505 +1.05VS_ CK505

32

SCL

31

SDA

30
29
28
27
26
25

24
23
22
21
20
19
18
17

33

SMB_CLK_S3
SMB_DATA_S3
REF_ 0/CPU_S EL

CLK_XTAL_IN
CLK_XTAL_OUT

CK_P WRGD

R_CLK _BUF_BC LK CLK_BU F_BCLK
R_CLK _BUF_BC LK# CLK_B UF_BCLK#

R94 33_0402_5%

1 2

R101 0_0402_5%

1 2

R103 0_0402_5%

1 2

1

C885
10P_0402_5 0V8J

2

CLK_1 4M_PCH

@

SMB_CLK_S3 4,9,1 0,13,26
SMB_DATA_S3 4,9,10 ,13,26
CLK_14 M_PCH 13

CLK_B UF_BCLK 13
CLK_B UF_BCLK# 13

U2

1

VDD_DOT

2

CLK_B UF_DOT9613
CLK_B UF_DOT96#13

CLK_ BUF_CKS SCD13
CLK_ BUF_CKSS CD#13

CLK_D MI13
CLK_D MI#13

B B

CLK_B UF_DOT96
CLK_B UF_DOT96#

CLK _BUF_CK SSCD
CLK_ BUF_CKS SCD#

CLK_D MI
CLK_D MI#

R93 0_0402_5%

1 2

R95 0_0402_5%

1 2

R98 0_0402_5%

1 2

R99 0_0402_5%

1 2

R100 0_0402_5%

1 2

R102 0_0402_5%

1 2

L_CLK _BUF_DOT96
L_CLK _BUF_DOT96#

L_CLK _BUF_CKS SCD
L_CLK _BUF_CKS SCD#

L_CLK _DMI
L_CLK _DMI#

CPU_STO P#

VSS_DOT

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SRC

10

SRC_1T

11

SRC_1C

12

VSS_SRC

13

SRC_2T

14

SRC_2C

15

VDD_SRC_IO

16

CPU_STOP#

RTM890N-6 32-GRT_QFN32_5X5

REF_0/CPU_SEL

CKPWRGD/PD#

CLK Ge n feat ure 1. 5V supp ort 6/29

+3VS

+1.5VS

1 2

3VS_1.5V S

C175

1

2

R1129 0_0603_ 5%

1 2

R1130 0_0603_ 5%

47P_0402_ 50V8J

0.1U_0 402_16V4Z
C177

C176

1

2

@

+1.05VS_C K505+1.05VS

1 2

R127 0_0603_ 5%

C C

10U_08 05_10V4Z

1

2

C178

10U_08 05_10V4Z

1

2

Close to U2

0.1U_0 402_16V4Z
C180

C179

1

2

CPU_STO P#

R126 10K_0402_5%

0.1U_0 402_16V4Z

1

2

47P_0402_5 0V8J

0.1U_0 402_16V4Z

C181

C183

C182

1

1

2

2

1 2

+3VS_CK505

+3VS

+3VS_CK505

1 2

R108 0_0603_ 5%

Close to U2

0.1U_0 402_16V4Z

0.1U_0 402_16V4Z

0.1U_0 402_16V4Z

10U_08 05_10V4Z

C172

C171

1

1

2

1

2

2

0.1U_0 402_16V4Z

C173

C174

1

1

2

2

C167

33P_0402_ 50V8J

14.31818MHZ_ 20P_1BX14318BE1A

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

12

2

2

C168

33P_0402_ 50V8J

1

1

CK_P WRGD

Q4

SSM3K7002F _SC59-3

1 2

13

D

S

R97
10K_0402_5%

2

G

1

2

0.1U_0 402_16V4Z

+3VS_CK505

C1049

CLK_E N# 41

Close to U2 within 500mil

(Def aul t)

0 133MHz

1

100MHz 100MHz

CPU_1PIN 30 CPU_0

133MHz

09/2/5 HP

+1.05VS

1 2

R141 10K_0402_5%@

1 2

R143 10K_0402_5%

REF_ 0/CPU_S EL

@

REF_ 0/CPU_S EL

C184

1 2

10P_0402_ 50V8J

EMI Capacitor

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

Title

Size Docum ent Num ber R ev

Dat e: Sheet o f

Compal Electronics, Inc.

CLOCK GENERATOR

LA-4902P

5

11 47Wedn esday, Decembe r 09, 20 09

0.3

1

PCH_RTC X1

1 2

R158 10M_0402_5%

18P_0402_5 0V8J

1

1

C189

A A

2

C833 47P_0402_5 0V8J

C834 47P_0402_5 0V8J

C835 47P_0402_5 0V8J

C836 47P_0402_5 0V8J

+3VALW

R173 10K_0402_5%

R1999 10K_0402_ 5%

B B

iTPM ENABLE/DISABLE

+3VS

R181 1K_0402_5%@

Enable=Stuff Disable=No Stuff

C C

+3VALW +3VALW +3VALW +3VALW

PCH Pin

D D

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

OSC4OSC

NC3NC

Y3

2

HDA_B IT_CLK_MDC

1 2

HDA_B IT_CLK_C ODEC

@

1 2

HDA_S DOUT_MDC

@

1 2

HDA_S DOUT_CO DEC

1 2

@

1 2

1 2

1 2

for SMSC EC

notice KBC state

12

R183
200_0402_5%@

PCH_JTAG_T MS PCH_JT AG_RST#PCH_JT AG_TDO PCH_JTAG _TDI

12

R189
100_0402_1%@

1 2

R194 51_0402 _5%

RefDes PCH JTAG Pre-Production PCH JTAG Production

R184
R190
R1067 No Install No Inst all

R189
R1068 No Install No Inst all 51ohm
R185
R191
R1069
R194
R186
R192
R1070 51ohmNo Install No In stall

PCH_RTC X2

32.768 KHZ_12.5P F_Q13MC14610002

1

C190
18P_0402_5 0V8J

2

LID_S W#

GPIO13

KBC_S PI_SI_R

KBC_S PI_CLK_R29

KBC_S PI_CS0#_R29

KBC_S PI_CS1#_R29

12

R184
200_0402_5%@

12

R190
100_0402_1%@

PCH_JT AG_TCK

ES1
No Install
No Install

200ohm
100ohm

200ohm
100ohm
No Install No In stall
51ohm
20Kohm
10Kohm

1

1U_060 3_10V4Z

R163

+RTCV CC

1 2

20K_0402_1%

1 2

R164 20K_0402_1%

1U_0603 _10V4Z

HDA_B IT_CLK_MDC25
HDA_B IT_CLK_C ODEC25
HDA_ SYNC_ MDC25
HDA_ SYNC_ CODEC25
HDA_ SPKR25

HDA_R ST#_MDC25
HDA_R ST#_COD EC25

HDA_ SDIN025

HDA_ SDIN125

HDA_S DOUT_MDC25
HDA_S DOUT_CO DEC25

AQUAW HITE_BATLED

09/2/5 HP

KBC_S PI_SI_R29

KBC_SP I_SO29

09/2/5 HP

ES2

100ohm

200ohm
100ohm

200ohm No Inst all
100ohm

51ohm
20Kohm
10Kohm

12

R185
200_0402_5%@

12

R191
100_0402_1%@

No Install200ohm
No Install
51ohm
No InstallR183
No Install

No Install
51ohm
51ohm
No Install
No Install

1

12

C191

SHORT PADS

2

1

SI1 NO4 1

C192

09/4/27 HP

2

R165 33_0402_5%

1 2

R166 33_0402_5%

1 2

R167 33_0402_5%

1 2

R168 33_0402_5%

1 2

R169 33_0402_5%

1 2

R170 33_0402_5%

1 2

R171 33_0402_5%

1 2

R172 33_0402_5%

1 2

R847 1K_0402_5%

09/2/5 HP

R939 15_0402_5%

1 2

1 2

R176 0_0402_ 5%

1 2

R180 0_0402_ 5%

R940 15_0402_5%

1 2

SI2 NO7

+RTCV CC +3VS

CLRP 1

R186
20K_0402_5%

@

R192
10K_0402_5%

@

AQUAW HITE_BATLE D_R

1 2

SI1 NO7

09/3/9 HP

12

12

2

1 2

R159 1M_0402_5%

1 2

R161 330K_0402_5%

High = Inte rnal VR Ena bled(Default)

PCH_RTC X1
PCH_RTC X2

PCH_R TCRST#

PCH_S RTCRST#

SM_IN TRUDER#

PCH_I NTVRMEN

HDA_B IT_CLK

HDA _SYN C

HDA_ SPKR

HDA_R ST#

HDA_ SDIN0

HDA_ SDIN1

HDA_S DOUT

GPIO13

PCH_JT AG_TCK

PCH_JTAG_T MS

PCH_J TAG_TDI

PCH_JT AG_TDO

SPI_C LK_PCH

SPI_C S0#_PCH

SPI_C S1#_PCH

SPI_MO SI_PCH

PCH_JT AG_TDO

PCH_JTAG_T MS

PCH_J TAG_TDI

PCH_JT AG_RST#

330K_0402_5% @

AQUAW HITE_BATLED#25 ,29

SM_IN TRUDER# SIRQ

PCH_I NTVRMEN

U4A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

JTAG_RST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK- M_FCBGA1071

R1067 51_0402_5%@

1 2

R1068 51_0402_5%@

1 2

R1069 51_0402_5%@

1 2

R1070 51_0402_5%@

1 2

+3VS

1 2

2

G

R964

@

AQUAW HITE_BATLED

1 2
13

D

Q66
SSM3K7002F _SC59-3

S

R965

GPIO33 iA MT Ena ble /D isable

Hi Disable

Lo Enable De fault

2

R160 10K_0402_5%

R162 10K_0402_5%

LOW=Default HIGH=No Reboot

RTCIHD A

SAT A

SPI JTAG

+1.05VS

10K_0402_5%

1 2

12

@

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LPC

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

D33
B33
C32
A32

C34

A34
F34

AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

AF15

T3

Y9

V1

USB_O C#015
USB_O C#115

USB_O C#215
USB_O C#315

USB_O C#415
USB_O C#515

USB_O C#615
USB_O C#715

HDA_ SPKR

SIRQ

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4

SATA_PRX_DTX_N5
SATA_PRX_DTX_P5
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5

SATAICO MPIPCH_JT AG_RST#

SATA_DET#0

HDD_H ALTLED_ R

PCH_JT AG_TCK

3

1 2

R175 37.4_0402_1 %

1 2

R177 10K_0402_1%

LPC_L AD0 23,29 ,30,31
LPC_L AD1 23,29 ,30,31
LPC_L AD2 23,29 ,30,31
LPC_L AD3 23,29 ,30,31

LPC_LF RAME# 23, 29,30,31

LPC_L DRQ#0 30

SIRQ 27, 29,30,31

SATA_PRX_DTX_N0 23
SATA_PRX_DTX_P0 23
SATA_PTX_DRX_N0 23
SATA_PTX_DRX_P0 23

SATA_PRX_DTX_N1 23
SATA_PRX_DTX_P1 23
SATA_PTX_DRX_N1 23
SATA_PTX_DRX_P1 23

09/2/5 HP

+1.05VS

+3VS

SATA_LED# 25,28

R1071

0_0402_5%

12

SI1 NO2 2

SI1 NO2

09/3/9 HP

NAND_ DET# 24

SI1 NO6 0

09/5/4 HP

SATA_PRX_DTX_N2 28
SATA_PRX_DTX_P2 28
SATA_PTX_DRX_N2 28
SATA_PTX_DRX_P2 28

SATA_PRX_DTX_N4 26
SATA_PRX_DTX_P4 26
SATA_PTX_DRX_N4 26
SATA_PTX_DRX_P4 26

SATA_PRX_DTX_N5 28
SATA_PRX_DTX_P5 28
SATA_PTX_DRX_N5 28
SATA_PTX_DRX_P5 28

HDD_H ALTLED 25

4

10K_0402_5%

HDD_H ALTLED

SATA_DET#0

PCH XDP Conn.

JP15

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7
1 2
1 2

1 2
1 2

XDP_FN1

R85233_0402_5%@

XDP_FN2

R85433_0402_5%@

XDP_FN3

R85633_0402_5%@

XDP_FN0

R85033_0402_5%@

DB1 NO 77

XDP_FN4

R107233_0402_5%@

1 2
1 2

1 2

+3VS

1 2

1 2

1 2

R8660_0402_5%

T122TPC12
T123TPC12

PWR _GD29,32

PM_PWR BTN#_R4,14

SI1 NO2 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

XDP_FN5

R86033_0402_5%@

XDP_FN6

R86233_0402_5%@

XDP_FN7

R86433_0402_5%@

PWR _GD

XDP_PW RBTN#_R

09/2/5 HP

PCH_J TAG_TCK_R

R8710_ 0402_5%

2008/09/15 2009/12/31

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH -030-01-L-D-A CON N@

Compal Secret Data

Deciphered Date

4

ITPCLK#/HOOK5

RESET#/HOOK6

+3VS

R178

@

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

VCC_OBS_CD

DBR#/HOOK7

GND15

TRST#

TMS

GND17

1

2

1 2

1 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58
60

D1

1

BAV70W_S OT323-3

C211

1U_0603 _10V4Z

Plac e n ear IBE X-M

R179
10K_0402_5%

XDP_FN1 6

R848 33_0402_5%@

XDP_FN1 7

R849 33_0402_5%@

XDP_FN8

R851 33_0402_5%@

XDP_FN9

R853 33_0402_5%@

XDP_FN1 0

R855 33_0402_5%@

XDP_FN1 1

R857 33_0402_5%@

XDP_FN1 2

R859 33_0402_5%@

XDP_FN1 3

R861 33_0402_5%@

XDP_FN1 4

R863 33_0402_5%@

XDP_FN1 5

R865 33_0402_5%@

+3VS

1K_0402_5%

R867

1 2

PCH_J TAG_TDO#_R

PCH_J TAG_TDI_R
PCH_JTAG _TMS_R

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

5

RTC Conn.

CON N@

BATT1.1+VREG3_511 25+RTCV CC

JBAT1
ACES_85205 -0200

2

R193

3

1 2

W=20 mil sW=20 mil s

12
12

12
12

12
12

12
12

12
12

R868 0_0402_5%
R869 0_0402_5% @
R870 0_0402_5%
R872 0_0402_5%

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

LA-4902P

1K_0402_5%

12
12
12
12

SI1 NO2 2

W=20 mil s

PCH_XDP _GPIO28 15
PCH_XD P_GPIO0 15

PCH_XDP _GPIO20 13
PCH_XDP _GPIO18 13

SATA_DET#0

HDD_H ALTLED_ R

PCH_XDP _GPIO36 15
PCH_XDP _GPIO37 15 ,20

PCH_XDP _GPIO16 15
PCH_XDP _GPIO49 15

PLT_RST# 4 ,15,21,23 ,25,31

XDP_DBRESET # 4,14

PCH_JT AG_TDO
PCH_JT AG_RST#PCH_J TAG_RST#_R
PCH_J TAG_TDI
PCH_JTAG_T MS

5

1

2

12 47Wedn esday, Decembe r 09, 20 09

GPIO_28

GPIO_0

09/2/16 HP

GPIO_36
GPIO_37
GPIO_16
GPIO_49

0.3

1

A A

PCIE_PRX_ DTX_N225

EXP

WLAN

NIC

B B

SI, No6 1

09/5/4 HP

EXP

C C

WLAN

PCIE_PRX_DTX_P225
PCIE_PTX_ C_DRX_N225
PCIE_PTX_ C_DRX_P225

PCIE_PRX_ DTX_N423
PCIE_PRX_DTX_P423
PCIE_PTX_ C_DRX_N423
PCIE_PTX_ C_DRX_P423

PCIE_PRX_ DTX_N621
PCIE_PRX_DTX_P621
PCIE_PTX_ C_DRX_N621
PCIE_PTX_ C_DRX_P621

PCH_XD P_GPIO1812

CLK_P CIE_LAN_ REQ1#21

R207 10K_0402_5%

+3VS

CLK_PCIE_ EXP#25
CLK_PCIE _EXP25

PCH_XD P_GPIO2012

CLKREQ_EXP #25

CLK_P CIE_MCAR D#23
CLK_P CIE_MCAR D23

CLKRE Q_WLAN#23

1 2

NIC

C212 0.1U_04 02_10V7K
C213 0.1U_04 02_10V7K

C214 0.1U_04 02_10V7K
C215 0.1U_04 02_10V7K

C218 0.1U_04 02_10V7K
C219 0.1U_04 02_10V7K

+3VALW

09/3/9 HP

R208 0_0402_5%
R209 0_0402_5%

+3VS

+3VALW

09/3/9 HP

R211 0_0402_5%
R212 0_0402_5%

+3VALW

+3VALW

+3VALW

1 2
1 2

1 2
1 2

1 2
1 2

R875 10K_0402_5%

1 2

R1119 0_ 0402_5%

SI1 NO5

1 2
1 2

R941 10K_0402_5%

1 2

R972 0_0402_5%

1 2

R942 10K_0402_5%

1 2

SI1 NO5

1 2
1 2

R943 10K_0402_5%

1 2

R944 10K_0402_5%

1 2

R1057 10K _0402_5%

1 2

PCIE_PRX_ DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_ DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_ DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_ DRX_N4
PCIE_PTX_DRX_P4

PCIE_PRX_ DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_ DRX_N6
PCIE_PTX_DRX_P6

1 2

CLK_PC IE_EXP#_R
CLK_PC IE_EXP_R

CLK_P CIE_MCAR D#_R
CLK_P CIE_MCAR D_R

2

U4B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK- M_FCBGA1071

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

PCI-E*

Link

Cont rol ler

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9

H14

C8

J14

C6

G8

M14

E10

G12

T13

T11

T9

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

AH51
AH53

AF38

T45

P43

T42

N50

SMBALERT#

SMBCLK

SMBDATA

SML0ALERT#

SML0CLK

SML0DATA

SML1ALERT#

SML1CLK

SML1DATA

PEG_C LKREQ#

CLK_EXP#_R
CLK_EXP_R

CLK_D P#_R
CLK_ DP_R

XTAL25_IN
XTAL25_OUT

R215

1 2

22_0402_5%

SI1 NO8 8

3

8/31/2009 HP

SML0CLK 21

SML0DATA 21

CL_CL K1 23

CL_DATA1 23

CL_RST1# 23

SI1 NO5

09/3/9 HP

R41 0_0402_5%

1 2

R59 0_0402_5%

1 2

R11 0_0402_5%

1 2

R13 0_0402_5%

1 2

CLK_D MI# 11
CLK_D MI 11

CLK_B UF_BCLK# 11
CLK_B UF_BCLK 11

CLK_B UF_DOT96# 11
CLK_B UF_DOT96 11

CLK_ BUF_CKS SCD# 11
CLK _BUF_CKS SCD 11

CLK_1 4M_PCH 11

CLK_ PCI_FB 15

R213 90.9_0402_ 1%

1 2

T102 TPC12

T103 TPC12

CLK_14M_S IO 30

C887

1

@

10P_0402_5 0V8J

2

DDR

intel LAN

EC_THERMAL

+1.05VS

CLK_EXP# 4
CLK_EXP 4

CLK_D P# 4
CLK_ DP 4

4

SMB_CLK_S3

SMB_DATA_S3

PEG_C LKREQ#

SMBCLK

SMBDATA SMB_DATA_S3

+3VS

SML1CLK

SML1DATA

1 2

R195 10K_040 2_5%

1 2

R197 10K_040 2_5%

1 2

R204 10K_040 2_5%

Q5A
2N7002DW H_SOT363-6

6 1

2

Q5B
2N7002DW H_SOT363-6

3 4

5

2N7002DW H_SOT363-6

2

2N7002DW H_SOT363-6

5

SMB_CLK_S3

Q77A

Q77B

61

34

+3VALW

SI1 NO3 2

09/4/10 HP

XTAL25_IN

XTAL25_OUT

SMBCLK

+3VS

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

SML0ALERT#

SMBALERT#

SML1ALERT#

SMB_CLK_S3 4,9,1 0,11,26

SMB_DATA_S3 4,9,10 ,11,26

CAP_C LK 25,29

CAP_DAT 25,29

1 2

R196 2.2K_0 402_5%

1 2

R198 2.2K_0 402_5%

1 2

R200 2.2K_0 402_5%

1 2

R202 2.2K_0 402_5%

1 2

R203 4.7K_0 402_5%

1 2

R205 4.7K_0 402_5%

1 2

R206 10K_040 2_5%

1 2

R935 10K_040 2_5%

1 2

R936 10K_040 2_5%

5

09/2/16 HP

This circui t will add/ delete in INTEL ES2 s ample to test.

1 2

R210 1M_0402_5%

Y4

1 2

25MHZ_20 P_1BG25000CK1A

18P_0402_ 50V8J

C222

1

2

18P_0402_ 50V8J

C1034

1

2

+3VALW

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA-4902P

5

13 47Wedn esday, Decembe r 09, 20 09

0.3

5

4

3

2

1

R230

R302

@

12

U4D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK- M_FCBGA1071

10/17 HP re move to P14 (close U5

DAC_ GRN

DAC _BLU

R303

@

150_0402_1%

12

LVDS

CRT

L7,L9,L11 a re 39uH

10P_0402_ 50V8J

C280

1

1

@

@

2

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

10P_0402_ 50V8J

C281

1

@

2

SDVO_STALLN

SDVO_STALLP

SDVO_INTN

SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

Pla ce cloce to U5

L

L7
0805CS-680 XJLC_0805

1 2

L9
0805CS-680 XJLC_0805

1 2

L11
0805CS-680 XJLC_0805

1 2

10P_0402_ 50V8J

C282

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

DPB_AUX#
DPB_AUX
DPB _R

DPB_TXN0
DPB_TXP0
DPB_TXN1
DPB_TXP1
DPB_TXN2
DPB_TXP2
DPB_TXN3
DPB_TXP3

DPC_AUX #
DPC_AUX
DP C_RSYS_RS T#

DPC_TXN0
DPC_TXP0
DPC_TXN1
DPC_TXP1
DPC_TXN2
DPC_TXP2
DPC_TXN3
DPC_TXP3

DPD_C _AUX#
DPD_C _AUX

DPD_C_TX N0
DPD_C_TXP0
DPD_C_TX N1
DPD_C_TXP1
DPD_C_TX N2
DPD_C_TXP2
DPD_C_TX N3
DPD_C_TXP3

DPB _R

DP C_R

DP D_R

1

2

R1017
R1018

R1019
R1020

DAC_ RED_RDAC_ RED

DAC_ GRN_R

DAC _BLU_R

1

C283

2

27P_0402_5 0V8J

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

1 2

R822 100K_040 2_5%

1 2

R823 100K_040 2_5%

1 2

R824 100K_040 2_5%

1

C284

2

27P_0402_5 0V8J

R818

C920 0.1U_04 02_10V7K

1 2

C921 0.1U_04 02_10V7K

1 2

C922 0.1U_04 02_10V7K

1 2

C923 0.1U_04 02_10V7K

1 2

C924 0.1U_04 02_10V7K

1 2

C925 0.1U_04 02_10V7K

1 2

C926 0.1U_04 02_10V7K

1 2

C927 0.1U_04 02_10V7K

1 2

C928 0.1U_04 02_10V7K

1 2

C929 0.1U_04 02_10V7K

1 2

1 2

C1050 0.1 U_0402_16V4Z

L8
0805CS-680 XJLC_0805

1 2

L10
0805CS-680 XJLC_0805

1 2

L12
0805CS-680 XJLC_0805

1 2

C285

27P_0402_5 0V8J

+3VS

+3VS

+3VS

R819

2.2K_0402_5%

DPB_C TRLCLK 28
DPB_CTR LDATA 28

DPC_C TRLCLK 28

DPC_C TRLDATA 28

DPD_C TRLCLK 19

DPD_C TRLDATA 19

DP D_R

RED _R 28

GREE N_R 28

BLUE _R 28

DPB_AUX# 28
DPB_AUX 28
DPB_ HPD 28

DPB_TXN0 28
DPB_TXP0 28
DPB_TXN1 28
DPB_TXP1 28
DPB_TXN2 28
DPB_TXP2 28
DPB_TXN3 28
DPB_TXP3 28

DPC_AUX # 28
DPC_AUX 28
DPC_ HPD 28

DPC_TXN0 28
DPC_TXP0 28
DPC_TXN1 28
DPC_TXP1 28
DPC_TXN2 28
DPC_TXP2 28
DPC_TXN3 28
DPC_TXP3 28

DPD_AUX # 19
DPD_AUX 19
DPD_ HPD 19

DPD_TXN0 19
DPD_TXP0 19
DPD_TXN1 19
DPD_TXP1 19
DPD_TXN2 19
DPD_TXP2 19
DPD_TXN3 19
DPD_TXP3 19

DMI_CTX_PRX_N05
DMI_CTX_PRX_N15
DMI_CTX_PRX_N25
DMI_CTX_PRX_N35

DMI_CTX_PRX_P05
DMI_CTX_PRX_P15
DMI_CTX_PRX_P25

D D

PGD_ IN29

09/5/18 HP

SI, No8 2

C C

B B

DMI_CTX_PRX_P35

DMI_CRX_PTX_N05
DMI_CRX_PTX_N15
DMI_CRX_PTX_N25
DMI_CRX_PTX_N35

DMI_CRX_PTX_P05
DMI_CRX_PTX_P15
DMI_CRX_PTX_P25
DMI_CRX_PTX_P35

+1.05VS

1 2

R222 49.9_04 02_1%

XDP_DBRESET #4,12

VGATE41

R1124

1 2

1K_0402_5%

M_PWROK32

PM_DRA M_PWRGD4

RPGOO D37
PM_RSMRST#29

+3VALW

SUS_P WR_ACK29

PM_PWR BTN#_R4,12
PWRBT N_OUT#25, 28,29

AC_PR ESENT29

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IR COMP

1 2

R223 0_0402_5%

VGATE

1 2

R225 0_0402_5%

R226 0_0402_5%

09/2/5 HP

R227 0_0402_5%

R228 10K_0402_5%
R958 10K_0402_5%

1 2

R229 0_0402_5%

PM_CL KRUN#

1 2

PM_DR AM_PWRGD

1 2
1 2

1 2

AUXPWR OK

LOW_BA T_R

IBEX_R#

SI, No5 8

SYS_RS T#

LOW_BA T_R

PM_SLP_LAN#

IBEX_R#

PCIE_ WAKE#

AC_PR ESENT

09/5/18 HP

SI, No8 2

U4C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK- M_FCBGA1071

1 2

R232 10K_04 02_5%

09/5/4 HP

1 2

R234 10K_04 02_5%@

1 2

R235 10K_04 02_5%

1 2

R236 10K_04 02_5%

1 2

R909 10K_04 02_5%

1 2

R238 10K_04 02_5%

@

1 2

R237 10K_04 02_5%

+3VS

+3VALW

VGATE

SLP_S3#

SLP_S4#

SLP_S5#

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

1 2

R876 10K_040 2_5%@

1 2

R877 10K_040 2_5%@

1 2

R878 10K_040 2_5%@

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

PMSYNCH

SLP_LAN#

1 2

R224 10K_04 02_5%

TP23

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI_CTX_ PRX_N0
FDI_CTX_ PRX_N1
FDI_CTX_ PRX_N2
FDI_CTX_ PRX_N3
FDI_CTX_ PRX_N4
FDI_CTX_ PRX_N5
FDI_CTX_ PRX_N6
FDI_CTX_ PRX_N7

FDI_CTX_ PRX_P0
FDI_CTX_ PRX_P1
FDI_CTX_ PRX_P2
FDI_CTX_ PRX_P3
FDI_CTX_ PRX_P4
FDI_CTX_ PRX_P5
FDI_CTX_ PRX_P6
FDI_CTX_ PRX_P7

FDI_ INT

FDI _FSY NC0

FDI _FSY NC1

FDI _LSY NC0

FDI _LSY NC1

PCIE_ WAKE#

PM_CL KRUN#

SUS_C LK

PM_SLP_LAN#

FDI_CTX_ PRX_N0 5
FDI_CTX_ PRX_N1 5
FDI_CTX_ PRX_N2 5
FDI_CTX_ PRX_N3 5
FDI_CTX_ PRX_N4 5
FDI_CTX_ PRX_N5 5
FDI_CTX_ PRX_N6 5
FDI_CTX_ PRX_N7 5

FDI_CTX_ PRX_P0 5
FDI_CTX_ PRX_P1 5
FDI_CTX_ PRX_P2 5
FDI_CTX_ PRX_P3 5
FDI_CTX_ PRX_P4 5
FDI_CTX_ PRX_P5 5
FDI_CTX_ PRX_P6 5
FDI_CTX_ PRX_P7 5

FDI_ INT 5

FDI _FSY NC0 5

FDI _FSY NC1 5

FDI _LSYN C0 5

FDI _LSYN C1 5

PCIE_ WAKE# 23 ,25

PM_CL KRUN# 27 ,29,30,31

8/31 HP

T130TPC12

T26 TPC12

SLP_S5# 28

SLP_S4# 33,40

SLP_S3# 25,29,3 2,33,35,3 8,39

PM_SLP_M# 29 ,32,33

H_PM _SYNC 4

PM_SLP_LAN# 29,33 ,40

09/3/9 HP

ENABLT20
ENAV DD20

INV_PW M20

SI1 NO6

09/3/9 HP

CRT _DDC_CL K18
CRT_D DC_DATA18

CRT _HSYN C18
CRT _VSYNC18

PV

DB2: No . 66

T125

PAD

T126

PAD

T127

PAD

T97

PAD

SI1 NO3 3

DAC _BLU
DAC_ GRN
DAC_ RED

1K_0402_0.5%

R301

150_0402_1% @

150_0402_1%

12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

2

Title

Size Docum ent Num ber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

LA-4902P

1

14 47Wedn esday, Decembe r 09, 20 09

0.3

5

PCI_ AD[0. .31]27

D D

PCI_C BE0#27
PCI_C BE1#27
PCI_C BE2#27
PCI_C BE3#27

PCI_R EQ2#27

C C

PCI_GN T2#27

PCI_ PIRQE#27
ODD_D ET#23
PCI_ PIRQG#27
ACCEL _INT#26

PCI_RS T#23, 27

PCI_ SERR#27, 29,31
PCI_ PERR#27

PCI _IRD Y#27
PCI_ PAR27
PCI_D EVSEL#27
PCI_F RAME#27

PCI_STOP #27
PCI_ TRDY#27

B B

A A

PLT_RST#4,12,21 ,23,25,31

PCI _PIRQE#

1 8

PCI_STO P#

2 7

PCI_ PIRQD #

3 6
4 5

PCI_R EQ2#

1 8

PCI_R EQ1#

2 7

PCI_F RAME#

3 6

PCI_ TRDY#

4 5

PCI _IR DY#

1 8

PCI _PERR#

2 7

PCI_D EVSEL#

3 6

PCI _SERR#

4 5

PCI_R EQ0#

1 8

PCI _PIRQB#

2 7

ODD_ DET#

3 6

PCI_R EQ3#

4 5

PCI_G NT3#

1 2

R282 1K_0402 _5%@

A16 swap ov eride Strap /Top-Block
Swap Overri de jumper

PCI_GNT3#

PCI _AD0
PCI _AD1
PCI _AD2
PCI _AD3
PCI _AD4
PCI _AD5
PCI _AD6
PCI _AD7
PCI _AD8
PCI _AD9
PCI_ AD10
PCI_ AD11
PCI_ AD12
PCI_ AD13
PCI_ AD14
PCI_ AD15
PCI_ AD16
PCI_ AD17
PCI_ AD18
PCI_ AD19
PCI_ AD20
PCI_ AD21
PCI_ AD22
PCI_ AD23
PCI_ AD24
PCI_ AD25
PCI_ AD26
PCI_ AD27
PCI_ AD28
PCI_ AD29
PCI_ AD30
PCI_ AD31

PCI _PIRQA#
PCI _PIRQB#
PCI_ PIRQC #
PCI_ PIRQD #

PCI_R EQ0#
PCI_R EQ1#
PCI_R EQ2#
PCI_R EQ3#

PCI_G NT0#

T112TPC12

MODEM_D ISABLE#

T113TPC12

PCI_G NT2#
PCI_G NT3#

PCI _PIRQE#
ODD_ DET#
PCI _PIRQG#
ACCEL _INT#

PCI _SERR#
PCI _PERR#

PCI _IR DY#

PCI_D EVSEL#
PCI_F RAME#

PCI_L OCK#

PCI_STO P#
PCI_ TRDY#

CLK_ PCI_KBC _R
CLK _PCI_FB_ R
CLK_PC I_TPM_R
CLK_P CI_1394_R
CLK_P CI_DB_P

RP28

8.2K_080 4_8P4R_5%
RP5

8.2K_080 4_8P4R_5%
RP6

8.2K_080 4_8P4R_5%
RP8

8.2K_080 4_8P4R_5%

Low=A16 swap
override/To p-Block
Swap Overri de enabled
High=Default

5

+3VS

H40
N34
C44
A38
C36

J34
A40
D45
E36
H48
E40
C40

M48
M45

F53

M40
M43

J36
K48
F40
C42
K46

M51

J52
K51

L34
F42

J40
G46
F44

M47

H36

J50
G42
H47
G34

G38
H51
B37
A44

F51
A46
B45

M53

F48
K45
F36
H53

B41
K53
A36
A48

K6

E44
E50

A42
H44
F46
C46

D49

D41
C48

M7

D5

N52
P53
P46
P51
P48

U4E

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCIRST#

SERR#
PERR#

IRDY#
PAR
DEVSEL#
FRAME#

PLOCK#

STOP#
TRDY#

PME#

PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

IBEXPEAK- M_FCBGA1071

PCI _PIRQA#

1 8

THER M_SCI#

2 7

PCI_ PIRQC #

3 6

PCI _PIRQG#

4 5

ACCEL _INT#

1 8

PCI_L OCK#

2 7
3 6
4 5

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVR AM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PCI

NV_WR#0_RE#
NV_WR#1_RE#

USB

CLK_P CI_SIO30

CLK_P CI_KBC29

CLK_P CI_DEBU G23

CLK_ PCI_DB31
CLK_ PCI_FB13
CLK_PCI_T PM31

CLK_P CI_139427

RP7

8.2K_08 04_8P4R_5%

RP9

8.2K_08 04_8P4R_5%

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

+3VS

4

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

@

1 2

AU2

R246 32.4_04 02_1%

AV7

AY8
AY5

AV11
BF5

USB20 _N0

H18

USB20_P 0

J18

USB20 _N1

A18

USB20_P 1

C18

USB20 _N2

N20

USB20_P 2

P20

USB20 _N3

J20

USB20_P 3

L20

USB20 _N4

F20

USB20_P 4

G20
A20
C20
M22
N22
B21
D21

USB20 _N8

H22

USB20_P 8

J22

USB20 _N9

E22

USB20_P 9

F22

USB20 _N10

A22

USB20_P 10

C22

USB20 _N11

G24

USB20_P 11

H24

USB20 _N12

L24

USB20_P 12

M24

USB20 _N13

A24

USB20_P 13

C24

USBR BIAS

B25

D25

Within
500 mils

USB_O C#0

N16

USB_O C#1

J16

USB_O C#2

F16

USB_O C#3

L16

USB_O C#4 USB_O C#1

E14

USB_O C#5

G16

USB_O C#6

F12

USB_O C#7

T15

C956 47P_0402_ 50V8J

C958 47P_0402_ 50V8J

C959 47P_0402_ 50V8J

C957 47P_0402_ 50V8J

1

1

1

1

@

@

@

@

2

2

2

2

8/31 HP

USB20 _N0 26
USB20_P0 26
USB20 _N1 26
USB20_P1 26
USB20 _N2 26
USB20_P2 26
USB20 _N3 26
USB20_P3 26
USB20 _N4 25
USB20_P4 25

USB20 _N8 26
USB20_P8 26
USB20 _N9 24
USB20_P9 24
USB20 _N10 31
USB20_P1 0 31
USB20 _N11 28
USB20_P1 1 28
USB20 _N12 20
USB20_P1 2 20
USB20 _N13 28
USB20_P1 3 28

1 2

R247 22.6_04 02_1%

R1026 47 _0402_5%

R248 22_0402_5%

R880 22_0402_5%

R251 22_0402_5%
R253 22_0402_5%
R258 22_0402_5%

R256 22_0402_5%

C961 47P_0402_ 50V8J

C960 47P_0402_ 50V8J

C962 47P_0402_ 50V8J

1

1

1

@

@

@

2

2

2

BUF_PLT_R ST#4

USB_O C#0 12
USB_O C#1 12
USB_O C#2 12
USB_O C#3 12
USB_O C#4 12
USB_O C#5 12

USB_O C#7 12

1 2

1 2

1 2

1 2
1 2
1 2

1 2

CONN

CONN

CONN

CONN

EXPRESS

Bluetooth

WWAN

Fingerpr int

DOCK

USB Ca mera

DOCK

SI1 NO6 7

09/2/5 HP

4

+3VS

7/2/2009 HP

SI1 NO2 4

09/4/10 HP

+3VALW

USB_O C#3

PCH_X DP_GPIO36

USB_O C#5
USB_O C#6
USB_O C#7

CLK_ PCI_KBC _R

CLK_P CI_DB_P
CLK _PCI_FB_ R
CLK_PC I_TPM_R

CLK_P CI_1394_R

1 2

R843 0_0402_ 5%

+3VS

5

U6

P

IN1

4

O

IN2

G

3

3

R239 10K_0402_5%

1 2

PCH_XD P_GPIO012

OCP#42

RUN SCI_EC #29

THERM_ SCI#4

PCH_ DDR_RS T4

LAN_ DIS#21 ,22

PCH_XDP _GPIO1612

ALS_EN#20

WWA N_DET#24

WW AN_TRANSMIT _OFF#24 ,25

PCH_XDP _GPIO2812

STP_PCI#

SATA_CLKR EQ#

PCH_XDP _GPIO3612

PCH_XDP _GPIO3712,20

DOC K_ID028

09/2/5 HP

DOC K_ID128

CLK_P CIE_LAN_ REQ#21

R485 10K_0402_5%

1 2

PCH_XDP _GPIO4912

WLAN _TRANSMIT_OF F#23

PCH_ NCTF617
PCH_ NCTF717

PCH_N CTF1917

PCH_N CTF2617

1 2

R968 0_0402_ 5%

1 2

R970 0_0402_ 5%

1 2

R971 0_0402_ 5%

1 2

R1073 0_0402_ 5%

1 2

R1074 0_0402_ 5%

1 2

R1990 0_0402_ 5%

SI1 NO4 5

09/4/27 HP

dele te R969

PLT_RST#

1

2

SN74A HC1G08D CKR_SC70-5@

3

PCH_X DP_GPIO0

RUN SCI_E C#

THER M_SCI#

GPIO8

GPIO15

PCH_X DP_GPIO16

ALS_EN#

WW AN_DET#

GPIO24

WW AN_TRANSM IT_OFF#

PCH_X DP_GPIO28

STP_PCI #

SATA_CLKR EQ#

PCH_X DP_GPIO36

PCH_X DP_GPIO37

DOC K_ID0

DOC K_ID1

CLK_P CIE_LAN _REQ#

GPIO48

PCH_X DP_GPIO49

WLAN _TRANSMIT_O FF#

BT_OFF 26

FPR_ OFF 31USB_O C#6 12
NPCI_ RST# 29 ,30

ISO_PR EP# 28
LED_L INK_LAN# _R 21,22
EXPRESS_ CD# 25

PCI_G NT0#

MODEM_D ISABLE#

PCI_GNT0#

0
0
1
1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

MEM_LED / GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK- M_FCBGA1071

R249 1K_0402_5%@

R254 1K_0402_5%@

Boot BIOS S trap

MODEM_DISAB LE# Boot BIOS Loc ation

0
1
0

2008/09/15 2009/12/31

1 2

1 2

LPC*
Reserved(NA ND)
PCI
SPI

GPIO

NCTF

RSVD

Compal Secret Data

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

CLKOUT_PCIE7P

PROCPWRGD

THRMTRIP#

INIT3_3V#

Deciphered Date

2

A20GATE

PECI

RCIN#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

TP24

AH45
AH46

AF48
AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

CLK_P CIE_LAN# _R

CLK_P CIE_LAN_ R

PCH_ PECI_ R

KB_RST#

H_THER MTRIP#_L

T29 T PC12

T30 T PC12

T31 T PC12

T32 T PC12

T33 T PC12

T34 T PC12

T35 T PC12

T36 T PC12

T37 T PC12

T38 T PC12

T39 T PC12

T40 T PC12

T41 T PC12

T42 T PC12

T43 T PC12

T44 T PC12

T45 T PC12

T46 T PC12

T47 T PC12

T48 T PC12

T49 T PC12

T50 T PC12

T51 T PC12

T52 T PC12

T53 T PC12

T54 T PC12

1

33_0402_5%
33_0402_5%

12
12

R218
R220

1 2

1 2

0_0402_5%

1 2

56_0402_5%

SI1 NO2 4

09/4/10 HP

SI1 NO4 5

09/4/27 HP

SI1 NO5 9

09/5/4 HP

09/2/5 HP

SI1 NO2 9

09/4/10 HP

SI1 NO3 1

Title

Size Docum ent Num ber R ev

Cus tom

LA-4902P

Dat e: Sheet o f

+3VS

R24210K_040 2_5%

R24454.9_0402_1 %

R245

NPCI_ RST#

SATA_CLKR EQ#

PCH_X DP_GPIO49

WW AN_DET#

ALS_EN#

RUN SCI_E C#

R243

12

GATEA20 29

CLK_C PU_BCLK# 4

CLK_C PU_BCLK 4

H_P ECI 4

KB_RST# 29

H_CP UPWR GD 4

H_THER MTRIP# 4

+VCCP

dele te R268

PCH_X DP_GPIO16

DOC K_ID0

DOC K_ID1

GPIO48

STP_PCI #

WLAN _TRANSMIT_O FF#

WW AN_TRANSM IT_OFF#

GPIO24

GPIO15

ISO_P REP#

CLK_P CIE_LAN _REQ#

USB_O C#0

USB_O C#2

USB_O C#4

EXPRESS_C D#

PCH_X DP_GPIO28

LED_L INK_LAN# _R

LAN_ DIS#

GPIO8

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

1

CLK_P CIE_LAN# 21

CLK_P CIE_LAN 21

R250 10K_0402_5%

1 2

R255 10K_0402_5%

1 2

R259 10K_0402_5%

1 2

R261 100K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

15 47Wedn esday, Decembe r 09, 20 09

R263 10K_0402_5%

R266 10K_0402_5%

R271 10K_0402_5%

R273 10K_0402_5%

R275 10K_0402_5%

R277 10K_0402_5%

R962 10K_0402_5%

R252 10K_0402_5%

R257 10K_0402_5%

R260 10K_0402_5%

R262 1K_0402_5%

R264 10K_0402_5%

R267 10K_0402_5%

R270 10K_0402_5%

R1117 10K _0402_5%

R959 10K_0402_5%

R960 10K_0402_5%

R1075 10K _0402_5%

R1083 10K _0402_5%

R961 10K_0402_5%

R844 0_0402_5%@

+3VS

+3VALW

+3VM_LAN

0.3