HP LA-3261P, Compaq 6910P Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Intel
Crestline_PM+ICH8-M core logic

3 3

IBT00 LA-3261P UMA

2007-03-28

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

REV:1A (MV2)

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA -3 26 1P U MA

E

1 55Wednesday, March 28, 2007

0.4

A

Compal confidential

File Name : LA-3261P

B

C

Chimay UMA

D

E

1 1

CRT & TV OUT

P16

LVDS Panel Interface

P17

Thermal Sensor
AD M1032ARMZ

P4

Fan c onn

P4

Intel Crestline MCH

SDV O

2 2

DVI (Docking)

P33

CH 7307 C

P16

DM I X4

PCI-E BUS

10/100/1000 LAN

Mini-Card

Intel 82566MM

P23

RJ 45/11 CONN

3 3

P24

LED

P30

CardBus Controller & PCMCIA conn

Ri coh R5C853 & R5C851

P25

Slot 0/Smart Card

1394 port

P28

6in1 Slot

PCI

daug hte r board

RTC CKT.

P19

Mo bile Merom

uFCPGA-478 CPU

H_ A#( 3.. 35)

H_ D#( 0..6 3)

FSB

667/800MH z 1.05V

FC BGA 1299

P7, 8, 9, 10, 11, 12

Intel ICH8-M

mB GA-676

P18, 19, 20, 21

SPI ROM & Debug port

16Mb*2 or 32Mb*1

P4, 5, 6

C- Link

SPI

LPC BUS

DDR2 667MHz 1. 8V

Dual Channel

USB2.0

Azalia

SATA Master

PATA Slave

P30

DDR2- SO-DIMM X2

BANK 0, 1, 2, 3

P13, 14

USB conn x2
(Docking)

FingerPrint er 2501B
USBx1

USB conn x3

BT Co nn

Mini-Card WWAN

P25P25

Audio CKT

AD1981HD

P26

SATA HDD Connector

P22

Multi-bay II Connector

P22

P33

P30

P28

P28

CK505

TSSOP- 64

Clock Generator
IC S 9LPR S355

P15

daug hte r board

MDC

P32

AMP & Audio Jack

MAX9710

P33

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN

P27

*LINE OUT

Power OK CKT.

P35

4 4

Power On/Off CKT.

P32

TPM1.2
SLB9635TT

P30

Touch P ad CON N.

SMSC KBC 1070

SMSC KBC 1021-NU

P31

Int.KBD

P32 P32

SMSC Super I/O

LPC47N217

COM1 LPT
( Docking ) ( Docking )

P33 P33

P29

*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

DC/DC Interface CKT.

P34

A

TrackPoint CONN.

B

P32

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA -3 26 1P U MA

E

2 55Tuesday, March 27, 2 007

0.4

A

Voltage Rails

power
plane

State

S0

S3/M1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

PCI Devices

EXTERNAL

CA RD B US & 139 4

DMA Channel
DM A0
DM A1
DM A2
DM A3
DM A4
DM A5
DM A6
DM A7

USB PORT#

O MEANS ON X MEANS OFF

+B

LDO3

LDO5

O

O

O

O

O

X

De st in at ion

0

1

2

3

4

5

6

7

8

9

Walk -up0 (R ight side)

Finge rprint

Reserv e

WWAN

Walk -up1 (Le ft Side)

Walk -up2 (Le ft Side)

Bluet ooth

Reserv e

Dockin g

Dockin g

+5VS

+3VS

+2.5VS

+1.8VS

+5VALW

+3VALW

O

O

O

O

X

+1.8V

+5V

+0.9V

+1.5VS

+1.25VS

+VGA_CORE

+CPU_CORE

+VCCP

O

O

X X

X

OO

X

X

X

X X X

ID SE L# RE Q/G NT# PI RQ

AD 22 2 C, D, E, G

Device
MODEM / LAN
ECP
FL OPP Y DISK
AUDIO
(Cascade)
Unused
Unused
Unused

+3VM

+1.05VM

+1.25VM

O

O

O

O

X

X

CLOCK

O

O

O

O

X

X

IRQ

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

De vic e

Syste m Timer

Keyboa rd

N/A

Seri al po rt (COM2),L AN/Modem

Seri al port (COM1)

Audio /VGA

Floppy

Para llel port

Syst em CM OS/Real-tim e clock

Micr osoft ACPI

N/A, Momem,LAN

Mass str orag e contr ol/ PCI sim ple communi cation cont rol

syna ctic PS2 port Gl idePAD

Nume ric Data Process

Prim ary I DE interfac e,HDD

Seco ndar y IDE innt erface,CD-R OM

Mobi le I ntel Crestline E xpress Chip set Family

Micr osof t UA A Bus Dri ver for Hig h Definitio n Audio

Inte l 82 801H (ICH8 Fa mily) PCI E xpress Root Port -27D0

Broa dcom NetXtrem e Gigabit E thernet

Inte l 82 801H (ICH8 Fa mily)PCI Ex press Root Port - 27D2

Broa dcom 80 2.11b/g WLA N

Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll

Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll

Rico h R5C 853 Cardbus Control

Rico h R5 C853 Integrates FlashMedia Control

Rico h R5 C853 Gemcore bas ed SmartCar d Control

Inte l 82 801H (ICH8 Fa mily)PCI Ex press Root Port - 27D6

Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll

Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll

Inte l 82 801H (ICH8 Fa mily)USB2 E nhanced Hos t Controll

Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll

SDA Stan dard Co mpliant SD Host Contro ller

HP M obil e Data Pro tection Sen sor

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA -3 26 1P U MA

3 55Tuesday, March 27, 2 007

0.4

5

D D

H_A#[ 3..16]7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_NMI19
H_SMI#19

12

R1255

56_0402_5%@

B

2

C

Q85
MMBT3904_SOT23

H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2

H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FER R#
H_IGNN E#

H_STPCLK#
H_INT R
H_NMI
H_SMI#

OCP# 20,44

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47

C C

B B

A A

H_A#[ 17..35]7

H_ADSTB#17

H_A20M#19

H_FER R#19

H_IGNN E#19

H_STPCLK#19
H_INT R19

+VCCP

H_PROCH OT# OCP#

E

3 1

@

JP12A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Mero m Ball-out Rev 1a

ADDR GROUP 0 ADDR GROUP 1

ICH

ADS#
BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

TH ERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

conn@

TDI

4

3

XDP Connector

H_ADS#H_A#3

H1

H_BNR #

E2

H_BPR I#

G5

H_DEF ER#

H5

H_D RDY#

F21

H_ DBSY#

E1

H_BR0#

F1

H_IER R#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_ TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCH OT#

D21

H_THERMDA_R

A24

H_THE RMDC_R

B25

H_THERMTRIP#

C7

CLK_CP U_BCLK

A22

CLK_CP U_BCLK#

A21

1113 Add res isto rs in ser ies with th e diode sig nals going to ADM1032.

For Mero m, R1798 and R1799 a re 0ohm
For Penr yn, R17 98 and R179 9 are 100oh m.

H_ADS# 7
H_BNR # 7

H_BPR I# 7

H_DEF ER# 7
H_D RDY# 7
H_D BSY# 7

H_BR0# 7

H_INIT# 19

H_LOCK# 7

H_RESET# 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

H_T RDY# 7

H_HIT# 7
H_HITM# 7

XDP_DBRESET# 20

R1798 0_0402_5%

1 2

R1799 0_0402_5%

1 2

R172

56_0402_5%

12

+VCCP

12

H_THERMDA
H_THERMDC

H_PROCH OT# 43

+VCCP

R410

68_0402_5%

H_THERMTRIP# 7,19

CLK_CP U_BCLK 15
CLK_CP U_BCLK# 15

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_PW RGOOD_R5

+VCCP +VCCP

0.1U_0402_16V4Z

1

C1099

2

2

layo ut n ote: Cha nge R237 to 649 ohm if using XTP to ITP adap ter

JP51

1

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

H_PW RGOOD_R
XDP_HOOK1

XDP_TCK

Thermal Sensor ADM1032ARMZ

3

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

conn@

1 2

2200P_0402_50V7K

+3VS

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAMTE_BSH-030-01-L-D-A

C273

0.1U_0402_16V4Z

H_THERMDA

C264

H_THERMDC

R228

1 2

10K_0402_5%

ITPCLK/HOOK4

ITPCLK#/HOOK5

RESET#/HOOK6

+3VS

2

1

THERM#

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

VCC_OBS_CD

DBR#/HOOK7

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

U16

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Addres s:100_1100

PWM Fan Control circuit

+3VS

FAN_PWM31

THERM#

1

INB

2

INA

XDP_DBRESET#_R

R243

1 2

04/ 10 no stuff

XDP_TDI

XDP_TMS

XDP_TDO

XDP_BPM#5

XDP_HOOK1

XDP_TRST#

XDP_TCK

CLK_CPU_XDP
CLK_CPU_XDP#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

R143 54.9_0402_1%

1 2

R236 54.9_0402_1%

1 2

R1670 54.9_0402_1%

1 2

R241 54.9_0402_1%

1 2

R1430 54.9_0402_1%@

1 2

R237 51_0402_1%

1 2

R239 54.9_0402_1%

1 2

1K_0402_1%

H_RESET#H_RESET#_R

R1431

1 2

XDP_DBRESET#XDP_DBRESET#_R

12

200_0402_1%

R1432

R1433 0_0402_5%

1 2

Plac e R1 431 withi n 200ps (~1 ") to CPU

R227

8

SCLK

7

SDATA

6

ALERT#

5

ICH_SM _CLK20,25

ICH_SM_DA20,25

0308 change desig n

5

U24

P

4

O

G

TC7SH00FU_ SSOP5

3

ICH_SM_CLK

ICH_SM_DA

THERM_SCI#

+5VS

1 2

ICH_SM_CLK
ICH_SM_DA

ACES_85204-03001

10K_0402_5%

1
2
3

1

THERM_SCI# 20

conn@

JP8

1
2

G1

3

G2

+3VS

1K_0402_5%@

+VCCP

CLK_CPU_XDP 15
CLK_CPU_XDP# 15

4
5

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA -3 26 1P U MA

1

4 55Tuesday, March 27, 2007

0.4

5

4

3

2

1

H_D #[0..15]7

D D

H_DSTBN#07
H_DSTBP#07

H_DIN V#07

H_D# [16..31]7

C C

H_DSTBN#17
H_DSTBP#17

H_DIN V#17

R1264 1K_0402_5%@

1 2

R1265 1K_0402_5%@

1 2

C1101 0.1U_0402_16V4Z@

1 2

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

T1

T2
T3

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DIN V#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DIN V#1 H_DIN V#3

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0 H_PW RGOOD
CPU_BSEL1
CPU_BSEL2

JP12B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Mero m Ball-out Rev 1 a

conn@

DATA GRP 1

MISC

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DIN V#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPW R#

H_CPUSLP #
H_PSI#

R1436

1K_0402_5%

H_PW RGOOD_R

12

layo ut n ote: Rou te TES T3 & TEST5 traces on g round refer enced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

0 1

0

1

CPU_BSEL0

1

0

H_D# [32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DIN V#2 7
H_D# [48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DIN V#3 7

H_DPRSTP# 7,19,43

H_DPSLP# 19
H_DPW R# 7
H_PW RGOOD 19

H_CPUSLP # 7
H_PSI# 43

H_PW RGOOD_R 4

12

R355

R1220

27.4_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

12

R245

R244

54.9_0402_1%

27.4_0402_1%

12

12

+VCC_C ORE +VCC_C ORE

JP12C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Mero m Ball-out Rev 1a

conn@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R1434 0_0402_5%

G21
V6

R1435 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENS E

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

+VCCP

12
12

C1100

CPU_V ID0 43
CPU_V ID1 43
CPU_V ID2 43
CPU_V ID3 43
CPU_V ID4 43
CPU_V ID5 43
CPU_V ID6 43

VCCSENSE 43

VSSSENSE 4 3

1

+

330U_D2E_2.5VM _R7

2

0228 change value

1

1

C531

C520

2

2

10U_0805_6.3V6M

Near pin B26

+1.5VS

0.01U_0402_16V7K

The trace width/space/other is
20/7/25.

+VCC_ CORE

1 2

1 2

R1269
100_0402_1%

R1270
100_0402_1%

VCCSENS E

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R1268
1K_0402_1%

12

R1271
2K_0402_1%

Close to CPU pin AD26
within 500mils.

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA -3 26 1P U MA

1

5 55Tuesday, March 27, 2007

0.4

5

Place these capac itors on L8

D D

JP12D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

C C

B B

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Mero m Ball-out Rev 1a

conn@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

(Nort h side ,Secon dary L ayer)

Place these capac itors on L8
(Nort h side ,Secon dary L ayer)

Place these capac itors on L8
(Sort h side ,Secon dary L ayer)

Place these capac itors on L8
(Sort h side ,Secon dary L ayer)

0314 change to mo unt

330U_D2E_2.5VM _R7

+VCCP

1

C940

0.1U_0402_10V6K

2

4

+VCC_ CORE

1

+

C931

2

+VCC_ CORE

1

C899

10U_0805_6.3V6M

2

+VCC_ CORE

1

C907

10U_0805_6.3V6M

2

+VCC_ CORE

1

C915

10U_0805_6.3V6M

2

+VCC_ CORE

1

C923

10U_0805_6.3V6M

2

Near CPU CORE regulator

330U_D2E_2.5VM_R7

1

+

C932

C933

2

330U_D2E_2.5VM _R7

1

C941

0.1U_0402_10V6K

2

1

C900

10U_0805_6.3V6M

2

1

C908

10U_0805_6.3V6M

2

1

C916

10U_0805_6.3V6M

2

1

C924

10U_0805_6.3V6M

2

1

+

C935

2

330U_D2E_2.5VM_R7

1

C942

0.1U_0402_10V6K

2

1

+

2

1

C901

10U_0805_6.3V6M

2

1

C909

10U_0805_6.3V6M

2

1

C917

10U_0805_6.3V6M

2

1

C925

10U_0805_6.3V6M

2

330U_D2E_2.5VM _R7

1

+

C937

C936

2

330U_D2E_2.5VM _R7

1

C943

0.1U_0402_10V6K

2

3

1

C902

10U_0805_6.3V6M

2

1

C910

10U_0805_6.3V6M

2

1

C918

10U_0805_6.3V6M

2

1

C926

10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

1

+

+

C934

@

2

820U_E9_2_5V_M_R7

2

1

C944

0.1U_0402_10V6K

2

1

C903

10U_0805_6.3V6M

2

1

C911

10U_0805_6.3V6M

2

1

C919

10U_0805_6.3V6M

2

1

C927

10U_0805_6.3V6M

2

Plac e these inside
sock et cavity o n L8
(North side
Seco ndary)

1

C945

0.1U_0402_10V6K

2

1

C904

10U_0805_6.3V6M

2

1

C912

10U_0805_6.3V6M

2

1

C920

10U_0805_6.3V6M

2

1

C928

10U_0805_6.3V6M

2

2

1

C905

10U_0805_6.3V6M

2

1

C913

10U_0805_6.3V6M

2

1

C921

10U_0805_6.3V6M

2

1

C929

10U_0805_6.3V6M

2

1

C906

10U_0805_6.3V6M

2

1

C914

10U_0805_6.3V6M

2

1

C922

10U_0805_6.3V6M

2

1

C930

10U_0805_6.3V6M

2

1

Mid Frequence Decoupling

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA -3 26 1P U MA

1

6 55Tuesday, March 27, 2007

0.4

5

W10

AD12

AC14
AD11
AC11

AG3

AJ14

AE11
AH12

AH13

M10
N12

AE3
AD9
AC9
AC7

AB2
AD7
AB1

AC6
AE2
AC5

AH8

AE9

AH5

AE7

AE5

AH2

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7
Y9

P4
W3
N1

Y3

AJ9

AJ5

AJ6

AJ7
AJ2

AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U15A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRES TLINE_1p0

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_D #[0..63]5

D D

C C

+VCCP

12

12

R1197

R1196

54.9_0402_1%

54.9_0402_1%

H_RESET#4

H_CPUSLP #5

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SW NG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP #

H_VRE F

layo ut note:

Rout e H_ SCOM P an d H_ SCOMP # with trac e width, sp acing and i mpedance (5 5 ohm) same as FSB dat a traces

Layout Note:
H_RCOM P / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

1K_0402_1%

R1208

0.1U_0402_16V4Z

H_VRE F

12

A A

1

C60

2

R1212

2K_0402_1%

H_RCOMP

12

R1199

24.9_0402_1%

12

R1206

221_0603_1%

H_SW NG

12

1

R1210

C896

2

100_0402_1%

0.1U_0402_16V4Z

Near B3 pinwith in 100 mils from N B

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

PM_PWROK20,31,45

V_DDR _MCH_REF13,14,42

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR #
H_BPR I#
H_BR0#
H_DEF ER#
H_ DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_D RDY#
H_HIT#
H_HITM#
H_LOCK#
H_ TRDY#

H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

VGATE20,31

Layout Note:
V_DDR_MCH_REF
trace width and
spacin g is 20/20.

H_A#[ 3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPR I# 4
H_BR0# 4
H_DEF ER# 4
H_DB SY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPW R# 5
H_D RDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TR DY# 4

H_DIN V#0 5
H_DIN V#1 5
H_DIN V#2 5
H_DIN V#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

R1483 0_0402_5%@

12

12

R1484 0_0402_5%

V_DDR _MCH_REF

1

C895

2

0.1U_0402_16V4Z

3

2.2U_0 603_6.3V4Z

2.2U_0 603_6.3V4Z

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_B DMI_TXN0

MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215

PM_BMBUSY#20

0612 a dd

1128 Install R1739

1226 Add C

0309 add

+1.8V

12

12

SMRCOMP_VOH

SMRCOMP_VOL

H_THERMTRIP#4,19

PM_POK_R

R1201

1K_0402_1%@

R1204

1K_0402_1%

@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

2

2

12

C1103

C1105

CFG59
CFG6
CFG79
CFG89
CFG99

R1437

1

1K_0402_1%

0.01U_0402_25V7K

12

R31

3.01K_0402_1%

NA le ad free

12

R1438

1

1K_0402_1%

2

0612 a dd

0.01U_0402_25V7K

DDR_A_MA1413
DDR_B_MA1414

+3VS

12

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5
CFG6
CFG7

CFG9
CFG10
CFG11
CFG12
CFG13

CFG16

CFG18
CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
THERMTRIP#

12

DPRSLPVR

C1370

R1446

100_0402_5%

1

C1102

1

2

C1104

R1439

10K_0402_5%

R1440

10K_0402_5%

R1441

<>

10K_0402_5%

CFG10
CFG11
CFG129
CFG139

CFG169

CFG18
CFG199
CFG209

H_DPRSTP#5,19,43
PM_EXTTS#013
PM_EXTTS#114

R1739 0_0402_5%

DPRSLPVR20,43

2006/02/13 2006/03/10

U15B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

1

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

2

BL2

NC_7

0.1U_0402_16V4Z

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRES TLINE_1p0

PLT_RST#PLT_RST#_R

12

Compal Secret Data

Deciphered Date

2

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0

DDR M UXIN GCLK

SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2

CFGRS VD

PM

DMI_TXN_3

DMI_TXP_0
DMI_TXP_1

DMI

DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

GRA PHI CS V ID

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

ME

NC

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MI SC

PLT_RST# 16,18 ,22,30

083 0 A dd pu ll- up an d pul l-dow n re sisto r.

2

M_CLK_DD R0

AV29

M_CLK_DD R1

BB23

M_CLK_DD R2

BA25

M_CLK_DD R3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE 0_DIMMA

BE29

DDR_CKE 1_DIMMA

AY32

DDR_CKE 2_DIMMB

BD39

DDR_CKE 3_DIMMB

BG37

DDR_C S0_DIMMA#

BG20

DDR_C S1_DIMMA#

BK16

DDR_C S2_DIMMB#

BG16

DDR_C S3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31

AR49

V_DDR _MCH_REF

AW4

CLK_M CH_DREFCLK

B42

CLK_M CH_DREFCLK#

C42

MCH_ SSCDREFCLK

H48

MCH_ SSCDREFCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

DFGT_ VID_0

E35

DFGT_ VID_1

A39

DFGT_ VID_2

C38

DFGT_ VID_3

B39

DFGT_VR_E N

E36

CL_CLK0

AM49

CL_CLK

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VRE F CL_VRE F

AM50

062 1 a dd CL K a nd DA T fo r DVI

SDVO_SCLK

H35

SDVO_SDAT

K36

CLKREQ#_B

G39

MCH _ICH_SYNC #

G40

A37

TEST_1

R32

TEST_2

12

R1444

20K_0402_5%

12

R1445

0_0402_5%

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Doc ument Number Re v

Cus tom

LA -3 26 1P U MA

Date: Sheet of

1

For Crestli ne: 20ohm
For Calero: 80.6ohm

M_CLK_DD R0 13
M_CLK_DD R1 13
M_CLK_DD R2 14
M_CLK_DD R3 14

M_CLK_DD R#0 13
M_CLK_DD R#1 13
M_CLK_DD R#2 14
M_CLK_DD R#3 14

DDR_CKE 0_DIMMA 13
DDR_CKE 1_DIMMA 13
DDR_CKE 2_DIMMB 14
DDR_CKE 3_DIMMB 14

DDR_CS0_D IMMA# 13
DDR_CS1_D IMMA# 13
DDR_CS2_D IMMB# 14
DDR_CS3_D IMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14

DFGT_ VID_0
DFGT_ VID_1
DFGT_ VID_3

R1786

M_ODT3 14

CLK_M CH_DREFCLK 15

CLK_M CH_DREFCLK# 1 5

MCH_ SSCDREFCLK 1 5

MCH_ SSCDREFCLK# 15

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

DMI_TXN0 20
DMI_TXN1 20
DMI_TXN2 20
DMI_TXN3 20

DMI_TXP0 20
DMI_TXP1 20
DMI_TXP2 20
DMI_TXP3 20

DMI_RXN0 20
DMI_RXN1 20
DMI_RXN2 20
DMI_RXN3 20

DMI_RXP0 20
DMI_RXP1 20
DMI_RXP2 20
DMI_RXP3 20

DFGT_ VID_0 45
DFGT_ VID_1 45
DFGT_ VID_2 45
DFGT_ VID_3 45
DFGT_VR_E N 45

CL_CLK0 20
CL_DATA0 20
M_PWROK 20,35
CL_RST# 20

0.1U_0402_16V4Z

SDVO_SCLK 16
SDVO_SDAT 16+VCCP

CLKREQ#_B 15
MCH _ICH_SYNC # 20

12

22K_0402_5%

20_0402_1%

R1194

R1195 20_0402_1%

C1106

+1.25VM_AXD

1

2

12
12

12

R1442

1K_0402_1%

12

R1443
392_0402_1%

04/ 10 ch ange size

+3VS

12

12

22K_0402_5%

R1787

22K_0402_5%

R1789

R1788

Compal Electronics, Inc.

7 55Tuesday, March 27, 2 007

1

+1.8V

12

22K_0402_5%

DFGT_ VID_2

0.4

5

D D

DDR_ A_D[0..63 ]13

C C

B B

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8

DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27
DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

AR43

AW44

BA45

AY46
AR41
AR45

AT42

AW47

BB45

BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40

BF44
BH45
BG40

BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38

AT38
AV13

AT13

AW11

AV11
AU15

AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8

AN10

AT9
AN9
AM9

AN11

U15D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRES TLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS 0

BB19
BK19
BF29

BL17

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS 1
DDR_A_BS 2

DDR_A _CAS#

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2

DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7
DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2
DDR_A _DQS#3
DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A _RAS#
SA_RCVEN #

DDR_A_W E#

DDR_A_BS 0 13
DDR_A_BS 1 13
DDR_A_BS 2 13

DDR_A _CAS# 13 DDR_B _CAS# 14
DDR_A _DM[0..7] 13

DDR_ A_DQS[0.. 7] 13

DDR_A _DQS#[0.. 7] 13

DDR_A _MA[0..13] 13

DDR_A _RAS# 13

T5

DDR_A_W E# 13

3

DDR_ B_D[0..63 ]14

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8

DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18DDR_A _DQS3
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41

DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49
BF50
BF49
BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK5

BK9

BK10

BH5
BG1
BC2
BK3
BE4
BD3

BA3
BB3
AR1

AU2

BL9

BL5

BJ8
BJ6
BF4

BJ2

AT3
AY2
AY3

AT2

2

U15E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRES TLINE_1p0

1

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS 1
DDR_B_BS 2

DDR_B _CAS#

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6

DDR_B _DQS7
DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B _D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B _RAS#

SB_RCVEN #

DDR_B_W E#

DDR_B _RAS# 14

T4

DDR_B_W E# 14

DDR_B_BS 0 14
DDR_B_BS 1 14
DDR_B_BS 2 14

DDR_B _DM[0..7] 14

DDR_ B_DQS[0.. 7] 14

DDR_B _DQS#[0.. 7] 14

DDR_B _MA[0..13] 14

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA -3 26 1P U MA

8 55Tuesday, March 27, 2 007

1

0.4

5

For Crestli ne:2.4kohm
For Calero: 1.5Kohm

+3VS

M_COMP
M_LUMA
M_CRMA

R175

M_BLUE
M_GREEN
M_RED

R180

BLON_PWM
ENABLT

DDC2_ CLK
DDC2_DAT A

ENAVDD

2.4K_0402_1%

R1447

TXCLK_L­TXCLK_L+
TXCLK_U­TXCLK_U+

TXOUT_L0­TXOUT_L1­TXOUT_L2-

TXOUT_L0+
TXOUT_L1+
TXOUT_L2+

TXOUT_U0­TXOUT_U1­TXOUT_U2-

TXOUT_U0+
TXOUT_U1+
TXOUT_U2+

75_0402_1%

12

R94

12

75_0402_1%

BLON_PWM17

ENABLT17

DDC2_ CLK17
DDC2_DAT A17

ENAVDD17

D D

TXCLK_L-17
TXCLK_L+17
TXCLK_U-17
TXCLK_U+17

TXOUT_L0-17
TXOUT_L1-17
TXOUT_L2-17

TXOUT_L0+17
TXOUT_L1+17
TXOUT_L2+17

TXOUT_U0-17
TXOUT_U1-17
TXOUT_U2-17

TXOUT_U0+17
TXOUT_U1+17
TXOUT_U2+17

M_COMP
M_LUMA

0622 change value

C C

M_CRMA

M_BLUE

M_GREEN

M_RED

0314 change desig n

+3VS

0821

1013 change value

DDC1_ CLK16

DDC1_DAT A16

M_HS YNC1 6

M_VSYNC16

DDC1_ CLK
DDC1_DAT A
M_H SYNC

M_VSYNC

R165

R166

0821

B B

+3VS

1013 change value

2.2K_0402_5%

2.2K_0402_5%

DDC2_ CLK
DDC2_DAT A

R92
R158

1 2
1 2

TV-Out Termination/EMI Filter

M_COMP

M_LUMA

A A

M_COMP

M_LUMA

M_CRMA

1

2

C238

5.6P_0402_50V8D

C7

5.6P_0402_50V8D

1

1

2

2

0314 add

R95 10K_0402_5%

1 2

R160 10K_0402_5%

1 2

12

75_0402_1%

75_0402_1%

12

12

R177

R176

2.2K_0402_5%

1 2

75_0402_1%

1 2

30.1_0402_1%

1 2

30.1_0402_1%

L38

1 2

CHB1608U301_ 0603

L37

1 2

CHB1608U301_ 0603

L17

1 2

CHB1608U301_ 0603

C251

5.6P_0402_50V8D

0314 add

75_0402_1%

12

12

R182

R181

HS YNC

VSYN C

1.15K_0402_1%

For Crestli ne:1.3kohm
For Calero: 255ohm

5.6P_0402_50V8D

U15C

J40

H39

E39

E40
C37
D35

K40

L41

L43
N41
N40
D46
C45
D44

E42

G51

E51

F49

G50

E50

F48

G44

B47

B45

E44

A47

A45

E27
G27

K27

F27

J27

L27

M35

P33

H32
G32

K29

J29
F29
E29

K33

G35

F33

C32

E33

12

R1449

CRES TLINE_1p0

Pl a c e c l o

Pl a c e c l o s e t o U 15

Pl a c e c l oPl ace c lo

1

1

2

2

C243

C8

5.6P_0402_50V8D

Note: C RT / TV-out s hould rout e to JP30 fir st then to the JP1 & JP2 on system side.

5

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

1

C253

2

5.6P_0402_50V8D

4

LVDS

TV VGA

se to U1 5

se to U1 5s e t o U 15

COMP 16,33

LUMA 16,33

CRMA 16,33

0314 change desig n

4

PCI-EXPRESS GRAPHICS

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

3

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

PEGCOMP

PEG_RXP1

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3

R1176

24.9_0402_1%

1 2

PEG_RXN1

C1058 0.1U_0402_16V4Z

1 2

C1059 0.1U_0402_16V4Z

1 2

C1060 0.1U_0402_16V4Z

1 2

C1061 0.1U_0402_16V4Z

1 2

C1062 0.1U_0402_16V4Z
C1063 0.1U_0402_16V4Z
C1066 0.1U_0402_16V4Z
C1067 0.1U_0402_16V4Z

+VCCP

1 2
1 2
1 2
1 2

0809 Ad d M AX9511

PEG_RXN1 16

PEG_RXP1 16

1013 Re mov e MAX9511

CRT Termination/EMI Filter

M_RED

M_GREEN

M_BLUEM_CRMA

1

C194

@

1

2

2

10P_0402_50V8J

10P_0402_50V8J

C240

@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L28

1 2

HLC06 03CSCC39NJT_0603

L35

1 2

HLC06 03CSCC39NJT_0603

L27

1 2

HLC06 03CSCC39NJT_0603

1

C233

@

2

10P_0402_50V8J

3

C_RED _L

C_GRN _L

C_BLU_L

1

C193

22P_0402_50V8J

2

0314 change desig n

2006/02/13 2006/03/10

PE GC OMP tr ace w idth
and sp acing is 2 0/25 mils .

SDVOB_R- 16
SDVOB_G- 16
SDVOB_B- 16
SDVOB_CLK- 16

SDVOB_R+ 16
SDVOB_G+ 16
SDVOB_B+ 16
SDVOB_CLK+ 16

Pl a c e C

Pl a c e C lo sed to U1 5

Pl a c e CPl ace C

L31

1 2

HLC06 03CSCCR11JT_0603

L34

1 2

HLC06 03CSCCR11JT_0603

L26

1 2

HLC06 03CSCCR11JT_0603

1

1

C237

2

2

22P_0402_50V8J

C232

22P_0402_50V8J

@

Compal Secret Data

Deciphered Date

2

lo sed to U1 5

lo sed to U1 5lo sed to U1 5

1

C195

1

2

2

10P_0402_50V8J

10P_0402_50V8J

C244

@

2

10P_0402_50V8J

@

CFG[2:0] FSB Freq select

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

RED

GREEN

BLUE

1

2

C245

RED 33

GREEN 33

BLUE 33

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet

1

Strap Pin Table

010 = FSB 800MHz

011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

*

Reserved

0 = Reserved

1 = Mobile CPU

*

0 = Normal mode

1 = Low Power mode

*

0 = Reverse Lane

1 = Normal Operation

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present

1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R1151 4.02K_0402_1%@

CFG57

CFG77

CFG87

CFG97

CFG127

CFG137

CFG167

1 2

R1152 4.02K_0402_1%@

1 2

R1451 4.02K_0402_1%@

1 2

R1153 4.02K_0402_1%@

1 2

R1155 4.02K_0402_1%@

1 2

R1156 4.02K_0402_1%@

1 2

R1157 4.02K_0402_1%@

1 2

CFG[17 :3] ha ve internal pull up

CFG[19 :18] h ave internal pull down

R1159 4.02K_0402_1%@

CFG197

CFG207

CFG5

1 2

R1160 4.02K_0402_1%@

1 2

J37

2 1

PAD-N O SHORT 2 x2m

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA -3 26 1P U MA

9 55Tuesday, March 27, 2 007

1

*

*

*

+3VS

0.4

of

5

+3VS_DAC_BG

0.022U_0402_16V7K

D D

+3VS_DAC_CRT

0.022U_0402_16V7K

+1.25VM

C C

1

C1108

2

1

C1113

2

MBK1608102Y ZF 0603

22U_0805_6.3V

0.1U_0402 _16V4Z

C1375

1

1

C1109

2

2

0621 Chan ge R to BLM18PG1 SN1D

BLM18PG181SN1D_0603

R1456

0.1U_0402_16V4Z

1

C1114

2

+3VS

1

+

C1126

150U_D_6.3V M

R1462

0_0603_5%

0316 add

2

+1.25VM_A_SM_CK

12

R1453

12

R1459

0_0603_5%

0.1U_0402_16V 4Z

R1461

1 2

0_0805_5%

C1127

22U_0805_6.3VAM

12

1U_0402_6 .3V4Z

C1226

1

2

0317 c hange value

+3VS

+3VS

+1.8V_TXLVDS

+3VS_PEG_BG

12

C1121

0317 c hange value

1

4.7U_0805_10 V4Z

2

22U_0805_6.3VAM

C1130

1

2

1116 Change to BLM18PG181SN1D_0603

+3VS_TVDACC

B B

0.022U_0402_16V7K

C1144

+3VS_TVDACA

0.022U_0402_16V7K

C1148

A A

+3VS_TVDACB

0.022U_0402_16V7K

C1152

1

C1145

2

1

C1149

2

1

C1153

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

BLM18PG181SN1D_0603

0.1U_0402 _16V4Z

1

2

5

R1468

R1472

R1473

12

12

12

+3VS

1

2

C1131

+3VS

+3VS

+3VS

R1452

0_0603_5%

+1.25VM_A_SM

C1128

1U_0603_10V4Z

1

2

+1.25VS_PEGPLL

VCC SYNC

12

1

C1107

2

+3VS_DA C_CRT

+1.25VS_DPLLA

+1.25VS_DPLLB

+1.25VM_HPLL

+1.25VM_MPLL

1000P_0402_50V7K

C1118

+1.25VS_PEGPLL

1

2

1U_0603_10V4Z

0.1U_0402 _16V4Z

C1132

1

2

+1.5VS_TV DAC

+1.5VS_Q DAC

+1.25VM_HPLL

+1.8V_LVDS

+1.5VS_QDA C

0.022U_0402_16V7K

10U_0805_10V4Z

0.1U_0402 _16V4Z

+3VS_DAC_BG

1

2

20 mils

1

C1129

2

+3VS_TVDACA

+3VS_TVDACB

+3VS_TVDACC

1

1

C1147

C1146

2

2

0119 Add C1374
20070301 Install C1374

+1.8V_LVDS

1U_0603_10V4Z

C1151

C1150

1

2

4

U15 H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE _1p0

1107 Change to 100 ohm

R1471

1

C1374

+

2

R1474

0_0603_5%

220U_D2_4VM

100_0603_1%

12

4

0.1U_0402 _16V4Z

1

2

12

+1.8V

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

+1.5VS

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

40 mils

1000P_0402_50V7K

1

C1269

2

3

+VCCP

330U_D2E_2. 5VM_R7

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

+1.8V_TXLVDS

1

220U_D2_4VM_R15

+

2

C1141

C1285

+1.25VM_AXD

0.47U_0603_10V7K

1

2

R1476

0_0603_5%

C830

C849

1U_0603_10V4Z

1

2

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

20mils

0.47U_0603_10V7K

C1142

1

2

12

1

+

2

1

2

C1143

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4.7U_0805_10V4Z

1

C838

2

0316 add

0.47U_0603_10V7K

C836

C1119

C1120

1

2

+3VS_HV

C1136

0.47U_0603_10V7K

1

2

+1.8V

2.2U_0805 _16V4Z

4.7U_0805 _10V4Z

1

1

C837

2

2

R1671

1 2

10U_0805_10V4Z

+1.25VM

0_0805_5%

0.1U_0402 _16V4Z

1

2

2006/02/13 2006/03/10

Compal Secret Data

+1.25VS_DPLLB

0.1U_0402_16V4Z

+1.25VS_DMI

+1.25VS_PEGPLL

+1.25VS_DP LLA

220U_D2_4VM

1

C1227

+

2

Deciphered Date

22U_0805_6.3VAM

C1110

1

2

1 2

0.1U_0402 _16V4Z

C1117

1

2

0.1U_0402 _16V4Z

C1122

1

2

C1133

1

2

0.1U_0402_16V 4Z

+VCC_PEG

220U_D2_4VM

1

C1137

+

2

2

R1454

1 2

10U_FLC-453232-1 00K_0.25A_10%

1

C1231

2

+1.25VS

R1457

0_0603_5%

BLM18PG121SN1D_0 603

10U_0805_10V4Z

C1123

1

2

10U_0805_10V4Z

C1276

1

2

C1138

1

2

2

+1.25VS

0619 c hange

+1.25VS

L77

12

R1463

1 2

10U_FLC-453232-1 00K_0.25A_10%

0316 add

10U_0805_10V4Z

04/ 10 stu ff

R1465

0_0805_5%

R1467

@

0_0805_5%

+1.25VS

12

12

04/ 10 no stu ff

2 1

+VCCP

CH751H-40PT_S OD323-2

+3VS

1

+V1.25VS_AXF

0619 c hange value

+VCCP

+1.25VS

D12

Title

Size Documen t Number Re v

Cust om

Date : Sheet of

+1.8V_SM_CK

10U_0603_6.3V6M

1

C1230

2

+1.5VS_TVDAC

+1.25VM_HPLL

C1134

0.1U_0402_16 V4Z

+1.25VM_MPLL

C1139

0.1U_0402_16 V4Z

+VCCP_ D

R1469

10_0402_5%

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

LA -3 26 1P U MA

1U_0603_10V4Z

10U_0805_10V4Z

C1112

C1111

1

1

2

2

1 2

0.1U_0402 _16V4Z

10U_0603_6.3V6M

1

C1115

2

0.022U_0402_16V7K

1

C1124

2

1

2

1

2

12

0.1U_0402_16V4Z

1

C1125

2

MBK2012121YZF _0805

1

C1135

10U_0805_10V4Z

2

MBK2012121YZF _0805

1

C1140

10U_0805_10V4Z

2

R1470

0_0402_5%

1

C1116

1

2

1 2

R1464

R1466

12

0_0805_5%

0_0805_5%

1 2

0_0603_5%

R1458

R1460

+1.25VM

12

+1.25VM

12

+3VS_HV

10 55Tuesd ay, March 27, 2007

+1.25VS

R1455

+1.8V

+1.5VS

0.4

5

4

3

2

1

+VCCP

D D

22U_0805_6.3VAM

220U_D2_4VM_R15

1

C806

+

2

0317 change value

C C

0.22U_0402_10V4 Z

0.22U_0402_10V4 Z

C803

C796

1

2

1

1

2

2

+1.05VM

10U_0805_10V4Z

04/ 10 mo nit or N B cra ck

B B

0.22U_0402_10V4 Z

C1158

1

2

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1159

1

1

2

2

+3VS

100K_0402_5%

MCHGN D4

Q123

@

RHU002N06_S OT323

0.22U_0402_10V4 Z

C1157

1

2

+3VS

A A

100K_0402_5%

R1701

@

MCHGN D6

Q118

@

RHU002N06_S OT323

CRAC K_GPIO28

13

D

1 2

2

G

S

+VCCP

0.1U_0402_16V4Z

C797

C798

1

2

10U_0805_10V4Z

C1154

C1155

1

1

2

2

0.1U_0402_16V4Z

C1160

C1161

1

2

04/ 10 mo nit or N B cra ck
101 3 n o insta ll
121 3 i nsta ll
012 9 i nsta ll
200 702 27 No inst all 200 702 28 Ch ange to +3VL

CRAC K_GPIO28

R1711

@

13

D

1 2

2

G

S

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36

AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28

AM26
AM28
AM29
AM31
AM32
AM33

AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34

T35
U29
U31
U32
U33
U35
U36

V32

V33

V36

V37

U15F

CRES TLINE_1p0

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

+3VS

1 2

100K_0402_5%

MCHGN D2

Q121

@

RHU002N06_S OT323

VCC NCTF

POWER

VCC AXM NCTF

R1709

@

CRAC K_GPIO28

13

D

2

G

S

4

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

100K_0402_5%

R1703

@

MCHGN D5

RHU002N06_S OT323

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

MCHGN D1
MCHGN D2
MCHGN D3
MCHGN D4
MCHGN D5
MCHGN D6

+3VS

Q119

@

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

R112

1 2

R132

1 2

R133

1 2

R122

1 2

R113

1 2

R111

1 2

0314 add

101 3 i ns tal l R 111 ,R113 ,R122 ,R13 2
121 3 N o- ins tal l R 111, R113 ,R122 ,R132
012 9 N o- ins tal l R 111, R113 ,R122 ,R132
200 702 27 In sta ll R111 ,R11 3,R12 2,R13 2

+3VL

R1702

CRAC K_GPIO28

1 2
13

D

1 2

100K_0402_5%

2

G

S

R1475

1 2

0_0603_5%

330U_D2E_2.5VM_R9

+1.8V

+1.05VM

1

C1286

C1175

1U_0603_10V4Z

Secur ity Classification

2

330U_D2E_2.5VM _R9

0316 change value

CRAC K_GPIO28 21,31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

22U_0805_6.3VAM

1

+

C808

2

0317 change value

10U_0805_10V4Z

1

1

+

C812

2

C811

2

10U_0805_10V4Z

2006/02/13 2006/03/10

C809

1

2

22U_0805_6.3VAM

1

2

0.1U_0402_16V4Z

1

C1156

2

0.01U_0402_16V7K

C794

C810

2

1

VCCGFX

1

2

Compal Secret Data

Deciphered Date

AT35

AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29

AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U15G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

CRES TLINE_1p0

2

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

VCCGFX

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

0.1U_0402_16V4Z

C1287

1

2

C1162 0.1 U_0402_16V4Z

C1163 0.1 U_0402_16V4Z

1

1

2

2

C1288

1

2

0.22U_0402_10V4 Z

C795 0.22U_060 3_10V7K

C1318 0.22U_0603_10V7K

1

1

2

2

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

LA -3 26 1P U MA

1

4.7U_0603_6.3V6M

1

C1176

2

0316 add

C814 1U_0 603_10V4Z

C1164 0.4 7U_0402_6.3V6K

1

1

1

2

2

2

11 55Tuesday, M arch 27, 2007

C813 1U_0 603_10V4Z

0.4

5

U15I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23
AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50

AE10
AE14

AF20
AF23
AF24
AF31

AG38
AG43
AG47
AG50

AH40
AH41

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW1

AW12
AW16

AC3

AD1

AD3

AD5

AD8

AE6

AG2

AH3

AH7
AH9

AL1

AN1

AN5
AN7
AP4

AR2

AR7

AU1

AU3

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRES TLINE_1p0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U15J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRES TLINE_1p0

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA -3 26 1P U MA

1

12 55Tuesday, M arch 27, 2007

0.4

5

DDR_A _DQS#[0.. 7]8

DDR_ A_D[0..63 ]8

DDR_A _DM[0..7]8

DDR_A _DQS[0..7 ]8

DDR_A _MA[0..14]7,8

D D

Lay out No te:
Pl ac e near JP 34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C458

C498

1

1

2

2

C C

B B

A A

Lay out No te:
Pl ac e one ca p clo se to eve ry 2 pul lup
res istors te rmina ted to +0.9 VS

+0.9V

0.1U_0402_16V4Z

1

2

C229

0.1U_0402_16V4Z

1

2

C239

RP27

RP29

RP32

RP31

RP33

RP35

R1742 56_0402_5%

0.1U_0402_16V4Z

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A _RAS#
DDR_C S0_DIMMA#

DDR_A_BS #0
DDR_A_MA10

DDR_A _CAS#
DDR_A_W E#

DDR_C S1_DIMMA#
M_ODT1

DDR_A_MA11

0612 a dd

5

2.2U_0805_16V4Z

C473

1

2

0.1U_0402_16V4Z

1

2

C250

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

2.2U_0805_16V4Z

C491

1

2

0.1U_0402_16V4Z

1

1

2

2

C272

C257

+0.9V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C465

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C281

C279

RP22 56_0404_4P2R_5%

DDR_A_BS #2

14

DDR_CKE 0_DIMMA

23

RP26 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP25 56_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_MA12

23

RP28 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP30 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS #1

23

RP34 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP24 56_0404_4P2R_5%

DDR_CKE 1_DIMMA

14

DDR_A_MA14

23

0.1U_0402_16V4Z

C255

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C274

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C280

C242

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C268

2

C252

C241

La yout Note :
Pl ac e the se re sis tor
cl osely JP34 ,all
tr ace len gth Max= 1.5"

C235

0.1U_0402_16V4Z

0317 add

1

+

C246
330U_D2_2.5VM_R 15

2

0.1U_0402_16V4Z

1

1

2

2

C227

C234

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP34

1

VREF

3

DDR_A _D4
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8
DDR_A _D14

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D9 DDR_A _D11
DDR_A _D15 DDR_A_D1 0

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_C KE0_DIMMA7

DDR_A_BS 28

DDR_A_BS 08

DDR_A_W E#8

DDR_A _CAS#8

DDR_CS1_D IMMA#7

M_ODT17

ICH_SMBDATA14,15,20

ICH_SMBCLK14,15,20

3

DDR_CKE 0_DIMMA

DDR_A_BS #2

DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS #0
DDR_A_W E#

DDR_A _CAS#
DDR_C S1_DIMMA#

M_ODT1

DDR_A _D37
DDR_A _D36

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D35
DDR_A _D32

DDR_A _D40
DDR_A _D44

DDR_A_DM 5

DDR_A _D41
DDR_A _D46

DDR_A _D49
DDR_A _D48

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50

DDR_A _D61 DDR_A_D5 7
DDR_A _D60

DDR_A_DM 7

DDR_A _D59
DDR_A _D58

ICH_SMBDATA
ICH_SMBCLK

+3VM

1

2

2.2U_0 603_6.3V4Z

2006/02/13 2006/03/10

C308

C311

Compal Secret Data

1

2

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

conn@

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

FOX_ASOA426-M4R-TR

SO-DIMM A

REVERSE

Top side

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

2

+1.8V

V_DDR _MCH_REF

2

DDR_A _D6

4

DDR_A _D0

6
8

DDR_A_DM 0

10
12

DDR_A _D5

14

DDR_A _D7

16
18

DDR_A _D13

20

DDR_A _D12

22
24

DDR_A_DM 1

26
28

M_CLK_DD R0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A _D20

44

DDR_A _D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

DDR_A_DM 2

DDR_A _D23
DDR_A _D22

DDR_A _D28DDR_A _D29
DDR_A _D25DDR_A _D24

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D31
DDR_A _D30

DDR_CKE 1_DIMMA

DDR_A_MA14

DDR_A_MA11

DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS #1
DDR_A _RAS#
DDR_C S0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A _D39
DDR_A _D38

DDR_A_DM 4

DDR_A _D34
DDR_A _D33

DDR_A _D45
DDR_A _D43

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D47
DDR_A _D42

DDR_A _D52
DDR_A _D53

M_CLK_DD R1
M_CLK_DDR#1

DDR_A_DM 6

DDR_A _D51DDR_A _D54
DDR_A _D55

DDR_A _D56

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

12

R455

R453

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z

C363

1

2

M_CLK_DD R0 7
M_CLK_DD R#0 7

PM_EXTTS#0 7

DDR_C KE1_DIMMA 7

0612 a dd

DDR_A_BS 1 8
DDR_A _RAS# 8
DDR_C S0_DIMMA# 7

M_ODT0 7

M_CLK_DD R1 7
M_CLK_DD R#1 7

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA -3 26 1P U MA

1

C362

1

V_DDR _MCH_REF 7,14,42

0.4

13 55Tuesday, M arch 27, 2007

0.1U_0402_16V4Z

1

2

5

DDR_B _DQS#[0.. 7]8

DDR_ B_D[0..63 ]8

DDR_B _DM[0..7]8

DDR_B _DQS[0..7 ]8

DDR_B _MA[0..14]7 ,8

D D

C C

B B

A A

Lay out No te:
Pl ac e near JP 10

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C265

1

2

0.1U_0402_16V4Z

1

2

C179

RP14

1 4
2 3

56_0404_4P2R_5%

RP17

1 4
2 3

RP16

56_0404_4P2R_5%

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP19

1 4
2 3

RP23

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

R1743

56_0402_5%

2.2U_0805_16V4Z

C247

1

2

0.1U_0402_16V4Z

1

2

C186

2.2U_0805_16V4Z

C236

1

2

Lay out No te:
Pl ac e one ca p clo se to eve ry 2 pul lup
res istors te rmina ted to +0.9 VS

+0.9V

0.1U_0402_16V4Z

1

2

C176

DDR_B_MA1
DDR_B_MA3

DDR_B_BS #0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS #1

DDR_B _RAS#
DDR_C S2_DIMMB#

DDR_B _CAS#
DDR_B_W E#

DDR_C S3_DIMMB# M_ODT2
M_ODT3

DDR_CKE 3_DIMMB

C159

1

2

0.1U_0402_16V4Z

1

1

2

2

C197

C213

+0.9V

RP10 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%

RP9

56_0404_4P2R_5%

2.2U_0805_16V4Z

C164

1

2

0.1U_0402_16V4Z

1

2

C220

14
23

14
23

14
23

14
23

14
23

14
23

14
23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C166

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C183

C210

DDR_B_MA9
DDR_B_MA12

DDR_B_MA14
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS #2
DDR_CKE 2_DIMMB

0.1U_0402_16V4Z

C219

1

2

0.1U_0402_16V4Z

1

2

C199

0612 a dd

5

0.1U_0402_16V4Z

C188

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C173

C218

La yout Note :
Pl ac e the se re sis tor
cl osely JP10 ,all
tr ace len gth Max= 1.5"

4

C161

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C177

C163

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP10

1

VREF

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

conn@

0.1U_0402_16V4Z

Deciphered Date

5
7
9

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

FOX_ASOA426-M4R-TR

SO-DIMM B
STANDARD

Bottom side

DDR_B _D0
DDR_B _D1

DDR_B _DQS#0
DDR_B _DQS0

DDR_B _D2
DDR_B _D3

DDR_B _D8
DDR_B _D9

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D20

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18
DDR_B _D19

DDR_B _D28

DDR_B_DM 3

DDR_B _D30
DDR_B _D31

DDR_CKE 2_DIMMB7

DDR_B _BS28

DDR_B _BS08

DDR_B _WE#8

DDR_B _CAS#8

DDR_CS3_D IMMB#7

M_ODT37

ICH_SMBDATA13,15,20

ICH_SMBCLK13,15,20

+3VM

0310 add

3

DDR_CKE 2_DIMMB

DDR_B_BS #2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS #0
DDR_B_W E#

DDR_B _CAS#
DDR_C S3_DIMMB#

M_ODT3

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43

DDR_B _D48
DDR_B _D49

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D51
DDR_B _D50

DDR_B _D56
DDR_B _D61 DDR_B_D5 7

DDR_B_DM 7

DDR_B _D59
DDR_B _D58

ICH_SMBDATA
ICH_SMBCLK

1

C312

2

2.2U_0 603_6.3V4Z

2006/02/13 2006/03/10

1

C301

2

Compal Secret Data

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS

DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1
GND

2

+1.8V

V_DDR _MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

2

DDR_B _D5
DDR_B _D4

DDR_B_DM 0

DDR_B _D6
DDR_B _D7

DDR_B _D12
DDR_B _D13

DDR_B_DM 1

M_CLK_DD R3
M_CLK_DDR#3

DDR_B _D14
DDR_B _D15

DDR_B _D21DDR_B _D17
DDR_B _D16

DDR_B_DM 2

DDR_B _D22
DDR_B _D23

DDR_B _D26
DDR_B _D24DDR_B _D25

DDR_B _DQS#3
DDR_B _DQS3

DDR_B _D29
DDR_B _D27

DDR_CKE 3_DIMMB

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS #1
DDR_B _RAS#
DDR_C S2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D39
DDR_B _D38

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46
DDR_B _D47

DDR_B _D52
DDR_B _D53

M_CLK_DD R2
M_CLK_DDR#2

DDR_B_DM 6

DDR_B _D54
DDR_B _D55

DDR_B _D60

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

10K_0402_5%

12

R254

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C89

2

2

M_CLK_DD R3 7
M_CLK_DD R#3 7

PM_EXTTS#1 7

DDR_C KE3_DIMMB 7

0612 a dd

DDR_B_BS 1 8
DDR_B _RAS# 8
DDR_C S2_DIMMB# 7

M_ODT2 7

M_CLK_DD R2 7
M_CLK_DD R#2 7

R257

1 2

10K_0402_5%

Title

Size Doc ument Number Re v

Date: Sheet of

+3VM

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3261P UMA

1

V_DDR _MCH_REF 7,13,42

C90

1

14 55Tuesday, M arch 27, 2007

0.4

5

PCI

SRC

CPU

CLK SEL1

1

1

FSLA

CLK SEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

+3VM

1 2

R1066 0_1206_5%

03/0 2 change

FSLC1FSLB

CLK SEL2

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL05

C C

CPU_BSEL15

B B

CPU_BSEL25

FSC

No Stuff

2.2K_0402_5%

FSA

0_0402_5%

0_0402_5%

10K_0402_5%

0_0402_5%

R1078

1 2

R1083

1 2

R1107

R1130

1 2

R1135

0529 change power plan e

A A

18P_0402_50V8J

14.31818MHZ_16P

2

C509

1

Y6

Rou ting th e trace at lea st 10 mil

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1135 R1139

R1083

R1086

R1074

1 2

12

R1079

12

+VCCP

+VCCP

1K_0402_5%

12

R1086

1K_0402_5%@

R1098

1K_0402_5%@

1 2

1 2

R1105

1K_0402_5%

12

R1113

@

0_0402_5%

R1128

1K_0402_5%@

1 2

1 2

R1131

1K_0402_5%

12

R1139

@

0_0402_5%

FSB

R1098

R1107

R1113

R1074

@

1 2

56_0402_5%

MCH_CLKSEL0 7

MCH_CLKSEL1 7

MCH_CLKSEL2 7

For ITP_ EN, 0 = SRC8/SRC8#; 1 = ITP/IT P#

For 27_S EL, 0 = E nable DOT96 & SRC1,

For PCI2 _EN, 0 = Over clocking of CPU and SR C Allowed

CLK_XTAL_OUT

CLK_XTAL_IN

12

2

C505
18P_0402_50V8J

1

5

+3VS +3VS + 3VS

1 2

ITP_EN 27_SEL

1 2

R1128

R1074R1086

R1128

+VCCP

1111 Add CLRP 4,CLRP5 for 667/800 FS B select
SHOR T CL RP5, NO SHORT CLRP 4 -- FSB 80 0
SHOR T CL RP4, NO SHORT CLRP 5 -- FSB 66 7

0216 Delete CLRP4,CLRP 5

CLKSATAREQ#20

CLK_DEBU G_PORT25,30

CLK_P CI_SIO29
CLK_PC I_TCG30
CLK_P CI_EC31

CLK_PCI_PCM25

CLK_P CI_ICH18

CLK_48M_ICH20

CLK_14M_ICH20
CLK_14M_SIO29
CLK_14M_KBC31

1= E nable S RC0 & 27MHz

1 = Over clock ing of CPU and SRC NOT allowed

R1245
10K_0402_5%

R1247
10K_0402_5%

@

+3VM_CK505

CLKREQ#_B7

1 2

1 2

4

1

C1165

10U_0805_10V4Z

2

R1690
10K_0402_5%

@

R1691
10K_0402_5%

4

R1693 475_0402_1%

R1077 33_0402_1%

1 2

1 2
1 2
1 2

1

C1166

0.1U_0402_16V4Z

2

+1.25VM_CK505

1 2

1 2

1 2
1 2
1 2

1 2

R1108
10K_0402_5%

1 2

PCI2_TME

R1246
10K_0402_5%

@

1 2

03/02 change

R1692475_0402_1%

R109722_0402_5%

12

R111412_0402_5%

12

R114012_0402_5%
R111012_0402_5%
R114112_0402_5%

R111722_0402_5%

CLK_XTAL_IN

CLK_XTAL_OUT

R108733_0402_1%
R108833_0402_1%
R108933_0402_1%

+1.25VM_CK505

1

C1167

0.1U_0402_16V4Z

2

+1.25VM

+3VM_CK505

PCI_CLK1

PCI2_TME

PCI_CLK3

27_SEL

ITP_EN

FSA

FSB

FSC

3

1

C1168

0.1U_0402_16V4Z

2

1

C1169

0.1U_0402_16V4Z

2

1

C1170

0.1U_0402_16V4Z

2

1

C1171

0.1U_0402_16V4Z

2

Pla ce cl ose to U7

R1068 0_1206_5%

1 2

C1172

10U_0805_10V4Z

U7

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Int ernal Pull-U p Resi stor
** In ternal Pull- Down R esistor

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

1

C1173

2

SRC1/SE1/27MHz_NonSS

3

1

C1174

2

0.1U_0402_16V4Z

PCI_STOP#

CPU_STOP#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1#/SE2/27MHz_SS

SRC0/DOT96

SRC0/DOT96#

CK_PWRGD/PD#

ICS9LPRS355_TSSOP64

2006/02/13 2006/03/10

SCLK

SDATA

CPU0

CPU0#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

1

2

48

NC

64
63

38
37

54
53

51
50

47
46

35
34

33
32

30
31

44
43

41
40

27
28

24
25

21
22

17
18

13
14

56

10U_0805_10V4Z

1

C1353

2

R_CPU _BCLK
R_CPU _BCLK#

R_MCH_BCLK
R_MCH_BCLK#

R_CPU_XDP
R_CPU_XDP#

R_PCIE_3GPLL #
R_PCIE_3GPLL

CLKRE Q#_H
R_CLKR EQ#_G

R_CLK _PCIE_MCard
R_CLK _PCIE_MCard#

R_CLK _Rob
R_CLK _Rob#

R_MCH_3GPLL
R_MCH_3GPLL#

R_P CIE_ICH
R_PCI E_ICH#

R_PCIE_SATA
R_PCIE_SATA#

SSCD REFCLK
SSCD REFCLK#

R_MC H_DREFCLK
R_MC H_DREFCLK#

Compal Secret Data

0.1U_0402_16V4Z

1

C1354

2

0.1U_0402_16V4Z

R1070

R1072

R1075

R1081

R1033 0_0402_5%

R1143

R1111

R1115

R1695

R1694

R1093

R1095

R14 10K_04 02_5%

R17 475_0402_1%

R5 0_0402_5%
R13 0_0402_5%

R1144

R1145

R1684

R1685

R1257

R1259

R1686 0_0402_5%
R1687 0_0402_5%

R1688

R1689

Deciphered Date

+1.25VM_CK505

1

2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

C1355

2

12

12

2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

1 2

R149 10K_0402_5%
475_0402_1%
475_0402_1%
R150 10K_0402_5%

1 2

0_0402_5%
0_0402_5%

+3VS

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

ICH_SMBCLK 13,1 4,20
ICH_SMBDATA 13,14,20

H_STP_PCI# 20
H_STP_CPU# 20

CLK_CP U_BCLK 4
CLK_CP U_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_CPU_XDP 4
CLK_CPU_XDP# 4

CLK_P CIE_DOCK# 33
CLK_P CIE_DOCK 33

+3VS

CPPE# 33

CLKREQ#_G 25

+3VS

CLK_P CIE_MCARD 25
CLK_P CIE_MCARD# 25

CLKREQ#_E 25

0612 add for Robson

CLK_P CIE_Rob 25
CLK_P CIE_Rob# 25

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_P CIE_ICH 2 0

CLK_P CIE_ICH# 20

CLK_PCIE_SATA 19
CLK_PCIE_SATA# 19

MCH_ SSCDREFCLK 7
MCH_ SSCDREFCLK# 7

CLK_M CH_DREFCLK 7
CLK_M CH_DREFCLK# 7

CK_PW RGD 20

1

C353

C357

C372

C373

C374

C375

C376

C378

C379

C380

CLK_48M_ICH

12

5P_0402_50V8C

CLK_14M_ICH

12

4.7P_0402_50V8C

CLK_P CI_ICH

12

4.7P_0402_50V8C

CLK_14M_KBC

12

4.7P_0402_50V8C

CLK_14M_SIO

12

4.7P_0402_50V8C

CLK_P CI_EC

12

4.7P_0402_50V8C

CLK_PC I_TCG

12

4.7P_0402_50V8C

CLK_PCI_PCM

12

4.7P_0402_50V8C

CLK_P CI_SIO

12

4.7P_0402_50V8C

CLK_DEBU G_PORT

12

5P_0402_50V8C

200 70 301 Ad d C AP for WWAN issue

0612 add for Robson

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Clock generator

LA-3261P UMA

15 55Tuesday, M arch 27, 2007

1

0.4

A

CRT Connector

101 3 Add CRT ci rcuit

1 1

+5VS +5VS

1

5

M_HS YNC9

M_VSYNC9

2 2

R53 51K_0402_5%

P

A2Y

G

3

1 2

1 2

R54 51K_0402_5%

Pla ce cl ose to do cki ng connect or

L_BLUE33

L_GREEN33

L_RED33

0315 add

C359

1 2

0.1U_0402_16V4Z

U33
SN74AHCT1G125GW_SOT353-5

HSYN C_G_A

4

OE#

1

5

P

OE#

A2Y

G

U54
SN74AHCT1G125GW_SOT353-5

3

C370

1 2

0.1U_0402_16V4Z

VSYNC_ G_A

4

150_0402_1%

12

R171

@

R545

1 2

0_0603_5%

1 2

5P_0402_50V8C@

12

150_0402_1%

R173

@

R546

0_0603_5%

C351

R174

B

12

@

150_0402_1%

C313

C314

12P_0402_50V8C

1

1

2

2

D_H SYNC

D_V SYNC

1

1

C352

5P_0402_50V8C@

2

2

1

12P_0402_50V8C

2

D_H SYNC 33

D_V SYNC 33

R542

1 2

BK1608LL560-T 0603

R543

1 2

BK1608LL560-T 0603

R544

1 2

BK1608LL560-T 0603

@

C310

18P_0402_50V8J

12P_0402_50V8C

0315 add

C317

D_DDC DATA33

D_DDC CLK33

1

@

2

1

C316

2

C

F1

1.1A_6 VDC_FUSE

RED_R

GREEN_R

BLUE_R

1

C318

2

18P_0402_50V8J

18P_0402_50V8J

@

D18

2 1

21

CH491 D_SC59

0.1U_0402_16V4Z

C315

W=40m ils

1

2

JP2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_0 70912FR0 15S207CR

conn@

+CRTVDD +CRTVDD

R162

2.2K_0402_5%

D_DDC DATA

D_DDC CLK

D

+CRTVDD+RCR T_VCC+5VS

BLUE_R
GREEN_R
RED_R

1

1

D4

DAN217_SC5 9

@

2

2

3

16
17

R2

1 2

2

G

S

2

G

1 3

D

S

RHU002N06_S OT323

2.2K_0402_5%

12

12

R183

2.2K_0402_5%

Q46

1 3

D

RHU002N06_S OT323

Q52

1

D19

D20

Place close to JP2

DAN217_SC5 9@

+CRTVDD

3

+3VS

DAN217_SC5 9

@

3

2

R4

1 2

2.2K_0402_5%

Pla ce cl ose to do cki ng connect or

DDC1_DAT A 9

DDC1_ CLK 9

E

layo ut n ote: D_H SYNC & D_VSY NC should b e routed to docking co nnector the n to VGA co nnector

TV-Out Connector

LUMA9,33

CRMA9,33

COMP9,33

12

12

3 3

la y o u t n

la y o u t n ote : T V-o ut si g na l s sho u ld b e r o ute d t o J P3 0 t h en to JP 1

la y o u t nl a y o ut n

4 4

R184

@

0315 add

150_0402_1%

150_0402_1%

ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1

ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1

@

R185

@

Cl

Cl ose to JP 1

os e t o J P1

ClCl

os e t o J P1o se to JP 1

12

R187

150_0402_1%

1

@

2

5.6P_0402_50V8D

C333

5.6P_0402_50V8D

1

2

C355

C354

@

0_0603_5%

R547

1 2

0_0603_5%

R548

1 2

0_0603_5%

R549

1 2

1

@

2

5.6P_0402_50V8D

Place close to JP1

DAN217_SC5 9

D3

@

DAN217 _SC59

1

2

3

@

D5

TV_LUMA

TV_CRMA

TV_COMP

DAN217_SC5 9

@

1

2

3

SUYIN_3 3007SR-07T1-C

+3VS

D1

1

2

3

JP1

1
2
3
4
5
6
7

conn@

+2.5VS +2.5VS

+2.5VS

12

DVI Transnitter

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R1369

CHB1608U301_ 0603

R497
10K_0402_5%

W= 20 m ils

AS

PEG_RXP19
PEG_RXN19

C

DVI_D VDD_2.5V

12

C178

C143

C150

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1.3K_0402_1%

C1043
C1042

R103

SDVOB_R+9
SDVOB_R-9

SDVOB_G+9
SDVOB_G-9

SDVOB_B+9
SDVOB_B-9

SDVOB_CLK+9
SDVOB_CLK-9

12

0.1U_0402_16V4Z

PLT_RST#7,18,22,30

R114

10K_0402_5%

0.1U_0402_16V4Z

SDVOB_INT-

0.1U_0402_16V4Z

1 2

2006/02/13 2006/07/26

DVI_A VDD_2.5V

C174

0.1U_0402_16V4Z

AS
PLT_RST#

DVI_V SWING

12

R498

10K_0402_5%

Compal Secret Data

Deciphered Date

02/2 8 ch ange -->so lve DVI iss ue

R1367

1 2

KC FBM-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z

DVI_A VDD_3V

DVI_D VDD_2.5V

U11

SDVOB_INT+
SDVOB_INT-

SDVOB_R+
SDVOB_R-

SDVOB_G+
SDVOB_G-

SDVOB_B+
SDVOB_B-

SDVOB_CLK+
SDVOB_CLK-

AS
RESET#
VSWING

ATPG
SCEN

PAD

49

1

C140
22U_0805_6.3VAM

2

28

1

DVDD12DVDD

AVDD_PLL

DGND7DGND30AGND31AGND39AGND45TGND18TGND24AGND_PLL

D

21

TVDD15TVDD

AVDD36AVDD42AVDD

DVI_A VDD_2.5V

6

C141

32
33

37
38

40
41

43
44

46
47

3
2

25

27
26

C358

C371

R_DVI _CLK-SDVOB_INT+
R_DVI _CLK+
R_DVI_TX0­R_DVI_TX0+
R_DVI_TX1­R_DVI_TX1+
R_DVI_TX2­R_DVI_TX2+

DVI_DETECT

10K_0402_5%

SDVO_SDAT
SDVO_SCLK

0.1U_0402_16V4Z

48

TDC0#

TDC0

TDC1#

TDC1

TDC2#

TDC2

HPDET

SC_DDC
SD_DDC

SC_PROM
SD_PROM

NC

NC

CH730 7C_LQFP48

35

34

0.1U_0402_16V4Z

0.1U_0402_16V4Z

13

TLC#

14

TLC

16
17
19
20
22
23

29

11
10

9
8

5

SPD

4

SPC

0830 Change to 3.9K oh m

Title

Size Doc ument Number Re v

Date: Sheet of

KC FBM-L11-201209-221LMA30T_0805

DVI_A VDD_3V

C368

R1673 0_0603_5%
R1674 0_0603_5%
R1675 0_0603_5%
R1676 0_0603_5%
R1677 0_0603_5%
R1678 0_0603_5%
R1679 0_0603_5%
R1680 0_0603_5%

R172010K_0402_5%

@

1 2
1 2

R1721

@

C1371

56P_0402_50V

SDVO_SDAT
SDVO_SCLK

R1368

1 2

1

C369
10U_0805_10V4Z

2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

0620 change

SDVO_SDAT 7
SDVO_SCLK 7

+5VS

DVI_C LK 33
DVI_DAT 33

+3VS

DVI_DETECT 33

1226 Add C for DVI I2C

R144 5.6K_0402_5%

1 2

R142 5.6K_0402_5%

1 2

1113 Change to 5.6K oh m

Compal Electronics, Inc.

CRT & TVout Connector

LA -3 26 1P U MA

16 55Tuesday, M arch 27, 2007

E

DVI_C LK- 33
DVI_CLK+ 33
DVI_TX0- 33
DVI_TX0+ 33
DVI_TX1- 33
DVI_TX1+ 33
DVI_TX2- 33
DVI_TX2+ 33

+2.5VS

0.4

5

4

3

2

1

JP35

B+_LCD

C586 10U_1206_25V6M

C587 68P_0402_50V8J

40

40

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

30

30

29

29

28

28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

BKLT_PWM

27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

LVDS CONN

41

41

42

D D

C C

42

43

43

44

44

45

45

46

46

ACES_88316-4000

conn@

2007 0209 Add 10uF for wavy is sue

1 2

1 2

1 2

10U_1206_25V6M

C1376

L62 KC FBM-L11-201209-221LMA30T _1210

LCDVD D

+3VS

+5VS_INV

TXCLK_U+ 9
TXCLK_U- 9

TXOUT_U2+ 9
TXOUT_U2- 9

TXOUT_U1+ 9
TXOUT_U1- 9

TXOUT_U0+ 9
TXOUT_U0- 9

TXOUT_L0- 9
TXOUT_L0+ 9

TXOUT_L1- 9
TXOUT_L1+ 9

TXOUT_L2- 9
TXOUT_L2+ 9

TXCLK_L- 9
TXCLK_L+ 9

0628 change si ze

12

ALS_EN 20

DDC2_ CLK 9
DDC2_DAT A 9

LCD POWER CIRCUIT

LCDV DD

12

R19

100_0402_1%

+3VALW

+3VS

LID_SW#20,32

Q5

R502

13

D

2

G

S

2

1 2

0_0402_5%

R1728

1 2

0_0402_5%@

R1729

1 2

LID_SW#

ENABLT9

0314 change

13

R474

1 2

47K_0402_5%

Q6
DTC124EK_SC59

+3V_U43

14

1

P

A

2

B

G

7

R501

1 2

100K_0402_1%

1

C29

2

0.1U_0402_16V4Z

+5VS

U43A
SN74LVC08APW_TSS OP14

3

O

R360

100K_0402_5%

1 2

B+

RHU002N06_S OT323

ENAVDD9

100K_0402_1%

0314 add

Q8

AO3413_SOT23

D

S

1 3

R12

G

2

1 2

1M_0402_5%

C28

1 2

1

C31

4.7U_0805_10V4Z

2

0.1U_0402_16V7K

0216 Change C28 to 0.1 uF

Q53
DTA114YKA_SC59

13

Q36
BSS138_SOT23

+5VS_INV

47K

10K

2

13

D

2

G

S

+3VALWLCDVD D

1

C20

4.7U_0805_10V4Z@

2

B B

BLON_PWM9

R102 0_0402_5%

1 2

BKLT_PWM

Support 3V inverter

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

LCD CONN.

LA -3 26 1P U MA

17 55Tuesday, M arch 27, 2007

1

0.4

5

+3VS

1 2

R1514 8.2K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

12

R1515 8.2K_0402_5%

D D

C C

R1516 8.2K_0402_5%

R1517 8.2K_0402_5%

R1518 8.2K_0402_5%

R1519 8.2K_0402_5%

R1520 8.2K_0402_5%

R1521 8.2K_0402_5%

R1585 10K_0402_5%

R1748 10K_0402_5%

+3VS

R1522 8.2K_0402_5%

R1523 8.2K_0402_5%

R1524 8.2K_0402_5%

R1525 8.2K_0402_5%

R1526 8.2K_0402_5%

R10 8.2K_0402_5%

R189 8.2K_0402_5%

R1530 8.2K_0402_5%

R1531 8.2K_0402_5%

R1532 8.2K_0402_5%

R1533 8.2K_0402_5%

PCI_DEVSEL#

PCI_STOP#

PC I_TRDY#

PCI_FRAME#

PCI_PLOCK#

PCI _IRDY#

PCI_S ERR#

PCI_P ERR#

MBAY_DET#

MDC_ DIS

PCI_P IRQA#

PCI_P IRQB#

PCI_P IRQC#

PCI_P IRQD#

PCI_P IRQE#

PCI_P IRQG#

PIRQH#

PCI_R EQ0#

PCI_R EQ1#

PCI_R EQ2#

PCI_R EQ3#

PCI_ AD[0..31]25

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_P IRQA#
PCI_P IRQB#

PCI_P IRQC#25
PCI_P IRQD#25

PCI_P IRQC#
PCI_P IRQD#

U26B

D20

AD0

E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14

G16

A15

B6

C11

A9
D11
B12
C12
D10

C7
F13
E11
E13
E12

D8

A6

E8

D6

A3

F9

B5

C5
A10

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH8M REV 1.0

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCI_R EQ0#
PCI_GNT0#
PCI_R EQ1#

PCI_R EQ2#
PCI_GNT2#
PCI_R EQ3#
PCI_GNT3#

PCI_CBE #0
PCI_CBE #1
PCI_CBE #2
PCI_CBE #3

PCI _IRDY#
PCI_PAR
PCI_P CIRST#
PCI_DEVSEL#
PCI_P ERR#
PCI_PLOCK#
PCI_S ERR#
PCI_STOP#
PC I_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_P CI_ICH
PCI_PME#

8.2K_0402_5%

PCI_P IRQE#
MBAY_DET#

PIRQH#

0_0402_5%

R1527

1 2

R188

12

MDC_ DIS
PCI_R EQ2# 25
PCI_GNT2# 25

PCI_CBE #0 25
PCI_CBE #1 25
PCI_CBE #2 25
PCI_CBE #3 25

PCI _IRDY# 25
PCI_PAR 25

PCI_DEVSEL# 25
PCI_P ERR# 25

PCI_S ERR# 25,31
PCI_STOP# 25
PCI_ TRDY# 25
PCI_FRAME# 25

PCI_PLTRST# 25
CLK_P CI_ICH 15
PCI_PME#

+3VALW

PCI_P IRQE# 25
MBAY_DET# 22
PCI_P IRQG# 25
ACCE L_INT 25

0301 change

0601 change

2

1

PCI_GNT3#

12

R1534

@

1K_0402_5%

B B

A16 swap override Strap

Low= A16 swap override Enble

PCI_GNT3#

A A

High= Default

Pla ce cl ose ly pi n B10

CLK_P CI_ICH

R1537

10_0402_5% @

1 2

1

C1177

8.2P_0402_50V@

5

2

*

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

4

12

1K_0402_5%

21

J35
PAD-N O SHORT 2 x2m

1

0

1

R1535

Boot BIOS Location

SPI

*

PCI_P CIRST#

PCI

LPC

SPI_CS1#_R20

SPI_CS1#_RPCI_GNT0#

12

R1536

@

1K_0402_5%

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

PCI_PLTRST#

Deciphered Date

2

R1051
0_0402_5%

R1057
0_0402_5%

+3VALW

5

U56

1

P

B

2

A

G

3

12

+3VALW

5

1

P

B

2

A

G

3

12

PCI_RST#

4

Y

TC7SH08FU_SSOP5@

U59

PLT_RST#

4

Y

TC7SH08FU_SSOP5@

Title

Size Doc ument Number Re v

Date: Sheet of

12

12

Compal Electronics, Inc.

PCI_RST# 22,25

R192
100K_0402_5%

PLT_RST# 7,16, 22,30

R191
100K_0402_5%

ICH8(1/4)-PCI/INT

LA-3261P UMA

1

18 55Tuesday, M arch 27, 2007

0.4

5

D D

+RTCVCC

R1540 330K_0402_1%

LAN100_SLP

1 2

R1542 1M_0402_5%

SM_INTR UDER#

1 2

R1543 330K_0402_1%

ICH_IN TVRMEN

1 2

0821 Ch ang e C528 and C516 to 15PF

R1733

1 2

10M_0402_5%

1

C528

15P_0402_50V8J

C C

+3VS

R1560
10K_0402_5%

HDA_BITCLK

R1561
10_0402_5%

@

1 2

1

B B

2

C1181

10P_0402_25V8K

@

R90

10K_0402_5%

MB2_LED#22

2

Y4

1 4

2 3

32.768KH Z_12.5P_MC-146

IDE_LED#

12

CLRP2 SHORT PAD S

GREEN_BATLED#25,31

+5VS

12

SATA_LED#

MB2_LED#

ICH_RTCX1

ICH_RTCX2

1

2

12

+3VS

12

R88
10K_0402_5%

21

D15 CH751 H-40_SC76

21

D16 CH751 H-40_SC76

+RTCVCC

C516
15P_0402_50V8J

+3VS

2

G

Q141

RHU002N06_S OT323

0823

1220 Upda te GPIO33 c ircuit

IDE_LED#

1 2

20K_0402_5%

1U_0603_10V4Z

HDA_B ITCLK_MDC32

HDA_B ITCLK_CODEC26

HDA _SYNC_COD EC26

HDA_S YNC_MDC32

HDA_R ST#_CODEC26

HDA_RST#_MDC26,32

HDA_S DOUT_MDC32

HDA_S DOUT_CODEC26

1 2

R1801 1K_0 402_5%

13

D

S

IDE_LED# 25

R1545

HDA_S DIN026
HDA_S DIN132

SATA_RXN0_C22
SATA_RXP0_C22

C1178

SATA_TXN022
SATA_TXP022

4

ICH_RTCX1
ICH_RTCX2

ICH_R TCRST#

CLRP1

2

SHORT PADS

1 2

1

ENER GY_DET24

GLAN_CLK23

LAN_R STSYNC23

LAN_RXD023
LAN_RXD123
LAN_RXD223

LAN_TXD023
LAN_TXD123
LAN_TXD223

+1.5VS

SATA_TXN0
SATA_TXP0

SM_INTR UDER#

R1549 24.9_0402_1%

1 2

33_0402_5%

R1551
R1550
R1553 33_0402_5%
R1554 33_0402_5%
R1555 33_0402_5%
R1556 33_0402_5%

R1558 33_0402_5%
R1559 33_0402_5%

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

33_0402_5%

3900P_0402_50V7K

C1179

1 2

C1180

1 2

3900P_0402_50V7K

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

SM_INTR UDER#

ICH_IN TVRMEN
LAN100_SLP

GLAN_CLK

LAN_R STSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

GLAN_COMP

HDA_BITCLK

T38P AD

SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R1564

1 2

24.9_0402_1%

Within 500 mils

HDA _SYNC
HDARST#

HDA_S DIN0
HDA_S DIN1

HDA_SDOUT

SATA_LED#

3

U26A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

A20GATE

DPRSTP#

CPUPWRGD/GPIO49

STPCLK#

THRMTRIP#

IHDA

IDE

SATA

W=20m ils

2

1

E5
F5
G8
F6

C4

G9

LDRQ0#

E6

AF13
AG26

A20M#

AF26
AE26

DPSLP#

AD24

FERR#

AG29

AF27

IGNNE#

AE24

INIT#

AC20

INTR

AH14

RCIN#

AD23

NMI

AG28

SMI#

AA24

AE27

AA23

TP8

V1

DD0

U2

DD1

V3

DD2

T1

DD3

V4

DD4

T5

DD5

AB2

DD6

T6

DD7

T3

DD8

R2

DD9

T4

DD10

V6

DD11

V5

DD12

U1

DD13

V2

DD14

U6

DD15

AA4

DA0

AA1

DA1

AB3

DA2

Y6

DCS1#

Y5

DCS3#

W4

DIOR#

W3

DIOW#

Y2

DDACK#

Y3

IDEIRQ

Y1

IORDY

W5

DDREQ

R981

1 2

0_0402_5%

C665
1U_0603_10V4Z

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_DR Q0#

GATEA20
H_A20M#

H_FER R#

H_PW RGOOD

H_IGNN E#

H_INIT#
H_INT R
KB_RST#

H_NMI
H_SMI#

H_STPCLK#

THRM TRIP_ICH#

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_A0
PD_A1
PD_A2

PD_CS1#
PD_CS3#

PD_IOR#

PD_IOW #

PD_DACK#

PD_IR Q

PD_ IORDY#

PD_DR EQ#

W=20m ils

DAN20 2U_SC70

1

2

LPC_A D[0..3] 2 9,30,31

LPC_FRAME# 29,30,31

LPC_DR Q#0 29

GATEA20 31
H_A20M# 4

R1548 0_0402_5%

H_FER R# 4

KB_RST# 31

PD_A0 22
PD_A1 22
PD_A2 22

PD_CS1# 22
PD_CS3# 22

PD_IOR# 22

PD_IOW # 22

PD_DACK# 22

PD_IR Q 22
PD_ IORDY# 22
PD_DR EQ# 22

D14

2

3

W=20m ils

T39 PAD

H_DPRSTP#H_DPRSTP_R#

12

H_DPSLP# 5

H_PW RGOOD 5

H_IGNN E# 4

H_INIT# 4
H_INT R 4

H_NMI 4
H_SMI# 4

H_STPCLK# 4

1 2

PD_ D[0..15] 22

+3VL+RTCVCC

R976

1 2

1K_0402_5%

R1557 24_040 2_1%

BATT1.1

+

W=20m ils

GATEA20

KB_RST#

H_FER R#

H_DPRSTP#

H_DPSLP#

H_DPRSTP# 5,7,43

+VCCP

12

R1538

10K_0402_5%

R1539

10K_0402_5%

R1541

56_0402_5%

R1544

56_0402_5%

R1546

56_0402_5%

wit hin 2 " f rom R 1557

R1552

56_0402_5%

H_THERMTRIP# 4,7

pla ced w ith in 2" fr om I CH8M

PD_ IORDY#

R1562 4.7K_0402_5%

PD_IR Q

1 2

R1563 8.2K_0402_5%

1 2

BATT1

CR2032 RTC BATTERY

JP42
ACES_85205-0200

1

2

-

conn@

1

+3VS

12

12

+VCCP

12

@

12

@

12

+3VS

A A

XOR CHA IN ENTRANCE S TRAP:RSVD

+3VS

R1567
1K_0402_5%

@

12

5

HDA_S DOUT_CODEC

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

LA -3 26 1P U MA

1

19 55Tuesday, March 27, 2007

0.4

5

SIRQ

+3VS

D D

+3VALW

C C

B B

0629 connect to +3VM

100K_0402_5%

1 2

@

USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4

USB_OC#7

A A

USB_OC#8
USB_OC#9
USB_OC#0

10K_1206_8P4R_5%

XMIT_OFF

USB_OC#5

WXMIT_OFF#

1 2

R1576 10K_0402_5%

1 2

R1578 8.2K_0402_5%

1 2

R1579 10K_0402_5%

@

R1582 8.2K_0402_5%

R1600 10K_0402_5%

R1595 8.2K_0402_5%

R1601 8.2K_0402_5%

R1602 8.2K_0402_5%

R1617 8.2K_0402_5%

R1590 10K_0402_5%

R1587 10K_0402_5%@

R1593 10K_0402_5%

R1594 8.2K_0402_5%

R1584 1K_0402_5%

R1597 10K_0402_5%

R1603 10K_0402_5%

R1589 1K_0402_5%

R1631 10K_0402_5%

ICH_SM_DA4,25

ICH_SM_CLK4,25

0316 change design

ICH_SMBDATA13,14,15

ICH_SMBCLK13,14,15

+3VM

R1604

12

R1568

1K_0402_5%

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

4 5
3 6
2 7
1 8

R1608
10K_0402_5%

1 2

R1609
10K_0402_5%

1 2

R1810
10K_0402_5%

1 2

THERM_SCI#

1 2

CLKSATAREQ#

1 2

GPIO37

1 2

GPIO18

1 2

GPIO22

1 2

GPIO20

1 2

1 2

1 2

1 2

ICH_LOW_B AT#

12

ICH_P CIE_WAKE#

1 2

1 2

LAN _PHYPC

1 2

XDP_DBRESET#

1 2

S4_STATE#

1 2

+3VM

R2062.2K_0402_5%

1 2

R1756 0_0402_5%

DPRSLPVR

ICH_R SVD

RP55

RP56

2007 0326 Add R1810

5

PM_CLKRUN#

GPIO39

H_STP_PCI#15

OCP#

LINKALERT#

LID_SW#

ICH _RI#

H_STP_CPU#15

0718 INSTALL R179

0612 Cha nge GPIO p in assignme nt
0825 Cha nge GPIO p in assignme nt

LAN_ PHYPC23

0622 change value

+3VS

12

12

2.2K_0402_5%

R2072.2K_0402_5%

R205

+5VS

Q24
RHU002N06_S OT323

D

13

S

G

2

G

S

G

RHU002N06_S OT323

2

S

G

2

RHU002N06_S OT323

D

13

Q25

RHU002N06_S OT323

2

D

13

+5VALW

Q130

@

ICH_SM_DA

ICH_SM_CLK

12

12

2.2K_0402_5%
R204

S

PM_SLP_M#

0601 add for SM bus

+3VALW

+3VS

1 2

1 2

1 2

1 2

1 2

IDE_RESET#

R11 8.2K_0402_5%

NPCI_RS T#

R3 8.2K_0402_5%

MB_PWR

R6 8.2K_0402_5%

ALS_EN#

R16 8.2K_0402_5%

PM_BMBUSY#

R9 8.2K_0402_5%

+3VALW

R1572

0320 add

+3VM

10K_0402_5%

R1580

@

10K_0402_5%

1 2

1 2

10K_0402_5%

1 2

1 2

ME_EC_DATA131

R1573

ME_EC_CLK131

@

10K_0402_5%

R1581

0821

+3VS

DOCK_ ID33

Q26
RHU002N06_S OT323

D

ICH_SMB_DATA

13

D

S

ICH_SMB_CL K

13

G

Q29

2

1 2

8.2K_0402_5%

R1591 0_0402_5%@

WLAN

Robson

ICH_SMB_DATA 25

ICH_SMB_CLK 25

Dock

GLAN_RXN23
GLAN_RXP23

GLAN Right side

GLAN_TXN23

GLAN_TXP23

SPI_CLK30
SPI_CS0#30
SPI_CS1#30

SPI_CS1#_R18

SPI_SI30
SPI_SO30

WXMIT_OFF#25

0110 Res olve +3vs leakage iss ue

0529 add for SB GPI

4

+3VALW

2.2K_0402_5%

XDP_DBRESET#4

PM_BMBUSY#7

R179 0_0402_5%

PM_CLKRU N#25,29,30,31

ICH_P CIE_WAKE#25

THERM_SCI#4

VGATE7,31

1 2

R349 0_0402_5%@

1 2

R1781 0_0402_5%

R1632

Cap_RST#_SB32

CLKSATAREQ#15

12

IDE_RESET#22

MCH _ICH_SYNC#7

ICH_R SVD

1 2

+3VS

R1723 10K_0402_5% @

PCIE_RXN225
PCIE_RXP225
PCIE_TXN225
PCIE_TXP225

PCIE_RXN425
PCIE_RXP425
PCIE_TXN425
PCIE_TXP425

PCIE_RXN533
PCIE_RXP533
PCIE_TXN533
PCIE_TXP533

BT_OFF28

R1007

10K_0402_5%

PREP#24, 26,33

4

0316 change design

12

12

R1571

R1570

2.2K_0402_5%

ICH_SMB_CL K
ICH_SMB_DATA

SIRQ25,29,30,31

1 2

T15P AD

SB_SPKR

1 2
1 2
1 2

R352

1 2

0_0402_5%

0320 change

12

LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

ICH _RI#

XDP_DBRESET#

PM_BMBUSY#

GPIO11

H_STP_PCI#
R_STP_CPU#

ICH_P CIE_WAKE#

SIRQ
THERM_SCI#

VRMPWRGD

SST_CTL

RUNS CI_EC#
ISO_PREP#

LAN_P HYPC_R
ALS_EN#

0901

T48P AD

Cap_RST#_SB
CLKSATAREQ#

IDE_RESET#

SB_SPKR

MCH _ICH_SYNC #

ICH_R SVD

low --> defa ult

Hig h - ->N o boo t

C11860.1U_0402_16V4Z

12

C11870.1U_0402_16V4Z

12

R160515_0402_5%
R160615_0402_5%
R160715_0402_5%

R16400_0402_5%

12

R16410_0402_5%

12

D57

21

CH751 H-40_SC76

CL_RST#125

LPC_PD#30

12

R145 0_0402_5%@

OCP#4,44

RUNS CI_EC#31

ISO_PREP#33
LID_SW #17,32

SPI_CS1#

SB_SPKR26

+3VALW +3VS

GPIO18
GPIO20
GPIO22

GPIO38
GPIO39

12
12

12
12

12
12

AJ26
AD19
AG21
AC17
AE19

AF17

AD15

AG12

AG22

AE20
AG18

AH11

AE17
AF12
AC13

AJ20

AJ22

AJ8
AJ9

AH9
AE16
AC19

AG8
AH12
AE11
AG10
AH25
AD16
AG13

AF9

AJ11

AD10

AD9

AJ13

AJ21

C7100.1U_040 2_16V4Z
C7110.1U_040 2_16V4Z

C7080.1U_0402_16V4Z
C7090.1U_0402_16V4Z

C13610.1U_04 02_16V4Z
C13620.1U_04 02_16V4Z

GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

SPI_CLK_R
SPI_CS0#_R
SPI_CS1#_R

SPI_S I_R
SPI_SO_R

USB_OC#0
USB_OC#1
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9

12

R1008

10K_0402_5%

ISO_PREP#PREP#

3

1101 For au to boot iss ue

U26C

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#

F4

SUS_STAT#/LPCPD#
SYS_RESET#

BMBUSY#/GPIO0

SMBALERT#/GPIO11

STP_PCI#/GPIO15
STP_CPU#/GPIO25

CLKRUN#/GPIO32

WAKE#
SERIRQ
THRM#

VRMPWRGD

TP7

TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

SPKR

MCH_SYNC#

TP3

ICH8M REV 1.0

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

PCIE_RXN5
PCIE_RXP5
PCIE_C_TXN5
PCIE_C_TXP5

AJ19
AG16
AG15
AE15

AF15
AG17
AD12

AJ18
AD14
AH18

M27
M26

P27

P26
N29
N28

L29

L28

K27
K26

J29

J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

SYS

U26D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA

GPIO

SMB

Clocks

GPIO

Power MGTController Link

GPIO

ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

MISC

PCI-Express

SPI

USB

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

MEM_LED/GPIO24

WOL_EN/GPIO9

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

Direct Media Interface

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

2006/02/13 2006/03/10

AJ12

HDD_H ALTLED

AJ10
AF11

GPIO37

AG11

CLK_14M_ICH

AG9

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

CLK_48M_ICH

G5

ICH_S USCLK

D3

SLP_S3#

AG23

SLP_S4#

AF21

SLP_S5#

AD18

S4_STATE#

AH27

PM_PWROK

AE23

DPRSLPVR

AJ14

ICH_LOW_B AT#

AE21

ON/OFF BTN#

C2

R1722

1 2

AH20

0_0402_5%

EC_RMRST#

AG27

E1

M_PWROK

E3

PM_SLP_M#

AJ25

CL_CLK0

F23
AE18

CL_DATA0

F22
AF19

CL_VR EF0_ICH

D24

CL_VR EF1_ICH

AH23

AJ23

XMIT_OFF

AJ27

CB_IN #

AJ24

R1738

AF22

0_0402_5%

AG19

0612 Cha nge GPIO p in assignme nt

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB26

DMI_RXP2

AB25

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CLK_P CIE_ICH#

T26

CLK_P CIE_ICH

T25

Y23

DMI_IRCOM P

Y24

USB20_N0

G3

USB20_P0

G2

USB20_N1

H5

USB20_P1

H4
H2
H1
J3
J2

USB20_N4

K5

USB20_P4

K4

USB20_N5

K2

USB20_P5

K1

USB20_N6

L3

USB20_P6

L2

USB20_N7

M5

USB20_P7

M4

USB20_N8

M2

USB20_P8

M1

USB20_N9

N3

USB20_P9

N2

USBR BIAS

F2
F3

CK_PW RGD_R

1 2

100_0402_5%

R1016 24.9_0402_1%

R1019 22.6_0402_1%

Within 50 0 m ils

Compal Secret Data

Deciphered Date

MB_PWR 22

NPCI_RS T# 29,31

CLK_14M _ICH 15
CLK_48M _ICH 15

T14 PAD

SLP_S3# 23 ,26,27,31,3 3,34,41,42,43,44
SLP_S4# 34,42
SLP_S5# 34,42

S4_STATE# 28

PM_PWROK 7 ,31,45

DPRSLPVR 7,43

D22CH751H-40PT_S OD323-2

ON/OFF BTN# 32

LAN_RST# 35

1 2

1 2

R148 0_0402_5%

M_PWROK 7,35

PM_SLP_M# 31,34,42,46

CL_CLK0 7
CL_CLK1 25

CL_DATA0 7
CL_DATA1 25

CL_RST# 7

XMIT_OFF 25

DMI_RXN0 7

DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7

DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7

DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7

DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_P CIE_ICH# 15
CLK_P CIE_ICH 1 5

1 2

USB20_N0 28
USB20_P0 28
USB20_N1 30
USB20_P1 30

USB20_N4 28
USB20_P4 28
USB20_N5 28
USB20_P5 28
USB20_N6 28
USB20_P6 28
USB20_N7 33
USB20_P7 33
USB20_N8 25
USB20_P8 25
USB20_N9 33
USB20_P9 33

1 2

2

R1569 10K_0402_ 5%

PM_RSMRST#

1 2

2 1

R1586

CK_PW RGD

AMT ADP_PRES 31

LAN_W OL_EN 34

Within 50 0 m ils

2

1 2

R1583

10K_0402_5%

100K_0402_5%

1 2

R1630

PM_RSMRST#

+1.5VS

Finger print

Left side

Left side

Bluetooth

Dock1

WWAN

Dock2

1

Pla ce cl ose ly pi n AG 9Pla ce cl ose ly pi n G5

PM_RSMRST# 31

12

+3VALW

0105 For LED issue

LOW_BAT# 31

+3VL

CK_PW RGD 15

1

C1184

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1185

2

J36

2 1

PAD-S HORT 2x2m

GPIO2931

PWR _GD25,3 1,34,35,43,44

10K_0402_5%

R1767

CLK_EN#43

RHU002N06_S OT323

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

R1574

10_0402_5%@

1

C1182

4.7P_0402_50V8C@

2

HDD_H ALTLED# 25

13

HDD_H ALTLED

R15
100K_0402_5%

1 2

2007 0228 auto boo t and leaka ge issue

SLP_S3#23,26,27, 31,33,34,4 1,42,43,44

R1588 3.24K_0402_1%

1 2

12

R1592

453_0402_1%

NA le ad free

LED_L INK_LAN#23,24,33

1 2

R1596 3.24K_0402_1%

12

R1598
453_0402_1%

NA le ad free

R161

1 2

Q20

0.22U_0402_10V4 Z

D

Q114

2

G

RHU002N06_S OT323

S

03/0 1 ch ange GPIO pin assignm ent

+3VALW

5

1

P

IN1

+3VALW

CB_IN #

2

G

10K_0402_5%

R434

@

D

1

S

2

2

IN2

G

3

G

2

13

D

S

Q140

0320 add

1 2

R1599 10K_0402_5%

+3VS

R433

330_0402_5%

1 2

ALS_EN

13

D

Q45

S

RHU002N06_S OT323

073 1 Eli man ate gl itch

080 9 Eli man ate gl itch

1 2

R147 0_0402_5%@

1 2

12

R146 0_0402_5%

R1757

@

100K_0402_5%

+3VM_LAN

+3VM

CABLE_DETECT 24

0_0402_5%

1 2

ALS_EN#

+3VS

1 2

13

2

G

C1365

@

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

LA -3 26 1P U MA

1

CLK_14M_ICHCLK _48M_ICH

12

R1575

10_0402_5%@

1

C1183

4.7P_0402_50V8C@

2

U83
SN74A HC1G08DCKR_SC70

4

O

+3VALW

12

R1797 10K_0402_5%

GPIO11

RHU002N06_S OT323

+3VALW

ALS_EN 17

CK_PW RGD

VRMPWRGD

20 55Tuesday, March 27, 2 007

0.4

5

D D

+5VS +3VS

12

R1610

100_0402_5%

C C

10_0402_5%

B B

A A

+3VALW+5VALW

12

R1611

1 2

+1.5VS

CHB1608U301_ 0603

0316 change design

C1223

0.1U_0402_16V4Z

1 2

+1.5VS

CHB1608U301_ 0603

21

D55

CH751 H-40_SC76

20 mils

ICH_V 5REF_RU N

1

C1190

0.1U_0402_16V4Z

2

21

D56

CH751 H-40_SC76

ICH_V 5REF_SUS

20 mils

1

C1200

0.1U_0402_16V4Z

2

R1366

+1.5VS

C1219

0.1U_0402_16V4Z

+3VM

1

+1.5VS

2

R1372

C1211

0316 change design

1 2

5

1

2

1U_0603_10V4Z

C1194

220U_D2_4VM

C1212

1

2

CHB1608U301_ 0603

R1365

C1224

10U_0805_10V4Z

+RTCVCC

1

C1188

2

0.1U_0402_16V4Z

40 mils

1

1

+

C1195

2

2

10U_0805_10V4Z

1

2

10U_0805_10V4Z

+1.5VS

C1220

0.1U_0402_16V4Z

1

2

2.2U_0 603_6.3V4Z

20 mils

1

C1189

2

0.1U_0402_16V4Z

ICH_V 5REF_RU N

ICH_V 5REF_SUS

10U_0805_10V4Z

1

C1196

C1197

2

2.2U_0 603_6.3V4Z

+1.5VS

C1213

1U_0603_10V4Z

+1.5VS

C1216

1U_0603_10V4Z

1

2

VCC_L AN1_05_INT_ICH_1

T30

VCC_L AN1_05_INT_ICH_2

T31

R1371

1 2

1

+1.5VS

CHB1608U301_ 0603

C1225

2

0316 change design

1

2

1

2

1

2

+1.5VS

4.7U_0805_10V4Z

1

C1228

2

+3VS

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AG7

AC10

W23

D28
D29

G24
H23
H24

M24
M25
N23
N24
N25

R24
R25
R26
R27

U24
U25

AE7
AF7

AH7

AC1
AC2
AC3
AC4
AC5

AC9

AA5
AA6

G12
G17

AC7
AD7

G18

G20

A16

T7

G4

E25
E26
E27
F24
F25

J23
J24
K24
K25
L23
L24
L25

P24
P25

T23
T24
T27
T28
T29

V23
V24
V25

Y25

AJ6

AJ7

H7

D1

F1
L6

L7
M6
M7

F17

F19

A24

A26
A27
B26
B27
B28

B25

4

U26F

VCCRTC

V5REF[1]
V5REF[2]

V5REF_SUS

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL

VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]

VCCLAN1_05[1]
VCCLAN1_05[2]

VCCLAN3_3[1]
VCCLAN3_3[2]

VCCGLANPLL

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

CORE

VCCA3 GP ATXARX

VCCP_ COREVCCPS USVCCPU SB

IDE

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[01]

VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB C ORE

VCCSUS3_3[06]

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]

VCC3_3[02]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

+VCCP

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29

AE28
AE29

AC23
AC24

AF29

AD2

AC8
AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12

AD11

J6
AF20

VCCS US1_5_ICH_1

AC16

VCCS US1_5_ICH_2

J7

0.1U_0402_16V4Z

C3

AC18
AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCC L1_05_ICH

G22

A22

F20
G21

0.1U_0402_16V4Z

1

C1193 0. 1U_0402_16V4Z

2

0.01U_0402_16V7K

1

C1198

2

0.1U_0402_16V4Z

+3VS

1

2

0.1U_0402_16V4Z

1

1

C1208

C1209

2

2

0.1U_0402_16V4Z

C1215

+3VALW

1

C1217

2

+3VALW

1

C1222

4.7U_0603_6.3V6M

2

T19

C1229

@

3

1

2

CHB1608U301_ 0603

R1370

1 2

1

C1199 10U_0805_10V 4Z

2

+1.25VS

22U_0805_6.3VAM

C1201

1

2

0.1U_0402_16V4Z

+3VS

(SA TA)

1

2

C1206

+3VS

1

C1210

2

0.1U_0402_16V4Z

+3VALW

1

2

0.1U_0402_16V4Z

1

C1218

2

+1.5VS

0316 change design

0317 change value

+3VS

(DM I)

1

C1205

2

1

C1214

2

04/ 10 mo nit or S B cra ck

+3VS

+VCCP

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

C1202

1

2

101 3 n o i nstal l

121 3 I nsta ll

200 702 27 No insta ll

+3VS

R1716

@

100K_0402_5%

@

RHU002N06_S OT323

13

D

1 2

2

G

Q124

S

2006/02/13 2006/03/10

RHU002N06_S OT323

Compal Secret Data

Deciphered Date

R1717

@

1 2

100K_0402_5%

2

G

Q125

@

C1203

1

2

C1192

+3VM

C1207

T17

T18

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

T28
T29

1

2

0.1U_0402_16V4Z

1U_0603_10V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

0.1U_0402_16V4Z

C1204

1

2

R1718

@

13

D

S

2

1 2

100K_0402_5%

2

G

Q126

@

RHU002N06_S OT323

U26E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

CRAC K_GPIO28CRAC K_GPIO28 CRAC K_GPIO28

13

D

S

Title

Size Doc ument Number Re v

Cus tom

LA -3 26 1P U MA

Date: Sheet of

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

R1719

@

100K_0402_5%

ICH GND1ICH GND2ICH GND4ICH GND3

@

RHU002N06_S OT323

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

1

K7

VSS[099]

L1

VSS[100]

L13

VSS[101]

L15

VSS[102]

L26

VSS[103]

L27

VSS[104]

L4

VSS[105]

L5

VSS[106]

M12

VSS[107]

M13

VSS[108]

M14

VSS[109]

M15

VSS[110]

M16

VSS[111]

M17

VSS[112]

M23

VSS[113]

M28

VSS[114]

M29

VSS[115]

M3

VSS[116]

N1

VSS[117]

N11

VSS[118]

N12

VSS[119]

N13

VSS[120]

N14

VSS[121]

N15

VSS[122]

N16

VSS[123]

N17

VSS[124]

N18

VSS[125]

N26

VSS[126]

N27

VSS[127]

N4

VSS[128]

N5

VSS[129]

N6

VSS[130]

P12

VSS[131]

P13

VSS[132]

P14

VSS[133]

P15

VSS[134]

P16

VSS[135]

P17

VSS[136]

P23

VSS[137]

P28

VSS[138]

P29

VSS[139]

R11

VSS[140]

R12

VSS[141]

R13

VSS[142]

R14

VSS[143]

R15

VSS[144]

R16

VSS[145]

R17

VSS[146]

R18

VSS[147]

R28

VSS[148]

R4

VSS[149]

T12

VSS[150]

T13

VSS[151]

T14

VSS[152]

T15

VSS[153]

T16

VSS[154]

T17

VSS[155]

T2

VSS[156]

U12

VSS[157]

U13

VSS[158]

U14

VSS[159]

U15

VSS[160]

U16

VSS[161]

U17

VSS[162]

U23

VSS[163]

U26

VSS[164]

U27

VSS[165]

U3

VSS[166]

U5

VSS[167]

V13

VSS[168]

V15

VSS[169]

V28

VSS[170]

V29

VSS[171]

W2

VSS[172]

W26

VSS[173]

W27

VSS[174]

Y28

VSS[175]

Y29

VSS[176]

Y4

VSS[177]

AB4

VSS[178]

AB23

VSS[179]

AB5

VSS[180]

AB6

VSS[181]

AD5

VSS[182]

U4

VSS[183]

W24

VSS[184]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

+3VL

+3VS+3VS+3VS

200 702 28 Ch ange to + 3VL

1 2
13

D

1 2

100K_0402_5%

2

G

Q127

S

1

ICH GND1

1 2

R138 0_0402_5%

ICH GND2

1 2

R152 0_0402_5%

ICH GND3

1 2

R153 0_0402_5%

ICH GND4

1 2

R137 0_0402_5%

121 3 n o i nstal l
200 702 27 Inst all

R1715

@

CRAC K_GPIO28 11,31

21 55Tuesday, March 27, 2 007

0.4

5

JP45

conn@

S1

GND

S2

RX+

S3

RX-

S4

GND

TX-

TX+

26

GND

3.3V

3.3V

3.3V
GND
GND
GND

5V
5V
5V

GND

Rsv

GND

12V
12V
12V

boss23boss24GND25GND

OCTEK_SAT-22DD1G

D D

SATA_RXN0

S5

SATA_RXP0

S6
S7

P1
P2
P3
P4
P5
P6
P7
P8

10U_0805_10V4Z

P9
P10
P11
P12
P13
P14
P15

1

C1232

2

0.1U_0402_16V4Z

SATA_TXP0 19

SATA_TXN0 19

1 2
1 2

C4743900P_0402_50V7K
C4753900P_0402_50V7K

clos e SATA c onnector

1

1

C1236

2

2

1000P_0402_50V7K

1U_0402_10V4Z

C1233

0.1U_0402_16V4Z

1

C1234

2

04/ 10 ch ang e fo otpri nt

C C

Kensington Conn

B B

4

SATA_RXN0_C 19
SATA_RXP0_C 19

+5VS

1

C1235

2

061 9 c hang e

110 9 R em ove ke nsin gton circ uit

3

+3V_U43

IDE_RESET#20

PLT_RST_B#

R1036 0_0402_5%

PCI_RST#18,25

R1037 0_0402_5%@

12

12

1 2

C641 0 .1U_0402_16V4Z

14

9

P

A

10

B

G

7

SN74LVC08APW_TSS OP14

MBAY_DET#18

MB_PWR20

RHU002N06_S OT323

+3V_U43

8

O

U43C

4.7K_0402_5%

0.1U_0402_16V4Z

470K_0402_5%

Q38

R301

RR72

C628

R83

2

G

2

12

33_0402_5%

+3VS

12

MBAY_DET#

1

2

+5VS

12

13

D

S

ODD_RST#

1 2

220K_0402_5%

R93

RHU002N06_S OT323

conn@

55

GND

56

GND

57

GND

58

GND

JAE_WM2M054JKB

C640

10U_0805_10V4Z

+5VS_MB

2

G

Q39

Multi Bay II connector

JP5

1

1

2

2

3

3

4

4

ODD_RST#

5

5

PD_D8

6

6

PD_D7

7

7

PD_D9

8

8

PD_D6

9

9

PD_D10

10

10

PD_D5

11

11

PD_D11

12

12

PD_D4

13

13

PD_D12

14

14

PD_D3

15

15

PD_D13

16

16

PD_D2

17

17

PD_D14

18

18

PD_D1

19

19

PD_D15

20

20

PD_D0

21

21

PD_DR EQ

22

22

23

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

+5VS

1

2

1

C633

0.1U_0402_16V4Z

2

12

R98

100_0402_5%

13

D

S

PD_IOR#

24

PD_IOW #

25
26

PD_ IORDY

27

PD_DACK#

28

PD_IR Q

29
30

PD_A1

31
32

PD_A0

33

PD_A2

34

PD_CS#1

35

PD_CS#3

36

MB2_LED#

37
38
39
40
41
42
43
44

MBAY_DET#

45
46
47
48
49
50
51
52
53
54

12

R1032

0_0402_5%

Q92
AO4407_SO8

1
2
3 6

4

+5VS_MB

8
7

5

10U_0805_10V4Z

Place close to JP29

+5VS_MB

1

C626

0.1U_0402_16V4Z

2

ZZZ 2

C624

1

PD_D [0..15] 19

PD_DR EQ# 19

PD_IOR# 19
PD_IOW # 19

PD_ IORDY# 19
PD_DACK# 19
PD_IR Q 19

PD_A1 19

PD_A0 19
PD_A2 19
PD_CS1# 19
PD_CS3# 19
MB2_LED# 19

+5VS_MB

1

2

1

C627

0.1U_0402_16V4Z

2

1

C625

0.1U_0402_16V4Z

2

ZZZ 3

14

12

PLT_RST#7,16,18,30

A A

SN74LVC08APW_TSS OP14

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

P

A

11

O

13

B

G

U43D

7

Compal Secret Data

Deciphered Date

PLT_RST_B#

2

PLT_RST_B# 25,29,30

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Aud io-wire

Compal Electronics, Inc.

HDD & CDROM

LA -3 26 1P U MA

1

PCB-MB

0.4

22 55Tuesday, March 27, 2007

5

4

3

2

1

1128 Ins tall Q102,R17 30, no inst all R1612,Q 104,Q105.

R1612 0_1206 _5%@

+3VM

1000P_0402_50V7K

R1613

D D

LAN_ PHYPC20

ADP_PRES31,3 8,39,40,44

RHU002N06_S OT323

SLP_S3#20,26,27, 31,33,34,4 1,42,43,44

C C

GLAN_CLK19

LAN_R STSYNC19

LAN_TXD019
LAN_TXD119
LAN_TXD219

LAN_RXD019
LAN_RXD119
LAN_RXD219

GLAN_RXP20
GLAN_RXN20

GLAN_TXP20

LED_L INK_LAN#20,24,33
LED_ACT_LAN#24,33

LAN_MDI0P24

LAN_M DI0N24

LAN_MDI1P24

LAN_M DI1N24

LAN_MDI2P24

LAN_M DI2N24

LAN_MDI3P24

LAN_M DI3N24

LAN_KBIAS_P

LAN_KBIAS_N

5

GLAN_TXN20

XTAL1

XTAL2_R

2

C1264

27P_0402_50V8J

1

R16161.4K_0402_1%

1 2

B B

1 2

R1622 649_0402_1%@

1 2

R1623 619_0402_1%@

A A

Y9

1 2

2

C1263

25MHZ_20P_1BG25000CK1A

27P_0402_50V8J

1

1M_0402_5%

2

G

Q104

@

Q105

@

RHU002N06_S OT323

near U 74

R1615 33_0402_5%

1 2

LAN_TXD0
LAN_TXD1
LAN_TXD2

LAN_RXD0
LAN_RXD1
LAN_RXD2

C490 0.1U _0402_16V4Z

1 2
1 2

C1319 0.1U_0402_16V 4Z

LED_L INK_LAN#
LED_ACT_LAN#

LAN_M DI0N

1 2

R1621 0_0402_5%@

clos ed to E6 p in

R1625 1.4K_0603_1%

1 2

R1804
30_0402_5%

1 2

R1614

1 2

100K_0402_5%

13

D

Q103

2

G

BSS138_SOT23

S

13

D

S

13

D

2

G

S

GLANCLK

GLAN_RXP_C
GLAN_RXN_C

GLAN_TXP
GLAN_TXN

LAN_KBIAS_P
LAN_KBIAS_N

LAN_MDI0P

LAN_MDI1P
LAN_M DI1N

LAN_MDI2P
LAN_M DI2N

LAN_MDI3P
LAN_M DI3N

IEEE_TEST_P
IEEE_TEST_N

12

1 2

R1627 100_0402_5%

XTAL2

0104 Intel r equest

1 2

S

D

13

G

SI2301BDS_SOT23

2

2

12

R1730
0_0402_5%

T68 PAD
T70 PAD

+3VM_LAN

Q102

C1243

1

U74

E2

JKCLK-JCLK

E3

JRSTSYNC

D1

JTXD0

F3

JTXD1

F1

JTXD2

D3

JRXD0

D2

JRXD1

C1

JRXD2

H2

GLAN_TXP-NC

J2

GLAN_TXN-NC

J4

GLAN_RXP-NC

H4

GLAN_RXN-NC

G7

KBIAS_P-RBIAS100

H7

KBIAS_N-RBIAS10

A4

LED0-LINK_UP_N

B4

LED1-ACT_LED_N

A5

LED2-SPEED_LED_N

B8

MDI_PLUS[0]-TDP

B9

MDI_MINUS[0]-TDN

D9

MDI_PLUS[1]-RDP

D8

MDI_MINUS[1]-RDN

F9

MDI_PLUS[2]-NC

F8

MDI_MINUS[2]-NC

H8

MDI_PLUS[3]-NC

H9

MDI_MINUS[3]-NC

A7

IEEE_TEST_P-NC

B7

IEEE_TEST_N-NC

J6

RSVD_J6-NC

J7

RSVD_J7-NC

E7

RBIAS_P-NC

E6

RBIAS_N-NC

B5

RSVD_B5-NC

A6

RSVD_A6-ADV10/LAN_DIS_N

C5

RSVD_C5-NC

B6

TEST_EN

RU825 66DM B0 Q870 BGA 81P

4

4.7U_0603_6.3V6M

C1242

1

2

XTAL1
XTAL2

LCI

GLCI

MDI

1 2

R1634 200_0402_5%@

40 mils

+3VM_LAN

H6

XTAL2-X2H5XTAL1-X1

JTAG

JTAG_TCK-ISOL_TCKG1JTAG_TDI-ISOL_TIH1JTAG_TDO-TOUTG3JTAG_TMS-ISOL_EXEC

G2

VSSA[17]-NC
VSSA[16]-NC

VSSA[15]-VSSA2

VSSA[14]-VSS

VSSA[13]-NC
VSSA[12]-VSS
VSSA[11]-VSS
VSSA[10]-VSS
VSSA[09]-VSS
VSSA[08]-VSS
VSSA[07]-VSS
VSSA[06]-VSS
VSSA[05]-VSS
VSSA[04]-VSS

VSSA[03]-VSSR

VSSA[02]-NC
VSSA[01]-VSS

VSS[04]-VSS
VSS[03]-VSSP

VSS[02]-VSS

VSS[01]-NC

VDD1P0[03]-VCCA
VDD1P0[02]-VCCT

VDD1P0[01]-VCCR

VCCF1P0-VCC

VCCFC1P0-VCC

VCC3P3[02]-VCCP

VCC3P3[01]-VCC

VCC1P8[04]-NC
VCC1P8[03]-NC
VCC1P8[02]-NC
VCC1P8[01]-NC

VCC1P0-VCCA2

VCC[02]
VCC[01]

V1P0_OUT-NC

CTRL_10-NC

CTRL_18-NC

THERM_D_P-NC
THERM_D_N-NC

R1629 200_0402_5%@

1 2

PAD
PAD

4.7U_0603_6.3V6M

J9
J8
J5
J3
J1
G9
G8
G6
F6
E9
D6
C9
C8
C7
C6
A9
A8
F4
E1
C4
A1

F7
E8
D7

E5

H3

F2
B3

G5
F5
D5
C2

G4

E4
D4

B1

C3
B2

A2
A3

+3VM_LAN

T69
T71

+V1.0_LAN_M

R1619 0_0603_5%

+3.3V_LAN

+1.8VM_LAN

1 2

+V1.0_LAN_M

V1P_OUT

LAN_CTRL_10
LAN_CTRL_18

LAN_THERM_D_P
LAN_THERM_D_N

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R1618

1 2

0_0603_5%

1 2

C1363 1U _0402_6.3V4Z

R1620 0_0603_5%

1 2

C1364 1U _0402_6.3V4Z

12

R1734 0_0402_5%

V1P_OUT

12

1 2

R1628 0_0603_5%@

3

+3VM_LAN

+1.8VM

+V1.0_LAN_M

+V1.0M_LAN

0620 add for PO WER ripple, close to c hip

2006/02/13 2006/07/26

0620 fix to IV RD

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
C1356

Compal Secret Data

Deciphered Date

2

C1245

C1244

1

0.1U_0402_16V4Z

4.7U_0603_6.3V6M

2

C1250

C1249

1

0.1U_0402_16V4Z

+3VM_LAN

0.1U_0402_16V4Z

2

C1254

1

LAN_CTRL_18

+3VM_LAN +V1.0M_LAN

0.1U_0402_16V4Z

2

1

LAN_CTRL_10

0.1U_0402_16V4Z

2

2

C1247

C1246

1

1

0.1U_0402_16V4Z

2

2

C1251

C1252

1

1

470P_0402_50V7K

2

C1255

1

C1258

BCP69_SOT223

2

C1357

1

C1360

2

2

1

470P_0402_50V7K

20 mils

2

1

Q106

BCP69_SOT223

3

1

1

2

10N_0603_50V7K

Q128

3

1

1

2

10N_0603_50V7K

20 mils

+1.8VM

2

470P_0402_50V7K

C1248

1

+V1.0_LAN_M

2

470P_0402_50V7K

C1253

1

+1.8VM

4
2

C1256

0.1U_0402_16V4Z

4
2

0.1U_0402_16V4Z

10U_0805_10V4Z

C1257

1

2

2

1

10U_0805_10V4Z

2

1

1

2

C1358

Title

Size Doc ument Number Re v

Date: Sheet of

0905

0905

C1359

Compal Electronics, Inc.

Intel 82566 Nineveh

LA-3261P UMA

1

23 55Tuesday, March 27, 2 007

0.4

5

LAN_M DI0N

+1.8VM

LAN_MDI0P

TRM_CT

12

C330

0.1U_0402_16V4Z

D D

C327

0.1U_0402_16V4Z

C328

0.1U_0402_16V4Z

C329

0.1U_0402_16V4Z

LAN_M DI1N

LAN_MDI1P

TRM_CT

12

LAN_M DI2N

LAN_MDI2P

TRM_CT

12

LAN_M DI3N

LAN_MDI3P

TRM_CT

12

T66

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

24HST1041A-3_24P

13

MX4-

1:1

1:1

1:1

1:1

MX4+

MCT4

MX3-

MX3+

MCT3

MX2-

MX2+

MCT2

MX1-

MX1+

MCT1

14

15

16

17

18

19

20

21

22

23

24

MDO0-

MDO0+

MCT0

MDO1-

MDO1+

MCT1

MDO2-

MDO2+

MCT2

MDO3-

MDO3+

MCT3

4

RJ-45 CONN.

R269

12

75_0402_1%

R270

12

75_0402_1%

R271

12

75_0402_1%

12

C320

1 2

1000P_1808_3KV7K

R272

75_0402_1%

C344

1 2

1000P_1808_3KV7K

3

LAN ENERGY DET

02/27 change

C1266 0.01U_0402_16V7K

LAN_MDI0P

LAN_MDI1P

C1267 0.01U_0402_16V7 K

CAP close d to LAN_MD IO bus

R55

1 2

12

10K_0402_5%

R69

1 2

12

10K_0402_5%

100K_0402_5%

2

1

0612 CHANGE

+3VM

100K_0402_5%

10P_0402_50V8J

12

R1638

1

C1268

2

12

R1635

ED_ACT

ED_VR EF

12

R1639

1.87K_0402_1%

200K_0402_5%

12

R1636

@

1.5K_0402_5%

5

U75

1

P

IN+

O

3

IN-

G

2

LMV33 1IDCKRG4_SC70-5~D

12

R1637

4

1 2

1

2

R51 0_0402_5%

C1265

0.1U_0402_16V4Z

ENER GY_DET 19

1113 Cha nge R 1639 to 1.4 K based on Intel WW44

1116 Intel r ecommend

0809 add fo r EMI reque st

R50 49.9_0402_1%

C560.1U_0402_16V4Z

C C

1 2

1 2

1 2

1 2

La yout Noti ce : Plac e
te rm ina tio n as clo se as
In tel 825 66 a s p os sible

1 2

R63 49.9_0402_1%

1 2

C540.1U_0402_16V4Z

R45 49.9_0402_1%

1 2

R48 49.9_0402_1%

1 2

C500.1U_0402_16V4Z

C490.1U_0402_16V4Z

R42 49.9_0402_1%

1 2

R44 49.9_0402_1%

1 2

R40 49.9_0402_1%

1 2

R41 49.9_0402_1%

1 2

LAN_MDI0N 23
LAN_MDI0P 23
LAN_MDI1N 23
LAN_MDI1P 23
LAN_MDI2N 23
LAN_MDI2P 23
LAN_MDI3N 23
LAN_MDI3P 23

MDO3-

MDO3+

D72

@

1 5

2

APL5301-18BC-TRL_SOT23-5

MDO2+

MDO2-

43

Note: M DO[ 3..0]+/- s ignals sho uld route to JP4 first then to JP30.

D73

+3VM_LAN_LED

LED_ACT_LAN#23,33

B B

+3VM_LAN_LED

LED_L INK_LAN#20,23,33

LED_ACT_LAN# LED_LINK_LAN#

2

1

A A

R266 300_0402_5%

MDO3-33

MDO3+3 3

MDO1-33

MDO2-33

MDO2+3 3

MDO1+3 3

MDO0-33

MDO0+3 3

R265 300_0402_5%

C1368

@

300p_0402_25V

1115 EMI REQUE ST

5

LED_L INK_LAN#

2

C1369

@

300p_0402_25V

1

12

LED_ACT_LAN#

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

12

JP4

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX_JM36113-P1122-7F

conn@

SHLD1

DETECT PIN1

DETCET PIN2

SHLD1

16

9

1

C579

0.1U_0402_16V4Z

2

10

15

+3VM_LAN +3VM_LAN _LED

S

12

R525

100K_0402_5%

PREP#20,26,33

RHU002N06_S OT323

2

G

Q61

4

CABLE_DETECT 20

20 mils

D

13

Q60

G

AO3413_SOT23

2

13

D

S

@

MDO1- MDO0-

1 5

2

MDO0+MDO1+

43

APL5301-18BC-TRL_SOT23-5

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA -3 26 1P U MA

1

24 55Tuesday, March 27, 2 007

0.4

A

B/B connector with PCI / LED / FIR / SC interface

XTPA0-28
XTPA0+28

CLK_P CIE_Rob#15
CLK_P CIE_Rob1 5

PCIE_RXN420

PCIE_RXP420

1 1

HDD_H ALTLED#20

2 2

+3VL

WL_BLUE_LED#30,32
GREEN_BATLED#19,31
AMBER_BATLED#31
LED_STB#31, 32,33
IDE_LED#19

+1.5VS

+3VS

+5VS

CLK_PCI_PCM15

PM_CLKRU N#20,29,30,31

PCIE_RXN4
PCIE_RXP4

PCIE_TXN420

PCIE_TXP420

PCI_CBE #318

PCI_CBE #218
PCI _IRDY#18

PCI_S ERR#18,31
PCI_P ERR#18

PCI_CBE #118

R37 0_0402_5 %

R36 0_0402_5 %

XTPA0-

XTPA0+

CLK_P CIE_Rob#
CLK_P CIE_Rob

12
12

PCIE_TXN4
PCIE_TXP4

CLK_PCI_PCM
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_CBE #3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_CBE #2
PCI _IRDY#
PM_CLKRUN#
PCI_S ERR#
PCI_P ERR#
PCI_CBE #1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1

HDD_H ALTLED#

WL_BLUE_LED#
GREEN_BATLED#
AMBER_BATLED#
LED_STB#
IDE_LED#

NF_RXN
NF_RXP

0731 Ins tall R13 83 and n o install R 1382, do no t support w ake on WWAN card

0811 Iso late SLOT power from SYSTEM power.

Mini-Express Card--WWAN

+3VALW

1

C959

3 3

2

0.1U_0402_16V4Z

+3VS_WWAN

1 2

R1071 0_0603_5%

1 2

R1073 0_0603_5%

0821 Chan ge +3VS to +3VS_WWAN

0811 Pins 37 and 43 connect to GND and remove +1.5VS

4 4

JP46

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

MOLEX 67910-0002 52P

conn@

+3VS

R1779

1 2

0_1206_5%

2
4
6
8
10
12
14
16
18

M_WXMIT_OFF#

20
22
24
26
28
30
32
34
36
38
40

WW_LED#

42
44
46
48
50
52

54

WXMIT_OFF#20

JP13

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990

91

91

93

93

95

95

97

97

99

99

101

GND

ACES_88394-1A71

+3VS_WWAN

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

1 2

R1382 0_0402_5% @

1 2

R1383 0_0402_5%

USB20_N8 20
USB20_P8 20

WW_LED# 30

D66

21

CH751 H-40_SC76

2

2

4

4

6

6

8

8

10

10

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

92

94

94

96

96

98

98

100

100

102

GND

0.01U_0402_16V7K

1

C295

2

UIM_VPP UIM_RST
UIM_DATA

M_WXMIT_OFF#

+3VALW

+3VS_WWAN

B

XTPB0­XTPB0+

PCI_P IRQG#
PCI_P IRQD#
PCI_R EQ2#
PCI_PLTRST#
CLKREQ#_E
PCI_P IRQE#
PCI_P IRQC#
PCI_RST#
PCI_GNT2#
SIRQ
PWR _GD
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCM_SPK
PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16
PCI_FRAME#
PC I_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11
PCI_AD9
PCI_CBE #0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

IRRX
IRTXOUT
IRMODE

SC_CD #

SC_CLK
SC_RST

SC_DATA

PC I_AD[0..31 ]

1

C540

2

0.1U_0402_16V4Z

S DIO(B R) NUP4301MR6T1 TSOP-6

4
5
6
7

R1780

@

10K_0402_5%

1 2

UIM_PWR

PCI_PLTRST# 18

PCI_RST# 18,22

4.7U_0805_10V4Z

C544

U72

1

CH1

2

Vn

CH23CH3

JP50

JP?

GND
VPP
I/O
DET

TAITW_PMPAT6-06GLBS7N14N0

0620 Upda te ROBSON S CHEMATIC
0824 add 13 94 signals

XTPB0- 28
XTPB0+ 28

PCI_R EQ2# 18

PCI_P IRQE# 18
PCI_P IRQC# 18

PCI_GNT2# 18
SIRQ 20,29 ,30,31
PWR _GD 20 ,31,34,35,43,44

PCM_SPK 26

PCI_PAR 18

PCI_FRAME# 18
PCI_ TRDY# 18
PCI_STOP# 18
PCI_DEV SEL# 18

PCI_CBE #0 18

IRRX 29
IRTXOUT 29
IRMODE 29

SC_CD # 28

SC_CLK 28
SC_RST 28

SC_DATA 28

0830 Change 1394 signa ls

PCI_P IRQG# 18
PCI_P IRQD# 18

CLKREQ#_E 15

+3VS

+SC_PWR

PCI_ AD[0..31] 18

+3VS_WWAN

1

2

6

CH4

5

Vp

4

1

VCC

2

RST

3

CLK

8

GND

9

GND

C

0622 chan ge to suppo rt AMT

+3VS

+3VS

D13

@

UIM_PWR

UIM_CLK

C554

4.7U_0805_10V4Z

1

DAN217_SC5 9

1

1

C960

2

2

0.1U_0402_16V4Z

Mini-Express Card---WLAN

0.1U_0402_16V4Z

1

C538

2

4.7U_0805_10V4Z

ICH_P CIE_WAKE#20

CLK_P CIE_MCARD#15

CLK_P CIE_MCARD15

CLK_DEBU G_PORT15,30

0821 Chan ge +3VS to +3VS_WLAN

+3VS_WLAN

1

C542

2

CH_DATA28

CH_CL K28

CLKREQ#_G15

PCIE_RXN220
PCIE_RXP220

PCIE_TXP220

CL_CLK120
CL_DATA120
CL_RST#120

0627 PIN 37,43 conn ected to GN D
PIN3 9,41 connected t o +3VS

0811 No install R1418,R135 8,R1359,R13 60

0906 Remo ve debug re sistors

ACCELEROMETER

ACCE L_INT18

ICH_SM_DA4,20

3

2

+3VS_ACL_IO +3VS_ACL

ICH_SM_CLK4,20

+3VS_ACL

0619 Follow ST Demo circuit

0.01U_0402_16V7K

1

C293

2

ICH_P CIE_WAKE#
CH_DATA
CH_CL K

1 2

CLK_P CIE_MCARD#
CLK_P CIE_MCARD

R1336 0_0402_5%

0906 Remo ve debug re sistors

R1348 0_0402_5%

1 2

PCIE_RXP2

1 2

R1349 0_0402_5%

PCIE_TXN2
PCIE_TXP2

R197 0_0402_5%
R195 0_0402_5%
R194 0_0402_5%

0313 change design

10K_0402_5%

R1359

R1391

0_0402_5%

12
12
12

+3VS +3VS_ACL

2 1

CH751 H-40_SC76

U64

1

2

3

4

5

12

6

7

8

Mus t b e p lac ed in the c ent er of the sys tem.

1 2

D

C294

0.1U_0402_16V4Z

CLKREQD#_M C

PCIE_C_RXN 2PCIE_RXN2
PCIE_C_RXP2

+3VS_WLAN

XMIT_OFF20

R1355

1 2

0_0805_5%@

D64

INT/RDY

SDD

SDA/SDI/SPC

VDD_IO

SCL/SPC

CS

NC

CK

+1.5VS_WLAN

4.7U_0805_10V4Z

1

2

C533

JP44

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

MOLEX 67910-0002 52P

D74

CH751 H-40_SC76

0811 HP reques t

R1356

1 2

0_0603_5%

16

GND

15

RES

14

GND

13

VDD

12

RES

11

VDD

10

RES

9

GND

LIS3LV02DL-TR _LGA16

1

0.1U_0402_16V4Z

2

conn@

0821 Install R1364

2
4
6
8
10
12
14
16
18

XMIT_OFF#

20
22
24
26
28
30
32
34
36
38
40

WW_LED#_R

42

WL_LED#

44

WP_LED#_R

46
48
50
52

54

10K_0402_5%@

21

RHU002N06_S OT323@

+3VS_ACL_IO

0.01U_0402_16V7K@

1 2

1 2

0_0402_5%

R1357

1 2

E

0824 Add +1. 5VS_WLAN

0811 Iso late SLOT power from SYSTEM power.

1

2

+3VS

+1.5VS

+3VS_WLAN

+1.5VS_WLAN

1 2

0_1206_5%

+1.5VS_WLAN

R1785

1 2

0_1206_5%

+3VS_WLAN

R1778

+3VALW

C954

0906 Remo ve debug re sistors

R1364 0_0402_5%@

0_0402_5%

1 2
1 2

R1363

0612 change power plan e

WW_LED#

1 2

WP_LED#

1 2

0627 Add 0 ohm on PI N 42,46

+3VALW

12

R517

12

R516

Q58

R1422 0_0402_5%

R1361

0_0402_5%

R1362

2

G

1 2

C994

100K_0402_5%@

XMIT_OFF#

13

D

S

1

C995

2

0.1U_0402_16V4Z

+3VS_ACL

PLT_RST_B# 22,29,30
+3VALW
+3VM

ICH_SMB_CLK 20
ICH_SMB_DATA 20PCIE_TXN220

WW_LED# 30

WL_LED# 30

WP_LED# 30

+3VS_ACL

1

1

2

2

C996

10U_0805_10V4Z

R1754

@

0_0402_5%

R1755

@

0_0402_5%

0619 Follow ST Demo circuit

0_0402_5%

+3VS_ACL_IO

0811 Reserve for SIM card does not meet rise time and a pull-up resistor is needed.

0821 Del ete SW1,C 986,R521,D6 5,R200

A

0116 Connected R1780.1 to UIM_PWR

B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Accelerometer

LA -3 26 1P U MA

25 55Tuesday, March 27, 2007

E

0.4

A

B

C

D

E

F

G

H

VDDA _CODEC

12

R329

10K_0402_5%

C390

1 2

13

D

0.1U_0402_16V4Z

2

PCM_SPK25

1 1

SB_SPKR20

2 2

Q35

RHU002N06_S OT323

Q68

RHU002N06_S OT323

Plac e close to U14

R1400

0_1206_5%

C409 0.1U _0402_16V4Z

C427 0.1U _0402_16V4Z

C431 0.1U _0402_16V4Z

G

VDDA _CODEC

2

G

12

12

12

12

S

12

R350

10K_0402_5%

13

D

0.1U_0402_16V4Z

S

C396

1 2

GNDAGND

DLINE _IN_L33

DLIN E_IN_R33

3 3

SENSE_A

4 4

R980

0_0402_5%@

1 2

SENSE_B

A

011 5 R37 0, R36 9 - change fr om 4.7k to 6.04k
R3 74, R3 75 - cha nge from 4.7k to 2. 00k

VDDA _CODEC

1 2

2

1

R341

1 2

150K_0402_1%

R359

1 2

150K_0402_1%

R370 6.04K_0402_5%
R375 2K_0402_5%
R369 6.04K_0402_5%
R374 2K_0402_5%

R969

2.67K_0402_1%

1 2

R970 39.2K_0402_1%

1 2

R972 20K_0402_1%

1 2

R973 10K_0402_1%

C977

1U_0402_6.3V4Z@

1 2

1 2

2N7002_SOT23

B

10K_0402_5%

R330

INT_MIC27

12

12

062 0 cha nge

SENSE_A_C

Q97

12

SENSE_A_A 27

SENSE_A_B 27

13

D

S

MONO_IN

1 2

C430 0.1U_0402_16V4 Z

2

C377

0.01U_0402_16V7K

1

0316 change

V_CODEC +3VS

1 2

INT_MIC

DLINE _IN_R_L

DLINE _IN_R_R

MIC127

MIC227

VDDA _CODEC

HDA_R ST#_CODEC19

HDA _SYNC_COD EC19

HDA_S DOUT_CODEC19

2

G

R988

1 2

100K_0402_5%

VDDA _CODEC

0_0603_5%

R159

1

C147

C395

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C425 1U_0603_10V4Z

1 2

C426 1U_0603_10V4Z

1 2

C423 1U_0603_10V4Z

1 2

C422 1U_0603_10V4Z

1 2

MIC2 MIC2_C

R231 2.2K_0402_1%

R169 0_0402_5%@

EAPD27,31

VDDA _CODEC

R974

0_0402_5%@

1 2

LINE_ IN_SENSE

1

C978

0.1U_0402_16V4Z

2

C

0.1U_0402_16V4Z

1

C417

2

1 2

C204 1U_0603_10V4Z

1 2

C205 1U_0603_10V4Z

1 2

1 2

L53
FBM-L10-160808-301-T_0603

T22 PAD

1

C148

2

T24 PAD

T21 PAD

DLINE _IN_RC_L

DLIN E_IN_RC _R

T23 PAD

T25 PAD

T26 PAD

MIC1_CMIC1

SENSE_A

SENSE_B

1 2

LINE_ IN_SENSE 33

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

C402

+5VAMP

1

+

2

C548

22U_B_10V

2

C552

1U_0603_10V4Z

1

080 9 Add an ti-po p cir cuit

2

1

D

38

U14

AVDD125AVDD2

14

AUX_L

15

AUX_R

16

MIC3

17

MIC4

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSEA

34

SENSEB

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

AD198 1HDJSTZ-REEL_LQFP48

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

MONO_OUT

HP_LOUT_L

HP_LOUT_R

BIT_CLK

SDATA_IN

GPIO_0
GPIO_1
GPIO_2
GPIO_3

VREF

MIC_BIAS_B

MIC_BIAS_C

MIC_BIAS_F

MIC_BIAS_D

PCBEEP

AVSS1
AVSS2

N/C
N/C
N/C

NC
NC

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SLP_S3#20,23,27, 31,33,34,4 1,42,43,44

2

C551
100P_0402_50V8J

1

1 2

R258

0_0805_5%

U18

1

IN

5

OUT

3

EN

4

ADJ

2

GND

MIC5205BM5_SOT23-5

0.01U_0402_16V7K

Plac e R2 58 be tween DGND & AGND & cl ose to U14

C1366

@

1 2

R1761

@

1 2

+5VS

300K_0402_5%

R1762

@

1 2

+3VS

10K_0402_5%

R1399

LINE_OUTL 27

LINE_ OUTR 27

PAD

L_HP 27

R_HP 27

12

1 2

1K_0402_5%

@

C1064

F

HDA_RST#_MDC19,32

0.1U_0402_16V4Z

9

35

36

37

39

41

6

8

43
44
2
3

27

28
29
30
32
12

31
33
40
45
46

26
42

2005/05/26 2006/07/26

+3VS_CODEC

1

1

C156

C175

2

2

0.1U_0402_16V4Z

LINE_OUTL

LINE_ OUTR

L_HP

R_HP

R1038 33_0402_5% @

HDA_S DIN0_CODE C

R168 4.7K_0402_5%@

1 2

R167 4.7K_0402_5%@

1 2

R136 10K_0402_5%

1 2

R32 4.7K_0402_5%@

1 2

AUD_R EF

T27
T13
T12
T11

MONO_IN

T7 PAD
T8 PAD
T10 PAD
T6 PAD
T9 PAD

PAD
PAD
PAD
PAD

1

2

12

C393
10U_0805_10V4Z

T20

33_0402_5%

1 2

0_0805_5%

HDA_B ITCLK_CODEC 19

R373

Compal Secret Data

Deciphered Date

E

V_CODEC

2

C553

1

4.7U_0603_6.3V6M

13

D

2

G

S

1

R1763

2

1 2

HDA_S DIN0 19

PORT_A_SNS 27

PREP# 20,24,33

1

C424

1U_0603_10V4Z

2

12

R456

49.9K_0402_1%

12

R457

143K_0402_1%

RHU002N06_S OT323

Q137

@

C1367

0.47U_ 0402_6.3V4Z

@

10P_0402_25V8K@

1

C416

0.1U_0402_16V4Z

2

1

1

+

C309

C307

22U_B_10V

@

R1758

Title

0.1U_0402_16V4Z

2

R1759

0_0402_5%

D

D

12

D

S

S

Q136

G

RHU002N06_S OT323

G

2

2

G

2

2

G

RHU002N06_S OT323

D

S

S

12

R1765

0_0402_5%

PLACE TO

X

HP O UT, DOCK HP LO

M/B MI C

DOCK L I

M/B SP K

X

Inter nal MIC

12

@

12

R1764

10K_0402_5%

@

1 3

Q135RHU002N06_S OT323

@

Q138

1 3

PORT

MONO_O UT

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

Compal Electronics, Inc.

AC97 CODEC AD1981B

LA -3 26 1P U MA

G

13

@

Q139

@

13

10K_0402_5%

R1760

@

1 2

1 2

R1766

10K_0402_5%

@

HP_R_ JACK 27R_C_H P27

HP_L_JACK 27L_C_HP27

26 55Tuesday, March 27, 2 007

H

2

10K_0402_5%

RHU002N06_S OT323

Size Doc ument Number Re v

Date: Sheet of

0.4

A

B

C

D

E

AMP. FOR INTERNAL SPEAKER

+5VALW

R443

1

2

LINE_ C_R_OUTR

LINE_ C_R_OUTLLINE_C_OUTL

R1407

12

0_0402_5%

13

D

2

G

S

2

G

Q32

1 2

0_1206_5%

@

150U_D_6.3VM

13

D

S

C1098

10U_0805_10V4Z

1 1

C503

LINE_ C_OUTR

LINE_ OUTR26

LINE_OUTL26

0620 change

2 2

1 2

0.1U_0402_16V4Z

C502

1 2

0.1U_0402_16V4Z

MUTE_LED#

EAPD26,31

A_SD31

SLP_S3#20,23,26, 31,33,34,4 1,42,43,44

10 dB

R1410

1 2

10K_0402_5%

R1411

1 2

10K_0402_5%

10 dB

R430 10K_0402_5%

1 2

12

R1421 0_0402_5%@

Q28

RHU002N06_S OT323@

RHU002N06_S OT323

Place close to U14 audio CODEC

VDDA _CODEC

12

R995

100K_0402_5%

PORT_A_SNS26

SENSE_A_A26

RHU002N06_S OT323

3 3

1116 Cha nge R261 and R253 to 56.2 ohm
2007 0227 Change R261 and R 253 to 60.4 ohm

J_R_HP

J_L_HP

4 4

DOCK_HPS#33

+

1 2

C577 150U_D_6.3VM

+

1 2

C581 150U_D_6.3VM

U73

S DIO(B R) NUP4301MR6T1 TSOP-6@

L_SPK+
L_SPK­R_SPK+
R_SPK-

1

C506

100P_0402_50V8J

2

R_C_H P

L_C_HP

1

2

100P_0402_50V8J

C514

13

D

Q49

S

0.1U_0603_16V4Z

HP_R_ JACK26

J_DLIN E_OUT_R
J_DLIN E_OUT_L

HP_L_JACK26

Plac e close to JP24

R_C_H P 26

L_C_HP 26

6

CH1

CH4

5

Vn

Vp

4

CH23CH3

1

1

C507

2

2

100P_0402_50V8J

A

13

D

S

2

G

C527

JP21

1

1

2

2

3

3

4

4

1

C518

E&T_3801-04

100P_0402_50V8J

2

Q48
RHU002N06_S OT323

2

G

VDDA _CODEC

D

Q44

1

2

+3VS

conn@

S

RHU002N06_S OT323

R261

1 2

60.4_0805_1%

R253

1 2

60.4_0805_1%

R445

1K_0402_1%

conn@

ACES_87213-0600

Place close to JP15

12

R423

100K_0402_5%

13

2

G

R_CR_ HP

L_CR_H P

12

12

R446

1K_0402_1%

JP27

1

1

2

2

3

3

4

4

5

5

6

6

4.7U_0805_10V4Z

CHB1608B121_0603

J_MIC_SENSE

+5VAMP

1

+

C662

2

5

INR

1

INL

4

MUTE

14

SHDN

C493

1

C536

2.2U_0 603_6.3V4Z

2

CHB1608B121_0603

1 2

L52

L51

1 2

470P_0402_50V7K

J_MIC1

J_MIC2

J_MIC _REF

12

8

18

VDD

PVDD1

PVDD2

PGND1

PGND211PGND315PGND4

6

20

VDDA _CODEC

12

R426

47K_0402_5%

12

2

R428

47K_0402_5%

1

R255

1 2

100K_0402_5%

R_CRL _HP

L_CRL_H P

C563

B

C659
10U_0805_10V4Z

1

C660

2

BIAS

NC1
NC2
NC3
NC4

12

R251

100K_0402_5%

1

C526

1U_0603_10V4Z@

2

1

2

1

2

2

R1405

R_SPK+

7

R_SPK-

9

R1406

L_SPK+

19

L_SPK-

17

3
10
13
16

VDDA _CODEC

8

5

P

+

6

-

G

TLV2462_SO8

4

DLINE_OUT_L

C564

470P_0402_50V7K

1

2

1U_0603_10V4Z

U39

OUTR+

OUTR-

OUTL+

OUTL-

PGND5

MAX9710ETP_QFN20

21

VDDA _CODEC

1

2

Place close to JP24

JP28

conn@

1

1

2

2

3

3

4

4

5

5

6

ACES_87213-0600

6

C539

0.1U_0402_16V4Z

1 2

15K_0402_5%

1 2

15K_0402_5%

MIC_RE F

7

O

U27B

1 2

Ke ep 1 0 mil w idt h

LINE_ C_R_OUTR

10 dB

LINE_ C_R_OUTL

10 dB

C471

1 2

1

2

R978

100_0402_5%

1 2

MIC126

MIC226

MIC_RE F

R_HP26
L_HP26

VDDA _CODEC

C982

4.7U_0805_10V4Z

MIC_SENSE

C1044 1U_0603_10V4Z

DLINE _OUT_L33
DLINE _OUT_R33

02/27 change

5

4

3
6
2
1

SUYIN_0 10030FR006G101Z L_6P

J_R_HP
J_L_HP

J_DLIN E_OUT_L
J_DLIN E_OUT_R

J_VDD A_CODEC

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.01U_0402_16V7K

conn@

MIC1

1
2

MIC2

3
4
5
6

R_HP

7

L_HP

8

9
10
11
12

ACES_87213-1200

JP24

8
7

conn@

Plac e close to U14

Issued Date

AMP. FOR INTERNAL MICROPHONE

Place close to U14 audio CODEC

conn@

JP36

INT_MIC_2

1
2

ACES_85205-0200

VDDA _CODEC

R196

1 2

3K_0402_5%

AMP. FOR EXTERNAL MICROPHONE

D62

2

3

@

PACDN042_SOT23~D

C585

1 2

1200P_0402_50V7K@

R193

1 2

C226

1

4.7U_0805_10V4Z

2

1

3K_0402_5%

HLC06 03CSCCR11JT_0603

C231

INT_MIC_3INT_MIC_1 INT_MIC_4

1 2

0.22U_0603_10V7K

1 2

68P_0402_50V8J

Place close to JP15

JP9

1
2
3
4
5
6
7
8
9
10
11
12

C

0.22U_0603_10V7K

J_VDD A_CODEC

47K_0402_5%

C492

0.22U_0603_10V7K

Q50

J_VDD A_CODEC

C276

EXT_MICA_1

1 2

12

R427

12

2

R429

47K_0402_5%

1

C275

EXT_MICB_1

1 2

VDDA _CODEC

13

D

2

G

S

Compal Secret Data

EXT_MICA

4.7U_0805_10V4Z

EXT_MICB

SENSE_A_B26

RHU002N06_S OT323

2005/05/26 2006/07/26

L58

1 2

HLC06 03CSCCR10JT_0603

R1424 0_0402_5%

R1423 0_0402_5%@

L61

1 2

HLC06 03CSCCR10JT_0603

R979
47K_0402_5%

1 2

MIC_SENSE

2

C984

0.1U_0402_16V4Z

1

R418

1 2

470_0402_5%

1 2

R425

470_0402_5%

C487

10U_0805_10V4Z

Deciphered Date

12

12

1

1

2

2

1

2

R424

3.9K_0402_1%

1 2

1 2

R421

3.9K_0402_1%

C486

10U_0805_10V4Z

D

C572

1

68P_0402_50V8J

2

JJ_MIC _REF

J_MIC _REF

C575
68P_0402_50V8J

EXT_MICB

EXT_MICA

L57

C571

R211

1 2

10K_0402_5%

R210

1 2

10K_0402_5%

C230

1 2

680P_0402_50V7K

R190

MIC_RE F

C446

R388

1 2

1

10K_0402_5%

2

JJ_MIC _REF

C249

EXT_MICA_2

JJ_MIC _REF

C248

EXT_MICB_2

1 2

L46

CHB1608B121_0603

1 2

L47

CHB1608B121_0603

470P_0402_50V7K

100P_0402_50V8J

J_VDD A_CODEC

1

2

100P_0402_50V8J

3

2

1

2

100P_0402_50V8J

5

6

1

C470

0.1U_0402_16V4Z

2

J_MIC_SENSE

C508

Title

Size Doc ument Number Re v

Date: Sheet o f

VDDA _CODEC

1

2

+

-

J_VDD A_CODEC

+

-

1

2

3

2

U46A

8

TLV2462_SO8

P

1

O

G

4

U46B

8

TLV2462_SO8

P

7

O

G

4

1

C522

470P_0402_50V7K

2

8

+

-

4

100P_0402_50V8J

100P_0402_50V8J

Compal Electronics, Inc.

AMP & Audio Jack

LA -3 26 1P U MA

1 2

100K_0402_5%

1

C441

2

0.1U_0402_16V4Z

U27A

TLV2462_SO8

P

INT_MIC

1

O

G

C488

1 2

R413

1 2

100K_0402_5%

J_MIC1

C489

1 2

R414

1 2

100K_0402_5%

J_MIC2

5

4

3
6
2
1

SUYIN_0 10030FR006G101Z L_6P

E

INT_MIC 26

27 55Tuesday, March 27, 2 007

conn@

JP15

8
7

0.4

5

4

3

2

1

Left side USB CONNECTOR 0

Left side USB CONNECTOR 1

USB_VCCA

U57

1

GND

2

D D

4.7U_0805_10V4Z

S4_STATE30

C550

S4_STATE

1

2

IN

3

IN

4

EN#

G548A2P1U

0621 change

OUT
OUT
OUT
OC#

8
7
6
5

R163

1

+

C567

2

150U_D_6.3VM

1 2

10K_0402_5%

Right side USB CONNECTOR 0

+5VALW

C C

1

C558

4.7U_0805_10V4Z

2

S4_STATE#20

RHU002N06_S OT323

S4_STATE

Q132

1
2
3
4

2

G

U65

GND

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGN_MSOP8~N

+5VALW

12

10K_0402_5%

R1

13

D

S

0621 change

8
7
6
5

R164

1

+

C569

2

150U_D_6.3VM

1 2

10K_0402_5%

W=60mils

1

2

C517

W=100mils

1

2

USB_V CCC

1

2

0.1U_0402_16V4Z

+5VALW

USB_VCCA+5VALW

1

C515

2

0.1U_0402_16V4Z

+5VALW

PJDLC05_SOT23~D

C521

1000P_0402_50V7K

C519

1000P_0402_50V7K

USB20_N4

D52

USB20_N020
USB20_P020

USB20_N420
USB20_P420

3

2

1

USB20_N4

1 2

USB20_P4

1 2

1 2

0_0805_5%

R1790

USB20_N0_R

1 2

USB20_P0_R

1 2

USB20_P0
USB20_N0

PJDLC05_SOT23~D

R6040_0603_5%

USB20_P4_R

R6050_0603_5%

0904 EMI reque st

R6170_0603_5%

1
2
3

R6140_0603_5%

4
5
6
7
8

2

3

D61

1

JP23

conn@

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_0 20173MR004S558ZL

JP26

conn@

1
2
3
4
GND
GND
GND
GND

SUYIN_0 20173MR004S558ZL

JP25

conn@

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_0 20173MR004S558ZL

R1792

1 2

0_0805_5%

1 2

0_0805_5%

R1791

1394 connector

USB20_N5_R
USB20_P5_R

1 2
1 2

1101 update EMI reques t

XTPB0-25
XTPB0+25
XTPA0-25
XTPA0+25

XTPB0+
XTPA0­XTPA0+

R6060_0603_5%

USB20_N5U SB20_N4_R
USB20_P5

R6070_0603_5%

USB20_N5 20
USB20_P5 20

USB20_P5
USB20_N5USB20_P4

PJDLC05_SOT23~D

D51

1 2
1 2
1 2
1 2

2

3

1

conn@

JP19
R16960_0402_5%
R16970_0402_5%

R16980_0402_5%
R16990_0402_5%

R_XTPB0-XTPB0­R_XTPB0+
R_XTPA0­R_XTPA0+

1

XTPB0-

2

XTPB0+

3

XTPA0-

4

XTPA0+

5

GND

6

GND

7

GND

8

GND

AMP_440168-2

JP22

conn@

B B

SMART Card connector

JP3

conn@
1
2
3
4
5
6
7
8
9

10

A A

5

11

1

11

12

2

12

13

3

13

14

4

14

15

5

15

16

6

16

17

7

17

18

8

18

19

9

19

20

10

20

ACES_85203-1002

SC_CLK
SC_RST

SC_CD #

SC_DATA

SC_CLK 25

SC_RST 25
+SC_PWR
SC_CD# 25

SC_DATA 25

4

+SC_PWR

1

2

C367

0.1U_0402_16V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

BT Connector

2006/02/13 2006/07/26

1
2
3
4
5
6
7
8

ACES_87212-0800

1

C306

1U_0603_10V4Z

2

BT_OFF20

Compal Secret Data

USB20_P6_R
USB20_N6_R

R458 1K_0402_5%@

1 2

R459 1K_0402_5%@

1 2

0612 no instal l

12

R518

100K_0402_5%

R454

1 2

47K_0402_5%

Deciphered Date

R562

0_0402_5%

12

0_0402_5%

12

R586

3

Q51 SI2301BDS_SOT23

S

D

13

G

2

0.01U_0402_16V7K

C556

1 2

0.1U_0402_16V4Z

2

+3VAUX_BT

USB20_P6
USB20_N6

BT_LED 30
CH_DATA 25

CH_CLK 25

2

D53

PACDN042_SOT23~D@

1

1

1

C546

C545

0.1U_0402_16V4Z

2

2

USB20_P6 20
USB20_N6 20

+3VAUX_BT+3VALW

1

C549

4.7U_0805_10V4Z

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

USB & BT Connector

LA -3 26 1P U MA

28 55Tuesday, March 27, 2 007

1

0.4

A

B

C

D

E

1 1

DCD#1
RI#1
CTS#1
DSR#1

4.7K_1206_8P4R_5%

IRRX

R76
1K_0402_5%

LPC_AD019 ,30,31
LPC_AD119 ,30,31
LPC_AD219 ,30,31

RP6

SIO_GPIO12

18

SIO_GPIO10

27

SIO_GPIO44

36

SIO_GPIO43

2 2

3 3

10K_1206_8P4R_5%

+3VS

+3VS

R120

1 2

R121

1 2

R119

1 2

10K_0402_5%

R68

1 2

10K_0402_5%

R77

1 2

10K_0402_5%

R79

1 2

10K_0402_5%

R80

1 2

10K_0402_5%

R100

1 2

10K_0402_5%

45

SIO_ IRQ

10K_0402_5%

SIO_DP IO45

10K_0402_5%

CAR D_ID#

PID0

PID1

SIO_GPIO11

SIO_GPIO40

NPCI_RS T#20,31

PLT_RST_B#22,25,30

+3VS

R108 0_0402_5%

1 2

R109 0_0402_5%@

1 2

R99 10K_0402_5%

1 2

1 2

+3VS

R67 10K_0402_5%

LPC_AD319 ,30,31

LPC_FRAME#19,30,31

LPC_D RQ#019

PM_CLKRUN#20 ,25,30,31

CLK_P CI_SIO15

SIRQ2 0,25,30,31

CLK_14M_SIO15

SER_SHD33

EXPCRD_RST#33

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DR Q#0

SIO_RST#
SIO_PD#

PM_CLKRUN#
CLK_P CI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO

SIO_GPIO40

PID0

PID1
SIO_GPIO43
SIO_GPIO44
SIO_DP IO45
CAR D_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_ IRQ

U8

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLO CK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

Base I /O Address

0 = 02Eh
1 = 04Eh*

CLK_P CI_SIO

12

R96

10_0402_5%@

1

C94
18P_0402_50V8J

@

2

LPC I/F

GPIO

POWER

RP3

1 8
2 7
3 6
4 5

1 2

SERIAL I/F

FIR

IRMODE/IRRX3

PARALLEL I/F

STROBE#

CLK_14M_SIO

12

1

@

2

+3VS

62

RXD1

63

TXD1

64

DSR1#

1

RTS1#

2

CTS1#

3

DTR1#

4

RI1#

5

DCD1#

37

IRRX2

38

IRTX2

39

41

INIT#

42

SLCTIN#

44

PD0

46

PD1

47

PD2

48

PD3

49

PD4

50

PD5

51

PD6

53

PD7

55

SLCT

56

PE

57

BUSY

58

ACK#

59

ERROR#

60

ALF#

61

7

VTR

11

VCC

26

VCC

45

VCC

54

VCC

R81
10_0402_5%@

C70
10P_0402_25V8K

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUS Y
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

1

C84

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RXD1 33

R64 1K_0402_5%

1 2

TXD1 33
DSR#1 33
RTS#1 3 3
CTS#1 3 3
DTR#1 33
RI#1 33
DCD#1 33

IRRX 25
IRTXOUT 25
IRMODE 25

LPTINIT# 33
LPTSLCTIN# 33
LPD0 33
LPD1 33
LPD2 33
LPD3 33
LPD4 33
LPD5 33
LPD6 33
LPD7 33
LPTSLCT 33
LPTPE 33
LPTBUS Y 33
LPTACK# 33
LPTERR# 33
LPTAFD# 33
LPTSTB# 33

1

1

C76

C88

2

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+5VS

21

D36

CH751 H-40_SC76

+5VS_PRN

LPD3
LPD2
LPD1
LPD0

LPD7
LPD6
LPD5
LPD4

LPTACK#
LPTBUS Y
LPTPE
LPTSLCT

LPTSTB#
LPTAFD#
LPTERR#

LPTSLCTIN#EXPCRD_RST#EXPCRD_RST#

+3VS

1

C57

2

LPTINIT#

RP51

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

RP52

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

RP53

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

RP54

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

R480

1 2

4.7K_0402_5%
R481

1 2

4.7K_0402_5%

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

D

Date: Sheet of

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA -3 26 1P U MA

29 55Tuesday, March 27, 2 007

E

0.4

5

4

3

2

1

0117 For SP I ROM debug

BIOS ROM

D D

20mil s

R1288

SPI_H OLD#_0

1 2

+3VM

20mil s

+3VM

20mil s

+3VM

12

12

C C

1 2

3.3K_0402_5%

R1292

@

R1287

3.3K_0402_5%

SPI_WP#

R1724

@

0_0402_5%

3.3K_0402_5%

SPI_H OLD#_0

+3VM

0821

SPI_CS1#20

R1811 0_0402_5%

SPI_CS0#20

12

1

C989

0.1U_0402_16V4Z

SPI_CLK

SPI_SI SPI_SI_0

0.1U_0402_16V4Z

SPI_CLK_L SPI_CLK _1

SPI_CS0#

47_0402_5%

47_0402_5%

C993

@

47_0402_5%@

47_0402_5%@

2

1 2

1 2

1

2

1 2

1 2

20mil s

SPI_WP#

SPI_H OLD#_0

SPI_CLK_0

R1290

R1294

S IC F L 32K AT2 6DF321-SU SOP 8P 2.7V

SPI0 (32M*1)

+3VM

20mil s

SPI_WP#

SPI_H OLD#_0

SPI_CS1#

R1296

SPI_SI_1

R1295

SPI1 (16M*1)

U66

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

U67

@

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_S O8-200mil

VSS

VSS

Debug port

VCC1_ PWRGD31,35

SPI_CLK_L
SPI_CS0#
SPI_SI_L
SPI_SO_L

CLK_DEBU G_PORT15,25

LPC_FRAME#19,29,31

+3VS

PLT_RST#7,16,18,22

LPC_AD019 ,29,31
LPC_AD119 ,29,31
LPC_AD219 ,29,31
LPC_AD319 ,29,31

B+
STB_LED#31
CAPS_LED#31
NUM_LED#3 1

R118 0_0402_ 5%@

1 2

R123 0_0402_ 5%@

1 2

1 2

12
1 2
1 2

SPICLK
SPICS0#
SPISI

SPISO
SPI_H OLD#_0
SPI_CS1#

4

R1291

SPI_SO_L0

2

Q

4

1 2

15_0402_5%

12

SPI_SO_L

SPI_SO

R1793
0_0402_5%

SPI_SO 20

R1794 0_0402_5%

SPI_SI_L

SPI_CLK_L

12

R1795 0_0402_5%

12

0907 Add 0 ohm for SPI

SPI_SI

SPI_CLK

SPI_SI 2 0

SPI_CLK 20

R170 0_0402_5%
CLRP3 SH ORT PADS
R201 0_0402_5%
R202 0_0402_5%

JP52

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

conn@

0629 Cha nge Pin3 to Pin 23, change Pin24 to GN D

2

Q

1 2

15_0402_5%

R1297

@

SPI_SO_L1SPI_SI_L

0821 SPI1 no install

0906 SPI1 in stall

1116 SPI1 no install

TPM1.2

0.1U_0402_16V4Z

1

2

13

1

C1054

0_0402_5%

0_0402_5%

2

12

R1409

0_0402_5%

1

C1055

0.1U_0402_16V4Z

2

26
23
20
17

21
22
16
27
15

12

USB20_P1_R

12

1

C1053

2

0.1U_0402_16V4Z

LPC_AD01 9,29,31
LPC_AD11 9,29,31
LPC_AD21 9,29,31

B B

A A

LPC_AD31 9,29,31

CLK_PC I_TCG15
LPC_FRAME#19,29,31
PLT_RST_B#22,25,29
SIRQ2 0,25,29,31
PM_CLKRUN#20 ,25,29,31

1 2

+3VS

R1380

+3VALW

S4_STATE28

USB20_N120
USB20_P120

PACDN042_SOT23~D@

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CLK_PC I_TCG
LPC_FRAME#
PLT_RST_B#
SIRQ
PM_CLKRUN#

4.7K_0402_5%@

Q142 SI2301BDS_S OT23

S

D

G

2

R1334
R1335

3

D54

5

+3VS+3VALW

1

2

19

10

5

VSB

VDD24VDD

VDD

TESTB1/BADD

TPM
SLB 9 635 TT 1.1

GND4GND11GND18GND

25

LPCPD#

TEST1

XTALO

XTALI

GPIO2

GPIO

SLB9635TT_TSSOP28

7

U69

LAD0
LAD1
LAD2
LAD3

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP

2007 0209 Add for FPR

R1808

@

1 2

1

C206

0.1U_0402_16V4Z

2

USB20_N1_R

0_0603_5%

JP38

1

1

2

2

3

3

4

4

ACES_85205-0400

conn@

C1052

0.1U_0402_16V4Z

LPC_PD#

28
9

R1379 0_0402_5%

8

TPM_XTALO

14

TPM_XTALI

13

2
6

1

NC

3

NC

12

NC

+3VS

PAD

PAD

R101 0_0402_5%@

T41

T42

Finger printer

4

Base I /O Address

0 = 02Eh

* 1 = 04Eh

LPC_PD# 20

12

1 2

+3VS

TPM_32K_CLK 31

TPM_XTALI

R1381

TPM_XTALO

10M_0402_5%

12

R1377

4.7K_0402_5%

12

R1378

4.7K_0402_5%@

12

18P_0402_50V8J

C1057

1 2

32.768 KHZ_12.5P_1TJS125BJ2A251

1

4

Y8

C1056

1 2

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IN

NC

OUT

NC

18P_0402_50V8J

Issued Date

2

3

2006/02/13 2006/07/26

3

+3VS

Q75

47K

DTA114YKA_SC59

10K

2

+3VS

1 3

47K

10K

+3VS

1 3

Compal Secret Data

Deciphered Date

2

Q88
DTA11 4YKA_SC59

47K

10K

2

Q89

@

DTA114YKA_SC59

1 3

WL_LED

WW_LED# 25

WL_LED# 25

WP_LED# 25

2

Mini-PCIE Card LED

BLUE

RHU002N06_S OT323

BT_LED28

100K_0402_5%

100K_0402_5%

Q79

13

D

2

G

R505

R504

Title

Size Doc ument Number Re v

Date: Sheet of

S

1 2

13

D

Q78

2

G

RHU002N06_S OT323

S

1 2

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA -3 26 1P U MA

1

WL_BLUE_LED# 25,32

0.4

30 55Tuesday, March 27, 2007

5

RP58

RP59

R578

R580

RP60

R1289

1070@

1021@

KSI0
KSI3
KSI2
KSI1

KSI7
KSI6
KSI5
KSI4

TP_CLK

TP_DATA

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

RUNS CI_EC#

18P_0402_50V8J

12

+3VL

+3VS

+3VL

D D

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

+5VS

1 2

10K_0402_5%

1 2

C C

B B

10K_0402_5%

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

+3VS

1 2

10K_0402_5%

CLK_P CI_EC

12

R86

10_0402_5%@

2

C80

10P_0402_50V8J@

1

AGND FILTER

C58

1 2

0.1U_0402_16V4Z

A A

32K_CLK

R91 0_0402_5%

1 2

R97 0_0402_5%@

1 2

PWR1

12

R14770_0603_5%

R14780_0603_5 %

1

C39

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1 2

R74
2M_0402_5%@

4IN1

Y2

1

C350

2

2

32.768 KHZ_12.5P_1TJS125BJ2A251

0821 Inst all R29 100 K ohm

5

C37

120K_0402_5%

1

OUT

C349

NC3NC

2

18P_0402_50V8J

ADP_EN 44

TPM_32K_CLK 30

1

C52

0.1U_0402_16V4Z

2

KSO[0.. 13]32

Pin3 250 : KSO12/ OUT8/K BRST

KSI [0..7]32

TP_CLK32
TP_DATA32
KBD_CLK33

KBD_DATA33

PS2_CLK33

PS2_DATA33

PM_CLKRUN#20 ,25,29,30

SIRQ2 0,25,29,30

CLK_P CI_EC15

RUNS CI_EC#20

LPC_AD319 ,29,30
LPC_AD219 ,29,30
LPC_AD119 ,29,30
LPC_AD019 ,29,30

LPC_FRAME#19,29,30

NPCI_RST#20,29

ADP_PS144

CR Y2

R75

+RTCVCC

12

R1783 0_0402_5%@

+3VL

R1784 0_0402_5%@

0821

1107 Install R1784
1128 Install R1783
0110 R178 4 connected to +3VL
2007 0226 Add R1809 t o GND

PGM

1 2

NO SHO RT PADS

FWP#

TEST

EA#

1

0.1U_0402_16V4Z

2

KSO[0.. 13]

1 2

1 2

1U_0603_10V4Z

PGM

FWP#

J3

4

C51

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

PM_CLKRUN#
SIRQ
CLK_P CI_EC
RUNS CI_EC#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME#
PLT_RST#

CR Y1

2

C661

@

1

R52

1 2

1K_0402_5%@

R29

1 2

100K_0402_5%

R65

1 2

1K_0402_5%

R28

1K_0402_5%@

R78

1K_0402_5%@

R27

1K_0402_5%

4

1

0.1U_0402_16V4Z

2

U47

21

KSO0

20

KSO1

19

KSO2

18

KSO3

17

KSO4

16

KSO5

13

KSO6

12

KSO7

10

KSO8

9

KSO9

8

KSO10

7

KSO11

6

KSO12/GPIO00/KBRST

5

KSO13/GPIO18

29

KSI0

28

KSI1

27

KSI2

26

KSI3

25

KSI4

24

KSI5

23

KSI6

22

KSI7

35

IMCLK

36

IMDAT

38

KCLK

40

KDAT

41

EMCLK

42

EMDAT

55

CLKRUN#

57

SER_IRQ

54

PCI_CLK

76

EC_SCI#

51

LAD[3]

50

LAD[2]

48

LAD[1]

46

LAD[0]

52

LFRAME#

53

LRESET#

45

LPCPD#/GPIO23

70

XTAL1

71

XTAL2

68

VCC0

R1809
0_0402_5%

1

C1317

@

1 2

0.1U_0402_16V4Z

2

+3VL

12

12

12

1213 Instal l R1646,C75

1

4.7U_0805_10V4Z

2

127NC128

NC94NC95NC96NC97NC

Power Mgmt/ SIRQ

LPC
Bus

44

C34

C36

NC1NC2NC3NC30NC31NC32NC33NC34NC43NC

RSMRST circuit

RSMRST_EC

BAV99DW-7_SOT363@

D68B

R1751

1 2

2.2K_0402_5%@

3

0_0402_5%

PWR _GD

+3VL

1

2

PWR1

14

106

119

VCC1

VCC139VCC158VCC184VCC1

VCC1

Keyboar d/M ouse Inter face

Acces s Bus Interf ace

SMSC_1070_TQFP-128P

AGND

VSS11VSS37VSS47VSS56VSS

VSS82VSS

72

1 2

E

2

4

5

3

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

104

117

R1749

0_0402_5%

Q131

C

123

MMBT3906_SOT23@

B

1

D68A
BAV99DW-7_SOT363

6

NC62NC63NC64NC65NC66NC

0619 change

@

3

12

R1642

@

R1646

12

+3VS

0_0402_5%1070@

1

T32

T33

PAD

C750.1U_0402_16V 4Z

1070@

2

49

15

CAP

VCC2

General Pu rpose I/O Int erface

24MHZ_OUT/GPIO19/WINDMON

Miscell ane ous

67

PM_RSMRST# 20

R1796 4.7K_0402_5%@

PAD

PM_SLP_M#

1 2

R38 0_0402_5%

GPIO30

100

126

GPIO2893GPIO2998GPIO3099GPIO31

GPIO32

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

GPIO27

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

EA Strap#/GPIO26/KSO17

CLOCKI

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

PWRGD

VCC1_PWRGD

TEST PIN

DMS_LED#/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

KBC1070_VTQFP128

+3VALW

12

1031 Modify circuit

2006/02/13 2006/07/26

CRACK_BGA

0621 Add PM_ SLP_M#

PM_SLP_M# 20,34,42,46

R141 0_0402_5%

1 2

PCI_S ERR# 18,25

KBC_P WR_ON

124

OUT0

GREEN_BATLED#

125

BATSELB_A#

123

KBRST#

122

A_SD

121

FAN_PWM

120

CHGCTR L

118

THM_MBAY#

107

ON/OFF BTN_KBC#

79

LOW_BAT#

80

KSO14

81

KSO15

83

RSMRST_EC

85

CRACK_BGA

86

EC_GPIO9

87

AB2A_DATA

88

AB2A_CLK

89

AB2B_DATA

90

AB2B_CLK

91

BATCON

92

THM_MAIN#

101

A20M

102

NUM_LED#

103

SLP_S3#

105
4

EC_GPIO27

74

D10 CH 751H-40_SC76

AB1A_DATA

111

AB1A_CLK

112

AB1B_DATA

109

AB1B_CLK

110

Cap_INT

73

EA#

108

CLK_14M_KBC

59

32K_CLK

75

PM_POK

60

PWR _GD

78

VCC1_ PWRGD

77
61

Pin50 250 - - 24MH z_Out

TEST

69

Pin52 250 - - XOSEL

116

AMBER_BATLED#

113

STB_LED#

115

CAPS_LED#

114

AB1B_DATA

AB1B_CLK

Compal Secret Data

Deciphered Date

1 2

0_0402_5%

R1726

1

1070@

C128910U_0805_10V4Z

2

R156 0_0402_5%

1 2

R155 0_0402_5%

1 2

R140 0_0402_5%

1 2

R154 0_0402_5%

1 2

10K_0402_5%

2 1

Cap_INT 32

1 2

R977 300_0402_5%

R127

@

0_0402_5%

1 2

1 2

0_0402_5%
R157

@

PWR_GD20,25,34,35,43,44

PGOOD_PU1943

SN74LVC08APW_TSS OP14

2

CRAC K_GPIO28 11,21

1013 no ins tall R1726
1213 Install R1726

GPIO29 20

EAPD 26,27

AMT ADP_PRES 20

KBC_P WR_ON 40

GREEN_BATLED# 19,25

BATSELB_A# 39

A_SD 27
FAN_PWM 4
CHGCTR L 38,39

THM_MBAY# 37
ON/OFF BTN_KBC# 32

LOW_BAT# 20
KSO14 32
KSO15 32

4.7K_0402_5%

R20

1 2

R18

1 2

4.7K_0402_5%

Cap_DAT 32
Cap_CLK 32
ME_EC_DATA1 20

BATCON 39
THM_MAIN# 37

R581

12

T37 PAD

ADP_PRES 23,38,3 9,40,44

CLK_14M_KBC 15

PM_POK 43
PWR _GD 20 ,25,34,35,43,44
VCC1_ PWRGD 30,35
ADP_PS0 44

ADP_I D 44
AMBER_BATLED# 25
STB_LED# 30
CAPS_LED# 30

Cap_DAT

Cap_CLK

1114 Elimin ate glitch

2

ME_EC_CLK1 20

+3VL

NUM_LED# 30
SLP_S3# 20 ,23,26,27,3 3,34,41,42,43,44

AB1A_DATA 37
AB1A_CLK 37

AB1B_DATA 37
AB1B_CLK 37

Pin91 250 - - nDMS _LED

R62 250@

+3V_U43

14

4

P

A

O

5

B

G

U43B

7

1

AB1A_CLK

1 8

AB1A_DATA

2 7

AB1B_CLK

3 6

AB1B_DATA

4 5

4.7K_1206_8P4R_5%

BIOS debug port

+3VL

12

R575

10K_0402_5%

D7

21

CH751 H-40_SC76

+3VL

D6 CH751H-40_SC76

21

Pin1 250 -- TEST Pin ( NC !! )
Pin57 250 - - MODE

R58 100K_0402_5%

+3VL

R59 100K_0402_5%
R60 100K_0402_5%

Remov e from daugh ter bo ard

KB_RST# 19

GATEA20 19

1 2
1 2
1 2

Place under KB area

+3VL

VCC1_ PWRGD

EC_GPIO9
CRACK_BGA

ACES_85201-0602@

THM_MAIN#

ADP_PS1

EC_GPIO27

CLK_14M_KBC

FWP# PM_POK

1 2

210K_0402_1%

1 2

R538 100K_0402_5%@

1 2

100K_0402_5%

R282

1 2

10_0402_5%

@

R25

1 2

10K_0402_5%

+3VL

VCC1_ PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

R600

R33

For KBC debugging used.

STB_LED#

6

U82

1 2

R1800

0_0402_5%

1

2

3

A1

GND

A2

NC7W Z07P6X_NL_SC70-6

PM_PWROK 7, 20,45

6

Y1

5

VCC

+3VL

4

Y2

0811 For OTS 214499

VGATE 7,20

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

LPC47N1021

LA-3261P UMA

31 55Tuesday, March 27, 2 007

1

+3VL

RP1

JP43

1
2
3
4
5
6

+3VL

C92

1 2

10P_0402_25V8K

@

JP31

1
2
3
4
5
6

ACES_85201-0602@

LED_STB# 25 ,32,33

0.4

SWITCH BOARD.

R21 0_0402_5 %@

Cap_RST#

1 2

Cap_RST#_SB 20

0901 Cha nge Cap_R ST#_SB to S B GPIO28

0809 Con nect Pi n1 to +3VL, Pin2 to +3 VS

+3VL +3 VS

JP18

Cap_DAT31

Cap_RST#

1 2
3 4
5 6
7 8
9 10

ACES_85203-1002

conn@

MDC 1.5 Conn.

HDA_S DOUT_MDC19

HDA_S YNC_MDC1 9

HDA_RST#_MDC19,26

1 2

R1753 0_0402_5%

0620 RESERVE FOR MDC

0622 change

Cap_INT

12

R30

10K_0402_5%

Cap_CLK 31
Cap_INT 31

WL_BLUE_LED# 25,30

1

2

C1
10P_0402_50V8K

@

0829 Chan ge to WL_BL UE_LED#

HDA_S DOUT_MDC

HDA_S YNC_MDC

R1313

HDA_S DIN1_MDC

HDA_S DIN119

12

33_0402_5%

HDA_RST#_ MDC_R

0104 Cha nge JP20 t o FFC conne ctor

JP20

@

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

Aces_85203-08421-11

On/off ,information buttonWL,Vol up,Vol down,Mute,Present button

1103 Conn ect pin2 to +3VS

JP32

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

conn@

RES0
RES1

GND3
GND4

IAC_BITCLK

131314141515161617171818191920

3.3V

20

C749220P_0402_50V4Z

LED_STB#

12

C750220P_0402_50V4Z

ON/ OFF#

12

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

+3VS

2
4
6
8
10

HDA_B ITCLK_MDC

12

TYCO_1-179396-2~D

LID_SW#

LED_STB#
ON/ OFF#

+3VALW

PJDLC05_SOT23~D

0.1U_0402_16V4Z

Connector for MDC Rev1.5

LID_SW# 17,20

LED_STB# 25,3 1,33

ON/ OFF# LID_ SW#

2

3

D76

1

+3VS

1

C5

2

HDA_B ITCLK_MDC 19

INT_KBD CONN.

KSO[0.. 15]31

KSI [0..7]31

KSO[0.. 15]

KSI [0..7]

30

30

29

29

28

28

27

27

26

26

25

KSO15
KSO10
KSO11
KSO14
KSO13

KSO12 KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2

KSI0
KSO1
KSO5

KSI3

KSI2
KSO0

KSI5

KSI4
KSO9

KSI6

KSI7

KSI1 KSI1

CP1

KSO9

4 5

KSI6

3

KSI7

2

KSI1

100P_1206_8P4C_50V8

CP3

KSI2

4 5

KSO0

3

KSI5

2

KSI4

100P_1206_8P4C_50V8

CP7

KSI3

4 5

KSO5

3

KSO1

2

KSI0

100P_1206_8P4C_50V8

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

FOX_GB1SV301-160K-7F

6
7
81

6
7
81

6
7
81

conn@

KSO2
KSO4
KSO7
KSO8

KSO6
KSO3
KSO12
KSO13

KSO14
KSO11
KSO10
KSO15

JP6

A30

60

A29

59

A28

58

A27

57

A26

56

A25

55

KSO15

A24

54

KSO10

A23

53

KSO11

A22

52

KSO14

A21

51

KSO13

A20

50

A19

49

A18

48

A17

47

A16

46

A15

45

A14

44

A13

43

A12

42

A11

41

A10

40

A9

39

A8

38

A7

37

A6

36

A5

35

A4

34

A3

33

A2

32

A1

31

CP6

4 5
3
2

100P_1206_8P4C_50V8

CP5

4 5
3
2

100P_1206_8P4C_50V8

CP2

4 5
3
2

100P_1206_8P4C_50V8

KSO3
KSO6
KSO8
KSO7
KSO4
KSO2

KSI0
KSO1
KSO5

KSI3

KSI2
KSO0

KSI5

KSI4
KSO9

KSI6

KSI7

6
7
81

6
7
81

6
7
81

Power button

12

R22

100K_0402_5%

ON/OF F#33

ON/ OFF#

C23

1U_0603_10V4Z

U5F

14

SN74LVC14APWLE_TS SOP14

P

13

O12I

G

1

7

2

R26

1 2

100K_0402_5%

1U_0603_10V4Z

+3VL

12

R536

100K_0402_5%

ON/OFF BTN_KBC#

13

D

2

G

S

1

C11

2

Q70

RHU002N06_S OT323

ON/OFF BTN_KBC# 31

1 2

D42

CH751 H-40_SOD323

R8

1 2

100K_0402_5%

ON/OFF BTN#

+3VALW

ON/OFF BTN# 20

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TrackPoint CONN. T/P BOARD.

+5VS

2

3

1

PJDLC05_SOT23~D

1

C321

0.1U_0402_16V4Z

2

D58

TP_DATA31

TP_CLK31

TP_DATA
TP_CLK

2

3

1

TP_DATA
TP_CLK

SP_DATA

SP_CLK

Title

Size Doc ument Number Re v

Date: Sheet of

Issued Date

JP14

1

2

SP_DATA

3
5
7

ACES_87153-0801L

conn@

2006/02/13 2006/07/26

SP_CLK

4
6

+5VS

8

PACDN042_SOT23~D@

Compal Secret Data

Deciphered Date

D67

+5VS

JP17

ACES_87212-0800

conn@

+5VS

1
2
3
4
5
6
7
8

1

C319

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-3261P UMA

32 55Tuesday, March 27, 2 007

0.4

A

DOCK CONN. 184PIN

L_RED

L_GREEN

1 1

L_BLUE

2 2

3 3

C746 1000P_0402_50V4Z@

1 2

C747 1000P_0402_50V4Z@

1 2

C748 1000P_0402_50V4Z@

1 2

0314 change

1013 change

RED9

GREEN9

BLUE9

KC FBM-L18-453215-900LMA90T_1812

1

C72

1000P_0402_50V7K

D_DDC DATA16

DVI_DETECT16

R1404 0_0603_5%

1 2

R1428 0_0603_5%

1 2

R1429 0_0603_5%

1 2

LINE_ IN_SENSE26

ACOCP_E N#44

2

ON/OF F#32

MDO2+2 4
MDO2-24

MDO0+2 4
MDO0-24

D_V SYNC16
D_H SYNC16

D_DDC CLK16

COMP9,16
CRMA9,16

LUMA9,16

DCD# 129

RI#129
DTR#129
CTS#129
RTS#129
DSR#129

TXD129
RXD129

LPTSTB#29
LPTAFD#29

LPTERR#29

L10

ON/ OFF#

MDO2+
MDO2-

MDO0+
MDO0-

LED_AC T_LAN#_DOCK
LED_L INK_LAN#_DOCK

DDC-DATA
DDC_C LK
DVI_DETECT

DOCK_ RED
DOCK_ GRN
DOCK_BLU

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

LPTSTB#
LPTAFD#
LPTERR#

12

1

C73

2

B

DOCK VINVIN

1000P_0402_50V7K

JP30A

172

G1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

JAE_SP03-14588-PCL03

R1479 100_0402_1%

DVI_TX1- DVI_TX1+
DVI_C LK- DVI_CLK+
DVI_TX0- DVI_TX0+

conn@

173

P1

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

DOCK VIN

83

83

84

84

85

85

86

86

87

87

88

88

89

89

90

90

91

91

92

92

93

93

94

94

95

95

96

96

97

97

98

98

99

99

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

1 2

R1480 100_0402_1%

1 2

R1481 100_0402_1%

1 2

R1482 100_0402_1%

1 2

DETECT

MDO3+
MDO3-

MDO1+
MDO1-

PWR_LED

1 2

R515 1K_0402_5%

DVI_CLK
DVI_DAT

DVI_TX2-

DVI_TX2+

DVI_TX1-

DVI_TX1+

DVI_C LK-

DVI_CLK+

DVI_TX0-

DVI_TX0+

DOCK_ ADP_SIGNAL

DOCK _ID

C

Clos ed to do ck JP30

DVI_TX2+DVI_TX2-

MDO3+ 24
MDO3- 24

MDO1+ 24
MDO1- 24

SLP_S5#_5R

DVI_CLK 16
DVI_DAT 16

DVI_TX2- 16

DVI_TX2+ 16

DVI_TX1- 16

DVI_TX1+ 16

DVI_CLK- 16

DVI_CLK+ 16

DVI_TX0- 16

DVI_TX0+ 16

DOCK_ ID 20

DOCK _ID

DOCK_ ADP_SIGNAL

R1387

1 2

10K_0402_5%@

R1401

1 2

1K_0402_1%

LPTSLCTIN#29

EXPCRD_RST#29

SLP_S534

LPTACK#29

LPTBUS Y29

LPTPE29

LPTSLCT29

LPD729
LPD629
LPD529
LPD429
LPD329
LPD229
LPD129
LPD029

LPTINIT#29

USB20_N720

USB20_P720

USB20_N920

USB20_P920

SER_SHD29

+3VS

ADP_S IGNAL

+5VALW

2

G

LPTACK#
LPTBUS Y
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

SER_SHD
EXPCRD_RST#
DETECT

12

R529

100K_0402_5%

SLP_S5#_5R

13

D

Q65

RHU002N06_S OT323

S

JP30B

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

176
169
175
179
181
177

165

166

JAE_SP03-14588-PCL03

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

GND
GND
GND
GND
GND
GND

G2

RING

D

E

2007 0226 Change RJ 11 connecto r

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HP S#

DLINE _IN_L
DLIN E_IN_R

DLINE_OUT_L
DLINE _OUT_R

PCIE_TXP5

PCIE_TXN5

1 2

0_0402_5%

1 2

0_0402_5%

CLK_P CIE_DOCK

CLK_P CIE_DOCK#

PREP#
VA_ON#

12

R66

1K_0402_5%

2

3

1

JP29

conn@

2
1

E-T_3800-02_2P

KBD_DATA 31
KBD_CLK 31
CPPE# 15
PS2_DATA 31
PS2_CLK 31
DOCK_HP S# 27

DLINE _IN_L 26
DLIN E_IN_R 26

DLINE _OUT_L 27
DLINE _OUT_R 27

PCIE_TXP5 20

PCIE_TXN5 20

PCIE_RXP5

R1346

R1347

CLK_P CIE_DOCK 15

CLK_P CIE_DOCK# 15

PREP# 20,24,26

C678

+

1 2

22U_1206_10V4Z@

SWAP

1

C59

0.1U_0402_16V4Z

2

PCIE_RXP5 20

PCIE_RXN5 20

conn@

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

GND
GND
GND
GND
GND
GND

TIP

DOCK_ MOD_RING
DOCK_MOD_TIP

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153

PCIE_RXP5_D OCK

154
155

PCIE_ RXN5_DOCK PCIE_RXN5

156
157
158
159
160
161
162
163
164

178
180
182
174
171
170

167

P2

168

PACDN042_SOT23~D@

+5VS

DOCK_MOD_TIPDOCK_ MOD_RING

D59

1013 Add CRT circuit

C360

12

0.1U_0402_16V4Z
U52

5

VCC

BLUE9
L_BLUE16

ISO_PREP#20

+3VM_LAN

4 4

R527

10K_0402_5%

12

LED_A CT_LAN#_DOCK_R LED _ACT_LAN#_DOCK

13

D

Q62

2

G

RHU002N06_S OT323

S

LED_ACT_LAN#

LED_L INK_LAN#_DOCK_R

13

D

Q63

2

G

RHU002N06_S OT323

S

LED_L INK_LAN#

A

L_BLUE

ISO_PREP#

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

R1805

1 2

0_0402_5%

LED_ACT_LAN# 23,24

1 2

0_0402_5%

LED_L INK_LAN# 20,23 ,24

GREEN9

L_GREEN16 L_RED16

C1372

R1806

LED_L INK_LAN#_DOCK

C1373

+3VS

C366

1 2

0.1U_0402_16V4Z
U51

5

VCC

1

L_GREEN L_RED

ISO_PREP# ISO_PREP#

100P_0402_50V8J@

12

100P_0402_50V8J @

12

B

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

0108 EMI reque st

LED_STB#25 ,31,32

Q59

RHU002N06_S OT323

SLP_S3#20,23,26, 27,31,34,4 1,42,43,44

2

G

Closed to JP30

RED9

+3VALW

12

R526

10K_0402_5%

PWR_LED

13

Secur ity Classification

D

S

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS+3VS

FSA66P5X_SC70-5

C365

12

0.1U_0402_16V4Z

U50

5

VCC

1

A

2

B

4

OE

3

GND

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Docking CONN.

LA -3 26 1P U MA

33 55Tuesday, March 27, 2 007

E

0.4

A

B

C

D

E

+1.25VM to +1.25VS Transfer

S
S
S

G

RU NON

+1.25VS+1.25VM

1
2
3
4

1

2

0.1U_0402_16V4Z

10U_0805_10V4Z

C1271

0317 add

1

+

1

C1272

2

C254
330U_D2_2.5VM_R 15

2

U77

8

D

7

D

6

1

1 1

2

C1270

5

10U_0805_10V4Z

D
D

SI4800 DY_SO8

+3VALW to +3VS Transfer

1

S

2

S

3

S

4

G

+3VS+3VALW

10U_0805_10V4Z

1

C132

2

0.1U_0402_16V4Z

1

C128

2

B+

12

R139

330K_0402_5%

J34

SHORT PAD S

2 2

SLP_S3

2

G

Q18

1

2

12

RHU002N06_S OT323

13

D

S

8
7
6

C127

5

10U_0805_10V4Z

RU NON

U13

D
D
D
D

SI4800 DY_SO8

12

R469

470_0402_5%

1

C120

0.01U_0402_25V7 Z

2

+5VALW to +5VS Transfer

+5VS+5VALW

U9

S

D

S

D

S

D

G

D

SI4800 DY_SO8

RU NON

1
2
3
4

1

2

0.1U_0402_16V4Z

1

C71

C77

10U_0805_10V4Z

2

8
7
6

1

C86

5

2

10U_0805_10V4Z

3 3

+3VALW to +3VM Transfer

+3VALW

12

R1647

100K_0402_5%

PM_SLP_M#20,31,42,46

0119 Add R1807 and n o stuff

0216 Ins tall R1 807 and non install R6 30

Discharge circuit-2 for V-M

+1.25VM

12

R631

470_0402_5%

13

Q111

D

2

G

S

Q112

RHU002N06_S OT323

LAN_WOL_EN# LAN _WOL_EN#

RHU002N06_S OT323

0718 Cha nge n et from PM_ SLP_M# to L AN_WOL_EN#

2

G

SLP_S3#20,23,26, 27,31,33,4 1,42,43,44

13

D

S

+1.05VM

2

G

Q116

BSS138_SOT23

LAN_WOL_EN20

12

R632

470_0402_5%

13

D

S

SLP_S3

SLP_S3#

RHU002N06_S OT323

LAN_WOL_EN#

100K_0402_5%

100K_0402_5%

LAN_WOL_EN#

RHU002N06_S OT323

2

G

Q19

R1807

R630

@

+3VL

12

R125

100K_0402_5%

13

D

S

Q113

+3VALW

12

12

100K_0402_5%

2

G

+3VM

2

G

2

13

D

S

BSS138_SOT23

12

R633

470_0402_5%

13

D

S

R1643

G

Q110

B+

12

13

D

S

C1273

10U_0805_10V4Z

Q108
BSS138_SOT23

SLP_S4

SLP_S4#20,42

+3VALW +3VM

8
7
6

1

5

2

12

R470

470_0402_5%

1

C121

0.01U_0402_25V7 Z

2

SLP_S4

2

G

Q23

RHU002N06_S OT323

U78

D
D
D
D

SI4800 DY_SO8

PM_SLP_M

+3VL

12

R129

100K_0402_5%

13

D

S

S
S
S

G

1
2
3
4

0.1U_0402_16V4Z

1

1

C1274

C1275

2

SLP_S5#20,42

10U_0805_10V4Z

2

100K_0402_5%

SLP_S533

SLP_S5#

RHU002N06_S OT323

Q22

SLP_S5

2

G

+5VALW

12

R135

13

D

S

Discharge circuit-1

+1.8V

+0.9V

12

0313 change

SLP_S4

1 2

C91

4 4

+VCCP +1.5VS

+1.5VS

1 2

0.1U_0402_16V4Z

C184

1 2

0.1U_0402_16V4Z

C93

1 2

0.1U_0402_16V4Z

+VCCP+VCC_ CORE

+1.8V

A

R1311 0_0402_5%

SLP_S5

1 2

R1312 0_0402_5%@

R186

470_0402_5%

13

D

Q27

2

G

S

RHU002N06_S OT323

B

SLP_S3

2

G

RHU002N06_S OT323

+3VS

12

R134

470_0402_5%

13

D

S

PWR _GD 20, 25,31,35,43,44

Q17

+1.5VS

12

R151

470_0402_5%

13

SLP_S3

RHU002N06_S OT323

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2

G

Q47

S

2006/02/13 2006/07/26

C

+2.5VS

12

13

SLP_S3

RHU002N06_S OT323

D

2

G

S

Compal Secret Data

Deciphered Date

R130

470_0402_5%

Q21

+5VS

SLP_S3

2

G

RHU002N06_S OT323

D

12

R116

470_0402_5%

13

D

Q16

S

0313 change

SLP_S4

1 2

R107 0_0402_5%

SLP_S5

1 2

R110 0_0402_5%@

Title

Size Doc ument Number Re v

Date: Sheet of

12

R1310

470_0402_5%

13

D

2

G

Q90

S

RHU002N06_S OT323

Compal Electronics, Inc.

DC/DC Circuits

LA-3261P UMA

34 55Tuesday, March 27, 2 007

E

0.4

PWR_OK circuit

+1.25VS

VCCP_POK41

DDR_P GOOD

CH751 H-40_SC76

+0.9V

+5VS

+3VS

D69

49.9K_0402_1%

R284

3.3K_0402_5%

D71 C H751H-40_SC76

21

12

12

232K_0402_1%

12

150K_0402_1%

R289

21

1 2

10K_0402_5%

R1747

12

R128

R1752

10K_0402_5%

2

12

B

R28510K_0402_5%

R288

1

2

+3VALW

12

C

Q134

E

MMBT3904_SOT23

3 1

R1261M_0402_5%

12

+5VALW

8

20K_0402_5%

R115

C32

1000P_0402_50V7K

12

1.24VREF_39 3

U80A

3

P

+

1

O

2

-

G

LM393M_SO8

4

011 3 Cha nge LMV33 1 t o L M39 3, De let e R 124 and C27

R117

1.8PGOOD42

0_0402_5%

2

G

DDR_P GOOD

12

13

D

S

Q133
RHU002N06_S OT323

J38

1 2

SHORT PADS

+3VS

12

R47

10K_0402_5%

PWR _GD 20, 25,31,34,43,44

KBC PWR_OK circuit

+3VL

12

R24

100K_0402_5%

1

C26

0.1U_0402_16V4Z

2

+3VL +3VL

14

U5D

P

9

O8I

G

SN74LVC14APWLE_TS SOP14

7

121 9 Add Sc hmi tt Tri gge r to e lim ina te gli tch and p ull do wn res istor

14

U5C

P

5

O6I

G

7

SN74LVC14APWLE_TS SOP14

12

R1802

100K_0402_5%

R1803

1 2

0_0402_5%

200 70227 Mov e R18 03

VCC1_ PWRGD 30,31

+3VM

D70

CH751 H-40_SC76

10K_0402_5%

1 2

1 2

76.8K_0402_1%

R1746

C2

DDR_P GOOD

M_PROK46

1000P_0402_50V7K

LAN_RST circuit

+3VL

1

C991

0.1U_0402_16V4Z

+3VM

120K_0402_5%

111 3 Tie R1 732 .2 to 3V M i nstea d of 3 VM_LAN

R1732

2

12

1

14

P

O2I

G

U5A

7

SN74LVC14APWLE_TSSOP14

R1745

21

1

2

R198

1 2

20K_0402_5%

12

R39

56.2K_0402_1%

R178

1 2

1.24VR EF

10K_0402_5%

Ne ed b e tun e t o
10 ms ec ti me del ay

CH751 H-40_SOD323

D60

12

R1350

1 2

100K_0402_1%

1

2

C990

0.1U_0402_16V

1.24VREF_39 3

1

2

+3VL

14

P

3

G

7

R199

1M_0402_5%

1 2

+5VALW

8

U80B

5

P

+

7

O

6

-

G

LM393M_SO8

4

C33
1000P_0402_50V7K

1

C992

0.1U_0402_16V4Z

2

O4I

SN74LVC14APWLE_TS SOP14

U5B

+3VALW

12

LAN_RST# 20

R49
10K_0402_5%

M_PWROK 7,20

1

FM2

1

H2
HOLEA

1

H11
HOLEB

1

H16
HOLEC

1

H28
HOLED

1

CF8

1

1

H19
HOLED

1

FM3

H3
HOLEA

1

H12
HOLEB

1

H17
HOLEC

1

CF9

1

H20
HOLED

H4
HOLEA

H13
HOLEB

1

FM1

1

CF7

1

H1
HOLEA

1

H10
HOLEB

1

H15
HOLEC

1

H18
HOLED

1

H27
HOLED

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

FM4

CF10

1

H5
HOLEA

1

H14
HOLEB

1

H32
HOLED

1

CF12

CF11

1

1

H6

H7

HOLEA

HOLEA

1

1

1

H21

H22

HOLED

HOLED

1

1

H33
HOLED

1

Title

Size Doc ument Number Re v

Date: Sheet of

CF14

CF13

1

1

H8

H9

HOLEA

HOLEA

1

H23
HOLED

1

H34
HOLED

1

H25

H24

HOLED

HOLED

1

1

H35

H36

HOLED

HOLED

1

1

1

1

Compal Electronics, Inc.

POK CKT

LA -3 26 1P U MA

H37
HOLED

1

35 55Tuesday, March 27, 2 007

0.4

5

D D

4

3

2

1

+B+

AC
Adapter
in

Page37

ACOK

C C

VIN

VS

SWITCH

B+ B+

+5VALWP

ENBL2 ENBL1

MA INPWON

+3VALWP 4A

MAX8734A

+1.25VM

DC/DC
(3V/5V)

VMB

VIN

Page40 Page45

+5VALWP 4A

ISL6269
DC/DC
(1.25V)

APL5912
LDO
(1.05V)

B+

+1.25VM

Page46

+1.05VM

Page46

ISL6263
DC/DC
(VCC_GFX)

+3VS

VCC_GFX

VS

G965
LDO
(2.5V)

+2.5VS 1A

Page41

+5 VS

VCC SH DN#

ISL6260 &ISL6208
DC/DC

PW R_GD

(CPU_CORE)

+3VLP 0.1A

Page43

BQ24703
Charger

B B

Battery

Page38

BATSELB_A

B+

SLP_S3#

MAX8743
DC/DC
(1.05V/1.5V)

ENBL1/ENBL2

Page41

+1.5VSP 4.2A

+1.05V_VCCP 6.4A

CPU_CORE
( 44A)

+5VALWP

Selector
Circuit

Page39

BATSELB_A#

Battery A
6 Cell

VMB

Battery B
8 Cell

TPS51116

B+

DC/DC
(+1.8VP/+0.9VSP)

VCC

+1.8VP 7A

SWITCH

A A

SWITCHSWITCH

Battery
Connector

Page37 Page37

A

VMB_A VMB_B

Battery
Connector
B

SLP_S5#

S3/S5

Page42

+0.9VP 2A

BATT

BATT_A

BATT_B

5

4

3

Title

POWER BLOCK DIAGRAM

Size D ocument Number Rev

Dat e: Sheet o f

2

36 55Tuesday, March 27, 2007

1

A

B

C

D

PC N1

9

SINGAL

GND6

8

1 1

GND5

7

6

4
3

FOX _JPD113E -LB103-7F

GND4

GND3

GND2
GND1

PWR1

PWR2

PC N2

1

BATT+

2

SMD

3

2 2

SMC

RES

TS

GND

TYCO_ C-1746 706_6P

4
5

6

100_040 2_5%

220P_04 02_25V8K

3 3

PC N3

1

BATT+

2

SMD

3

SMC

4

B/I

5

TS

6

GND

SUYIN_ 20163 S-06G1 -K

5

1

2

EC_ SMD_A

EC_ SMC_A

PR4

PC1 43

EC_ SMD_B
EC_ SMC_B

AB /I_B
TS_B

ADP _SIGNAL

12

PR5

100_040 2_5%

12

A DPIN

12

12

PC1 44

220P_ 0402_25V8K

PR1 1
1K_0402 _5%

1 2

12

PC 1

100 P_0402_50V8J

AB /I_A 38

12

PR3
1K_0402 _5%

12

PC145
220P_04 02_25V8K

PR7

1K_0402 _5%

1 2

PR9

12

PR2

1M_0402 _1%

12

210K_04 02_1%

SMB 3025500YA_2 P

1 2

PC2
1000P_0 402_50V7K

12

+3VL

PL1

EC_ SMD_A1

EC_ SMC_A1

12

PC 4

PC 3

1000P _0402_50V7K

PL2

FBM-L18-4 53215-900LMA9 0T_1812

1 2

VMB_A

12

100 P_0402_50V8J

PC5
1000P_0 402_50V7K

AB1A_DA TA 31

AB1 A_CLK 31

VMB_B

PL3

FBM-L18-4 53215-900LMA9 0T_1812

1 2

12

PC8
1000P_0 402_50V7K

12

12

PC6

0.01 U_0402_5 0V4Z

BATT_B

12

PC9

0.01 U_0402_5 0V4Z

12

PR1
15K_040 2_5%

BATT_A

VIN

+3VL

12

PR1 0

210K_04 02_1%

THM _MAIN# 31

12

PR1 4

100_040 2_5%

4 4

12

PR1 5

100_040 2_5%

EC_ SMD_B1

EC_ SMC_B1

A

THM _MBAY# 31

AB1B_DA TA 31

AB1 B_CLK 31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Title

Size D ocum ent Nu mber R ev

Cu stom

Da te: S heet of

Compal Electronics, Inc.

BATTERY CONN

LA-3261P UMA

D

37 55T uesda y, March 27, 200 7

A

B

C

D

1 1

2 2

3 3

4 4

VIN

PQ5

DTA144EUA_SC70

47K

47K

2

1 2

PR18 47K_0402_5%

1 2

PC13

47P_0402_50V8J

220K_0402_5%

BATCAL#44

AC de tector
High 11.689V
Low 9.879V

12

12

PR50

Airl ine detect or
High 17.521V
Low 16.871V

13

12

PR343

P2

12

PR36

12

PR40

PR45
130K_0402_1%

PC29

10K_0603_0.1%

12

12

PC12

0.1U_0603_16V7K

13

2

G

1 2

100K_0603_1%

PR39

2.15K_0402_1%

1 2

12.4K_0603_1%

12

22P_0402_50V8J

PQ3
AO4407_SO8

1
2
3 6

4

PR16
200K_0402_5%

D

PQ93
RHU002N06_S OT323

S

PR21
150K_0402_5%

PD7

12

1SS355_SOD323

CHGCT RL31,39

ACDET

PR34

1 2

330K_0402_5%

VL

8

PU3A

3

P

+

2

-

G

4

PR46

1 2

1M_0402_5%

8

PU3B

5

P

+

6

-

G

LM393M_SO8

4

PR54

1 2

33K_0402_1%

4

REF

5

ANODE

APL1431LBBC_SOT23-5

A

ADP_EN# 44

1

O

LM393M_SO8

7

O

VL

PU5

CATHODE

NC

NC

P2

8
7

5

SRSET44

PR26

1 2

191K_0402_1%

3

2

1

8
7

5

PR19

ACDR V#

@RHU002N06_SOT323

ADP_PRES

1 2

12

PC18

+3VL

12

PR37

10K_0402_1%

2

+3VL

AC_CH G

1.24VREF

PQ4

AO4407_SO8

1
2
36

PR398

4

@200K_0402_5%

1 2

12

PR399

0_0402_5%

1 2

13

D

S

PR397

@0_0402_5%

AC_CH G

PR29

1 2

137K_0402_1%

12

PC23

1U_0603_10V6K

12

PC25

0.1U_0402_10V6K

O4I

1

PC27
@0.1U_0402_16V7K

AC_CH G 39

PQ10

ACDET

2

G

G

1 2

PQ131

PR396

0_0402_5%

1U_0603_10V6K

+3VL

5

PU4
SN74LVC1G17DBVR_SOT23-5

P

NC

G

3

12

12

PR51

@47K_0402_1%

RHU002N06_S OT323

P4

PR20

0.015_2512_1%

1 2

ADP_PRES 23,31,3 9,40,44

12

PR22

@150K_0402_5%

100_0402_1%

2

1 2

PC16

1U_0603_10V6K

1 2

PR24
1K_0402_1%

PR25

1K_0402_1%

ALARM

+3VL

13

D

S

PR27

100K_0402_5%

BQ24703VREF

12

12

PR30

100K_0402_1%

12

PC21

PR33

4.7U_08 05_6.3V6K

80.6K_0402_1%

ADP_PRES 23,31,3 9,40,44

+3VL

12

PR43

4.7K_0402_5%

PR47

1 2

100K_0402_5%

BQ24703VREF

12

13

D

2

G

S

PR49
100_0402_5%

PL4

FBM-L11-322513-151LMAT_1210

1 2

ACN 44

PU2

8
9

26

5

12

28
19

2
3

12

13

4

7

10
11

BQ24703_QFN28

12

12

PC24

12

150P_0402_50V8J

ALARM 39

PQ11
RHU002N06_S OT323

B

ACN

ACDRV#
ACP
ACDET

ENABLE
ACSEL
ALARM
SRSET
ACSET
ACPRES27VHSP
IBAT
VREF

COMP
NC1
NC2

BATDRV#

PGND

29

PR35
150_0402_1%

PC26

4.7U_0805_6.3V6K

VCC

PWM#

SRP
SRN

BATP

BATSET

BATDEP

GND

PQ2
AO4407_SO8

1
2
3 6

P2B+

PR17

0_0402_5%

1 2

12

10U_1206_25V6M

RLZ16B_LL34

ACDR V#

12

PC15

PC28

4.7U_1206_25V6K
PD5

100P_0402_50V8J

BATT

2 1

12

PR42
196K_0402_1%

12

PR382

25.5K_0402_1%

12

PR48

10K_0402_1%

12

PC17

1U_0805_25V4Z

DH_ CHG

13

D

S

PQ110

RHU002N06_S OT323

NC4
NC3

1

PC14

2

25
22
21
16
15
12
24

18

VS

20

6
1
17
23
14

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8
7

5

4

CHG_B+

PR23

0_0402_5%

12

36

241

PQ7

FDS4435_SO8

578

LX_CHG

1 2

10UH_PCMB104T-100MS_6A_20%

12

PD8
EC31QS04

SE_CHG+

SE_CHG-

BATT

12

PR44

5.62K_0603_0.1%

12

PR380
100K_0603_0.1%

12

PR381

7.68K_0603_0.1%

12

PR360

2

G

2.8K_0603_0.1%

1 2

2005/03/10 2006/03/10

PR383

200K_0402_1%

Compal Secret Data

Deciphered Date

C

BATT

PL5

13

D

PQ8 RHU002N06_SOT323

2

G

S

12

PR28

0.015_1206_1%

1 2

PR31

3K_0402_1%

PC22

1 2

0.1U_0402_16V7K

CELLSEL#

BATT

CV=12.6V(6 CELLS LI-ION)

1

12

12

PC19

PR32

3K_0402_1%

4.7U_1206_25V6K

16.8V(8 CELL LI-ION)

PC20

2

CC=3A for 2.4AHr

10U_1206_25V6M

CC=3.57A for 2.55AHr

Icharger=3A
CELLSEL# =0,Vcharger= 12.6V
CELLSEL# =1,Vcharger= 16.8V

+3VL

2

G

12

PR384

100K_0402_5%

13

D

S

PQ112

RHU002N06_S OT323

CFET_B 39,44

38 55Tuesday, March 27, 2 007

+3VL

12

CELLSEL#

PR385

330K_0402_5%

PR386

AB/I_A37

1 2

330K_0402_5%

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

13

D

2

G

S

I_A#44

PQ111

RHU002N06_S OT323

Compal Electronics, Inc.

LA-3261P UMA

D

Charger

A

B

C

D

+3VL

1 1

+3VL

BATSELB_A

BATSELB_A#

2 2

PC31

1 2

1000P_0402_50V7K

PC33

1 2

1000P_0402_50V7K

PQ14

PR59

1 2

22K_0402_5%

RHU002N06_S OT323

PQ15

PR60

1 2

22K_0402_5%

2

G

2

G

1 2

13

D

RHU002N06_S OT323

S

13

D

S

ALARM38

PR57

47K_0402_5%

RHU002N06_S OT323

PQ16

13

D

S

1

INB

2

INA

2

G

5

PU7

P

4

O

G

74LVC1G02_04_SOT353

3

+3VL

5NC1

PU8

P

4

A2Y

G

SN74L VC1G14DCKR_SC70-5

3

ADP_PRES 23,31,3 8,40,44

1

INB

2

INA

+3VL

5NC1

PU9

BATSELB_A#31

BATSELB_A#

+3VL

P

4

A2Y

G

SN74L VC1G14DCKR_SC70-5

3

BATSELB_A

12

PC34

3 3

12

PC35

0.047U_0402_16V7K

CHGCTR L

4 4

PC180

1 2

1000P_0402_50V7K

CFET_A

CFET_B

PR342

1 2

1K_0402_5%

PD17

2

3

RB715F_SOT323

2

G

12

12

PR344

PD14

470K_0402_5%

1SS355_SOD323

+3VL

5

P

1

2

12

G

3

PR77

+3VL

PR70

1 2

13

D

S

PU13

O4I

NC

SN74LVC1G17DBVR_SOT23-5

5NC1

P

470K_0402_5%

A2Y

G

3

AC_CH G38

PQ94
RHU002N06_S OT323

1

PU11
SN74L VC1G14DCKR_SC70-5

4

PR71

10K_0402_1%

1 2

RHU002N06_S OT323

S

ADP_PRES

BATCON 31

PQ27

G

D

13

2

220P_0402_50V7K

PR69

220K_0402_5%

BATSELB_A#

1 2

100K_0402_5%

A

B

12

PC30

5

PU6

P

4

O

G

74LVC1G02_04_SOT353

3

LATCH

+3VL

PU10

5

1

P

IN1

O

2

IN2

G

3

SN74A HC1G08DCKR_SC70

+3VL

PU12

5

1

P

IN1

O

2

IN2

G

3

SN74A HC1G08DCKR_SC70

BATT_A

@0.1U_0402_10V6K

BATT_B

RHU002N06_S OT323

PQ13

S

+3VL

G

PD9

2

1

PR55

1 2

100_0402_5%

D

13

3

RB715F_SOT323

2

12

PC32

RHU002N06_S OT323

12

PR58

1.5M_0402_5%

0.1U_0603_50V4Z

BATT

12

PR61
470K_0402_5%

1

C

2

B

PQ18

E

12

CFET_A

4

PR65

1 2

10K_0402_5%

PQ23

BATT_IN

RHU002N06_S OT323

2

G

13

D

PQ20

2

G

S

13

D

S

BATT

4

PR74

CFET_B#

PR75

1 2

10K_0402_5%

CFET_B38,44

CFET_B

PQ31

BATT_IN

2

G

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10K_0402_5%

PQ28

2

G

13

D

RHU002N06_S OT323

S

2005/03/10 2006/03/10

3

PD12

PR63

1 2

10K_0402_5%

1SS355_SOD323

RHU002N06_S OT323

12

PR68
470K_0402_5%

C

2

B

E

12

PD16

1 2

1SS355_SOD323

13

D

RHU002N06_S OT323

S

1

3

PR62

PMBT2222_SOT23

470K_0402_5%

PQ26

1 2

PR72

PMBT2222_SOT23

1 2

470K_0402_5%

Compal Secret Data

Deciphered Date

C

3 6
2
1

1
2
3 6

PQ12

D

1 3

G

2

PD13

SX34-40_SMA

4

AO4407_SO8

PQ24

AO4407_SO8

4

PD15

SX34-40_SMA

PR56

S

1 2

0_0402_5%

2 1

RHU002N06_S OT323

RHU002N06_S OT323

21

5

7
8

PQ21

8
7

5

21

PD10
1SS355_SOD323

1 2

PD11

RLZ6.2 C_LL34

PQ17

BATT_IN

PQ19

4

5

7
8

AO4407_SO8

PQ25

AO4407_SO8

8
7

5

4

RHU002N06_S OT323

PQ30

RHU002N06_S OT323

BATT_IN

BATT_IN

13

D

2

G

S

13

D

2

G

12

S

36
2
1

PR64

4.7K_0402_5%

12

PR66
470K_0402_5%

BATT_A

PQ22

12

1
2
36

PR67
470K_0402_5%

BATT_B

12

PR73

4.7K_0402_5%

PQ29

13

D

2

G

S

13

D

2

G

S

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Battery selector

LA-3261P UMA

D

39 55Tuesday, March 27, 2 007

A

B

C

D

E

+3.3V/+5V

B+

1 1

PC36

5

PQ34
AO4468_SO8

4

LX5

5

PQ126
AO4468_SO8

4

DL5

PC48

0.1U_0603_50V4Z

0.1U_0603_50V4Z

1 2

LX_5V4 4

DH5

VL

12

PC52

0.1U_0603_50V4Z

RHU002N06_S OT323

PR79
0_0402_5%

1 2

2VREF_1999

1 2

0_0402_5%
PR91

MAINPWON

12

PR97
499K_0402_1%

PQ36

BST5B

BST5A

PR93

1 2

@0_0402_5%

13

D

S

1 2

PR89
0_0402_5%

2VREF_1999

2

G

VL

PC45

4.7U_0805_10V4Z

14

16

15
19
21

12

12

+3VL

12

13

D

PQ37

S

3

2

1

12

18

BST5

DH5

LX5
DL5
OUT5

MAX8734EEI_QSOP28

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

SKIP#

8

REF

PC50

0.22U_0603_10V7K

PR98
100K_0402_5%

RHU002N06_S OT323

2

G

PD18
CHP20 2U_SC70

B++

12

0.1U_0603_50V4Z

PC46

13

20

V+

LD05

PU14

GND

LDO3

23

25

+3VLP

12

PC51

4.7U_0805_10V4Z

VL

PR80

1 2

47_0402_5%

12

PC44

17

5

TON

ILIM3

VCC

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

10

PR95
0_0402_5%

1 2

KBC_PWR_ON 3 1

12

PC40

0.1U_0603_50V4Z

2VREF_1999

1U_0805_16V7K

PGOOD

+3VLP

BST3B

PR83

1 2

PR86

1 2

1 2

200K_0402_1%

1 2

200K_0402_1%

12

PJP1

2 1

PAD-OP EN 2x2m

PR84

200K_0402_1%

PR87

499K_0402_1%

100K_0402_5%
PR242

PL6
FBM-L11-322513-151LMAT_1210

1 2

2 2

B++

1

12

PC38

2

2200P_0402_50V7K

4.7UH _SIQB745-4R7_4A_30%

PC39

10U_1206_25V6M

12

PL7

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

+5VALWP

B++

1

12

PC47

@22U_1206_6.3V6M

PC197

150U_B2_6.3VM

3 3

PR88

+

1 2

2

@10.2K_0402_1%

PR92

0_0402_5%

1 2

12

PR90

47K_0402_5%

12

PC37

0.1U_0603_50V4Z

1 2

PR82
0_0402_5%

1 2

BST3A

+3VALWP

+3VL

B++

DH3

12

12

PC41

2200P_0402_50V7K

PC42

AO4468_SO8

4.7U_1206_25V6K

AO4468_SO8

PQ35

PQ127

5

D8D7D6D

S1S2S3G

4

5

4

DL3

LX3

D8D7D6D

S1S2S3G

12

PL8

4.7UH _SIQB745-4R7_4A_30%

+3VALWP

PR94

1 2

@3.57K_0402_1%

PR96

1 2

0_0402_5%

1

+

PC49

2

150U_B2_6.3VM

RHU002N06_S OT323

13

D

PQ77

2

G

S

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ADP_PRES 23,31 ,38,39,44

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

3.3 V / 5 V

LA-326 1P UMA

40 55Tuesday, March 27, 2007

E

0.1

A

1

12

PQ38
AO4468_SO8

PQ40
AO4712_SO8

1 2

1 2

PR123

0_0402_5%

PC53

2200P_0402_50V7K

DH_1.05V_2

0.1U_0603_50V4Z

PD30

1SS355_SOD323

2

CHP202 U_SC70

PC59

DL_1.05V

12

5

1 1

+1.05V_VCCP

1

+

PC63

2

220U_B2_2.5VM

2 2

3.3UH_MPL73-3R3_6A_20%

12

PR106

5.1K_0402_1%

12

PR107
100K_0402_1%

PL10

12

D8D7D6D

S1S2S3G

D/K8D/K7D/K6D/K

S/A1S/A3G

S/A

2

4

5

4

SLP_S3#20,23 ,26,27,31, 33,34,42,43,44

3 3

1.5VSP/ +1.05V_VCCP/+2.5V

PJP2

+1.5VSP

+1.05V_VCCP

4 4

+1.05VMP +1.05VM

1 2

PAD-OP EN 3x3m

PJP6

PAD-OP EN 4x4m

1 2

PJP8

+0.9VP

VCCGFXP VCCGFX

1 2

PAD-OP EN 3x3m

PJP14

1 2

PAD-OP EN 4x4m

PJP15

2 1

PAD-OP EN 2x2m

+1.5VS

(4A,160mils ,Via NO.=8)

(6A,24 0mils ,Via NO.= 12)

+VCCP

(2A,80mils ,Via NO.= 4)

+0.9V

+5VALWP

+3VALWP

+1.25VMP +1.25VM

+2.5VSP

(8A,24 0mils ,Via NO.= 16)

(1A,40mils ,Via NO.= 2)

A

PC71

PC54

10U_1206_25V6M

12

@0.001U_0402_50V7M

B

3

1 2

BST_1.05V_2

PR103

2.2_0402_5%

1 2

B

1

PD19

2

PR101

0_0402_5%

DH_1.05V_1

LX_1.05V

MAX8743EEI_QSOP28

VCC_MAX8743

PJP3

1 2

PAD-OP EN 4x4m
PJP5

1 2

PAD-OP EN 4x4m
PJP13

1 2

PAD-OP EN 4x4m

PJP9

2 1

PAD-OP EN 2x2m

1U_0805_25V4Z

BST_1.05V_1

25

26

27
24

28

11

C

MAX8743_B+

12

PR100

9

VDD

UVP

BST2

DH2
LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR113

10

20K_0402_1%

PR114

20K_0402_1%

12

PC69

0.22U_0603_10V7K

+5VALW

BST_1.5V_1

21

19
18
17
20
16

15
14
12

7
5

13
3

12

12

PR117

100K_0402_1%

12

BST_1.5V_2

PR102

0_0402_5%

1 2

DH_1.5V_1

12

PC55

4.7U_0805_10V4Z

PR104
0_0402_5%

1 2

12

PR118

100K_0402_1%

PC62

0.1U_0603_50V4Z

12

LX_1.5V

PR108

0_0402_5%

10U_1206_6.3V6M

DL_1.5V

12

PC134

VCCP_POK 3 5

+3VALW

2 1

12

SLP_S3#20,23 ,26,27,31, 33,34,42,43,44

PQ39

1

D2

2

D2

3

G1

4

S1/A

SI4914_SO8

DH_1.5V_2

PJP11
PAD-OP EN 2x2m

PR99

0_0402_5%

PC56

PC60

0.1U_0603_50V4Z

PU15

1

2

@0_0402_5%

+5VALW

+3VALW

1 2

12

20_0603_5%

VCC_MAX8743

12

12

PC61

4

22

1U_0805_16V7K

BST1

V+

8

OVP

12

PR120

VCC

SKIP

GND

6

23

2VREF

12

DH1

LX1
DL1

CS1
OUT1

FB1

ON1

PR116

0_0402_5%

(4.5A, 180mils ,Via NO.= 9)

(3A,120mils ,Via NO.= 6)

(3A,40mils ,Via NO.= 6)

(1A,40mils ,Via NO.= 2)

+2.5VS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

D1/S2/K
D1/S2/K
D1/S2/K

10K_0402_5%

1 2

G2

PR243

8
7
6
5

3.3UH _SIQB74-3R3RF_4 .8A_30%

12

PC70

@0.001U_0402_50V7M

12

PC181

D

PL9

FBM-L11-322513-151LMAT_1210

PL11

1 2

PD31

12

1SS355_SOD323

12

PR121
0_0402_5%

PU26

VIN2VO

1

EN

5

GND

6

GND

G965-18P1U_SO8

@0.1U_0603_16V7K

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

12

12

PC57

2200P_0402_50V7K

12

12

12

PC58

PR105

5.1K_0402_1%

PR111

10K_0402_1%

SLP_S3# 20,23, 26,27,31, 33,34,42,43,44

12

PR244
13K_0603_1%

12

PR245
12K_0402_1%

ADJ

GND

GND

3

4

7

8

Compal Electronics, Inc.

2.5VALW/1.5VS/1.05VCCP

LA-3261P UMA

D

4.7U_1206_25V6K

1

+

PC66

2

220U_B2_2.5VM

+2.5VSP

12

B+

+1.5VSP

PC135
10U_1206_6.3V6M

41 55Tuesday, March 27, 2 007

5

D D

4

3

2

1

DDR_ B+

+1.8V

1

PL13

12

PC72

2

2200P_0402_50V7K

+5VALWP

12

PR124

0_1206_5%

12

PC75

10U_0805_10V4Z

C C

+0.9VP

V_DDR_MCH_REF7,13,14

+5VALW

B B

12

12

PC79
22U_1206_6.3V6M

PR127
0_0402_5%

1 2

PC76

10U_0805_10 V4Z

12

PC81

0.033U_040 2_16V7K

23

24

1

2

3

4

5

6

8

9

VLDOIN

VTT

VTTGND

VTTSNS

GND

MODE

VTTREF

TPS51116R GE_QFN24

COMP

VDDQSNS

VDDQSET

7

NC

CS_GND

17

12

PU17

NC

VBST

DRVH

LL

DRVL

PGND

CS

V5FILT

PGOOD

S5

S3

V5IN

Thermal pad

15

25

BST_1.8V_1 BST_1.8V_2

22

21

20

19

18

16

14

13

11

10

DH_1 .8V_1

PR125

0_0402_5%

1 2

PR126

0_0402_5%

1 2

12

PC82

LX_1.8V

DL_1 .8V

4.7U_0 805_10V4Z

PR131

PR132

PR133

PR134

PC74

0.1U_ 0603_50V4Z

1 2

DH_1 .8V_2

12

PC83

0.001U_0402_50V7M

@0_0402_5%

12

0_0402_5%

12

@0_0402_5%

12

@0_0402_5%

12

12

5

PQ45

D8D7D6D

AO4468_SO8

S1S2S3G

4

2.2UH _IHLP-2525CZ- 01_8A_+-20%

1 2

5

D8D7D6D

PQ46
AO4712_SO8

S1S2S3G

4

PR129

20K_0603_1%

PR130

3_0402_5%

12

SLP_S5# 20,34

SLP_S4# 20,34

SLP_S3# 20,23,26,27,31,33,34,41,43,44

SLP_S4# 20,34

PL12

FBM-L11-322513-151LMAT_1210

PC73
10U_1206_25V6M

1

+

PC78
220U _D2_4 VY

2

12

B+

+1.8V

12

12

PC80

22P_0402_50V8J

14.3K_060 3_0.1%
PR128

PR387

0_0402_5%

12

12

PC84

A A

@0.001U_0402_50V7M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

3

12

PC85

@0.001U_0402_50V7M

Compal Secret Data

Deciphered Date

1 2

PR317

0_0402_5%

PM_SLP_M# 20,31,34,46

1 2

PR294

100K_0402_5%

1.8PGOOD 35

2

+3VALW

Title

Size D ocument Number R ev

B

Dat e: Sheet o f

Compal Electronics, Inc.

1.8V/0.9VS

LA-3261P UMA

1

12

10K_0603_0.1%
PR135

42 55Tuesd ay, March 27 , 2007

8

7

6

5

4

3

2

1

+CPU_B+

H H

PQ50

SI7 840D P_SO8

+CPU_B+

PR1 49
10_ 0603_5%

4

3

5

6

28
29
30
31
32
33
34

37

36

1

2

38

35

12

13

11

10

9

8

12

0.0 1U_0 402_25V 7K
PC1 06

19

20

VSS

VDD

VR_TT#

RBIAS

NTC

SOFT

VID0
VID1
VID2
VID3
VID4
VID5
VID6

DPRSTP#

DPRSLPVR

PSI#

PGD_IN

CLK_EN#

VR_ON

VSEN

RTN

VDIFF

FB

COMP

VW

DROOP

14

PR1 90

PC1 27

330 P_0402 _50V7K

PU 19

12

1 2

18

VIN

DFB15VO

12

+3VS

1 2

39

40

3V3

PGOOD

PWM1

ISEN1

PWM2

ISEN2

CS_GND

FCCM

PWM3

ISEN3

OCSET

VSUM

16

PR1 91

1K_ 0402_1%

VO

PR1 55

1.9 1K_060 3_1%

PGO OD_P U19 31

ISL 6260 CRZ -T_QFN4 0

PWM 1

27

ISE N1

23

PWM 2

26

ISE N2

22

41

24

25

21

7

VSU M

17

12

PC1 23

PR1 86

4.5 3K_040 2_1%

12

PR1 77

0_0 402_5%

1 2

0.2 2U_0 603_10V7K

PC1 26

12

+5VS

PR1 81

12

11. 5K_040 2_1%

12

PR1 85

1.9 6K_040 2_1%

PC1 22

1 2

@10 00P_04 02_50V7K

12

12

12

0.1 U_04 02_16V7K

PH 3

PR1 89

@1K _0402_1 %

10K B_06 03_5 %_ERTJ1 VR103J

G G

+5VS

10_ 0603_5%

PR1 52

1 2

+VCCP

12

12

PH 2

12

12

12

12

12

PR1 71

PR1 74

PR1 78

12

51K _0603_1 %

PC1 25

12

12

PC1 08

PR3 70
68_ 0402_5%

12

12

12

PC1 18

12

0_0 402_5%

PR1 87

1U_ 0603_ 10V6K

PC1 19

PR1 83

12

N TC

12

12

12

6.3 4K_060 3_1%

F F

PC1 09

N TC

12

0.0 1U_0 402_16V 7K

H_PROCHOT#4

E E

CP U_VI D05
CP U_VI D15
CP U_VI D25
CP U_VI D35
CP U_VI D45
CP U_VI D55
CP U_VI D65

H_DPRSTP#5, 7,19

DPRSLPVR7,20

D D

H_PSI#5

PM_POK31

CLK_EN#20

PWR_GD20,25,31,34,35,44

VCCSENSE5

+V CC_ CORE

VSSSENSE5

C C

@27 .4_04 02_1%

B B

PR1 79,P R18 0 a re for tes t n eed whe n M /B is withou t CPU
R12 69,R 127 0 a re same fu nti on w ith PR179,P R180
Lay out Not e: Use 27.4 Oh m(P R318 ,PR 319 ) ro uti ng for Vssens e and
Vcc sens e

PR1 80

@10 _0402_1 %

PR3 19

@10 _0402_1%

12

12

PR1 60

4.2 2K_060 3_1%

SLP_S3#20,23, 26,27,31,3 3,34,41,42,44

12

PR1 79

PR1 82

180 _0603_1 %

PC1 24

1 2

220 P_0402 _25V8K

147 K_0402_ 1%

12

0.0 15U_ 0402_16 V7K

180 0P_040 2_50V7K

12

PR1 58

0_0 402_5%

PR1 59

12

PC1 15

470 KB_0 402_5% _ERTJ0E V474J

12

0_0 402_5%

PR1 62

12

0_0 402_5%

PR1 64

0_0 402_5%

12

0_0 402_5%

0_0 402_5%

PR1 66

12

0_0 402_5%

0_0 402_5%

PR1 69

12

0_0 402_5%

PR1 72

12

0_0 402_5%

PR3 28

1 2

@10 0_0402_ 5%

PR3 18

@27 .4_04 02_1%

100 0P_040 2_50V7K

PC1 20

1 2

1 2

PC1 21

0.0 22U_ 0402_16 V7K

6.9 8K_040 2_1%

PR1 61

PR1 63

PR1 65

PR1 68

499 _0402_1 %

0_0 402_5%

0_0 402_5%

12

100 0P_040 2_50V7K

PR1 84

1.2 K_0402 _1%

100 0P_040 2_50V7K
PR1 88

+5VS

12

PC1 04

1U_ 0603_1 0V6K

+5VS

12

PC1 14

PU 18

5

VCC

6

FCCM

2

PWM

3

GND

ISL 6208 CRZ -T_QFN8

1U_ 0603_ 10V6K

PU 20

5

VCC

6

FCCM

2

PWM

3

GND

ISL 6208 CRZ -T_QFN8

UGATE

BOOT

PHASE

LGATE

UGATE

PHASE

LGATE

BOOT

1

8

7

4

2_0 402_5%

BST _CPU 1_1

DH _C PU1

LX_ CPU1

BST _CPU 2_1

1

DH _C PU2

8

LX_ CPU2

7

4

PR1 48

D L_CP U1

PR1 57

2_0 402_5%

D L_CP U2

12

BST _CPU 1_2

0.2 2U_0 603_10V 7K

1 2

12

BST _CPU 2_2

0.2 2U_0 603_10V 7K

1 2

PC1 05

PC1 16

PR3 46

0_0 402_5%

SI7 840D P_SO8

DH_ CPU 1_MDH_ CPU 2_M

12

IRF 783 2Z_SO 8

PQ5 4

12

PR3 48
0_0 402_5%

3 5

241

5

D8D7D6D

PQ52

IRF 783 2Z_SO 8

PQ5 6

S1S3G

S

2

3 5

D8D7D6D

S1S3G

PQ53

IRF 783 2Z_SO 8

4

241

5

S

IRF 783 2Z_SO 8

4

2

D8D7D6D

S1S3G

PQ5 7

S

2

D8D7D6D

S1S3G

2

12

12

PC1 00

PC1 01

0.0 1U_0 402_50V 4Z

220 0P_040 2_50V7K

5

12

4.7 _1206_5 %

PR3 47

4

1 2

680 P_0603_ 50V7K

PC1 82

12

PC1 10

PC1 11

0.0 1U_0 402_50 V4Z

220 0P_040 2_50V7K

5

12

PR3 49

S

4

1 2

PC1 83

1

12

2

PC1 02

4.7 U_12 06_25V6K

.36 UH_ MPC1 040LR 36_ 24A _20%

1 2

PR1 51

10K _0402_1 %

1 2

PR1 53

5.1 1K_040 2_1%

1 2

VSU M

12

12

PC1 12

4.7 U_12 06_25V6 K

.36 UH_ MPC1 040LR 36_ 24A _20%

10K _0402_1 %

4.7 _1206_5 %

1 2

PR1 73

5.1 1K_040 2_1%

1 2

VSU M

680 P_0603 _50V7K

PL16

1

2

PR1 70

PL15

FBM -L18-453 215-900LM A90T_18 12

1 2

PC1 03

10U _1206_2 5V6M

<BO M Stru cture>

PC1 07

0.2 2U_0 603_16V7K

12

PR1 54

12

@0_ 0402_5%

+CPU_B+

PC1 13
10U _1206_2 5V6M

PL17

1 2

<BO M Stru cture>

PC1 17

0.2 2U_0 603_16V 7K

12

PR1 75

@0_ 0402_5%

12

1 2

VO

1

+

2

PR1 50
10_ 0402_1%

1 2

VO

PC1 48

47U _25V_M

PR1 67
10_ 0402_1%

B+

+V CC_C ORE

+V CC_C ORE

A A

8

7

6

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Doc ume nt N umber R e v

C

LA -326 1P UMA

Dat e: Sh eet o f

2

CPU_CORE

43 55T ues day, Mar ch 27, 2007

1

5

PU2 2A

8

D D

PR1 96

1 2

LM358A_ SO8

0_040 2_5%

1

3

P

+

0

2

-

G

4

P4

12

PR1 95

0_040 2_5%

1 2

1 2

PR1 99

10K_040 2_1%

PR1 97

6.81 K_0402_1%

1 2

100 K_0603_0.5%

12

PC1 30

1U_ 0805_50V4 Z

C

E

3 1

12

PC1 32

0.1 U_0402_16V 7K

ADP _PRES23,31 ,38,39,4 0

RHU 002N06 _SOT323

PQ62

NDS 0610_NL_ SOT23-3

D

S

G

2

5

+

6

-

2005 .8.20

2

PQ92

13

VI N

3

+

2

-

1M_0402 _5%

1 2

8

PU2 5B

P

O

G

LM393M_SO8

4

C C

12

PR2 12

B+

ADP _SIGNA L

12

PR223

PR2 40

12

12

0_040 2_5%

137K_04 02_1%

PR235
10K_040 2_1%

13

D

S

B B

A A

0_0402_ 5%

MMBT3904_SOT32 3

ADP _PRES23,31 ,38,39,4 0

47.5 K_0402_1%

1 2

PR2 29
1M_0402 _5%

1 2

PR2 58

29.4 K_0402_1%

2

G

PQ65
@RH U002N0 6_SOT323

10K_040 2_1%

5

PR2 41

PR2 17

VI N

12

12

VI N

12

12

PQ61

2

B

PR224

22.6 K_0402_1%

PR236
10K_040 2_1%

PR2 00

4

REF

5

ANODE

APL 1431LBBC_SOT 23-5

13

D

G

S

8

PU2 5A

P

1

O

G

LM393M_SO8

4

PR2 38

7

4

PU2 2B

LM358A_ SO8

CATHODE

PQ113

12

1 2

4

PU2 3

5

+

0

6

-

1 2

PC1 29

0.22 U_0603_16V 7K

3

2

NC

1

NC

13

D

2

G

S

RHU 002N06 _SOT323

+3VL

12

SLP_S3#20,23 ,26,27, 31,33,3 4,41,42,4 3

VI N

12

PR2 31
220K_04 02_5%

PR2 37

47K_0 402_5%

PD2 3

1SS 355_SOD323

ADP _EN# 38

7

12

PR2 06

7.8 7K_0402_1%

12

PR2 10

422_0 603_1%

D

I_A# 38

S

PD2 5

1SS 355_SOD323

PR221
10K_040 2_5%

+3VL

PR2 30

47K_040 2_5%

2

G

12

PR2 39

220K_ 0402_5%

12

12

PR2 60

39. 2K_0402_1%

13

D

2

G

S

PQ73

12

RHU 002N06 _SOT323

13

PQ74

2

G

RHU 002N06 _SOT323

12

PR259
1M_0402 _1%

12

PR2 02

2K_04 02_5%

E

3

B

12

PQ58

2

C

1

MMBT390 6_SOT23

PR261
1M_0402 _1%

CFE T_B 38,3 9

12

3

PR1 94

330K_04 02_5%

8

5

P

+

6

-

G

4

PR2 01

1 2

0_0402_ 5%

PR2 07

3.9K_ 0402_5%

@CH 751H-4 0_SOD323

PW R_GD 20,2 5,31,3 4,35,43

1

PR2 14

2

PC1 47

3.9 K_0402_5%

3900P _0402_50V7K

12

PU2 1B

7

O

LM393M_SO8

PD2 2

1 2

1U_ 0603_10V6K

1 2

PC1 46

+3VS

PR2 15

470K_ 0402_5%

12

10K_040 2_5%

2

12

PR2 65
47K_040 2_5%

12

PR256

G

12

PR1 92
133K_04 02_1%

12

PR2 05

80. 6K_0402_1%

PR2 11

1 2

0_0402_ 5%

13

D

PQ60
RHU 002N06 _SOT323

S

PR2 16

PC1 31

12

2

+5VS

3

+

2

-

0.0 27U_0402_1 6V7K

OCP # 4 ,20

ACO CP_EN#3 3

8

4

12

PC1 33

0.1U _0603_16V7 K

12

470K_04 02_5%

AD P_ID 31

BATCAL# 3 8

13

D

PQ95

2

G

RHU 002N06 _SOT323

S

12

ADP _EN 31

13

D

PQ64
RHU 002N06 _SOT323

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SRSET38

1 2

PR2 33

100K_04 02_5%

1 2

C

PQ63

2

B

E

3 1

2005/03/10 2006/03/10

3

AC N 38

PR225
@100K_0 402_5%

MMBT3904_SOT32 3

Compal Secret Data

Deciphered Date

+3VS

12

PR2 22

71.5 K_0402_1%

12

12

PR228
21K_060 3_1%

PR234

3.48 K_0402_1%

2

PR1 93

1 2

100K_04 02_5%

PU2 1A

P

O

G

LM393M_SO8

1 2

1

PD2 0

CH7 51H-40 _SOD323

1

PR2 03
604K_06 03_1%

+5VS

VI N

1 2

12

PR257

10K_040 2_5%

PQ70

DTA 144EUA_SC 70

12

12

1 2

PD2 1

CH7 51H-40 _SOD323

PC1 28

1U_ 0805_16V7K

PR208
10_0402 _5%

13

PD2 8

47K

47K

2
12

PR2 54

150K_04 02_5%

PD2 7

1SS 355_SOD323

PR2 55

1 2

1 2

1K_0402 _5%

+5VS

PR2 19

1M_0402 _5%

PR2 20

10K_040 2_5%

1 2

PR2 32

21K_060 3_1%

1 2

1 2

3

+

2

-

+5VS

PR2 26

1M_0402 _5%

1 2

5

+

6

-

Title

Size D ocum ent Nu mber R ev

Cu stom

Da te: S heet of

Compal Electronics, Inc.

LA-3261P UMA

1SS 355_SOD323

1 2

12

PR2 53
210K_04 02_1%

ADP _SIGNA L

PD2 6

1 2

1SS 355_SOD323

8

PU2 4A

P

1

O

G

LM393M_SO8

4

8

PU2 4B

P

7

O

G

LM393M_SO8

4

ADP_OCP

+3VS

12

+3VS

12

1

PQ72

D

1 3

2

12

220K_ 0402_5%

PR2 51

1 2

13

D

S

+5VS

S

G

12

PD 24

1SS 355_SOD323

RHU 002N06 _SOT323

NDS 0610_NL_ SOT23-3

LX_5V 40

+3VS

PQ71

2

G

ADP _PRES 23 ,31,38 ,39,40

PR218
10K_040 2_5%

ADP _PS0 31

PR2 27
10K_040 2_5%

ADP _PS1 31

44 55T uesda y, March 27, 200 7

PR2 52

220K_ 0402_5%

5

+3VS

12

PR326

30K_0402_1%

D D

PQ80

DFGT _VR_EN7

2

G

PM_PWROK7,20,31

DFGT _VID_37
DFGT _VID_27

12

68P_0402_50V8J

5

DFGT _VID_17
DFGT _VID_07

@0_0402_5%

PR320

1 2

DFGT _VR_EN7

PC173

C C

+3VS

10K_0402_5%

PR304

+5VS

B B

A A

1 2

PR321

1 2

1_0402_5%

PC168

2.2U_ 0603_6.3V6K

PR327

1 2

0_0402_5%

13

D

@RHU002N06_SOT 323

S

PR297

1.91K_0402_1%

PR324

@0_0402_5%

1 2

+3VS

PR325 100K_0402_1%

12

VCC_P RM

1 2

1 2

PR310 6.98K_0402_1%

12

374_0402_1%

VGAVR_ ON

+3VS

PR298 0_0402_5%
PR299 0_0402_5%
PR300 0_0402_5%
PR301 0_0402_5%
PR302 0_0402_5%

PR303 10K_0402_5%

12

PC169

0.01U_0402 _25V7K

PC170
1000P_0402_50V7K

PC174

PR315

12

1 2
1 2
1 2
1 2
1 2

1 2

1 2

12

180P_0402_50V8J

12

+5VS

PR305

1 2

0_0402_5%

PR306
150K_0402_1%

PR308

12.4K_0603_1%

12

PR296
10_0402_5%

12

PC167
1U_0603_10V6K

VGAVR_ ON

12

ISL626 3_QFN32

PR314

2.21K_0402_1%

PR316

12

4.99K_0402_1%

4

16
31

27
26
25
24
23

30
32
29

22

1

2

3

4

5

6

12

PC177

560P_0402_50V7K

4

3

GFX_B+

12

PR295
10_0402_5%

12

PC166

0.01U_0402 _25V7K

15

VCC
PGOOD

D4
D3
D2
D1
D0

SPIR
FDE
VR_ON

PVCC

RBIAS

SOFT

OCSET

VW

COMP

FB

12

PU30

14

VIN

VSS

VDIFF

7

BOOT

UGATE

PHASE

LGATE

PGND

VSUM

I2UA

DFB

DROOP

VSEN

RTN

EP

33

17

18

19

21

20

13

12

VO

28

11

10

8

9

PC164

1000P_0402_50V7K

BST_GFX

PR307

1 2

20K_0402_1%

12

12

PR272

2.2_0402_5%

1 2

PR312

1 2

1.91K_0402_1%
PC175

1 2

330P_0402_50V7K

12

PC176
1000P_0402_50V7K

PC178
1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

12

VSUM1
VCC_P RM

PR313

1 2

1K_0402_1%

3

AO4468_SO8

DH_GFX

PC156

0.22U_0603 _10V7K

AO4712_SO8

DL_GFX

PR286

1 2

0_0402_5%

PR288

1 2

0_0402_5%

Compal Secret Data

PQ78

LX_GFX

PQ79

12

Deciphered Date

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

PC172

0.1U_0402_ 16V7K

2 1

Parel lel fr om VCC GFX an d GND undern eath GMCH a t Int erface Power pin

2

GFX_B+

12

12

PC151

2200P_0402_50V7K

1.5UH _IHLP-2525CZ-01_ 9A_+-20%_15mohm

12

PD29

@SX34_SMA

@

VCCGFX

PR279

7.68K_0805_1%

PR281

1 2

3.57K_0402_1%

PC152

10U_1206_25V6M

1 2

PL19

PH4

1 2

10KB_0603_5 %_ERTJ1VR103J

PR309

1 2

4.53K_0402_1%

PC160

1 2

0.033U_0402_16V7K

1 2

PC179

0.022U_040 2_16V7K

2

1

PL18

FBM-L11-322513-151LMAT_1210

12

PC153

4.7U_1206_ 25V6K

12

PR311
0_0402_5%

Title

Size D ocument Number R ev

B

Dat e: Sheet o f

12

VCCGFXP

1

+

2

B+

PC157

330U_ D2E_2.5VM_R9

Compal Electronics, Inc.

VCCGFX

LA-3261P UMA

45 55Tuesd ay, March 27 , 2007

1

5

4

3

2

1

12

PC89

4.7U_1206_25V6K

12

PC92

2.2U_0603_6.3V6K

B+_6269

PR249

1 2

0_0402_5%

PC95

10P_0402_50V8J

PR137

10K_0402_5%

PU28

17

GND

1

VIN

2

VCC

3

FCCM

4

EN

12

12

12

+6269_VCC

12

16

15UG14

PGOOD

COMP5FB6TEST

PR142

150K_0402_1%

PC97
1000P_0402_50V7K

12

PHASE

PR143

57.6K_0402_1%

PR147
11K_0402_1%

7

12

1 2

BOOT

13

BOOT

PVCC

LG

PGND

ISEN

VO

8

12

PC96

0.01U_0402_16V7K

PR144

1 2

12K_0402_1%

PR136

BOOT1

0_0402_5%

+5VALW

12

PR138

0_0402_5%

PR139

1 2

2.2_0603_5%

12

1 2

2.2U_0603_6.3V6K

11

10

PR141

9

1 2

7.5K_0402_1%

ISL626 9ACRZ-T_QFN16

1 2

PC91

PC90

0.1U_0402_16V7K

+6269_VCC

M_PROK35

PM_SLP_M#20,31, 34,42

UG

LG

LX6269

1 2

PR323

0_0402_5%

PQ47

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

SI4914_SO8

+3VALW

12

PR293
@10K_0402_1%

1 2

PR292

0_0402_5%

APL5912-KAC-TRL_SO8

8
7
6
5

1 2

3.3UH_MPL73-3R3_ 6A_20%

6

PU27

7

POK

VCNTL

8

EN

GND

1

VOUT

VOUT

PL14

VIN

VIN

FB

+5VALW

12

PC139
1U_0603_10V6K

5

9

3

4

2

47K_0402_1%

150K_0402_1%

PR247

PR248

12

12

+1.25VMP

PC142

220U_B2_2.5VM

12

PC140
27P_0402_50V8J

1

+

2

+1.25VM

12

PC138
10U_1206_6.3V6M

+1.05VMP

12

PC141
22U_1206_6.3V6M

D D

B+

C C

PL20

FBM-L11-322513-151LMAT_1210

12

+6269_VCC

PM_SLP_ M#20,3 1,34,42

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

+1.25VMP/+1.05VMP

LA -3 26 1P U MA

1

46 55Tuesday, March 27, 2007

5

Version Change List (

Version Change List ( P. I. R. List ) for Power Circuit (1)

Version Change List ( Version Change List (

It

It em

em Is

ItIt

D D

Page# TTTTitle

emem

Page#Page#

Page42 1.8 V/0.9V 3/9/2006

1

Page45 VCC GFX 3/9/ 2006 Change VCC GFX IC sol uti on from MA X8776 t o ISL6263MAX8776 VI D table ca n't meet I nte l VID SPEC

2

Page43 CPU _CORE 3/10/2006 HP RL

3

itle

itleitle

P. I. R. List ) for Power Circuit (1)

P. I. R. List ) for Power Circuit (1)P. I. R. List ) for Power Circuit (1)

Reque

Request

ate

ateate

RequeReque

OOOOwner

wner

wnerwner

HP RL

4

st

stst

Power S equ ence

Is sue Description

sue DescriptionDDDDate

IsIs

sue Descriptionsue Description

3

No inst all PR131 and in stall PR132
Change SLP _S5# at PR 134 .1 to SLP_S4#
No inst all PR133 and in stall PR134
Add a 0 oh m resistor PR 317 (no st uff) on M_PWROK

Add 27. 4 o hm pull-do wn (no stuff) on
VCCSEN SE & VSSSENSE ne ar VR

2

So

So lution Description

lution Description RRRRev.

SoSo

lution Descriptionlution Description

1

ev.Page#

ev.ev.

DB

DBCompal

DB

Page46 3/9/200 6 H P RL1.25VM/ 1.0 5VM M_PWROK

4

Page46 1.25VM /1. 05VM 4/10/ 200 6 Compa l Corr ect 1.25VM vo ltage setting Change PR1 44 to 12K and PR147 to 11K. DB1-A

5

Page45 VCCGFX 4/10/2 006 Com pal Pow er Sequenc e DB1-AAdd a 0 ohm PR324 (no st uff) on PM_PWROK

6

Page45 VCCGFX 4/24/2 006 Com pal DB1-AAdd a 3 0Ko hm PR325

7

C C

Page42 1.8V/0.9 V Power S equ enceHP MJ5/15/ 200 6 DB1-B

8

Page46 Add PU3 4HP MJ Pow er Good5/15/20 061.25VM/1.05 VM

9

Page38

10

Page43 CPU _CORE 6/5/2006 H P MJ

11

Page41 6/5/200 6

12

Page37, 38, 44 6/22/20 06 HP MJ DB2

13

B B

A A

Page41

14

Page43 CPU _CORE Add 68o hm pull up to +V CCP at PU19.4

15

Page44 ADP _OCP 11/ 08/2006 H P R L Ident ify 65W ad apter a s f ull adapter

16

Page43 CPU _CORE 11/08/2006

17

18

Page42 1.8 V/0.9V 11/13/20 06 HP Add P M_S LP_M# sequ ence Add PR387 SI2

19

Charge

VCCP&1. 5VS DB2

/1.05VC CP

5/15/20 06

8/17/20 06 HP MJ For sequ enc e fine tune Add PC1 81 but not be in stalled2.5VALW /1. 5VS

8/17/20 06 HP RL Add PR3 45 as 68ohm b etw een +VC CP and PU19.4

11/08/2 006

compal

compal Swap +1.05V_VCCP and +1.5VS location

compal

compal

In S3 s tat e, DFGT_VR _EN will n o b e activ ely driven,
it is bet ter to hav e a pull d own resist or on DFGT_VR_EN.

For reducing charge temperture.

for improving power plane.

Chimay sup port for n ew battery ce ll chemi stries

per Int el DG1.0 sec. 4. 4.1.3 F igure 50

For EMI co ncern, add sn abber

Base on "E nergy STAR " s pec, re duc e S5 and S 3
power c ons umption (A C mo de)

Add a 0 oh m resistor PR 323 (in sta ll) on M _PWROK
change PR2 93 pin1 to +3VL

Change 1.5 S to 1.8V in page 42 at pin 23 (VLDOIN)

Change PL5 from 8.2uh MPL73-8R2 to 10UH_PCMB104T-100
Change PR28 from 0.015_2512 to 0.015_1206

investigate that SLP_S3# connect VR_ON
and PM_POK connect PGD_IN

Change PR107 from 100k to 10K,PR111 from 10K to 100K.

P38 : re mov e P R52 , P R38, PR41 ,PR53 , PQ9
P39 :r em ove PR 262 , PR2 63, PR 264, PR76, PQ7 5, PQ 76, P Q32

P37 : A dd PQ 81~ PQ9 1 PR329 ~PR34 1,PD 32~PD 36
P38 :A dd P D37
P44 :A dd PQ 92,P D38,P D39

Change PR2 23 from 18 0K to 182K,
PR258 f rom 29.4K to 22.6K

Add PR3 49 and PR347 as 4.7ohm,
Add PC1 83 and PC182 as 680pF
Change boo st resisto r ( PR148 a nd PR157)f rom 0 to 2 ohm

Uninsta ll PQ11ChargePage38

DB

DB2

DB2

DB2Power S equ ence

SI

SI

SI2

SI2

SI2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

PW R PI R S hee t ( 1)

1

47 55Tuesday, March 27, 2007

5

Version Change List (

Version Change List ( P. I. R. List ) for Power Circuit (2)

Version Change List ( Version Change List (

It

It em

em Is

ItIt

D D

Page# TTTTitle

emem

Page#Page#

Page43 2/28/20 07

20

itle

itleitle

P. I. R. List ) for Power Circuit (2)

P. I. R. List ) for Power Circuit (2)P. I. R. List ) for Power Circuit (2)

Reque

Request

ate

ateate

RequeReque

OOOOwner

wner

wnerwner

Compal Fine tu ne CPU COR E s olutionCPU_COR E

st

stst

4

Is sue Description

sue DescriptionDDDDate

IsIs

sue Descriptionsue Description

3

No inst all PC122
Change PR1 85 from 3K to 1.96K
Change PR1 90 from 6. 19K to 6.34K

2

So

So lution Description

lution Description RRRRev.

SoSo

lution Descriptionlution Description

1

ev.Page#

ev.ev.

MV

Page44 Chan ge PR223 f rom 182K t o 137K

21

Page38 Compal Reserve ci rcu it for tes ting En ergy STAR Reserve PR 397, PR398 , P R399 an d PQ131

22

C C

B B

ADP_OCP 2/28/20 07

Charger 3/1/200 7

System ide ntity

Change PR2 58 from 22 .6K to 29.4K

Add PR3 96 as 0 ohm.

MVHP

MV

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

PW R PI R S hee t ( 1)

1

48 55Tuesday, March 27, 2007

5

4

3

2

1

For DB1-B

<2006.03.29>

D D

<2006.04.10>

C C

<2006.04.21>

1

2

SATA footpr int is wron g

1

2

3

4

5

SPI BIOS ca n not flash .

6

1

2

3

4

22SATA conn ector's PCB footpr int is wron g 0.2chan ge t o OCTEK_SA T-22DD1G_22 P

R243 no inst all and R15 89 install (XDP_DBRESE T#)foll ow I ntel su ggestion fo r XDP_DBRES ET# 4, 20

Chan ge c ompo nent' s footprint for supply and layout easy 07 R14 43 c hange from 0603 s ize to 0402

+VCC _PEG sho uld be 1.05V inste ad of 1.25V for Creat line

10

R146 5 in stall and R1467 no i nstall

Add Q118 , Q1 19, Q1 20, Q121, Q 122, Q123, R1700, R170 1, R1702

Moni tor NB cracked pin s

R170 3, R 1704 , R170 5, R1706, R 1707, R1708 , R1709, R1 710, R171111

21Moni tor SB cracked pin s

Add Q124 , Q1 25, Q126, Q127, R171 6, R1712, R 1713, R1717

R171 8, R1 714, R1719, R1715

Dele te Q1 02, R178 an d Q115

For SPI BIO S flash iss ue

23

Q102 pin 1 sh ort to pi n3-->+3VM c onnect to + 3VM_LAN

PLT_ RST# connect to PM_LAN_EN

For LAN link status 18 cha nge PCI_ PIRQG t o LED_LINK_ LAN# and ad d R1727 0 o hm

For LAN act ive status

23

Add LED_A CT_LAN# thi s net

For ADP_PRE S new desi gn add D68 and dis connect LED _LINK_LAN#20

For LAN net name

chan ge n et na me from LAN _RST to LAN _RSTSYNC

19

chan ge n et n ame from LANLINK_STA TUS# to LE D_LINK_LAN#

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

0.230 A dd R 170, R201, R202 and CLRP3 j open Rese rve resisters on Debug po rts

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

5

<2006.04.24>

B B

1

For Compal Fan design 4 chan ge F an connec tor pin 1 and pin4

For N IC RST 20 cha nge net name from PM_LAN_EN t o LAN_RST#

Add a Re sist er R1722( 0 ohm), R1 732, R1731( no install)35

chan ge n et name from PGD_I N to LAN_RS T#

0.2

0.2

Inst all C991, C99 0, C992, D6 0, R1350

For DB1-C

<2006.05.15>

Syst em can not power o n

1

LAN can not wo rk

2

3

For R TC CLK add R 173319

For LAN functi on

For P WR OK 35 Cha nge R124 pin2's voltage fro m 0.9v to 1 .24VREF

Adju st C 990 and R1350 value to 0 .1uF and 10 0K ohm.

23

modi fy L AN relativ e schematic s

0.3

0.3

0.3

Chan ge R 1732 pin2's vol tage from 3 VM to 3VM_L AN

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

HW P IR

LA-326 1P UMA

1

49 55Tuesday, March 27, 2007

0.4

5

4

3

2

1

For DB2

<2006.05.29>

D D

<2006.06.12>

C C

1

2

3

4

5

6

7

1

modi fy CR ACK_GPIO28 circuits 0.4

for LAN IVRI thermal pr otect and l imit curren t. 23 ad d R1

Add resi sters for GPI pins f loating

Chan ge KBC R ST pin chan ge f rom PLT_RS T# to NCPI_ RST#31

New PCIE ass ignments

11

20

28Chan ge t o USB port assignment s

20

2

3

Chan ge S W design t o Capsense SW.

Add new fea ture (Robso n)

32

15

18Chan ge GPIO pi ns

4

20

Add R173 6, jp53, R 1737 and Q1 29Add new f eature (Kil l switch) 22

dele te R 1700, R170 7, R1705--> NB

dele te R 1712, R171 3, R1714--> SB21

on R 1108 , R1 690, R1245 from +3.3VM _CK505 to + 3VSChan ge p ull up fo r CK505 str apping 15

addR 3, R6, R9, R11, R1 5

Move Doc k1 f rom US B8 to USB7 and move WW AN from USB 3 to USB8

Upda ted Change s:
PCIe - port1 = Free
PCIe - port2 = WLAN
PCIe - port3 = Free
PCIe - port 4 = Robson
PCIe - port 5 = Docking
PCIe - p ort6 = Intel LOM is fixe d at this l ocation

Chan ge S W Co nnector J P18 type an d relative circuits

Add R5, R13 o n SRC6 and R14, R17 on CLKREQ_E#

chan ge G PIO4 (SB) from L ED_LINK_LAN # to PCI_PI RQG#

chan ge G PIO1 (SB) from CB_PE# to LANLINK_STA TUS#(i)

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

0.4

0.4

0.4

0.4

0.4

0.4

5

6

Chan ge H P debug p ort power source

Chan ge KB C 1070 GPIO pins

Add R174 0, R1741 and connect to +3vs

30

CRAC K_GP IO28 from GPIO2 8(KBC) to G PIO8(KBC)

31

add R155 , R1 56, R18 , R20 and t heir signal s connect t o JP18

Add Cap_I NT on GPIO2 5(KBC)

B B

7

8

9

chan ge WA LN power so urce

Chan ge U 75 powe r source fo r LAN funct ion

Chan ge U SB power switch cont rol pin

1 0

For support 2GB DIMMs

25 cha nge from +3val w to +3vM

U75 shou ld b e powered b y V3.3M ins tead of 1.8 VM

23

From S5 to S4_S TATE# to co ntrol USB p ower

28

BJ29 pin and BE24 p in (NB)conn ect to DDR DIMMA, B(A1 4 pin)

7

13, 14

1 1

For Cres tline sigh tings requi res

Modi fy P WROK circuits f or All powe r source ch eck

<2006.06.14>

A A

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

7

add a 0o hm R1759 o n pin N20(N B).

Chan ge R 1732 pin2's vol tage from 3 VM to 3VM_L AN

35

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

HW P IR

LA-326 1P UMA

1

50 55Tuesday, March 27, 2007

0.4

5

4

3

2

1

For DB2

<2006.06.19>

D D

<2006.06.20>

C C

<2006.06.21>

<2006.06.22>

1

2

3

1

2

3

4

5

6

7

8

1

2

1

2

3

Chan ge r esis ter value m eet G-vendo r suggestio n 0.4chan ge R1 359, R1362 VALUE

Kill swit ch design c hange 2 2

Chan ge PWR_ OK circuit 35 d elete R157 a nd PGD_IN n et

Rese rve resister o n HDA _RST# _MDC

dele te t wo compon ents on Deb ug part dele te R1740 , R174130

21

Add new f eature -->R obson

Fix LAN p ower circui t to IVRD

impr ove LAN Power ripp le

Chan ge US B control s ignal

Isol ate p ower noise for NB 10

Enab le WLAN for AMT 25

Impr ove TV-o ut signals and fix TV garbage iss ue

25

32

28Cont rol Audio volu me when boo t

25

23

23

16impr ove DVI issue

28

32

Add R174 9, R1750, R1751 and Q131, D68Ad d Int el RSMRST c ircuit 31

chan ge R 1736 pin2 contact to +RTCVCC

Rese rve R175 3 0 ohm

add EAPD link to KBC GPIO31

Add and chang e JP13 pin assignment for Robson

Dele te R 1 (0. 68ohm), R16 24, and ins tall R1734

Add C136 4, C1 363 on +3V_ LAN and +1. 8VM_LAN

Add SDVO _CLK /Data net name to NB SDVO_CLK/ Data pins

Chan ge c ontr ol signal name to S4 _STATE and add Q132

chan ge R 1453, R 1456 from R esister to bead

Inst all R1753Hold RESET t o modem

Inst all R 194, R195 a nd R197

10

chan ge R 175, R176, R177 from150 ohm to 75 ohm

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

0.4

0.4

0.4

0.4

0.4

0.4

foll ow I ntel Demo circuit for XDP 284Chan ge p ull up R158 9 value for XDP_DBRESE T# from 10K to 1K

<2006.06.23>

B B

1

2

3

4

Chna ge F an Connect or pins' co unt

dele te M DC disable reserve pa rt 32

Impl ement STB_LED# driver

4

Chna ge J P8 from 4p ins to 3 pi ns.

delet e U43B

31

add U4 3B

Modi fy powe r OK circui t 35 add Q13 4, Q133, R3 9, C2

Dele te R 286, R127, C30, R117, R35, R34, R118, U79

5

6

<2006.07.18>

<2006.07.31>

<2006.08.09>

A A

1

2

3

1

1

2

5

Dele te R epeated fu nction circ uit 11

20 Ins tall R179For C -status

34 Cha nge disc harge circuit ne t from PM_S LP_M# to LA N_WOL_EN#For discharg e issue

HP re quest 31 Ins tall R15 5,R156 and un-install R127,R157

25 Ins tall R1383 and no ins tall R1382Do n ot s upport wak e on WWAN c ard

Add anti-pop circuit 26 Add anti- pop circuit

Elim inate glit ch 20 Add R17 67, n o install R 434, C1365, R1757 0.5

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

delet e R1311 7For N on-l ink part (INV_PWM f rom KBC to LCD)

Dele te D21,R52 0

Compal Secret Data

Deciphered Date

0.5

0.5

0.5

0.5

0.5

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

HW P IR

LA-326 1P UMA

1

51 55Tuesday, March 27, 2007

0.4

5

4

3

2

1

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

3

4

D D

<2006.08.11>

C C

<2006.08.21>

5

1

2

3

4

5

6

7

1

2

3

HP re quest 32 Conn ect JP18 pi n1 to +3VL, pin2 to +3 VS 0.5

EMI r equest 0.5

Add M AX9511 9, 16,33 Ad d MAX951 1

For OTS 214499 31 Ad d U82

HP re quest

HP re quest

HP re quest

HP re quest

HP re quest

SIM I/O pull-up footprint is requeste d.

HP re quest

Add D72 and D73 fo r EMI reque st24

0.5

0.5

No i nsta ll R1418, R1358,R1359 ,R1360

25

JP44 PIN 37,43 conn ected to GN D

25

JP44 PIN 39,41 conn ected to +3 VS

Isol ate SLOT powe r from SYST EM power.

25

Remo ve 1. 5V from WWA N slot

25

Inst all s chottkey di ode D74

25

Add R1780 a nd no insta ll

25

25 cha nge +3VS to +3VS_WLAN ,Change +3V S on R1383. 2 to +3VS_W WAN

Chan ge + 3VS on R1071.1 and R1703.1 to +3VS_WW AN

Chan ges for MAX9511

9 0.5HP re quest

Remo ve SW 1,C986,R521 ,D65,R200

25HP re quest 0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

4

5

B B

6

<2006.08.23>

<2006.08.25>

<2006.08.29>

A A

<2006.08.30>

1

2

1

2

1

1

5

HP re quest

HP re quest

HP re quest 19 Move D75 to SB and delete R17 82 0 .5

HP re quest

HP re quest

OTS i ssue 32 Cha nge JP18 pin 8 to WL_BLU E_LED#

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

30

31 0.5

25 Add 139 4 signals o n M/B 0.5

25

20 0.5Swap GPI O01 and G PIO11 conne ctions.

16 Cha nge R142, R144 to 3.9K oh m

2005/03/01 2005/04/06

Need to conn ect SPI_H OLD#_0 and SPI_HOLD#_1 together.

Item 191,192,1 93

Inst all R1363 and NO INSTALL R136425 0.5HP re quest

Add a 0 ohm 0805 on 1 .5VS to WLA N mini card connector

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

0.5

0.5

0.5

0.5

HW P IR

LA3 261P_UMA

1

52 55Tuesday, March 27, 2007

0.1

5

4

3

2

1

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

3

<2006.09.01>

D D

<2006.09.04>

<2006.09.06>

<2006.10.13>

C C

<2006.10.31>

<2006.11.01>

1

1

1

2

3

4

1

2

3

1

1

2

HP re quest

EMI r equest 28 Add R17 90,R1791,R1 792 0.5

HP re quest

HP re quest

HP re quest

HP re quest

Auto power o n issue

1394 issue 28 Modi fy EMI r equest 0.6

7 Add R1786 ,R1787,R178 8,R1789 0.5Int el update

Remo ve R 23 and NP CI_RST# con nection

32

Remo ve P LT_R ST# connection to R21.2 an d connect G PIO28 from ICH8

23 Cha nge C1257 and C1359 t o 10uF 0805

Remo ve R 1412,1413 ,1414,1415, 1416,1417

25

Remo ve R1 418,1358,13 53,1360

30

Add 0 oh m for SPI , R1793,179 4,1795

0.5

0.5

0.525

0.5

0.5

0.6HP r eques t (MAX9511 issue) 9,16,3 3 Remo ve M AX9511 fro m CRT circu it

11,21, 31 No inst all BGA cr ack circuit 0.6

32 Cha nge KB connector 0.6

31 Cha nge RSMRST c ircuit, add R1796 0.6

20 Aut o po wer on issue(add Q140, R1797 ) 0 .6

<2006.11.03>

<2006.11.07>

B B

<2006.11.09>

<2006.11.11>

<2006.11.13>

A A

1

1

2

1

1

1

2

3

4

5

HP re quest 32 Conn ect J P32 pin2 to +3VS 0. 6

HP re quest 31 Inst all R1784, no install R17 83 0.6

Inte l document 10 Ch ange R1471 to 1 00 ohm 0.6

Layou t space 22 R emove kensinto n circuit 0.6

HP re quest 15 Add CLRP 4 and CLRP5 for FSB 667/800 select 0.6

35HP re quest

Tie R173 2.2 to 3V M instead o f 3VM_LAN 0.6

HP re quest 24 Chan ge R 1639 to 1.4K based on Intel W W44 0.6

HP re quest 4 Add res isto rs i n series with the di ode signals going to A DM1032. 0.6

HP re quest 31 Elim inat e gl itch circuit, in stall R1483 and no ins tall R1484 0.6

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

HW P IR

LA3 261P_UMA

53 55Tuesday, March 27, 2007

1

0.1

5

4

3

2

1

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

<2006.11.16>

D D

<2006.11.28>

<2006.12.19>

<2006.12.26>

C C

<2007.01.02>

<2007.01.04>

1

2

3

1

2

1

2

3

1

2

1

1

2

HP re quest

10

Chan ge R 1468, R14 72, R1473 t o bead 0.6

HP re quest 24 Chan ge R1 639 to 1.87 K ohm 0. 6

HP re quest 27 Chan ge R 261 and R253 to 56. 2 ohms 1%. 0.6

HP re quest 23 Inst all Q102 ,R1730, no install R1 612,Q104,Q1 05. 0.6

HP re quest 7 In stall R1739 0.6

HP re quest 35 Add Schm itt Tri gger to eli minate glit ch 0.7

HP re quest 31 Inst all R164 6,C75 0.7

HP re quest 19 Upda te GPI O33 circuit 0.7

HP re quest 7 Ad d C a nd no insta ll 0.7

Chro ntel reque st 16 Add C for DVI I2C 0.7

ME re quest 25 Chan ge JP5 0 for rewro k 0.7

Inte l request 23 0.7Add R1804

ME re quest 32 Chan ge JP 20 to FFC c onnector 0.7

<2007.01.08>

<2007.01.10>

B B

<2007.01.13>

<2007.01.15>

<2007.01.16>

<2007.01.17>

<2007.01.19>

A A

<2007.02.09>

1

1

1

1

1

1

1

2

1

5

EMI r equest 33 Add R18 05,R 1806 0 ohm , reserve C 1372, C1373 0.7

HP re quest 31 R178 3 conn ected to +3 VL 0.7

Comp al request 35 Ch ange LMV 331 to LM3 93, delete R124 and C2 7 0.7

HP re quest 26

R370 , R3 69 - ch ange from 4 .7k to 6.04 k
R374 , R3 75 - ch ange from 4 .7k to 2.00 k

0.7

HP re quest 25 Conn ected R1780.2 to UIM_PWR 0.7

HP re quest 30 Add pad fo r BIOS debu g 0.7

HP re quest

CRT wavy issue

34

Add R1807 a nd no stuff

10

Add C1374 for CRT wa vy issue

0.7

0.7

CRT wavy issue 17 Ad d 10 uFX2 for CRT w avy issue(C 586, C1376) 0.9

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

HW P IR

LA3 261P_UMA

54 55Tuesday, March 27, 2007

1

0.1

5

4

3

2

1

M. B . V e r.Re as o n fo r ch an ge PA G E Mod i fy L is tFi xe d Is su eIt em

<2007.02.09>

D D

<2007.02.16>

<2007.02.26>

<2007.02.27>

C C

<2007.02.28>

<2007.03.01>

2

1

2

3

4

5

1

1

2

1

1

2

HP re quest

+3VM _LAN leaka ge 20 0.9

30

Add Q142 for F PR 0.9

Add U83 for aut o boot and leakage iss ue

Comp al request 15 De lete C LPR4, CLRP5 0.9

HP re quest 34 Inst all R1807 an d non insta ll R630 0.9

LVDS sequenc e issue 17 Cha nge C2 8 to 0.1uF 0.9

HP re quest 31 Add R1809 to G ND 0.9

Safe ty request 33 Ch ange RJ11 conne ctor 0.9

HP re quest 0.92 7 Chan ge R 261 and R 253 to 60.4 ohm

HP re quest 35 Move R1803 0.9

HP re quest 11,21 Cha nge to +3V L 0 .9

HP re quest 10 CRT wavy issue -- ad d C1374 0.9

HP re quest 15 Add CAP fo r WWAN issu e 0.9

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

HW P IR

LA3 261P_UMA

1

55 55Tuesday, March 27, 2007

0.1