HP 6440b, 6540b Schematics

1 1

Compal Confidential

Schematics Document

2 2

AUBURNDALE/CLARKSFIELD with Intel IBEX PEAK-M core logic

Dior DIS

3 3

2008-10-30

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-4891

0.1

1 50Thursday, October 30, 2008

0.1

Compal Confidential

File Name : Dior DIS

Thermal Sensor ADM1032

1 1

Page 23

LCD conn

CRT

Fan Control

Page 4

Page 20

Page 19

CRT to Docking

Page 33

HDMI conn

Page 23

2 2

Express Card 54

WWAN Card

Sub-board

Page 34

DP to Docking

ATI M92S/M93S

Page 21,22,23,24,25

Page 29

Page 33

VRAM*4

Page 26

Mini-Card UWB

PCI-E BUS

Dior DIS

Mobile

PEG

Page 29

CPU Dual Core

Socket-rPGA989

37.5mm*37.5mm

Page 4,5,6,7,8

DMI X4

Intel Ibex Peak M

1071pins

25mm*27mm

USB2.0

Azalia

SATA0

Dual Channel

XDP Conn.

DDR3-SO-DIMM X 2DDR3 1066/1333MHz 1.5V

BANK 0, 1, 2, 3

USB x2(Docking) USB x2(Sub/B) FingerPrinter VFM451

USBx1

USB conn x 2(For I/O) BT Conn USB x 1

Page 4

Page 9,10

Page 34

Page 31

Accelerometer

LIS302DLTR

Page 31

CK505

Clock Generator ICS9LPRS397

Page 11

daughter board

10/100/1000 LAN Marvell

88E8072/88E8075

Page 27

WLAN Card

Page 29

1394/Card Reader

Sub-board

Page 34

Page 12,13,14,15,16,17

ONFI Interface

SATA1

Braidwood

RJ45 CONN

3 3

Page 28

1394 port

SD/MMC/ MS/XD Slot

Page 18

NAND card

LPC BUS

USB x1(Camara)

MDC V1.5

Audio CKT

Sub-board

SATA ODD Connector

Page 20

Page 30

92HD75

Page 34

Page 18

2.5" SATA HDD Connector

Page 18

RJ11

Page 30

TPA6047A

AMP & Audio Jack

Page. 33

(2) PS/2 Interfaces (2) USB 2.channels

Docking CONN.

Page 34

(2) SATA Channels

RTC CKT.

Page 34

Power OK CKT.

4 4

Power On/Off CKT.

DC/DC Interface CKT.

Page 37

Page 30

Page 38

LED

Page 34

TPM1.2

SLB9635TT

Page 32 page 35

Touch Pad CONN.

TrackPoint CONN.

SPI ROM 4MB

SMSC KBC 1098

Page 34

Page 30

Page 32

Super I/O IT8305E

Int.KBD

Page 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

COM1 LPT ( Docking ) ( Docking )

Page 33 Page 33

2008/10/24 2009/10/24

Page 36

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

(2) Display Port Channels (1) Serial Port (1) Parallel Port (1) Line In (1) Line Out (1) RJ45 (10/100/1000) (1) VGA (1) 2 LAN indicator LED's (1) Power Button (1) I2C interface

Compal Electronics, Inc.

Block Diagram

LA-4891

0.1

2 50Monday, October 27, 2008

0.1

Voltage Rails

State

( O MEANS ON X MEANS OFF )

+RTCVCC

power plane

+B +3VL +0.75V

+5VALW +3VALW

+1.5V

+5VS +3VS +1.5VS +NVVDD +VCCP +CPU_CORE +1.05VS +1.8VS

Symbol Note :

: means Digital Ground

: means Analog Ground

Install below 43 level BOM structure for ver. 0.1

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

O O O O O O

O O O O O

O O O O

X X X

OO OO

DEBUG@ : means just build when PCIE port 80 CARD function enable. M92@ : Install for M92 Graphic controller 8072@ : Install for 8072 NIC controller 1098@ : Install for 1098 KBC controller CK32@ : Install for 32 pin CLOCK GEN

Install below 45 level BOM structure for ver. 0.1

45@ : means just put it in the BOM of 45 level.

Remove before MP

Reserve below BOM structure for ver. 0.1

@ : means just reserve , no build CONN@ : means ME part. M93@ : Install for M93 Graphic controller 8075@ : Install for 8075 NIC controller

SMBUS Control Table

SOURCE

BATT

THERMAL

SODIMM CLK CHIP

XDP G-SENSOR

MINI CARD

DOCK

NIC

SENSOR

1091@ : Install for 1091 KBC controller CK72@ : Install for 72 pin CLOCK GEN

SMB_EC_CK1 SMB_EC_DA1

SMBCLK SMBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

SMSC1098

Calpella

X X X

X X

V V

X X

V V V

X X

X X X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-4891

3 50Monday, October 27, 2008

0.1

H_CPURST#

1 2

24.9K_0402_1%

T1PAD T1PAD

R14

1 2

0_0402_5%

R15

1 2

0_0402_5%

R19

1 2

0_0402_5%

1 2

R20

1 2

R21

0_0402_5%

R23

1 2

0_0402_5%

R25

1 2

0_0402_5%

R29

1 2

0_0402_5%

R30

1 2

12.4K_0402_1%

R220_0402_1% R220_0402_1%

1 2

R920_0402_1% R920_0402_1%

1 2

R349.9_0402_1% R349.9_0402_1%

1 2

R549.9_0402_1% R549.9_0402_1%

1 2

TP_SKTOCC#

H_CATERR#

H_PECI_ISO

H_PROCHOT#_D

H_THERMTRIP#_R

R18

0_0402_5%

H_PM_SYNC_R

0_0402_5%

VCCPWRGOOD_1

VCCPWRGOOD_0

VDDPWRGOOD_R

H_PWRGD_XDP_RH_PWRGD_XDP

PLT_RST#_R

R32

COMP3 COMP2 COMP1 COMP0

H_CPURST#_R

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

MISC THERMAL

PWR MANAGEMENT

Layout rule：10mil width trace length < 0.5", spacing 20mil

D D

H_PECI15

H_PROCHOT#47

H_THERMTRIP#15

H_PM_SYNC14

H_CPUPWRGD

H_CPUPWRGD15

C C

PM_DRAM_PWRGD14

VTTPWRGOOD37

BUF_PLT_RST#15

PWM Fan Control

B B

circuit

+5VS

09/24 HP

R42

0_0603_5%

1 2

0.1U_0402_10V6K@C20.1U_0402_10V6K@

+5VS_FAN

FAN_PWM35

conn@

JP2

ACES_85204-03001

CLOCKS

DDR3

JTAG & BPM

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

PM_EXT_TS#[0] PM_EXT_TS#[1]

MISC

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

PM_EXTTS#0

from DDR

H_CPUPWRGD

H_PWRGD_XDP

10/09 HP

PM_PWRBTN#_R

PM_EXTTS#1

VDDPWRGOOD_R

+VCCP

R26 0_0402_5%R26 0_0402_5%

RP2

CLK_BCLK

A16

CLK_BCLK#

B16

CLK_CPU_XDP

AR30

CLK_CPU_XDP#

AT30

CLK_PEG

E16

CLK_PEG#

D16

R40 0_0402_5%R40 0_0402_5%

A18

1 2

A17

1 2

R39 0_0402_5%R39 0_0402_5%

SM_RCOMP0

AL1

SM_RCOMP1

AM1

SM_RCOMP2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

TCK

XDP_TMS

AP28

TMS

XDP_TRST#

AT27

XDP_TDI_R

AT29

TDI

XDP_TDO_R

AR27

TDO

XDP_TDI_M

AR29

XDP_TDO_M

AP29

XDP_DBRESET#

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

1 4 2 3

T91 PADT91 PAD

1 2

R17 0_0402_5%R17 0_0402_5%

0_4P2R_5%

CK32@

RP4

0_4P2R_5%

CK32@

CLK_CPU_BCLK_P 15 CLK_CPU_BCLK#_P 15

CLK_EXP 13 CLK_EXP# 13

DRAMRST# 9,10

PM_EXTTS#1_R 9,10

0.1U_0402_10V6K

PM_PWRBTN#_R14

SMB_DATA_S39,10,11,13,27,29,31,33 SMB_CLK_S39,10,11,13,27,29,31,33

+VCCP

R48

R48 1K_0402_5%

1K_0402_5%

1 2

R24

R24 1K_0402_5%

1K_0402_5%

1 2

R1 10K_0402_5%R1 10K_0402_5%

1 2

R7 10K_0402_5%R7 10K_0402_5%

1 2

R12 4.75K_0402_1%R12 4.75K_0402_1%

1 2

R13 12K_0402_1%R13 12K_0402_1%

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

XDP_BPM#4 XDP_BPM#5

XDP_BPM#6 XDP_BPM#7

H_CPUPWRGD_R PM_PWRBTN#_R

XDP_TCK

H_CATERR# H_PROCHOT#_D H_CPURST#_R

DDR3 Compensation Signals

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

Layout Note:Please these resistors near Processor

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

+VCCP

+1.5V

XDP_TDI_R XDP_TMS XDP_PREQ# XDP_TDO

XDP_TCK

1 2

R8 51_0402_5%@R8 51_0402_5%@

1 2

R10 51_0402_5%@R10 51_0402_5%@

1 2

R4 51_0402_5%@R4 51_0402_5%@

1 2

R6 51_0402_5%R6 51_0402_5%

This shall place near XDP

1 2

R11 51_0402_5%@R11 51_0402_5%@

This shall place near CPU

XDP Connector

JP1

GND0

OBSFN_A0

OBSFN_A1

GND2

OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16

SAMTE_BSH-030-01-L-D-A CONN@

Processor Pullups JTAG MAPPING

1 2

R34 50_0402_1%R34 50_0402_1%

1 2

R36 68_0402_5%R36 68_0402_5%

1 2

R37 68_0402_5%@R37 68_0402_5%@

1 2

R44 100_0402_1%R44 100_0402_1%

1 2

R45 24.9_0402_1%R45 24.9_0402_1%

1 2

R46 130_0402_1%R46 130_0402_1%

ITPCLK/HOOK4

ITPCLK#/HOOK5

RESET#/HOOK6

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

VCC_OBS_CD

DBR#/HOOK7

GND15

TRST#

GND17

+VCCP

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

CLK_CPU_XDP

CLK_CPU_XDP#

42 44

XDP_RST#_R

XDP_DBRESET#

48 50

XDP_TDO

TD0

TDI

TMS

XDP_TRST#

XDP_TDI

XDP_TMS

58 60

XDP_TDI_R

XDP_TDI_M

XDP_TDO_R

XDP_TRST#

+VCCP

XDP_RST#_R

R33 0_0402_5%R33 0_0402_5%

R35 0_0402_5%@R35 0_0402_5%@

R38

R38 0_0402_5%

0_0402_5%

1 2

R41 0_0402_5%@R41 0_0402_5%@

R43 0_0402_5%R43 0_0402_5%

10/09 HP

Close to XDP

R47 51_0402_5%R47 51_0402_5%

+VCCP

1K_0402_5%

R27

1 2

PLT_RST#

1 2

R31 0_0402_5%

1 2

H_CPURST#

XDP_TDI

XDP_TDOXDP_TDO_M

+3VS

R22

R22 1K_0402_5%

1K_0402_5%

1 2

PLT_RST# 12,15,21,27,29,32,34

XDP_DBRESET# 12,14

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

LA-4891

4 50Monday, October 27, 2008

0.1

JCPU1A

DMI_CRX_PTX_N014 DMI_CRX_PTX_N114 DMI_CRX_PTX_N214 DMI_CRX_PTX_N314

DMI_CRX_PTX_P014 DMI_CRX_PTX_P114

D D

DMI_CRX_PTX_P214 DMI_CRX_PTX_P314

DMI_CTX_PRX_N014 DMI_CTX_PRX_N114 DMI_CTX_PRX_N214 DMI_CTX_PRX_N314

DMI_CTX_PRX_P014 DMI_CTX_PRX_P114 DMI_CTX_PRX_P214 DMI_CTX_PRX_P314

C C

R51 1K_0402_5%R51 1K_0402_5% R52 1K_0402_5%R52 1K_0402_5%

R55 1K_0402_5%R55 1K_0402_5% R56 1K_0402_5%R56 1K_0402_5%

R57 1K_0402_5%R57 1K_0402_5%

B B

12 12

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS PEG_RX#[0]

PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

EXP_ICOMPI

1 2

EXP_RBIAS

1 2

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N15

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P15

PCIE_CTX_GRX_C_N0 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N15

PCIE_CTX_GRX_C_P0 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P15

Layout rule：trace length < 0.5"

R49 49.9_0402_1%R49 49.9_0402_1%

R50 750_0402_1%R50 750_0402_1%

PCIE_CRX_GTX_N[0..15] 21

PCIE_CRX_GTX_P[0..15] 21

C6 0.1U_0402_10V6KC6 0.1U_0402_10V6K

1 2

C7 0.1U_0402_10V6KC7 0.1U_0402_10V6K

1 2

C8 0.1U_0402_10V6KC8 0.1U_0402_10V6K

1 2

C9 0.1U_0402_10V6KC9 0.1U_0402_10V6K

1 2

C10 0.1U_0402_10V6KC10 0.1U_0402_10V6K

1 2

C11 0.1U_0402_10V6KC11 0.1U_0402_10V6K

1 2

C12 0.1U_0402_10V6KC12 0.1U_0402_10V6K

1 2

C13 0.1U_0402_10V6KC13 0.1U_0402_10V6K

1 2

C14 0.1U_0402_10V6KC14 0.1U_0402_10V6K

1 2

C15 0.1U_0402_10V6KC15 0.1U_0402_10V6K

1 2

C16 0.1U_0402_10V6KC16 0.1U_0402_10V6K

1 2

C17 0.1U_0402_10V6KC17 0.1U_0402_10V6K

1 2

C18 0.1U_0402_10V6KC18 0.1U_0402_10V6K

1 2

C19 0.1U_0402_10V6KC19 0.1U_0402_10V6K

1 2

C20 0.1U_0402_10V6KC20 0.1U_0402_10V6K

1 2

C21 0.1U_0402_10V6KC21 0.1U_0402_10V6K

1 2

C22 0.1U_0402_10V6KC22 0.1U_0402_10V6K

1 2

C23 0.1U_0402_10V6KC23 0.1U_0402_10V6K

1 2

C24 0.1U_0402_10V6KC24 0.1U_0402_10V6K

1 2

C25 0.1U_0402_10V6KC25 0.1U_0402_10V6K

1 2

C26 0.1U_0402_10V6KC26 0.1U_0402_10V6K

1 2

C27 0.1U_0402_10V6KC27 0.1U_0402_10V6K

1 2

C28 0.1U_0402_10V6KC28 0.1U_0402_10V6K

1 2

C29 0.1U_0402_10V6KC29 0.1U_0402_10V6K

1 2

C30 0.1U_0402_10V6KC30 0.1U_0402_10V6K

1 2

C31 0.1U_0402_10V6KC31 0.1U_0402_10V6K

1 2

C32 0.1U_0402_10V6KC32 0.1U_0402_10V6K

1 2

C33 0.1U_0402_10V6KC33 0.1U_0402_10V6K

1 2

C34 0.1U_0402_10V6KC34 0.1U_0402_10V6K

1 2

C35 0.1U_0402_10V6KC35 0.1U_0402_10V6K

1 2

C36 0.1U_0402_10V6KC36 0.1U_0402_10V6K

1 2

C37 0.1U_0402_10V6KC37 0.1U_0402_10V6K

1 2

PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N8

PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11

PCIE_CTX_GRX_N12

PCIE_CTX_GRX_N13

PCIE_CTX_GRX_N14

PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_P3

PCIE_CTX_GRX_P4

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P9

PCIE_CTX_GRX_P10

PCIE_CTX_GRX_P11

PCIE_CTX_GRX_P12

PCIE_CTX_GRX_P13

PCIE_CTX_GRX_P14

PCIE_CTX_GRX_P15

PCIE_CTX_GRX_N[0..15] 21

PCIE_CTX_GRX_P[0..15] 21

V_DDR_CPU_REF1

V_DDR_CPU_REF0

09/18

T2 PADT2 PAD T3 PADT3 PAD T4 PADT4 PAD T5 PADT5 PAD T6 PADT6 PAD T7 PADT7 PAD T8 PADT8 PAD T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD T13 PADT13 PAD T14 PADT14 PAD T15 PADT15 PAD T16 PADT16 PAD T17 PADT17 PAD T18 PADT18 PAD T19 PADT19 PAD T20 PADT20 PAD

0_0402_5%@

1 2 1 2

0_0402_5%@

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

CFG0

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

H16

B19 A19

A20 B20

U9 T9

AC9 AB9

C1 A3

J29 J28

A34 A33

C35 B35

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18

R58

R59

RESERVED

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

RSVD_TP_59 RSVD_TP_60

RSVD62 RSVD63 RSVD64 RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2

KEY

D15

0_0402_5%@

C15

1 2

AJ15

1 2

AH15

0_0402_5%@

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

VSS

R53

R54

IC,AUB_CFD_rPGA,R1P0

Deciphered Date

IC,AUB_CFD_rPGA,R1P0

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

LA-4891

5 50Monday, October 27, 2008

0.1

CFG Straps for PROCESSOR

CFG0

CFG3

A A

CFG4

1 2

R60 3.01K_0402_1%@ R60 3.01K_0402_1%@

PCI-Express Configuration Select

1: Single PEG 0: Bifurcation enabled

CFG0

Not applicable for Clarksfield Processor

1 2

R62 3.01K_0402_1%R62 3.01K_0402_1%

CFG3-PCI Express Static Lane Reversal

CFG3

1 2

CFG4-Display Port Presence

CFG4

10/02

1: Normal Operation 0: Lane Numbers Reversed

15 -> 0, 14 ->1, .....

R63

3.01K_0402_1%@

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

CFG7

1 2

R61 3.01K_0402_1%@R61 3.01K_0402_1%@

Only temporary for early CFD samples (rPGA/BGA) No needed by MoW41.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

JCPU1C

JCPU1D

D D

DDR_A_D[0..63]9

C C

B B

DDR_A_BS09 DDR_A_BS19 DDR_A_BS29

DDR_A_CAS#9 DDR_A_RAS#9 DDR_A_WE#9

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ10 AL10

AK12

AK11

AM10 AR11

AL11

AT11 AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14 AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

F10

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

H10

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_DQ[20]

G10

SA_DQ[21]

SA_DQ[22]

J10

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39] SA_DQ[40]

AJ9

SA_DQ[41] SA_DQ[42] SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45] SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 9 M_CLK_DDR#0 9 DDR_CKE0_DIMMA 9

M_CLK_DDR1 9 M_CLK_DDR#1 9 DDR_CKE1_DIMMA 9

DDR_CS0_DIMMA# 9 DDR_CS1_DIMMA# 9

M_ODT0 9 M_ODT1 9

DDR_A_DM[0..7] 9

DDR_A_DQS#[0..7] 9

DDR_A_DQS[0..7] 9

DDR_A_MA[0..15] 9

DDR_B_D[0..63]10

DDR_B_BS010 DDR_B_BS110 DDR_B_BS210

DDR_B_CAS#10 DDR_B_RAS#10 DDR_B_WE#10

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR10 AT10

SB_DQ[0]

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SB_DQ[7]

SB_DQ[8]

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61] SB_DQ[62] SB_DQ[63]

AB1

SB_BS[0]

SB_BS[1]

SB_BS[2]

AC5

SB_CAS#

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 10 M_CLK_DDR#2 10 DDR_CKE2_DIMMB 10

M_CLK_DDR3 10 M_CLK_DDR#3 10 DDR_CKE3_DIMMB 10

DDR_CS2_DIMMB# 10 DDR_CS3_DIMMB# 10

M_ODT2 10 M_ODT3 10

DDR_B_DM[0..7] 10

DDR_B_DQS#[0..7] 10

DDR_B_DQS[0..7] 10

DDR_B_MA[0..15] 10

IC,AUB_CFD_rPGA,R1P0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LA-4891

6 50Monday, October 27, 2008

0.1

+CPU_CORE

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA,R1P0

CPU CORE SUPPLY

POWER

1.1V RAIL POWER

CPU VIDS

SENSE LINES

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

PSI#

AH14

10U_0805_10V4K

AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

G15

C38

10U_0805_10V4K

C42

10U_0805_10V4K

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR_R

H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V

AN35

VCC_SENSE VSS_SENSE

VCCSENSE VSSSENSE

1 2 1 2

AJ34 AJ35

B15 A15

10U_0805_10V4K

C39

10U_0805_10V4K

C43

+VCCP

10U_0805_10V4K

C60

C59

PSI# 47 H_VID[0..6] 47

1 2

R67 0_0402_5%R67 0_0402_5%

H_VTTVID1 44

IMVP_IMON 47

0_0402_5%

R68

R68 R69 0_0402_5%R69 0_0402_5%

VTT_SENSE 44 VSS_SENSE_VTT 44

Close to CPU

1 2

R70 100_0402_1%R70 100_0402_1%

1 2

R71 100_0402_1%R71 100_0402_1%

10U_0805_10V4K

C40

C44

VCCSENSE VSSSENSE

10U_0805_10V4K

C41

C45

10U_0805_10V4K

C52

+CPU_CORE

+VCCP

10U_0805_10V4K

C46

10U_0805_10V4K

C53

C54

PROC_DPRSLPVR 47

VCCSENSE 47 VSSSENSE 47

+VCCP

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

+VCCP

47P_0402_50V8J@

C744

47P_0402_50V8J

09/24 HP

47P_0402_50V8J@

C745

C746

47P_0402_50V8J@

09/24 HP

C741

47P_0402_50V8J@

C742

47P_0402_50V8J@

C747

C748

+VCCP

10U_0805_10V4K

C61

+VCCP

10U_0805_10V4K

C65

10U_0805_10V4K

C67

C66

47P_0402_50V8J@

C743

47P_0402_50V8J

10U_0805_10V4K

C55

+CPU_CORE

47P_0402_50V8J@

CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

10U_0805_10V4K

VTT1_45

J23

VTT1_46

H25

C62

VTT1_47

K26

10U_0805_10V4K

VTT1_48

J27

VTT1_49

J26

C68

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

2008/10/24 2009/10/24

GRAPHICS

FDI PEG & DMI

Compal Secret Data

SENSE

GRAPHICS VIDs

POWER

0.6A

Deciphered Date

VAXG_SENSE

VSSAXG_SENSE

LINES

GFX_VR_EN

GFX_DPRSLPVR

DDR3 - 1.5V RAILS

1.1V1.8V

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25

R64 1K_0402_5%R64 1K_0402_5%

AM24

AJ1

1U_0603_10V4Z

AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

C47

330U_D2_2VM_R6M

C56

1U_0603_10V4Z

C71

+1.5V

1U_0603_10V4Z

C48

10U_0805_10V4K

C57

10U_0805_10V4K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C73

C73

C72

Title

Size Document Number Rev

Custom

Date: Sheet of

1U_0603_10V4Z

C50

C49

C58

+VCCP

C63

C69

LA-4891

C51

10U_0805_10V4K

C64

+VCCP

10U_0805_10V4K

C70

+1.8VS

4.7U_0603_6.3V6K

10U_0805_10V4K

C75

C74

Compal Electronics, Inc.

Auburndale(4/5)-PWR

7 50Monday, October 27, 2008

0.1

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17 AR15 AR12

AP20 AP17 AP13 AP10

AN34 AN31 AN23 AN20

AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AL34

AL31

AL23

AL20

AL17

AL12

AK29 AK27 AK25 AK20 AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AG10

AE35

VSS8 VSS9 VSS10 VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14 VSS15 VSS16 VSS17 VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75 VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

JCPU1I

K27

VSS161

VSS162

VSS163

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

VSS179

VSS180

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

VSS185

VSS186

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

VSS202

VSS203

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

VSS208

VSS209

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

VSS227

VSS228

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

VSS233

VSS

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

NCTF

AT1 AR34 B34 B2 B1 A35

VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R

VSS_NCTF1_R

AT35

+CPU_CORE

T54T54 T55T55 T78T78 T79T79 T80T80 T56T56 T57T57

CPU CORE

10U_0805_10V4K

C76

10U_0805_10V4K

C88

10U_0805_10V4K

C77

C78

10U_0805_10V4K

C90

C89

22U_0805_6.3V6M

C99

C98

10U_0805_10V4K

C80

C79

10U_0805_10V4K

C91

C92

22U_0805_6.3V6M

C101

C100

10U_0805_10V4K

C81

10U_0805_10V4K

C93

22U_0805_6.3V6M

C102

10U_0805_10V4K

C82

C83

10U_0805_10V4K

C95

C94

22U_0805_6.3V6M

C103

Under cavity

10U_0805_10V4K

C85

C84

10U_0805_10V4K

C96

C97

330U_D2_2VM_R6M

C109

C108

10/14 HP

10U_0805_10V4K

C87

C86

Inside cavity

between Inductor and socket

22U_0805_6.3V6M

330U_D2_2VM_R6M

470U_D2_2VM_R4.5M

C106

470U_D2_2VM_R4.5M

C107

C104

22U_0805_6.3V6M

470U_D2_2VM_R4.5M

C105

C110

22U_0805_6.3V6M

C112

C113

C111

C113

IC,AUB_CFD_rPGA,R1P0

A A

IC,AUB_CFD_rPGA,R1P0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

LA-4891

8 50Monday, October 27, 2008

0.1

V_DDR_CPU_REF

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C114

C114

D D

C C

B B

A A

DDR_CKE0_DIMMA6

DDR_A_BS26

M_CLK_DDR06 M_CLK_DDR#06

DDR_A_BS06 DDR_A_WE#6

DDR_A_CAS#6

DDR_CS1_DIMMA#6

+3VS

DDR_A_D0

C115

DDR_A_D1 DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# M_ODT0 DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

1 2

10K_0402_5%

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C136

C136

C135

+1.5V +1.5V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDIMMA1 CONN@JDIMMA1 CONN@

VREF_DQ1VSS1

VSS2

DQ0

DQ1 VSS49DQS#0

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R79

10K_0402_5%

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

R80

VTT1

205

DQ4 DQ5

VSS3

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA VTT2

A15 A14

A11

A7 A6

A4 A2

CK1

BA1

S0#

NC2

SCL

TOP SLOT

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#1_R

SMB_DATA_S3 SMB_CLK_S3

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DRAMRST# 4,10

DDR_CKE1_DIMMA 6

M_CLK_DDR1 6 M_CLK_DDR#1 6

DDR_A_BS1 6 DDR_A_RAS# 6

DDR_CS0_DIMMA# 6 M_ODT0 6

M_ODT1 6

1 2

R78 0_0402_5%R78 0_0402_5%

1 2

R104 0_0402_5%@R104 0_0402_5%@

09/18 as short as possible

DDR_VREF_CA_DIMMA

PM_EXTTS#1_R 4,10

SMB_DATA_S3 4,10,11,13,27,29,31,33 SMB_CLK_S3 4,10,11,13,27,29,31,33

V_DDR_CPU_REF

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C130

C130

C129

DDR_A_D[0..63]6 DDR_A_DM[0..7]6 DDR_A_DQS[0..7]6 DDR_A_DQS#[0..7]6 DDR_A_MA[0..15]6

V_DDR_CPU_REF

V_DDR_CPU_REF0

+1.5V

R76

1K_0402_1%

Layout Note: Place near DIMM

10U_0603_6.3V6M

C116

C117

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5V

10U_0603_6.3V6M

C118

Layout Note: Place near DIMM

10U_0603_6.3V6M

C119

C120

2008/10/24 2009/10/24

+0.75VS

C131

10U_0603_6.3V6M

C121

1U_0603_10V4Z

C132

V_DDR_CPU_REF

R77

R77 1K_0402_1%

1K_0402_1%

C122

1U_0603_10V4Z

Compal Secret Data

10U_0603_6.3V6M

C123

C134

C133

1U_0603_10V4Z

Deciphered Date

0.1U_0402_10V6K

0.1U_0402_10V6K C124

C124

1U_0603_10V4Z

C159

10U_0603_6.3V6M

C159

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K C125

C125

VREFDQ

0.1U_0402_10V6K

V_DDR_CPU_REF

V_DDR_CPU_REF0

V_DDR_CPU_REF1

0.1U_0402_10V6K

C126

R76, R77, R78, R81,

R104, R110

330U_D2_2VM_R6M

C128

C127

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-4891

0.1

9 50Monday, October 27, 2008

0.1

V_DDR_CPU_REF

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

C137

+3VS

DDR_CKE2_DIMMB6

DDR_B_BS26

M_CLK_DDR26 M_CLK_DDR#26

DDR_B_BS06 DDR_B_WE#6

DDR_B_CAS#6

DDR_CS3_DIMMB#6

2.2U_0603_6.3V4Z

D D

C C

B B

A A

V_DDR_CPU_REF DDR_B_D0

DDR_B_D1

C138

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# M_ODT2 DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

1 2

10K_0402_5%

0.1U_0402_10V6K

C157

C158

+1.5V +1.5V

3A@1.5V

3A@1.5V3A@1.5V

CONN@

JDIMMB1

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2 DQS247VSS17

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R82

1 2

R83 10K_0402_5%R83 10K_0402_5%

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2 DQ22

DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1 RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

A14

82 84

A11

88 90

94 96

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

BOT SLOT

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT3

DDR_VREF_CA_DIMMB DDR_B_D36

DDR_B_D37 DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#1_R

SMB_DATA_S3 SMB_CLK_S3

DRAMRST# 4,9

DDR_CKE3_DIMMB 6

M_CLK_DDR3 6 M_CLK_DDR#3 6

DDR_B_BS1 6 DDR_B_RAS# 6

DDR_CS2_DIMMB# 6 M_ODT2 6

M_ODT3 6

R81

1 2 1 2

R110 0_0402_5%@R110 0_0402_5%@

09/18 as short as possible

PM_EXTTS#1_R 4,9

SMB_DATA_S3 4,9,11,13,27,29,31,33 SMB_CLK_S3 4,9,11,13,27,29,31,33

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

0_0402_5%

DDR_VREF_CA_DIMMB

DDR_B_DQS#[0..7]6 DDR_B_D[0..63]6 DDR_B_DM[0..7]6 DDR_B_DQS[0..7]6 DDR_B_MA[0..15]6

V_DDR_CPU_REF

0.1U_0402_10V6K

C151

V_DDR_CPU_REF1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C152

C152

Layout Note: Place near DIMM

10U_0603_6.3V6M

C139

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C141

C140

Layout Note: Place near DIMM

+0.75VS

1U_0603_10V4Z

C153

C154

2008/10/24 2009/10/24

+1.5V

10U_0603_6.3V6M

C142

1U_0603_10V4Z

C155

10U_0603_6.3V6M

C143

1U_0603_10V4Z

C156

Compal Secret Data

10U_0603_6.3V6M

C145

C144

Deciphered Date

10U_0603_6.3V6M

C146

0.1U_0402_10V6K

C147

C148

0.1U_0402_10V6K

C149

C150

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

LA-4891

10 50Monday, October 27, 2008

0.1

CLK_BUF_DOT9613

CLK_BUF_DOT96#13

27M_CLK23

D D

+1.05VS_CK505+1.05VS

1 2

R970_0603_5% R970_0603_5%

1 2

R840_0603_5% R840_0603_5%

+3VS_CK505

+3VS

C C

10U_0805_10V4K

C177

C176

10U_0805_10V4K

C164

0.1U_0402_10V6K

C165

C166

CLK_BUF_CKSSCD13

CLK_BUF_CKSSCD#13

Close to U2/U3

0.1U_0402_10V6K

0.1U_0402_10V6K C179

C179

C178

Close to U2/U3

0.1U_0402_10V6K

C167

C168

CLK_DMI13

CLK_DMI#13

0.1U_0402_10V6K

C180

0.1U_0402_10V6K

0.1U_0402_10V6K C169

C169

+VCCP

CPU_1PIN 30 CPU_0

(Default)

0 133MHz

B B

FSLC1FSLB

CLKSEL1

CLKSEL2

133MHz

100MHz 100MHz

CPU

FSLA

CLKSEL0

MHz

SRC MHz

PCI MHz

CLK_BUF_DOT96 CLK_BUF_DOT96#

27M_CLK L_27M_CLK

CLK_BUF_CKSSCD CLK_BUF_CKSSCD#

CLK_DMI

R93 0_0402_5%CK32@R93 0_0402_5%CK32@

CLK_DMI#

R95

C181

STP_PCI#_R

R98 10K_0402_5%

CPU_STOP#

0.1U_0402_10V6K

0.1U_0402_10V6K C170

C170

1 2

R99 10K_0402_5%

1 2

C221

10P_0402_50V8J@

C174

EMI Capacitor

1 2

R100 10K_0402_5%@R100 10K_0402_5%@

1 2

R101 10K_0402_5%

CK32@

1 1000 1001 33.3

R122

4.7K_0402_5%

A A

R128

4.7K_0402_5%@

1000

133

166

R123

4.7K_0402_5%@

+1.05VS_CK505_U3+1.05VS_CK505_U3

100

R129

33.30

33.3

4.7K_0402_5%

4.7K_0402_5%@

FSCFSBFSA

+1.05VS_CK505_U3

R124

R130

4.7K_0402_5%

R85 0_0402_5%CK32@R85 0_0402_5%CK32@

1 2

R87 0_0402_5%CK32@R87 0_0402_5%CK32@ R89 33_0402_5%CK32@R89 33_0402_5%CK32@

1 2

R91 0_0402_5%CK32@R91 0_0402_5%CK32@

1 2

R92 0_0402_5%CK32@R92 0_0402_5%CK32@

1 2

CK72@

REF_0/CPU_SEL

10P_0402_50V8J@

REF_0/CPU_SEL

VDD_DOT

C642

14.31818MHZ_20P_1BX14318BE1AY814.31818MHZ_20P_1BX14318BE1A

VSS_DOT

DOT_96

DOT_96#

VDD_27

27MHZ

27MHZ_SS

VSS_27

VSS_SATA

SRC_1/SATA

SRC_1#/SATA#

VSS_SRC

SRC_2

SRC_2#

VDD_SRC_IO

CPU_STOP#

SLG8SP585VTR_QFN32_5X5

CLK_XTAL_OUT_72

CLK_XTAL_IN_72

Need add jump wire for debug if needed

C641

33P_0402_50V8J

L_CLK_BUF_DOT96 L_CLK_BUF_DOT96#

L_CLK_BUF_CKSSCD R_CLK_BUF_BCLK CLK_BUF_BCLK L_CLK_BUF_CKSSCD#

L_CLK_DMI L_CLK_DMI#

0_0402_5%CK32@

CPU_STOP#

+3VS_CK505

33P_0402_50V8J

Need add jump wire for debug if needed

+1.05VS_CK505_U3 +3VS_CK505_U3

0.1U_0402_10V6K

0.1U_0402_10V6K C185

C185

+3VS +3VS +3VS

R125

R125 10K_0402_5%

10K_0402_5%

1 2

ITP_EN PCI2_TME

R131

10K_0402_5%

1 2

R126

10K_0402_5%

1 2

27_SEL

R132

R132 10K_0402_5%

10K_0402_5%

1 2

0.1U_0402_10V6K

0.1U_0402_10V6K C184

C184

R127

R127 10K_0402_5%

10K_0402_5%

1 2

R133

10K_0402_5%

1 2

+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505

SCL

SDA

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_CPU_IO

VDD_SRC

1 2

Issued Date

30 29 28 27 26 25

24 23 22 21 20 19 18 17

+3VS_CK505_U3

+1.05VS_CK505_U3

R11333_0402_5% R11333_0402_5%

PCI2_TME

R10533_0402_5% R10533_0402_5% R10633_0402_5% R10633_0402_5%

R10933_0402_5% R10933_0402_5%

ITP_EN

R10833_0402_5% R10833_0402_5%

CLK_XTAL_IN_72 CLK_XTAL_OUT_72

R11633_0402_5% R11633_0402_5%

R15133_0402_5% R15133_0402_5%

R12033_0402_5% R12033_0402_5%

PCI_CLK3

FSC

REF_0/CPU_SEL

CKPWRGD/PD#

TGND

+1.05VS_CK505_U3

1 2 1 2 1 2

1 2 1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMB_CLK_S3 SMB_DATA_S3

CLK_XTAL_IN CLK_XTAL_OUT

CK_PWRGD

R_CLK_BUF_BCLK# CLK_BUF_BCLK#

VDDREF

VDDPCI

VDD48

VDD96_IO

VDDPLL3

VDDSRC

VDDCPU

VDDPLL3_IO

VDDSRC_IO

VDDCPU_IO

PCI

PCI2/TME

PCI3

PCI4/27_Select

PCI_F5/ITP_EN

FSA

USB_48MHz/FSLA

FSB

FSLB/TEST_MODE

FSLC/TEST_SEL/REF0

GNDSRC

GNDPCI

GND48

GND

GNDCPU

GNDSRC

GNDREF

ICS9LPRS397EKLFT MLF 72P

2008/10/24 2009/10/24

R90

33_0402_1%CK32@

R94 0_0402_5%CK32@R94 0_0402_5%CK32@

1 2 1 2

R96 0_0402_5%CK32@R96 0_0402_5%CK32@

CK_PWRGD

PCI_STOP#

CPU_STOP#

CPUT0_LPR_F CPUC0_LPR_F

CPUT1_LPR_F CPUC1_LPR_F

CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR

27MHz_NonSS/SRCT1_LPR/SE1

Compal Secret Data

SRCT7_LPR SRCC7_LPR

SRCT6_LPR SRCC6_LPR

SRCT10_LPR

SRCC10_LPR

SRCT11_LPR

SRCC11_LPR

SRCT9_LPR SRCC9_LPR

SRCT4_LPR SRCC4_LPR

SRCT3_LPR SRCC3_LPR

SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_SS/SRCC1_LPR/SE2

CK_PWRGD/PD#

Deciphered Date

CLK_14M_PCHREF_0/CPU_SEL

2N7002_SOT23-3

SCLK

SDATA

54 53

71 70

68 67

CR7#

64 63

61 60

CR#6

57 56

CR10#

50 51

CR#11

48 47

CR#9

44 45

CR#4

39 40

CR#3

35 36

32 33

24 25

28 29

CR#A

REF1

SMB_CLK_S3 4,9,10,13,27,29,31,33 SMB_DATA_S3 4,9,10,13,27,29,31,33 CLK_14M_PCH 13

CLK_BUF_BCLK 13 CLK_BUF_BCLK# 13

R152

1 2

10K_0402_5%

Q13

SMB_CLK_S3 SMB_DATA_S3CLK_14M_PCH

STP_PCI#_R CPU_STOP#

CLK_CPU_BCLK_C CLK_CPU_BCLK#_C

R_CLK_UWB_U3 R_CLK_UWB_U3#

R_CLK_PEG_U3 R_CLK_PEG_U3#

CLK_PCIE_CARD_U3 CLK_PCIE_CARD_U3#

R_CLK_PCIE_MCARD_U3 R_CLK_PCIE_MCARD_U3#27_SEL

R_CLK_PCIE_WWAN_U3 R_CLK_PCIE_WWAN_U3#

R_CLK_PCIE_LAN_U3 R_CLK_PCIE_LAN_U3#

R_CLK_PCIE_EXP_U3 R_CLK_PCIE_EXP_U3#

R_CLK_PEG R_CLK_PEG#

R_CLK_BUF_CKSSCD R_CLK_BUF_CKSSCD#

R_CLK_BUF_DOT96 R_CLK_BUF_DOT96#

27M_CLK_R

CK_PWRGD

T60PAD T60PAD

C182

14 23

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

C182

33P_0402_50V8J

+3VS_CK505

CLK_EN# 47

R102 0_0402_5%@R102 0_0402_5%@

1 2

RP1

0_4P2R_5%

Force SRC output with default register when use 72pin CLK GEN

R464 0_0402_5%R464 0_0402_5%

1 2

R463 0_0402_5%R463 0_0402_5%

1 2

R103 0_0402_5%R103 0_0402_5%

1 2

R119 0_0402_5%R119 0_0402_5%

1 2

R121 0_0402_5%R121 0_0402_5%

1 2

R161 0_0402_5%R161 0_0402_5%

1 2

R154

1 2 1 2

R153

R153 R193

R193

1 2 1 2

R166

R441 0_0402_5%R441 0_0402_5%

1 2

R455 0_0402_5%R455 0_0402_5%

1 2

R456 0_0402_5%R456 0_0402_5%

1 2

R458 0_0402_5%R458 0_0402_5%

1 2

R86 0_0402_5%R86 0_0402_5%

1 2

R114 0_0402_5%R114 0_0402_5%

1 2

R541 0_0402_5%R541 0_0402_5%

1 2

R542 0_0402_5%R542 0_0402_5%

1 2

R539 0_0402_5%R539 0_0402_5%

1 2

R540 0_0402_5%R540 0_0402_5%

1 2

R543 33_0402_5%R543 33_0402_5%

1 2

Need add jump wire for debug if needed

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CLOCK GENERATOR

LA-4891

14.31818MHZ_20P_1BX14318BE1AY114.31818MHZ_20P_1BX14318BE1A

CLK_XTAL_OUT

CLK_XTAL_IN

STP_PCI# 15

C183

33P_0402_50V8J

0.1

11 50Monday, October 27, 2008

0.1

C190

1U_0603_10V4Z

1 2

R139 20K_0402_1%R139 20K_0402_1%

1 2

R140 20K_0402_1%R140 20K_0402_1%

C193

1U_0603_10V4Z

HDA_SPKR34

HDA_SDIN034 HDA_SDIN130

LID_SW#20,30,35

for SMSC EC

notice KBC state

+RTCVCC

R135

1 2

R137

1 2

CLRP1

SHORT PADS

CLRP2

SHORT PADS

R141 33_0402_5%R141 33_0402_5%

1 2

R142 33_0402_5%R142 33_0402_5%

1 2

R143 33_0402_5%R143 33_0402_5%

1 2

R144 33_0402_5%R144 33_0402_5%

1 2

R145 33_0402_5%R145 33_0402_5%

1 2

R146 33_0402_5%R146 33_0402_5%

1 2

R148 33_0402_5%R148 33_0402_5%

1 2

R149 33_0402_5%R149 33_0402_5%

1 2

R150 100K_0402_5%@R150 100K_0402_5%@

KBC_SPI_CLK_R35 KBC_SPI_CS0#_R35 PCH_SPI_CS1#_R35

KBC_SPI_SI_R35

KBC_SPI_SO35

1M_0402_5%

1M_0402_5% 330K_0402_5%

330K_0402_5%

High = Internal VR Enabled(Default)

1 2

10/07 HP

PCH_RTCX1

1 2

R134 10M_0402_5%R134 10M_0402_5%

18P_0402_50V8J

C188

D D

+3VALW

C C

B B

OSC4OSC

NC3NC

1 2

R147 10K_0402_5%R147 10K_0402_5%

1 2

C752 47P_0402_50V8J@C752 47P_0402_50V8J@

1 2

C753 47P_0402_50V8J@C753 47P_0402_50V8J@

1 2

C754 47P_0402_50V8J@C754 47P_0402_50V8J@

1 2

C755 47P_0402_50V8J@C755 47P_0402_50V8J@

PCH_RTCX2

32.768KHZ_12.5PF_Q13MC14610002Y232.768KHZ_12.5PF_Q13MC14610002

C189

C189 18P_0402_50V8J

18P_0402_50V8J

LID_SW#

HDA_BIT_CLK_MDC HDA_BIT_CLK_CODEC HDA_SDOUT_MDC HDA_SDOUT_CODEC

10/01 HP

HDA_BIT_CLK_CODEC34

+RTCVCC

HDA_BIT_CLK_MDC30

HDA_SYNC_MDC30

HDA_SYNC_CODEC34

HDA_RST#_CODEC34

HDA_SDOUT_MDC30

HDA_SDOUT_CODEC34

HDA_RST#_MDC30

SM_INTRUDER# PCH_INTVRMEN

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1

HDA_SDOUT

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_RST#

1 2

R157 15_0402_5%R157 15_0402_5%

1 2

R165 15_0402_5%R165 15_0402_5%

U4A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

+3VS

1 2

R136 10K_0402_5%R136 10K_0402_5%

1 2

R138 1K_0402_5%@R138 1K_0402_5%@

LOW=Default HIGH=No Reboot

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LPC

RTCIHDA

SPI JTAG

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21 SATA1GP / GPIO19

SERIRQ

D33 B33 C32 A32

C34 A34

F34 AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16 AF15

Y9 V1

SIRQ

HDA_SPKR

T21 PADT21 PAD

SIRQ

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

SATA_PRX_DTX_N3 SATA_PRX_DTX_P3 SATA_PTX_DRX_N3 SATA_PTX_DRX_P3

SATA_PRX_DTX_N4 SATA_PRX_DTX_P4 SATA_PTX_DRX_N4 SATA_PTX_DRX_P4

SATAICOMP

1 2

R158 10K_0402_5%R158 10K_0402_5%

SATA_DET#0 HDD_HALTLED

0.01U_0402_16V7K

0.01U_0402_16V7K C199

C199 C201

C201

0.01U_0402_16V7K

0.01U_0402_16V7K C202

C202 C203

C203

0.01U_0402_16V7K

R155

1 2

37.4_0402_1%

LPC_LAD0 29,32,35,36 LPC_LAD1 29,32,35,36 LPC_LAD2 29,32,35,36 LPC_LAD3 29,32,35,36

LPC_LFRAME# 29,32,35,36 LPC_LDRQ#0 36

SIRQ 32,35,36

SATA_PRX_DTX_N0 18 SATA_PRX_DTX_P0 18 SATA_PTX_DRX_N0 18 SATA_PTX_DRX_P0 18

SATA_PRX_DTX_N1 18 SATA_PRX_DTX_P1 18 SATA_PTX_DRX_N1 18 SATA_PTX_DRX_P1 18

SATA_PTX_C_DRX_N3

1 2

SATA_PTX_C_DRX_P3

1 2

0.01U_0402_16V7K

SATA_PTX_C_DRX_N4

1 2

SATA_PTX_C_DRX_P4

1 2

+1.05VS

+3VS

SATA_LED# 33,34

HDD_HALTLED 34

10K_0402_5%

HDD_HALTLED SATA_DET#0

SATA_PRX_DTX_N3 33 SATA_PRX_DTX_P3 33 SATA_PTX_C_DRX_N3 33 SATA_PTX_C_DRX_P3 33

SATA_PRX_DTX_N4 33 SATA_PRX_DTX_P4 33 SATA_PTX_C_DRX_N4 33 SATA_PTX_C_DRX_P4 33

+3VS

R159

1 2

R160

R160 10K_0402_5%

10K_0402_5%

+3VALW +3VALW +3VALW +3VALW

R355

200_0402_5%

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST#

R354

100_0402_1%

A A

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK PCH_JTAG_RST#

R156 51_0402_5%R156 51_0402_5%

RefDesPCH Pin R358 R535 R355 R354 R536 R537 R156 R643 R353

R358

200_0402_5%

R535

100_0402_1%

1 2

PCH_JTAG_TCK

PCH JTAG Enable PCH JTAG Disable ES1 ES1ES2 ES2 No Install

200ohm 100ohm 200ohm

200ohm

No Install No Install No Install No Install 20Kohm 10Kohm

No Install

No Install 200ohm 100ohm 100ohm 200ohm 100ohm 100ohm 51ohm 51ohm 51ohm 20Kohm 20Kohm 10Kohm 10Kohm

R536

R536 20K_0402_1%

20K_0402_1%

1 2

R537

R537 10K_0402_5%

10K_0402_5%

1 2

No Install No Install No Install No Install No Install No Install 51ohm No Install No InstallNo Install

R643

20K_0402_1%

1 2 12

R353

R353 10K_0402_5%

10K_0402_5%

CONN@

JBATT1

W=20mils

JBATT1 E-T_3801-E02N-01R_2P

E-T_3801-E02N-01R_2P

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

LA-4891

12 50Monday, October 27, 2008

0.1

+3VS

R162

R163

1 2

1K_0402_5%

1 2

PCH_JTAG_TDO PCH_JTAG_TDI

PCH_JTAG_TMS

PCH_JTAG_TCK

PM_PWROK14,35,47

PLT_RST#4,15,21,27,29,32,34

XDP_DBRESET#4,14

JP3

OBSFN_A0

OBSFN_A1

GND

OBSDATA_A0

OBSDATA_A1

GND

OBSDATA_A2

OBSDATA_A3

GND

HOOK0

HOOK2

HOOK4

HOOK5

VCCOBS_AB

HOOK6

HOOK7

GND

TDO

TRST#

TDI

TMS

TCK1

GND

TCK0

MOLEX_52435-2472_24P-T

CONN@

D38

W=20mils

C208

1U_0603_10V4Z

Place near IBEX-M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DAN202U_SC70

2008/10/24 2009/10/24

+BATT_D

W=20mils

Compal Secret Data

Deciphered Date

R748

1 2

1K_0402_5%

+BATT1.1+3VL+RTCVCC

D D

PCIE_PRX_DTX_N234

EXP

Media Card

WLAN

C C

NIC

WWAN

B B

EXP

Media Card

WLAN

NIC

A A

PCIE_PRX_DTX_P234 PCIE_PTX_C_DRX_N234 PCIE_PTX_C_DRX_P234

PCIE_PRX_DTX_N334 PCIE_PRX_DTX_P334 PCIE_PTX_C_DRX_N334 PCIE_PTX_C_DRX_P334

PCIE_PRX_DTX_N429 PCIE_PRX_DTX_P429 PCIE_PTX_C_DRX_N429 PCIE_PTX_C_DRX_P429

PCIE_PRX_DTX_N627 PCIE_PRX_DTX_P627 PCIE_PTX_C_DRX_N627 PCIE_PTX_C_DRX_P627

PCIE_PRX_DTX_N729 PCIE_PRX_DTX_P729 PCIE_PTX_C_DRX_N729 PCIE_PTX_C_DRX_P729

CLK_PCIE_EXP_PCH#34 CLK_PCIE_EXP_PCH34

CLKREQ_EXP#34

CLK_PCIE_CARD_PCH#34 CLK_PCIE_CARD_PCH34

CLK_PCIE_MCARD_PCH#29 CLK_PCIE_MCARD_PCH29

CLKREQ_WLAN#29

CLK_PCIE_LAN_PCH#27 CLK_PCIE_LAN_PCH27

CLK_PCIE_LAN_REQ#27

C210 0.1U_0402_10V6KC210 0.1U_0402_10V6K

1 2

C211 0.1U_0402_10V6KC211 0.1U_0402_10V6K

1 2

C209 0.1U_0402_10V6KC209 0.1U_0402_10V6K

1 2

C212 0.1U_0402_10V6KC212 0.1U_0402_10V6K

1 2

C213 0.1U_0402_10V6KC213 0.1U_0402_10V6K

1 2

C214 0.1U_0402_10V6KC214 0.1U_0402_10V6K

1 2

C217 0.1U_0402_10V6KC217 0.1U_0402_10V6K

1 2

C218 0.1U_0402_10V6KC218 0.1U_0402_10V6K

1 2

C219 0.1U_0402_10V6KC219 0.1U_0402_10V6K

1 2

C220 0.1U_0402_10V6KC220 0.1U_0402_10V6K

1 2

+3VALW

+3VS

R180

0_0402_5%

1 2

0_0402_5%

1 2

R181

R183

0_0402_5%

1 2

0_0402_5%

1 2

R184

+3VALW

R185

0_0402_5%

1 2

0_0402_5%

1 2

R186

+3VALW

R192

0_0402_5%

1 2

0_0402_5%

1 2

R194

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7

1 2

R676 10K_0402_5%R676 10K_0402_5%

1 2

R640 10K_0402_5%R640 10K_0402_5%

CLK_PCIE_EXP_PCH#_R CLK_PCIE_EXP_PCH_R

CLK_PCIE_CARD_PCH#_R CLK_PCIE_CARD_PCH_R

CLK_PCIE_MCARD_PCH#_R CLK_PCIE_MCARD_PCH_R

1 2

R770 10K_0402_5%R770 10K_0402_5%

CLK_PCIE_LAN_PCH#_R CLK_PCIE_LAN_PCH_R

U4B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

AM51 AM53

AJ50 AJ52

AK53 AK51

P13

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

R74610K_0402_5% R74610K_0402_5%

PCI-E*

From CLK BUFFER

Clock Flex

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Controller

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

CLKOUT_DMI_P

CLKIN_BCLK_N

CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

B9 H14 C8

J14 C6 G8

M14 E10 G12

T13 T11 T9

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

Set it as GPI11

SMBALERT# SMBCLK SMBDATA

SML0ALERT# SML0CLK SML0DATA

SML1ALERT# SML1CLK SML1DATA

PEG_CLKREQ#

CLK_DP# CLK_DP

XTAL25_IN XTAL25_OUT

R187 90.9_0402_1%R187 90.9_0402_1%

1 2

CLK_14M_KBC_P

CLK_48M_SIO_P

1 2

R195 47_0402_5%R195 47_0402_5%

R118 47_0402_5%R118 47_0402_5%

SMBALERT# 27

T51 PADT51 PAD

CLK_PEG_PCH# 21 CLK_PEG_PCH 21

CLK_EXP# 4 CLK_EXP 4

T52 PADT52 PAD T53 PADT53 PAD

CLK_DMI# 11 CLK_DMI 11

CLK_BUF_BCLK# 11 CLK_BUF_BCLK 11

CLK_BUF_DOT96# 11 CLK_BUF_DOT96 11

CLK_BUF_CKSSCD# 11 CLK_BUF_CKSSCD 11

CLK_14M_PCH 11

CLK_PCI_FB 15

09/22 HP

10/07 HP

+1.05VS

CLK_14M_KBC_PCH 35

CLK_48M_SIO_PCH 36

SMB_CLK_S3 SMB_DATA_S3 SML1CLK_R SML1DAT_R

PEG_CLKREQ#

SMBCLK

SMBDATA

+3VS

SML1CLK

SML1DATA

1 2

R169 10K_0402_5%R169 10K_0402_5%

1 2

R171 10K_0402_5%R171 10K_0402_5%

1 2

R173 10K_0402_5%R173 10K_0402_5%

1 2

R175 10K_0402_5%R175 10K_0402_5%

1 2

R177 10K_0402_5%R177 10K_0402_5%

SMBALERT# SML1ALERT#

2N7002DW T/R7_SOT-363-6

6 1

2N7002DW T/R7_SOT-363-6

6 1

2N7002DW T/R7_SOT-363-6

+3VS

XTAL25_IN XTAL25_OUT

10/02 HP

R350

1 2

R351

1 2

R352

1 2

Q7A

SMB_CLK_S3

Q7B

SMB_DATA_S3

Q8A

Q8B

1 2

R182 1M_0402_5%R182 1M_0402_5%

1 2

25MHZ_20P_1BG25000CK1A

18P_0402_50V8J

C223

Note: remove 25MHz crystal for ES2 silicon.

+3VS

0_0402_5%@

SML1CLK_RSMBCLK

0_0402_5%@

SML1DAT_RSMBDATA

0_0402_5%@

SML1CLK_R

SML1DAT_R

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA SMBALERT# SML0ALERT# SML1ALERT#

SMB_CLK_S3 4,9,10,11,27,29,31,33

SMB_DATA_S3 4,9,10,11,27,29,31,33

R357

1 2

0_0402_5%@

10/04 HP

R360

1 2

0_0402_5%@

18P_0402_50V8J

C224

1 2

R167 2.2K_0402_5%R167 2.2K_0402_5%

1 2

R168 2.2K_0402_5%R168 2.2K_0402_5%

1 2

R170 4.7K_0402_5%

1 2

R172 4.7K_0402_5%

1 2

R174 4.7K_0402_5%

1 2

R176 4.7K_0402_5%

1 2

R207 10K_0402_5%R207 10K_0402_5%

1 2

R272 10K_0402_5%R272 10K_0402_5%

1 2

R771 10K_0402_5%R771 10K_0402_5%

CAP_CLK 23,30,35

CAP_DAT 23,30,35

10/04 HP

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA-4891

13 50Monday, October 27, 2008

0.1

U4C

DMI_CTX_PRX_N05 DMI_CTX_PRX_N15 DMI_CTX_PRX_N25 DMI_CTX_PRX_N35

DMI_CTX_PRX_P05 DMI_CTX_PRX_P15 DMI_CTX_PRX_P25

D D

C C

DMI_CTX_PRX_P35 DMI_CRX_PTX_N05

DMI_CRX_PTX_N15 DMI_CRX_PTX_N25 DMI_CRX_PTX_N35

DMI_CRX_PTX_P05 DMI_CRX_PTX_P15 DMI_CRX_PTX_P25 DMI_CRX_PTX_P35

+1.05VS

1 2

R196 49.9_0402_1%R196 49.9_0402_1%

XDP_DBRESET#4,12

VGATE47

PM_PWROK12,35,47

PM_DRAM_PWRGD4

PM_PWRBTN#_R4

R199

1 2

0_0402_5%@

RPGOOD43 PM_RSMRST#35

+3VALW

ON/OFFBTN#30

AC_PRESENT23,35,38

LOW_BAT#35

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

1 2

R227 0_0402_5%R227 0_0402_5%

1 2

R198 0_0402_5%R198 0_0402_5%

1 2

R210 10K_0402_5%R210 10K_0402_5%

PM_DRAM_PWRGD

R200

1 2 1 2

R201 10K_0402_5%R201 10K_0402_5%

1 2

R639 10K_0402_5%R639 10K_0402_5%

1 2

R202 0_0402_5%R202 0_0402_5%

1 2

R204 0_0402_5%R204 0_0402_5%

PWROK

AUXPWROK

0_0402_5%

LOW_BAT#_R

IBEX_R#

U4C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

SYS_RESET#

SYS_PWROK

B17

PWROK

MEPWROK

A10

LAN_RST#

DRAMPWROK

C16

RSMRST#

SUS_PWR_DN_ACK / GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

DMI

SUS_STAT# / GPIO61

System Power Management

SLP_LAN# / GPIO29

FDI

CLKRUN# / GPIO32

SUSCLK / GPIO62

SLP_S5# / GPIO63

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0 FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

J12

P12

BJ10

1 2

R262 1K_0402_5%R262 1K_0402_5%

1 2

R263 1K_0402_5%R263 1K_0402_5%

1 2

R289 1K_0402_5%R289 1K_0402_5%

1 2

R361 1K_0402_5%R361 1K_0402_5%

1 2

R362 1K_0402_5%R362 1K_0402_5%

PCIE_WAKE#

PM_CLKRUN#

SUS_STAT#

SUS_CLK

SLP_LAN#

PCIE_WAKE# 27,29,34

PM_CLKRUN# 32,35,36

T110PADT110PAD

T109PADT109PAD

SLP_S5# 33

SLP_S4# 38,46

SLP_S3# 27,34,35,37,38,41,43,44,45,46,49

H_PM_SYNC 4

U4D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

1K_0402_0.5%

R203

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

B B

PM_CLKRUN# PM_RSMRST#

LOW_BAT#_R SLP_LAN# IBEX_R# PCIE_WAKE# AC_PRESENT

A A

1 2

R205 10K_0402_5%R205 10K_0402_5%

1 2

R209 10K_0402_5%R209 10K_0402_5%

1 2

R340 10K_0402_5%R340 10K_0402_5%

1 2

R211 10K_0402_5%R211 10K_0402_5%

1 2

R212 1K_0402_5%R212 1K_0402_5%

1 2

R439 10K_0402_5%R439 10K_0402_5%

+3VS

+3VALW

PWROK

10/07 HP

1 2

R206 10K_0402_5%R206 10K_0402_5%

1 2

R747 10K_0402_5%R747 10K_0402_5%

SLP_S3#

1 2

R538 10K_0402_5%@R538 10K_0402_5%@

SLP_S4#

1 2

R546 10K_0402_5%@R546 10K_0402_5%@

SLP_S5#

1 2

R547 10K_0402_5%@R547 10K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/24 2009/10/24

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

LA-4891

14 50Monday, October 27, 2008

0.1

RP17

PCI_PIRQG# PCI_PIRQC# PCI_PIRQA# PCI_PIRQE#

PCI_STOP# PCI_SERR# PCI_IRDY#

D D

C C

B B

A A

PCI_PIRQD#

PCI_REQ2# PCI_REQ1# PCI_FRAME# PCI_TRDY#

PCI_GNT3#

RP17

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP18

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP16

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

1 2

R257 1K_0402_5%@R257 1K_0402_5%@

A16 swap overide Strap/Top-Block Swap Override jumper

Low=A16 swap

override/Top-Block

PCI_GNT3#

Swap Override enabled

High=Default

MODEM_DISABLE#30

CLK_PCI_DEBUG_PCH29

ACCEL_INT#31

CLK_PCI_SIO_PCH36 CLK_PCI_KBC_PCH35

CLK_PCI_DB_PCH32

CLK_PCI_FB13 CLK_PCI_TPM_PCH32

ODD_DET#18

PCI_RST#29

PCI_SERR#32,35

PLT_RST#4,12,21,27,29,32,34

ACCEL_INT# PCI_LOCK# PCI_DEVSEL# PCI_PERR#

PCI_REQ0# PCI_PIRQB# ODD_DET# PCI_REQ3#

T113PADT113PAD

+3VS

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

PCI_GNT0# MODEM_DISABLE# PCI_GNT2# PCI_GNT3#

PCI_PIRQE# ODD_DET# PCI_PIRQG# ACCEL_INT#

PCI_SERR# PCI_PERR#

PCI_IRDY# PCI_DEVSEL#

PCI_FRAME# PCI_LOCK# PCI_STOP#

PCI_TRDY#

CLK_PCI_KBC_R CLK_PCI_FB_R

CLK_PCI_TPM_R

CLK_PCI_DB_P

R223 39_0402_5%R223 39_0402_5%

1 2

R225 39_0402_5%R225 39_0402_5%

1 2

R191 39_0402_5%R191 39_0402_5% R189 39_0402_5%R189 39_0402_5%

R224 51_0402_5%R224 51_0402_5%

1 2

R228 47_0402_5%R228 47_0402_5%

1 2

RP19

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP20

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

10/07 HP

U4E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

PME#

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071

12 12

+3VS

CLK_PCI_KBC_R

CLK_PCI_DB_P

CLK_PCI_FB_R CLK_PCI_TPM_R

BUF_PLT_RST#4

PCI

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

NV_ALE

BD3

NV_CLE

AY6

AU2 AV7 AY8

AY5 AV11

BF5

USB20_N0

H18

USB20_P0

J18

USB20_N1

A18

USB20_P1

C18

USB20_N2

N20

USB20_P2

P20

USB20_N3

J20

USB20_P3

L20

USB20_N4

F20

USB20_P4

G20

USB20_N5

A20

USB20_P5

C20

USB20_N6

M22

USB20_P6

N22 B21 D21

USB20_N8

H22

USB20_P8

J22

USB20_N9

E22

USB20_P9

F22

USB20_N10

A22

USB20_P10

C22

USB20_N11

G24

USB20_P11

H24

USB20_N12

L24

USB20_P12

M24

USB20_N13

A24

USB20_P13

C24

USBRBIAS

B25 D25

Within 500 mils

USB_OC0#

N16

BT_OFF

J16

WEBCAM_OFF

F16

FPR_OFF

L16

USB_OC4#

E14

ISO_PREP#

G16

LANLINK_STATUS#

F12

USB_OC#7

T15

PCI_GNT0# MODEM_DISABLE#

PCI_GNT0#

R258

R258 100K_0402_5%

100K_0402_5%

1 2

R236 1K_0402_5%@R236 1K_0402_5%@

1 2

R238 1K_0402_5%@R238 1K_0402_5%@

Boot BIOS Strap

MODEM_DISABLE# Boot BIOS Location

1 1

1 2

R250 0_0402_5%R250 0_0402_5%

+3VS

NV_CE0# 18 NV_CE1# 18 NV_CE2# 18 NV_CE3# 18

NV_DQS0 18 NV_DQS1 18

NV_DQ0 18 NV_DQ1 18 NV_DQ2 18 NV_DQ3 18 NV_DQ4 18 NV_DQ5 18 NV_DQ6 18 NV_DQ7 18 NV_DQ8 18 NV_DQ9 18 NV_DQ10 18 NV_DQ11 18 NV_DQ12 18 NV_DQ13 18 NV_DQ14 18 NV_DQ15 18

NV_ALE 18 NV_CLE 18

1 2

R220 32.4_0402_1%R220 32.4_0402_1%

NV_RB# 18 NV_RE#_WR#0 18

NV_RE#_WR#1 18 NV_WE#_CK0 18

NV_WE#_CK1 18

1 2

R221 22.6_0402_1%R221 22.6_0402_1%

LPC Reserved(NAND) PCI SPI*

IN1

IN2

SN74AHC1G08DCKR_SC70-5@U5SN74AHC1G08DCKR_SC70-5@

USB20_N0 31 USB20_P0 31 USB20_N1 31 USB20_P1 31 USB20_N2 34 USB20_P2 34 USB20_N3 34 USB20_P3 34 USB20_N4 34 USB20_P4 34 USB20_N5 27 USB20_P5 27 USB20_N6 29 USB20_P6 29

USB20_N8 31 USB20_P8 31 USB20_N9 29 USB20_P9 29 USB20_N10 32 USB20_P10 32 USB20_N11 33 USB20_P11 33 USB20_N12 20 USB20_P12 20 USB20_N13 33 USB20_P13 33

BT_OFF 31 WEBCAM_OFF 20 FPR_OFF 32

ISO_PREP# 33

LANLINK_STATUS# 27,28,33,35

PLT_RST#

CONN CONN CONN CONN EXPRESS GLAN (8075) WLAN

Bluetooth WWAN Fingerprint DOCK USB Camera DOCK

R213 10K_0402_5%R213 10K_0402_5%

+3VS

Danbury Technology Enable NV_ALE High=Endabled

NV_ALE

DMI Termination Voltage NV_CLE Set to Vss when LOW

NV_CLE

1 2

RUNSCI_EC#35

THERM_SCI#23

WWAN_TRANSMIT_OFF#29

NPCI_RST#35,36

CLKREQ_WWAN#29

WLAN_TRANSMIT_OFF#29

PCH_NCTF617 PCH_NCTF717

PCH_NCTF1917

PCH_NCTF2617

Low=Disable (@)

+V_NVRAM_VCCQ

R245

1 2

1K_0402_5%@

Set to Vcc when HIGH

1 2

R254 1K_0402_5%@R254 1K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4F

BMBUSY#

OCP#

OCP#48

RUNSCI_EC# THERM_SCI# GPIO8 CB_IN#

CB_IN#28

GPIO15 GPIO16 ALS_EN# VGA_RST# GPIO24 WWAN_TRANSMIT_OFF#

LAN_DIS#27

STP_PCI#11

+3VS

LAN_DIS# STP_PCI# SATA_CLKREQ# NPCI_RST# GPIO37 GPIO38 GPIO39 GPIO45 CLKREQ_WWAN# GPIO48 GPIO49 WLAN_TRANSMIT_OFF#

2008/10/24 2009/10/24

U4F

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

SLOAD / GPIO38

SDATAOUT0 / GPIO39

PCIECLKRQ6# / GPIO45

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

GPIO57

VSS_NCTF_1

A49

VSS_NCTF_2

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

D53

VSS_NCTF_29

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071

WLAN_TRANSMIT_OFF# GPIO24 GPIO15 ISO_PREP# GPIO45 USB_OC0# USB_OC4# USB_OC#7 GPIO8 CB_IN# WWAN_TRANSMIT_OFF#

Compal Secret Data

GPIO

NCTF

R231 10K_0402_5%R231 10K_0402_5% R235 10K_0402_5%R235 10K_0402_5% R246 1K_0402_5%R246 1K_0402_5% R239 10K_0402_5%R239 10K_0402_5% R663 10K_0402_5%R663 10K_0402_5% R284 10K_0402_5%R284 10K_0402_5% R226 10K_0402_5%R226 10K_0402_5% R229 10K_0402_5%R229 10K_0402_5% R230 10K_0402_5%R230 10K_0402_5% R253 10K_0402_5%R253 10K_0402_5% R233 10K_0402_5%@R233 10K_0402_5%@

on-die VR: *Enable: 1 (internal PU) Disable: 0 (install R233)

Deciphered Date

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

RSVD

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

CLKOUT_PCIE7P

A20GATE

PROCPWRGD

THRMTRIP#

INIT3_3V#

+3VALW

AH45

T22 PADT22 PAD

AH46

T23 PADT23 PAD

CLK_PCIE_WWAN_PCH#_R

AF48

CLK_PCIE_WWAN_PCH_R

AF47

R216 10K_0402_5%R216 10K_0402_5%

PCH_PECI_R KB_RST#

H_THERMTRIP#_L

54.9_0402_1%

T24 PADT24 PAD T25 PADT25 PAD T26 PADT26 PAD T27 PADT27 PAD T28 PADT28 PAD T29 PADT29 PAD T30 PADT30 PAD T31 PADT31 PAD T32 PADT32 PAD T33 PADT33 PAD T34 PADT34 PAD T35 PADT35 PAD T36 PADT36 PAD T37 PADT37 PAD T38 PADT38 PAD T39 PADT39 PAD T40 PADT40 PAD T41 PADT41 PAD T42 PADT42 PAD T43 PADT43 PAD T44 PADT44 PAD T45 PADT45 PAD T46 PADT46 PAD T47 PADT47 PAD

T48 PADT48 PAD T49 PADT49 PAD

KB_RST# NPCI_RST# SATA_CLKREQ# GPIO49 VGA_RST# ALS_EN# RUNSCI_EC# GPIO37 GPIO16 GPIO38 GPIO39 GPIO48 THERM_SCI# STP_PCI#

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

LA-4891

PECI

RCIN#

TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5

TP24

AM3 AM1 BG10 T1 BE10 BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39

P6 C10

0_0402_5%

R214

R2150_0402_5% R2150_0402_5%

+3VS

CLK_CPU_BCLK#_P 4 CLK_CPU_BCLK_P 4

1 2

R2170_0402_5% R2170_0402_5%

KB_RST# 35 H_CPUPWRGD 4

1 2

R218

R219

56_0402_1%

R259 10K_0402_5%R259 10K_0402_5% R222 10K_0402_5%R222 10K_0402_5% R435 10K_0402_5%R435 10K_0402_5% R243 10K_0402_5%R243 10K_0402_5% R240 10K_0402_5%R240 10K_0402_5% R237 10K_0402_5%R237 10K_0402_5% R247 10K_0402_5%R247 10K_0402_5% R248 10K_0402_5%R248 10K_0402_5% R251 10K_0402_5%R251 10K_0402_5% R252 10K_0402_5%R252 10K_0402_5% R256 10K_0402_5%R256 10K_0402_5% R255 10K_0402_5%R255 10K_0402_5% R283 10K_0402_5%R283 10K_0402_5% R527 10K_0402_5%R527 10K_0402_5%

12 12

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

GATEA20 35

H_PECI 4

H_THERMTRIP# 4

+VCCP

WWAN

CLK_PCIE_WWAN_PCH# 29

CLK_PCIE_WWAN_PCH 29

+3VS

15 50Thursday, October 30, 2008

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