HP 6530B, 6730B Schematics

Danzka Dubra 08

[e-mail]

HP 6530B 6730B
6050A2219901-MB-A03

SI1_BUILD

2007.11.02

DATE CHANGE NO.

REV

DRAWER
DESIGN
CHECK
RESPONSIBLE

SIZE =
FILE NAME :

P/N

EE

3

XXXX-XXXXXX-XX

XXXXXXXXXXXX

DATE POWER

VER :

DATE

INVENTEC

TITLE

DD08

CODE

SIZE

A3

DOC. NUMBER

CS

SHEET OF

169

REV

AX1Model_No

TABLE OF CONTENTS

PAGE

5- DC& BATTERY CHARGER
6- SELECT & BATTERY CONN
7- SYSTEM POWER(3V/5V)
8- SYSTEM POWER(+V1.8/+V1.25S)
9- GRAPHIC POWER(+VGFX_CORE)
10- SYSTEM POWER(+VCCP/+V1.5S)
11- CPU POWER(VCC_CORE)
12- DDR TERMINATION VOLTAGE
13- POWER(SLEEP)
14- POWER(SEQUENCE)
15- CLOCK_GENERATOR
16- PENRYN-1
17- PENRYN-2
18- PENRYN-3
19- PENRYN-4
20- THERMAL&FAN CONTROLLER

21- CANTIGA-1
22- CANTIGA-2

23- CANTIGA-3-HOST
24- CANTIGA-4-DDR2
25- CANTIGA-5-POWER
26- CANTIGA-6-POWER
27- CANTIGA-7-POWER

PAGE
28- DDR2-DIMM0
29- DDR2-DIMM1

30- DDR2-DAMPING
31- CRT& SVIDEO CONN
32- LCD CONN

33- ICH9-1
34- ICH9-2
35- ICH9-3
36- ICH9-4
37- ICH9-5
38- HDD CONN
39- ODD CONN
40- USB CONN/USB(DB)
41- FINGER PRINT&BlueTooth
42- TPM V1.2
43- FWH/SPI/HDD PROTECTION

Webcam & 5 IN 1connector

44- KBC

PAGE

52- MINI CARD(WWAN/WLAN)& SIM CARD
53- DOCKING CONN
54- LED/SWITCH CONN

55- SCREW

56- SWITCH DOUGHTER BOARD
57- Finger Print board
58- 7 IN 1 CONTROLLER(TT)

59- 7 IN 1 CONNECTOR(TT)

60- 7 IN 1 CONTROLLER(TS)
61- 7 IN 1 CONNECTOR(TS)

62- AUDIO CNTR
63- AZALIA CODEC
64- EARPHONE & MIC JACK
65- AUDIO AMP &INT. SPEAKER CNTR

66- MDC CNTE
67- NEW CARD CNTR
68- NEW CARD

45- INT.KBC/POINT DEVICES
46- SUPER I/O
47-AUDIO CONN AND EXPRESS CARD CONN

48- DVI CONTROLLER
49- 1394

50- LAN INTERFACE-1
51- LAN RJ45 CONN

CHANGE by

EDI CHEN

26-Oct-2007

INVENTEC

TITLE

DD08

CODE

SIZE

A3

DOC. NUMBER

Model_No AX1

CS

SHEET

REV

OF

692

ICS9LPRS397

[e-mail]

HP 6530B 6730B
6050A2219901-MB-A03

Clock generator

ADT7421

Thermal

Sensor

Docking

1394

CONN

P49

SDVO

PCI

Penyrm

(uFCPGA)

FSB
677/800/1067

Cantiga

DMI

ICH9-M

P16~19

P21~27

P33~37

SPI

SATA

PCIE1

USB7/PCIE2

DDR2 Interface
DDR2 Interface

EEPROM

P43_FOR KBC 1070
P44_FOR KBC 1091

HDD

P38

USB2/PCIE3

DDR II _SODIMM0

667 MHz

P28

UWB

P41

PCIE4

DDR II _SODIMM1

667 MHz

P29

24 Pin Debug port

(LPC, SPI, Serial debug)

USB3

P44

XDP

P19

P15

LCM

P32

P20

DOCK

S-VIDEO

P54

DOCK

CRT

P54

P54

DVI

DOCK

1394

Controller

S-VIDEO

P31

CRT

P31

TMDS

P54

Controller

ACCELEROMETER

STMicro LIS302DL

LVDS

DVI

P48

SMBUS

P43

Agere FW322-07

NV100

SATA FIX ODD

P49

P53

USB0

CONN A

P40

USB1

CONN B

P40

BATTERY

USB4

CONN C

P6

USB5

CONN D

P43P43

USB6

USB8

Bluetooth

P41

MDC_1.5/Modem

Module 56K

System Charger &

DC/DC System power

P5~13

USB10

FINGER PRINT

P41

(DB)

RJ11

P54

USB9

Camera

P43

3.3V, 33MHz/Azalia

Dock

P54

AZALIA_1984A

P47

Dock

USB11

P54

P47

PCIE6

BROADCOM

10/100/1000

BCM5784

RJ45

P51

MINI CARDTOP

LPC

P50

WWAN/Robson

WLAN/WiMAX

SIM

CARD

TPM

V1.2

(FF)

P42

EXPRESS CARD

P52

Super I/O

47N217

(FF)

SERIAL

PORT

CHANGE by

MINI CARDBOT

WLAN/Robson

P47

FLASH MEDIA

SMSC USB2228

P52

P59~60

5 IN 1
SLOT

Kahuna Lite2

KBC1070

P46

P46

BOARD

EDI CHEN

KEY

P45

P44

TOUCH

PAD

26-Oct-2007

INVENTEC

P45

TITLE

SIZE

A3

DD08

DOC. NUMBER

CODE

Model_No AX1

CS

SHEET

REV

OF

693

Adapter

(90W)

LIMIT_SIGNAL

+VBDC

OCP

Charger

(BQ24740)

ADP_EN
OCP_OC#
ADP_PS0
ADP_PS1

CHGCTRL_3

ADP_PRES

AC_AND_CHG

ADP_PRES

KBC_PW_ON

5/3.3V

(TPS51120)

+V5A

+V3A
+V5AL
+V3AL

+V5S

+V3S

BATSELB

AC_AND_CHG

CHGCTRL_3

Selector

(Discrete)

+VBATR

+VBATA

+VBATB SLP_S3#_3R

BATCON

Main Battery

Travel Battery

PWR_GOOD_3

PM_DPRSLPVR

PSI#

H_DPRSTP#

SLP_S4#_3R

SLP_S3#_3R

DFGT_VR_EN

IO POWER

(TPS51117)

IO POWER

(TPS51117)

GPU POWER

(ADP3209)

IMVP VI

(ADP3208)

+V1.8

+VCCP

+VGFX_CORE

V1.8_PG

VCCP_PG

VGFX_PG

SLP_S3#_3R

+VCC_CORE

LR

(G2997)

LR

(APL5913)

VR_PWRGD_CK505

CHANGE by

+V0.9S

M_VREF

+V1.5S

V1.5S_PG

EDI CHEN 26-Oct-2007

INVENTEC

TITLE

DD08

DOC. NUMBER

CODE REV

SIZE

A3

Model_No AX1

CS

SHEET

OF

694

+VADPBL

[e-mail]

5-

1

2

+VBDC

Q510

AM4407P

8

D

7
6
5

G

R580

15K_5%

2VREF

5-,7-,14-

R27

14.3K_1%

5-,6-

R105

12

100K_1%

1

S

2
3
4

1

R25

100K_1%

2

1

R24

8.25K_1%

2

1

2

+VADPBL

5-

R50

220K_5%

Q17

2N7002W

R104

1

100K_1%

23.7K_1%

R108

1

24K_1%

1

1
2

2

3

D

G

1

S

2

R51

100K_5%

12

CHENKO_LL4148_2P

5
6

C13

1
2

0.22uF_6.3v

2

1

R107

2

2

C511

1

C19

2

0.1uF_16v
10pF_50v

1

R49

220K_5%

2

14-

BATCAL#

D11

14-

21

R23

12

270K_5%

+V5AL

5-,6-,7-,14-

8

U5-B

+

7

OUT

-

ON_LM393DR2G_SOP_8P

4

R31

1M_5%

12

+V5AL

5-,6-,7-,14-

8

U5-A

3

+

1

OUT

2

-

1

4

2

ON_LM393DR2G_SOP_8P

+V5AL

5-,6-,7-,14-

R106

12

1M_5%

8

3

+

1

OUT

2

U18-A

-

TI_LMV393IDGKR_SOP_8P

4

+VADP

14-,53-

C512

1
2

0.1uF_25v

ADP_EN#

D509

SSM14_1A40V

1

2

Q509

8

1

S

D

7

2

6

3

54

G

AM4825P_AP

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

2

R26

ADPDRV#

10K_5%

1

5-,6-,44-,50-

6-

AC_AND_CHG

C12

0.1uF_16v

R109

12

10K_5%

+VADPBL

12

47K_5%

ADP_PRES

CHGCTRL_3

6-,44-

+V3AL

1

G

Q13

2N7002W

D

1

G

S

NFM60R30T222

12

5-

R578

22K_5%

2

1

D

S

3

2

DC JACK

3

C509

1
2

LIMIT_SIGNAL

1

R579

4.7K_5%

2

10pF_50v

D17

2

RLZ18C

FOX_JPD113E_NB103_7F_9P

C508

1
2

0.1uF_25v

5-,14-,53-

5-

Q24

1

1

S

2
3
4

AM4825P_AP

L500

4

R103

12

3K_5%

5-

R81

1

2

R74

12

280K_1%

1

1

R75

200K_1%

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

R32

SLP_S3#_3R

10K_5%

3

+V3A

2

7-,9-,13-,14-,19-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

5-

ADPDRV#

VCTRL_3

44-

Q508

2N7002W

C35

2

1uF_6.3v

2

7-,8-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

CELLS

R79

453K_1%

R30

422K_1%

12

R78

1M_1%

JACK1

1
2
3
4
5

6789

8

D

7
6
5

G

C42

12

1uF_25v

R100

12

44-

0_5%

1

2

1

2

+VBDC+VBAT

1

2

5-,6-

1uF_6.3v

ADP_PRES

+VBAT

5-

0.01_1%_1W

1

R80

140K_1%

R82

BQREF

R76

100K_5%

1uF_6.3v

C39

CFET_A

6-

2N7002W

1

5-,6-,44-,50-

OLD_DOCK_DET

7-,8-,9-,10-,11-,13-,32-,44-

R66

12

2

20K_5%

1

2

5-

1

2

1

C40

2

R19

12

150K_5%

Q9

3

D

G

S

2

14-

+VBATR

C41

12

1uF_25v

U9

2

ACN

3

ACP

5

ACDET

9

AGND

13

EXTPWR

16

SRSET

6

ACSET

10

VREF

8

IADSLP

21

DPMDET

4

LPMD

20

CELLS

1

CHGEN

11

VDAC

12

VADJ

15

IADAPT

TI_BQ24740_QFN_28P

5-

1

C38

100pF_50v

2

2

G

D

3

Q10

BSS138

R18

200K_5%

12

100K_5%

HIDRV

LODRV

LPREF

ISYNSET

PowerPad

ICS

S

1

OCP_ADJ

6-

R17

PVCC

PH

BTST

REGN

PGND

SRP

SRN

BAT

5-,11-,13-,14-,20-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

1

R89

R525

3.9K_5%

D_MMST3904

R526

1

Q507

330K_5%

2

1

2

3

C

B

E

2

C527

1
2

0.1uF_10v

12

100K_5%

C514

3900pF_16v

+V3S

+V5S

1

R43

10K_5%

2

3

9

+

14

OUT

8

-

U6-C

12

ON_LM339DR2G_SOP_14P

R85

80.6K_1%

1

1

R87

133K_1%

2

11

+

10

-

C43

1

1
2

0.027uF_10v

2

D8

21

CHENKO_LL4148_2P

3

D

G

Q14

S

2N7002W

2

R86

12

10K_5%

R88

2

1

100K_5%

3

U6-D

13

OUT

ON_LM339DR2G_SOP_14P

12

R84

12

604K_1%

11-,14-,44-

PWR_GOOD_3

34-

OCP_OC#

BQREF

S

1

Q8

BSS138

1

2

2

G

D

3

R16

511K_1%

1

Q7

2N7002W

LIMIT_SIGNAL

R562

12

5-

165K_1%

ICS

5-

1

2

3

D

G

S

2

C528

0.22uF_10v

12

TI_LMV321IDBVR_SOT23_5P

R561

12

10K_5%

12

R560

105K_1%

R29

100_5%

12

5-,14-,53-

5-,11-,13-,14-,20-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

U507

1

1IN+

2

GND

3

1IN-

CHENKO_LL4148_2P

CHENKO_LL4148_2P

3

2

D

S

Q12

G

BSS84_3P

1

14-

VBIAS

Vcc+

OUT

R559

2K_1%

D510

D7

21

R527

3.9K_1%

+V5S

5

4

1

2

2

1

1

1

2

2

OCP

14-

8765

C529

1
2

1uF_25v

1
2

C61

C59

1uF_10v

1

2

13

R77

33K_5%

C530

1

0.1uF_25v

1

2

2

C60

0.1uF_16v

D18

CHENMKO_BAT54_3P

C516

1
2

0.1uF_25v

ALARM

0.1uF_16v

4.7uF_25v

12

R110

100K_5%

6-

C58

1
2

+V3AL

1
2

28

26

25

27

24

23

22

19

18

17

7

14

29

C56

C57

4.7uF_25v

1

4.7uF_25v

2

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

1

+V5AL

2

5-,6-,7-,14-

R111

12

1M_5%

8

5

+

7

OUT

6

-

U18-B

4

TI_LMV393IDGKR_SOP_8P

CHANGE by

G

4

G

4

2VREF

5-,7-,14-

12

D

1S23

8

765

D

S

123

Q26

SI7326DN

R112

10K_5%

EDI CHEN

Q25

SI7326DN

PCMB0603T_8R2MS

R114

93.1K_1%

R113

20K_1%

R115

8.06K_1%

L501

12

C29

4.7uF_25v

1

2

1

2

1

3

D

S

2

2

2N7002W

1
2

4.7uF_25v

G

1

Q27

26-Oct-2007

C301

2

6-

OCP_OC

+VBDCR

R67

0.01_1%_1W

12

1

1

R72

R73

0_5%

0_5%

2

2

C37

0.033uF_16v

2

1

Kevin sense

C34

1

1

2

2

1uF_25v

CFET_B

INVENTEC

TITLE

DD08

DC &BATTERY CHARGER

CODE

SIZE

A3

Model_No AX1

CS

SHEET

+VBDC

1
2

C36

1uF_25v

DOC. NUMBER

OF

5-,6-

C27

4.7uF_25v

C2812

4.7uF_25v

695

REV

BATSELB

CHGCTRL_3

CHENKO_LL4148_2P 2

BATSELB#

BATSELB

C513

0.1uF_16v

C33

1000pF_50v

2

5-,44-

D14

C32

1000pF_50v

12

6-

R21

22K_5%

C11

1000pF_50v

2

6-,44-

R22

22K_5%

+V3AL

1
2

16

6-,44-

C31

0.047uF_10v

1

R71

12

1K_5%

1

1

2

2

5

2N7002DW

1

1

2

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

6-

5

U503-A

2

TC7PA14FU

BATSELB#

1

1

R68

470K_5%

2

2

2

3

D

1

G

S

2

1

R70

470K_5%

2

Q20

2N7002W

AC_AND_CHG

ADP_PRES

ALARM

1

Q11

S1

G1

D1
D2

G2

S2

2

1

6
3

4

Q21

3

D

S

2

2N7002W

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

U504

5

74HC1G14GV

4

3

1

R28

10K_5%

2

Q22

2N7002W

2

5-

S

5-,6-,44-,50-

U502-A

TC7W02FU

8

1

5-

2

4

R69

47K_5%

5

U503-B

34

TC7PA14FU

2

5-,6-,44-,50-

1

G

3

D

BATSELB

G

1

TC7W02FU

7

ADP_PRES

C10

0.1uF_16v

1
2

8

1

7

2

U8-A

4

TC7W08FU

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

1

R20

220K_5%

2

5
6

6-,44-

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

1

U502-B

2

8

5

3

6

4

12

10K_5%

U8-B

8

TC7W08FU

4

C515

0.1uF_16v

R61

3

470K_5%

10K_5%

Q512

1

S1

2

G1

6

D1

3

D2

5

G2

4

S2

2N7002DW

Q19

R59

2

2

1

10K_5%

G1

5

G2

2N7002DW

+VBATA +VBATB

6-

BAV70

D515

Q518

2N7002W

3

2

D

S

G

1

+VBDC

5-,6-

1

R581

Q511

D_MMST3904

2

1

2

1

D512

B

R582

CHENKO_LL4148_2P

5-,6-

+VBDC

5-,6-

1

R55

470K_5%

D_MMST3904

2

2

R56

10K_5%

1

1

S1
D1

D2

4

S2

6-

12

+V3AL

CHENKO_LL4148_2P

6
3

R596

12

3

100_5%

C545

0.1uF_25v

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

3

C

E

2

21

CFET_A#

CFET_A

Q18

1

B

D12

21

1
2

3

C

E

2

5-,6-

1
2
3
4

AM4825P_AP

1

R583

470K_5%

2

SSM34_3A40V

1

2

CFET_B#

CFET_B

1

R600

1.5M_5%

2

SS5P4

D513

2

K

1

Q513

S

D

G

D15

21

Q23

1

S

2
3

G

AM4825P_AP

R57

470K_5%

Q517

2N7002W

3

2

S

D

G

1

D517

1

UDZW7.5B

2

Q514

8

8

7

7
6

6

5

54

AM4825P_AP

8

8

D

7

7

6

6

54

5

R601

12

0_5%

1

D

S

2
3

G

Q15

S1

2

G1

D1
D2

5

G2

S2

2N7002DW

Q30

D

S

G

AM4825P_AP

Q516

2

G1

5

G2

2N7002DW

D516

2

CHENKO_LL4148_2P

1

1

6
3

4

1
2
3
4

1

S1

6

D1

3

D2

4

S2

R619

10K_5%

1

3

2

D506

CHENMKO_BAV99

OCP_ADJ

1

R614

10K_5%

2

1

3

2

+V3AL

1

R618

10K_5%

2

1

2

CHENMKO_BAV99

1

100K_5%

R593

100_5%

2

12
12

R595

100_5%

3

D511

1

R518

2

100_5%

12
12

R519

100_5%

5-,7-,14-

1

3

3

2

D507

R522

125-

294K_1%

+V3AL+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

1

R612

2

R575

12

1K_5%

C543

1

100pF_50v

3

D518

2

CHENMKO_BAV99

1

C218

100pF_50v

2

R520

12

1K_5%

C220

100pF_50v

R521

69.8K_1%

2

R524

100K_1%

R523

150K_1%

C107

1

100pF_50v

2

100pF_50v

1
2

1

C108

SDA_MAIN

1

R45

SCL_MAIN

470K_5%

2

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

1

R44

4.7K_5%

2

CHENMKO_BAV99

+VBATB

1

R571

470K_5%

2

1

R592

4.7K_5%

2

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

SDA_MBAY
SCL_MBAY

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

CHENMKO_BAV99

D16

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

+VBATA

6-

44­44-

+V3AL +V5AL

D505

6-

5A_200mil

R616

10K_5%

44­44-

+V3AL

1

2

CHENMKO_BAV99

44-

U505

74LVC1G17GW

2

R552

220K_5%

1

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

5

4

2

3

1
2

C526

0.1uF_16v

44-

CFET_A

CFET_B

5-,6-

5-,6-

BAV70

D13

THM_TRAVEL#

3

12

INVENTEC

TITLE

CHANGE by OF

EDI CHEN

26-Oct-2007

A3

C219

100pF_50v

MAIN BATT

CN10

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

1

C16

2

0.1uF_25v

1
2

1
2

+V3AL

1

2

E

E

B

B

C

D-MMST3906

C

1

2

1

R15

220K_5%

2

Q5

R611

100K_5%

G

1

Q6

2N7002W

1

2

3

D

S

2

THM_MAIN#

SYN_200263MS006G114ZT_6P

CN502

1

1

2

2

3

3

4

4

5

5

6

6

1
2

C55

1

0.1uF_25v

2

TRAVEL BATT

BATCON

DD08

SELECT & BATTERY CONN

CODE

DOC. NUMBERSIZE

Model_No AX1

CS

SHEET

696

ALLTOP_C144M6_108A5_L_8P

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

44-

REV

+V5AL

[e-mail]

5-,6-,7-,14-

KBC_PW_ON

VCC1_POR#_3

5-,9-,13-,14-,19-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

+V3A

PAD4

POWERPAD_2_0610

C307

1

1uF_10v

2

44-,50-

14-,44-

17.4K_1%

C323

4.7uF_25v

CYNTEC_PCMC063_3R3

1

C306

330uF_4v

2

2

5

2N7002DW

R382

+VBATP

7-

Q64

G2

1
2

G1

L25

1

S1

6

D1

3

D2

4

S2

12

C322

4.7uF_25v

12

1

R367

330K_5%

2

R381

7.32K_1%

2N7002W

12

1
2

Q65

G

1

51120GND

8765

D

876

D

S

123

1

R369

OPEN

2

3

D

S

2

RSMRST#

SI7326DN

G

4S123

5

G

FDS6690AS

4

Q52

Q57

7-,34-,44-

C340

0.1uF_16v

12

R905

0_5%

12

R350

4.7_5%

12

5-,7-,14-

C359

1000pF_50v

9

EN5

10

EN3

11

PGOOD2

12

EN2

13

VBST2

14

DRVH2

15

LL2

16

DRVL2

2VREF

51120GND

1
2

8

VO2

TI_TPS51120_QFN_32P

PGND2

17

7

VFB2

COMP2

CS2

VREG3

18

6

19

5

GND

V5FILT

20

4

VREF2

VREG5

21

VFB1

VIN

3

22

12

1

2

VO1

COMP1

SKIPSEL

TONSEL

PGOOD1

VBST1

DRVH1

DRVL1

CS1

PGND1

23

24

R380

0_5%

EN1

LL1

U36

33
32
31
30
29
28
27
26
25

R824

0_5%

7-,34-,44-

12

+VBATP +VBATR

7-

5-,8-,9-,10-,11-,13-,32-,44-

R348

OPEN

2

R347

C338

4.7_5%

12

12

0.1uF_16v

3
4

POWERPAD_4A

1

RSMRST#

PAD6

7.32K_1%

R379

12

51120GND

SLP_S3#_3R

5-,8-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

2VREF

5-,7-,14-

30K_1%

1

G

4

G

41S23

R378

765

65

2

8

D

1S23

SI7326DN

8D7

C324

4.7uF_25v

Q51

Q55

FDS6690AS

+VBATP

7-

C325

1

1

4.7uF_25v

2

2

L23

12

SLF10040_4R7N7R0

C282

220uF_6.3v

8-,9-,10-,11-,12-,13-,31-,32-,36-,40-,43-

1

1
2

1uF_10v

2

+V5A

PAD5

POWERPAD_2_0610

C305

+V3AL

5-,6-,14-,33-,37-,44-,45-,47-,54-,56-

1

C339

4.7uF_6.3v

2

R349

10K_1%

+V5AL

1

4.7uF_6.3v

2

5-,6-,7-,14-

C327

1

2

C328

1

0.1uF_16v

2

1

R823

8.25K_1%

2

R331

12

10_5%

1
2

51120GND

C329

1uF_10v

1
2

C326

4.7uF_25v

EDI CHEN 26-Oct-2007

INVENTEC

TITLE

DD08

SYSTEM POWER(3V/5V/12V)

CODE

DOC. NUMBERSIZE

A3

Model_No AX1

CS

SHEET

REV

OFCHANGE by

697

5-,7-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

SLP_S3#_3R

VCCP_PG

14-

1

R604

OPEN

7-,8-,9-,10-,11-,12-,13-,31-,32-,36-,40-,43-

R98

12

10_5%

R99

2

1

330K_1%

2

C49

1
2

1uF_10v

U19

1

EN_PSV

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

7

GND

TI_TPS51117_QFN_14P

VCCPGND

1

R606

0_5%

2

VBST
DRVH

V5DRV

DRVL

PGND

LL

TRIP

TML

+V5A

+VBATR

5-,7-,8-,9-,10-,11-,13-,32-,44-

8765

D

C65

R125

12

12

0_5%

VCCPGND

0.1uF_16v

1

R605

10K_1%

2

14
13
12
11
10
9
8
15

1
2

C64

1uF_10v

G

Q519

FDS8884

41S23

8765

D

G

Q522

4

1S23

FDS6676AS

C547

C549

1

1

2

2

4.7uF_25v

4.7uF_25v

L5

12

CYNTEC_PCMC063_1R5

VCCPGND

1

R584

12.1K_1%

2

1

R585

30K_1%

2

+VCCP

15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

PAD2

POWERPAD_2_0610

1

C76

220uF_2v_15mR_Panasonic

2

SLP_S4#_3R

V1.8_PG

12-,34-

1
2

4.7uF_25v

L13

R201

43.2K_1%

C162

12

+VBATR

12

12

51117GND

1
2

5-,7-,8-,9-,10-,11-,13-,32-,44-

7-,8-,9-,10-,11-,12-,13-,31-,32-,36-,40-,43-

+V5A

R180

12

10_5%

R200

2

1

OPEN

14-

C131

1uF_6.3v

1
2

TI_TPS51117_QFN_14P

51117GND

U26

1

EN_PSV

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

7

GND

R183

12

0_5%

R181

12

300K_1%

14

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

8

PGND

15

TML

1
2

0_5%

C129

1uF_10v

R199

12

1

2

51117GND

12

R182

15.4K_1%

C161

0.1uF_16v

8765

D

Q35

G

FDS8884

41S23

8

76

5

D

G

S

123

4

Q34

FDS6690AS

12

12

OPEN

1
2

R393

C362

OPEN

1

2

C363

OPEN

OPEN

C163

4.7uF_25v

PCMC063T_2R2MN

R394

R184

30K_1%

12

C400

0.1uF_16v

C401

2200pF_50v

12

220uF_2.5v

C159

12-,21-,25-,26-,28-,29-

PAD3

POWERPAD_2_0610

1

2

+V1.8

INVENTEC

TITLE

DD08

SYSTEM POWER(+V1.8/+V1.25S)

CODE

CHANGE by

EDI CHEN

26-Oct-2007

CS

SHEET

DOC. NUMBER REVSIZE

869

A3

AX1Model_No

OF

5-,7-,13-,14-,19-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

[e-mail]

DFGT_VR_EN

SLP_S3#_3R

5-,7-,8-,10-,12-,13-,14-,34-,44-,47-,50-,53-

330pF_50v

C63

12

R124

1K_1%

R727

0_5%

1

12

R728

C548

1
2

1000pF_50v

ADP3209AGND

0_5%

+V3A

12

470pF_50v

2

12

C48

DFGT_VID_4

DFGT_VID_3

DFGT_VID_2

DFGT_VID_1

DFGT_VID_0

R122

12

10K_5%_OPEN

R121

21-

1

OPEN

R123

12

0_5%

2

R97

33.2K_1%

1

R96

20K_1%

25-

VCC_AXG_SENSE

25-

VSS_AXG_SENSE

12

100K_5%_OPEN

1
2

ADP3209AGND

12

12

12

12

12

R391

1
2

ADP3209AGND

R116

0_5%

R117

0_5%

R118

0_5%

R119

0_5%

R120

0_5%

VGFX_PG

ADP3209AGND

C538

680pF_50v

+VBATR

14-

1

R607

0_5%

2

2

R586

100K_1%

1

ADP3209AGND

R92

1

1K_5%

C45

100pF_50v

2

1
2
3
4
5
6
7
8

R93

1

261K_1%

1
2

FBRTN
FB
COMP
SS
ST
PMON
PMONFS
CLIM

32

9

2

ADP3209AGNDADP3209AGND

31

PGDLY

PWRGD

CSCOMP10CSREF11CSSLIM

LLINE

1
2

28

27

25

30

EN

VID029VID1

VID226VID3

VID4

DRVH

PVCC
DRVL
PGND

VRPM

RAMP

RPM

RT

14

12

13

15

16

ADI_ADP3209_LFCSP_32P

2

R587

255K_1%

1

C541

1
2

0.01uF_16v

ADP3209AGND

C540

1000pF_50v

U10

24

VCC

23

BST

22
21

SW

20
19
18
17

GND

33

TML

ADP3209AGND

ADP3209AGND

C46

1
2

270pF_50v

1
2

ADP3209AGND

R91

4.7_5%

12

2

R588

357K_1%

1

1
2

+V5A

R90

12

10_5%

C62

2.2uF_6.3v

D514

CHENMKO_BAT54_3P

13

C44

12

1uF_16v

1
2

C47

680pF_50v

7-,8-,10-,11-,12-,13-,31-,32-,36-,40-,43-

Q521

FDS8884

C542

1uF_10v

Q520

FDS6676AS

G

41

G

41S23

R95

2

140K_1%

8765

D

S

23

8765

D

1

+VBATR

5-,7-,8-,9-,10-,11-,13-,32-,44-

C551

1
2

4.7uF_25v

C550

1
2

4.7uF_25v

PCMC063T_1R0MN

12

2

R94

158K_1%

1

+VGFX_CORE

25-

L4

PAD1

2
3

1

4

POWERPAD_4A

21-

21-

21-

21-

21-

2

C537

1
2

12

22pF_50v

C539

0.012uF_16v

ADP3209AGND

5-,7-,8-,9-,10-,11-,13-,32-,44-

R144

12

0_5%

INVENTEC

TITLE

DD08

GRAPHIC POWER (+VGFX_CORE)

SIZE DOC. NUMBERCODE

CHANGE by OF

EDI CHEN

26-Oct-2007

A3

Model_No AX1

CS

SHEET

REV

699

13-,18-,26-,36-,41-,47-,52-

+V1.5S

POWERPAD_2_0610

PAD7

10-

+V1.5S_FB

SLF6040T_4R7N3R6

1

C308

2

220uF_2.5v_R35

L26

12

5

S1_D2

6
7

4

S2

FDS6900AS

Q58

+V5A

7-,8-,9-,11-,12-,13-,31-,32-,36-,40-,43-

2

1SS355W

1

D22

+VBATR

D1

1
2

G1

8

3

G2

5-,7-,8-,9-,11-,13-,32-,44-

C333

1
2

4.7uF_25v

1
2

C332

4.7uF_25v

12

C330

0.1uF_16v

12

R332

0_5%

C331

1uF_10v

R795

12

10K_1%

16

U32

DH

1

LX

2

BST

3

VCC VOUT

4

DL

PAD

GND

5

17

1
2

12

14

15

13

NC4

ILIM

NC3

EN

PGOOD

FB

NC1

NC2

RTN

7

8

6

SEMTECH_SC412A_MLPQ_16P

R333

0_5%

SC412GND

R794

12

0_5%

12

11

10

9

5-,7-,8-,9-,12-,13-,14-,34-,44-,47-,50-,53-

R755

12

0_5%

C343

1
2

0.01uF_16v

SC412GND

SLP_S3#_3R

14-

V1.5S_PG

1

R335

10.5K_1%

2

1

R334

10K_1%

2

SC412GND

10-

+V1.5S_FB

EDI CHEN

26-Oct-2007

INVENTEC

TITLE

DD08

SYSTEM POWER(+VCCP/+V1.5S)

A3

CS

SHEET

DOC. NUMBER

OFCHANGE by

10 69

REVSIZE CODE

AX1Model_No

PWR_GOOD_3

[e-mail]

PM_PWROK

VR_PWRGD_CK505#

330pF_50v

C575

1

2

1000pF_50v

VCOREGND

17-

PSI#

5-,14-,44-

C95

220pF_25v

12

1
2

17-,21-,33-

21-,34-

R157

12

68.1K_1%

C93

680pF_50v

PM_DPRSLPVR

21-,34-,44-

34-

12

C96

12

R158

1.65K_1%

0.012uF_16v

H_DPRSTP#

C94

+V5S

R666

0_5%

VCOREGND

CSREF

18-

18-

11-

VCCSENSE

VSSSENSE

5-,13-,14-,20-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

12

1

18pF_50v

2

1
2

C574

R160

12

499_1%

VCOREGND

C573

4700pF_25v

12

C576

1000pF_50v

H_VID6

18-

H_VID5

18-

H_VID4

18-

H_VID3

18-

H_VID2

18-

H_VID1

18-

H_VID0

18-

49

48

47

46

PSI

TML

1

EN

DPRSLP

DPRSTP

2

PWRGD

3

PGDELAY

4

CLKEN

5

FBRTN

6

FB

7

COMP

U25

8

SS

ADI_ADP3208_LFCSP_48P

9

ST

10

VARFREQ

11

VRTT

12

TTSEN

PMON

CLIM

PMONFS

15

13

14

2

R668

115K_1%

1

VCOREGND

1
2

VCOREGND

45

16

VID0

LLINE

44

VID1

CSCOMP

17

41

43

VID4

VID242VID3

RAMP22RPM23RT SP

CSFEF18CSSUM

20

19

1

C578

1000pF_50v

2

40

39

VID5

VRPM

21

2

1

2

1

38

VID6

R156

137K_1%

R670

274K_1%

2

1
2

R667

100K_5%

VCOREGND

37

VCC

36

BST1

35

DRVH1

34

SW1

33

PVCC1

32

DRVL1

31

PGND1

30

PGND2

29

DRVL2

28

PVCC2

27

SW2

26

DRVH2

25

BST2

GND

24

R693

210K_1%

12

12

C92

0.01uF_16v

VCOREGND

1

1

C599

2

1000pF_50v

VCOREGND

R669

12

220K_1%

1

C577

2

150pF_50v

2

R691

10_5%

1

C597

2.2uF_6.3v

R672

76.8K_1%

1

+V5A

1
2

R186

4.7_5%

12

12

R185

4.7_5%

12

100_5%

2

7-,8-,9-,10-,12-,13-,31-,32-,36-,40-,43-

C133

2.2uF_6.3v

D520

3

BAT54A

1

C135

12

1uF_16v

12

C132

1uF_16v

+VBATR

5-,7-,8-,9-,10-,11-,13-,32-,44-

R692

R673

12

169K_1%

R671

12

169K_1%

1

R202

220K_5%

2

NTC thermistor, place near L16

+VBATR

5-,7-,8-,9-,10-,11-,13-,32-,44-

1

C224

2

100uF_25v

2

1
2

C600

4.7uF_25v

4.7uF_25v

4.7uF_25v

1
2

C601

X 3

FDS6676AS

C598

1
2

Q525

G

4S123

C134

1
2

2.2uF_6.3v

C666

1
2

4.7uF_25v

4.7uF_25v

4.7uF_25v

C668

C667

1

1

2

2

X 3

G

4

Q528

FDS6676AS

6789

5

Q523

SI7686DP_T1_E3

4G321

L12

ETQP4LR36WFC_PANASONIC

6

5

G

41S23

89

Q527

8

7

FDS6676AS

D

567

Q524

SI7686DP_T1_E3

R718

22_5%

C636

2200pF_50v

1

2

1
2

8765

D

4G321

765

8

765

8

D

D

G

S

123

Q526

FDS6676AS

S

4

123

2200pF_50v

C663

R745

22_5%

1

2

1
2

12

11-

CSREF

L15

12

ETQP4LR36WFC_PANASONIC

2
R216

10_1%

1

2
R215

10_1%

1

+VCC_CORE

18-

CHANGE by

EDI CHEN 26-Oct-2007

INVENTEC

TITLE

DD08

CPU POWER(VCC_CORE)

CODE

SIZE

A3

DOC. NUMBER

Model_No AX1

CS

SHEET

REV

OF

6911

SLP_S4#_3R

SLP_S3#_3R

8-,34-

5-,7-,8-,9-,10-,13-,14-,34-,44-,47-,50-,53-

+V1.8

8-,21-,25-,26-,28-,29-

C160

1
2

4.7uF_6.3v

+V5A

7-,8-,9-,10-,11-,13-,31-,32-,36-,40-,43-

U27

GMT_G2997F6U_MSOP10_10P

TML11VDDQSNS

10 2

VIN

9

S5

8

GND

7

S3

6

VTTREF

C158

1
2

1uF_10v

C125

1

0.1uF_16v

2

NOTE: DDR2 REGULATOR

21-,28-,29-

VLDOIN

PGND

VTTSNS

VTT

1

3
4
5

M_VREF

+V0.9S

1
2

30-

C127

10uF_6.3v

1
2

C128

10uF_6.3v

CHANGE by

EDI CHEN 26-Oct-2007

INVENTEC

TITLE

DD08

DDR TERMINATION VOLTAGE

SIZE DOC. NUMBER

CODE

A3

Model_No AX1

CS

OFSHEET

REV

6912

5-,7-,9-,13-,14-,19-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

[e-mail]

CHENMKO_BAT54_3P

R771

120K_1%

12

13-

GATE_3S

D102

0.012uF_16v

+V3A

6

13

C284

5

2

13

FDC655BN

12

+V3S

5-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

Q48

4

D

S

G

GATE_5S

1

1

R312

47_5%

C283

10uF_6.3v

2

2

7-,8-,9-,10-,11-,12-,31-,32-,36-,40-,43-

R779

120K_1%

12

13-

C304

0.012uF_16v

1
2

6
5

2

1

FDC655BN

+V5A

+V5S

5-,11-,14-,20-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

Q50

4

D

S

3

G

1

C321

2

10uF_6.3v

1

R330

100_5%

2

R341

100_5%

+V1.5S

10-,18-,26-,36-,41-,47-,52-

1

2

SSM3K7002F

0.033uF_16v

SLP_S3#_3R

5-,7-,9-,13-,14-,19-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

5-,7-,8-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

SLP_S3#_3R

Q49

3

D

G

1

S

2

+VBATR

1

C360

_OPEN

2

5-,7-,8-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

Q71

1

G

SSM3K7002F

5-,7-,8-,9-,10-,11-,13-,32-,44-

1

R384

47K_5%

2

1

Q72

MMBT3904

+V3A

1

R351

100K_5%

2

3

D

S

2

MMBT3906

3

C

B

E

2

1

R383

130K_1%

2

SSM3K7002F

+VBATR

5-,7-,8-,9-,10-,11-,13-,32-,44-

1

R385

2.7K_5%

2

Q73

2

E

1

B

C

3

Q69

3

D

G

1

S

2

R857

12

0_5%

R854

12

1K_5%

D26

1

RLZ18C2

Q56

1

G

SSM3K7002F

1

2

1

2

D

S

R858

R856

0_5%

Q61

3

2

1

R859

0_5%0_5%

13-

GATE_5S GATE_3S

2

1

R855

0_5%

2

1

G

SSM3K7002F

3

D

S

2

13-

INVENTEC

TITLE

DD08

POWER(SLEEP)

SIZE

26-Oct-2007EDI CHEN

A3

DOC. NUMBER

CODE REV

CS

SHEET

13

AX1Model_No

OFCHANGE by

69

VGFX_PG

V1.5S_PG

V1.8_PG

VCCP_PG

5-,7-,8-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

SLP_S3#_3R

+V3S

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

5-,11-,13-,14-,20-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

LIMIT_SIGNAL

+VADP

5-,14-,53-

1

R48

47K_5%

2

1

R47

200K_5%

2

53-

OLD_DOCK_DET

+V5S

5-,53-

Q16

E

B

C

CE

B

D-MMST3906

D10

CHENKO_LL4148_2P

ACOCP_EN#

1

R46

210K_1%

2

1

2

5-

9-

10-

8-

8-

12

R722

1K_5%

R752

12

68.1K_1%

R750

12

102K_1%

1

R514

137K_1%

2

1

R515

10K_1%

2

R747

12

10K_5%

R753

12

10K_5%

R751

12

10K_5%

R754

12

10K_5%

D523

21

CHENKO_LL4148_2P

R749

49.9K_1%

+VADP

R512

12

1M_5%

+VADP

R504

10K_1%

12

20K_5%

1

C664

1
2

1000pF_50v

2

5-,14-,53-

1

R500

22.6K_1%

2

1

R513

10K_1%

2

5-,14-,53-

1

R502

29.4K_1%

2

1

ON_LM393DR2G_SOP_8P

2

R748

2VREF

5-,7-,14-

R720

100K_5%

12

C642

1
2

0.1uF_16v

5-

ON_LM393DR2G_SOP_8P

3
2

R503

12

1M_5%

5
6

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

+V3S

1

44-

21

ADP_EN#

ADP_ID

1

2

1

2

R719

10K_5%

2

5-,11-,44-

PWR_GOOD_3

+V3A

5-,7-,8-,9-,10-,12-,13-,14-,34-,44-,47-,50-,53-

1

R615

R510

220K_5%

R511

220K_5%

47K_5%

2

3

D

1

G

S

2

Q503

2N7002W

VBIAS

+

OUT

-

+

OUT

-

8

4

8

U501-B

4

U501-A

R721

12

1M_5%

+V5AL

5

+

6

-

1

7

OUT

5-,6-,7-,14-

8

U510-B

7

ON_LM393DR2G_SOP_8P

4

5-,7-,9-,13-,19-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

1

R624

10K_5%

2

1

R501

47K_5%

2

D504

CHENKO_LL4148_2P

5-

+VADP

5-,14-,53-

1

R914

1_5%

2

C500

1

1uF_25v

2

R137

12

100K_5%

SLP_S3#_3R

3

C

1

B

E

D_MMST3904

2

Q29

5-

44-

BATCAL#

ADP_EN

D100

12

3

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

12

R251

R917

51.1K_1%

23.7K_1%

1

2

12

C233

2200pF_50v

R249

23.7K_1%

1

2

+V5AL

5-,6-,7-,14-

R253

12

1M_5%

12

R254

100K_5%

12

C752

0.1uF_16v

+V3S

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

1

R35

71.5K_1%

2

OCP_OC

1

R37

21K_1%

2

1

R34

3.48K_1%

2

1uF_6.3v

1

5-

47K_5%

R38

C14

1
2

2

CHANGE by

Q151

3

D

1

G

S

2

SSM3K7002F

C15

1
2

0.1uF_16v

R39

2

1

470K_5%

R36

12

10K_5%

R33

12

21K_1%

EDI CHEN 26-Oct-2007

DAN202K

1

R918

57.6K_1%

2

R919

115K_1%

R250

12

1M_5%

+V5AL

5-,6-,7-,14-

8

U510-A

3

+

1

OUT

2

-

ON_LM393DR2G_SOP_8P

4

2VREF

5-,7-,14-

5-,11-,13-,14-,20-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

12

+V3AL

5-,6-,7-,14-,33-,37-,44-,45-,47-,54-,56-

R252

10K_5%

12

+V5S

R40

12

1M_5%

3

U6-A

5

+

2

OUT

4

­12

ON_LM339DR2G_SOP_14P

R83

12

1M_5%

3

U6-B

7

+

1

OUT

6

-

ON_LM339DR2G_SOP_14P

12

INVENTEC

TITLE

DD08

POWER(SEQUENCE)

SIZE CODE

A3

CS

SHEET

+V3AL

12

R920

14K_1%

12

R921

100K_5%

_NTC

7-,44-

VCC1_POR#_3

1

R41
10K_5%

2

44-

ADP_PS0

1

R42
10K_5%

2

44-

ADP_PS1

DOC. NUMBER

Model_No AX1

OF

6914

REV

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

[e-mail]

11/02

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

+VCCP

L509

BLM18AG471SN1D

1

CLKREQ_MCH#

CLKREQ_SATA#

CLKREQ_NC#

CLKREQ_MINI_TOP#
CLKREQ_MINI_BOT#

CPPE#

CLKREQ_LAN#

2

C670

10uF_6.3v

15-,21­15-,34­15-,47­15-,53­15-,52­15-,52­15-,50-

12

12

R689

12

R822
R267 1 2

12
1

R723
R268 1 2

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

R266

10K_5%_OPEN

12

1

C239

5.6pF_50v

2

34-

X2

12

1

C243

2

33pF_50v

30PPM

R260

12

12

R239

12

0_5%

C269

22pF_50v

10K_5%

10K_5%R265

CLK_R3S_CBPCI
CLK_R3S_KBPCI

CLK_R3S_SIOPCI

CPU_BSEL1

CPU_BSEL2

CLK_3S_REF

C242

33pF_50v

R934

12

10K_5%

17-,21­17-,21­15-

CLK_PWRGD

14.31818MHZ

1
2

Please place close to CLKGEN within 500mils

*CLKREQ# pin controls SRC Table.

Byte5: bit6 =1

ENABLE_SRC2

Byte5: bit4 =1

CR#_3

CR#_6

CR#_A

CR#_4

Byte5: bit6 =0(PWD)

ENABLE_SRC0

Byte5: bit4 =0(PWD)

DISABLE_SRC4

Layout note: All decoupling 0.1uF disperse closed to pin

C267

1
2

0.1uF_16v

+V3S

10K_5%
10K_5%R286 1 2
10K_5%
10K_5%
10K_5%R226

2

10K_5%
10K_5%

1
2

CLK_R3S_ICH14

CLK_R3S_TPM

ICH_3S_SMCLK

ICH_3S_SMDATA

CLKREQ_MCH#

CLKREQ_SATA#

CLKREQ_NC#

1
2

CLK_R3S_ICH48

C246

C249

1

1

2

0.1uF_16v

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

CPU_BSEL0

34­49­42­44­46-

1, 0.5

1

C240

5.6pF_50v

2

20-,28-,29-,34-,43­20-,28-,29-,34-,43-

15-,21­15-,34-

15-,47-

2

0.1uF_16v

0.1uF_16v

17-,21-

R289

34-

R264
R280
R281
R279

1, 0.5

1

1

C257

C260

2

2

5.6pF_50v

5.6pF_50v

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

Byte5: bit5 =0(PWD)

DISABLE_SRC3

Byte5: bit3 =0(PWD)

DISABLE_SRC6

C270

10K_5%_OPEN

1

2.2K_5%

12

12
1

C258

1
2

5.6pF_50v

R287

C247

1

1
2

C245

0.1uF_16v

2

0.1uF_16v

+VCCP

1

R290

2

2

2

R288

10K_5%

1

33_5%

33_5%

12
2

33_5%1
33_5%

22_1%

2

R284 22_1%12

+V3S

C261

1
2

5.6pF_50v

R278

12

10K_5%

Byte5: bit5 =1

ENABLE_SRC3

Byte5: bit3 =1

ENABLE_SRC6ENABLE_SRC4

+V3S

CLK_3S_ICH48

CLK_3S_CBPCI

CLK_3S_TPM

CLK_3S_SIOPCI

CR#_7

CR#_9

CR#_10

CR#_11

LAYOUT NOTES : THE R684 , R685 , R683 CLOSED TO U21

1
2

C266

0.1uF_16v

15-

FSA

0
0

1
2

1

C268

0.1uF_16v

FSB

0

1
2

1
1 0

CLK_3S_REF

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

Layout note: All decoupling 0.1uF disperse closed to pin

L20

BLM18AG471SN1D

1

2

U29

62

VDDSRC_IO

52

VDDSRC_IO

38

VDDSRC_IO

23

VDD96_IO

55

VDDSRC

6

VDDREF

31

VDDPLL3_IO

66

VDDCPU_IO

19

VDD48

12

VDDPCI

72

VDDCPU

27

VDDPLL3

20

USB_48MHZ_FSLA

2

FSLB_TEST_MODE

7

FSLC_TEST_SEL_REF0

8

REF1

13

PCI1

14

PCI2_TME

15

PCI3

1

CK_PWRGD_PD#

10

SCLK

9

SDATA

5

X1

4

X2

18

GNDPCI

22

GND48

26

GND

30

GND

42

GNDSRC

59

GNDSRC

69

GNDCPU

3

GNDREF

34

GNDSRC

11

NC

65

CR#7
CR#A

37

CR#3

41

CR#4

73

TML-PAD

Byte5: bit2 =0(PWD)

DISABLE_SRC7

Byte5: bit1 =0(PWD)

DISABLE_SRC9

Byte5: bit0 =0(PWD)

DISABLE_SRC10

Byte6: bit7 =0(PWD)

DISABLE_SRC11

C264

10uF_6.3v

1

12

2

PCI_STOP#

CPU_STOP#

CPUT1_LPR_F
CPUC1_LPR_F

CPUT0_LPR_F
CPUC0_LPR_F

CPUC2_ITP_LPR_SRCC8_LPR

CPUT2_ITP_LPR_SRCT8_LPR

SRCT11_LPR
SRCC11_LPF

SRCT10_LPR
SRCC10_LPR

SRCT9_LPR
SRCC9_LPR

SRCT7_LPR
SRCC7_LPR

SRCT6_LPR
SRCC6_LPR

PCI4_27_Select

PCI_F5_ITP_EN

SRCT4_LPR
SRCC4_LPR

SRCT3_LPR
SRCC3_LPR

SRCT2_LPR_SATAT_LPR

SRCC2_LPR_SATAC_LPR

27MHz_NonSS_SRCT1_LPR_SE1

27MHz_SS_SRCC1_LPR_SE2

SRCT0_LPR_DOTT_96_LPR
SRCC0_LPR_DOTC_96_LPR

ICS_ICS9LPRS397_MLF_72P

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

ENABLE_SRC7

ENABLE_SRC9

ENABLE_SRC10

ENABLE_SRC11

C248

1
2

0.1uF_16v

54
53

68
67

71
70

63
64

48
47

50
51

44
45

61
60

57
56

16
17

39
40

35
36

32
33

28
29

24
25

4321

CR#9

46

CR#11

49

CR#10

58

CR#6

Byte5: bit2 =1

Byte5: bit1 =1

Byte5: bit0 =1

Byte6: bit7 =1

C241

0.1uF_16v

CLK_UWB#
CLK_UWB

CLK_3S_MINICARD
CLK_3S_ICHPCI

CHANGE by

R262
R261

C265

0.1uF_16v

22_5%

12

22_5%

12

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

+V3S

C244

1
2

0.1uF_16v

1

R269

10K_5%

2

15-,50­15-,52­15-,52­15-,53-

R270

10K_5%

1

2

R243
R246
R247
R244

33_5%

12

33_5%

CLKREQ_LAN#
CLKREQ_MINI_BOT#
CLKREQ_MINI_TOP#
CPPE#

44-

CLK_R3S_KBC14

46-

CLK_R3S_SIO14

CLK_R3S_DEBUG

CLK_R3S_ICHPCI

0_5%12
0_5%_OPEN

12

0_5%_OPEN

12
12

0_5%

R283

12

R275

C259

5.6pF_50v

15-,44­15-,35-

1, 0.5

1
2

34-

PCISTOP#_3

34-

CPUSTOP#_3

23-

CLK_MCHBCLK

23-

CLK_MCHBCLK#

16-

CLK_CPUBCLK

16-

CLK_CPUBCLK#

19-

CLK_XDP#

41-

CLK_R_UWB#

41-

CLK_R_UWB

19-

CLK_XDP

52-

CLK_PCIE_MINI_BOT

52-

CLK_PCIE_MINI_BOT#

52-

CLK_PCIE_MINI_TOP

52-

CLK_PCIE_MINI_TOP#

50-

CLK_PCIE_LAN

50-

CLK_PCIE_LAN#

21-

CLK_PEG_MCH

21-

CLK_PEG_MCH#

53-

CLK_DOCK_REF

53-

CLK_DOCK_REF#

15-,44-

CLK_R3S_DEBUG

15-,35-

CLK_R3S_ICHPCI

47-

CLK_PCIE_NC

47-

CLK_PCIE_NC#

34-

CLK_PCIE_ICH

34-

CLK_PCIE_ICH#

33-

CLK_SATA1

33-

CLK_SATA1#

21-

SSCLK1_DREF

21-

SSCLK1_DREF#

21-

CLK_DREF

21-

CLK_DREF#

1
2

+V3S

R274

2

166
200
266

10K_5%

R277

2

OPEN

1

1

ITP_EN =0
SRC8/SRC8#

ITP_EN =1
ITP/ITP#

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

FSC

0

0

FSB CLOCK
FREQUENCY

EDI CHEN

667
800

1066

HOST CLOCK

FREQUENCY

1-Nov-2007

R285

12

OPEN

R276

12

10K_5%

27_Selet =0

LCD_SST 100MHZ

27_Selet =1

27MHZ non-spread clock

INVENTEC

TITLE

DD08

CLOCK_GENERATOR

CODE

SIZE

A3

DOC. NUMBER

Model_No AX1

CS

SHEET

1, 0.5

+V3S

C262

5.6pF_50v

OF

REV

6915

H_A#(35:3)

H_ADSTB#1

H_STPCLK#

H_A20M#
H_FERR#

H_IGNNE#

H_INTR

H_NMI

H_SMI#

23-

H_A#(3)
H_A#(4)
H_A#(5)
H_A#(6)
H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)

H_REQ#(4:0) H_RS#(2:0)

H_A#(17)
H_A#(18)
H_A#(19)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)
H_A#(32)
H_A#(33)
H_A#(34)
H_A#(35)

23-

33­33­33-

33­33­33­33-

23-

H_REQ#(0)
H_REQ#(1)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)

H_ADSTB#0

23-

CN16-1

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD010

FOX_PZ4782K_274M_41_478P

GMCH

CPU

ADS#
BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

ADDR GROUP 0

INIT#

CONTROL

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#

PREQ#

TCK

TDI

ADDR GROUP 1

TDO
TMS

XDP/ITP SIGNALS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

ICH

H CLK

BCLK0
BCLK1

RESERVED

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

ICH8

12

R740

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

56_5%

+VCCP

+VCCP

10mils/10mils

23-

H_ADS#

23-

H_BNR#

23-

H_BPRI#

23-

H_DEFER#

23-

H_DRDY#

23-

H_DBSY#

23-

H_BREQ#0

33-

H_INIT#

23-

H_LOCK#

19-,23-

23-

23­23-

19­19­19­19­19-

16-,19­16-,19­16-,19-

19-

16-,19-

19-,34-

20­20-

21-,33-

15­15-

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

1

H_CPURST#

H_TRDY#
H_HIT#

H_HITM#

H_BPM0_XDP#
H_BPM1_XDP#
H_BPM2_XDP#

H_BPM3_XDP#
H_BPM4_PRDY#

H_BPM5_PREQ#
H_TCK
TDI_FLEX
H_TDO

H_TMS
XDP_DBRESET#

H_THERMDA
THERM_MINUS

PM_THRMTRIP#

CLK_CPUBCLK
CLK_CPUBCLK#

12

54.9_1%

12

54.9_1%

12

54.9_1%

12

54.9_1%

51_5%

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

R656

2

H_RS#(0)
H_RS#(1)
H_RS#(2)

R665

R662

R663

R664

16-,19-

16-,19-

16-,19-

16-,19-

23-

H_BPM5_PREQ#

TDI_FLEX

H_TMS

H_TCK

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

1

R738

56_5%

CLOSED TO CPU

2

51 ohm +/-1% pull-up to +VCCP
(VCCP) if ITP is implemented

19-

1

R659

54.9_1%

2

H_TRST#

PM_THRMTRIP# should be T at CPU

EDI CHEN

26-Oct-2007

INVENTEC

TITLE

DD08

MEROM-1

DOC. NUMBER REV

CODE

SIZE

A3

Model_No AX1

CS

SHEETCHANGE by OF

6916

H_D#(63:0)

[e-mail]

H_DSTBN#0
H_DSTBP#0

H_DINV#0

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

1

R743

1K_1%

2

1

2

R744

2K_1%

GTLREF

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

17-,23-

23­23­23-

17-,23-

H_DSTBN#1
H_DSTBP#1

H_DINV#1

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

CN16-2

H_D#(0)
H_D#(1)
H_D#(2)
H_D#(3)
H_D#(4)
H_D#(5)
H_D#(6)
H_D#(7)
H_D#(8)
H_D#(9)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(14)
H_D#(15)

H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(30)
H_D#(31)

23­23­23-

15-,21­15-,21­15-,21-

1

2

R737

OPEN

1

2

R739

OPEN

C572

1
2

OPEN

Place C642(0.1uF_16V) close to the TEST4 pin.
Make sure TEST4 routing is reference
to GND and away from other noisy signals.

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

DATA GRP 0

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

DATA GRP 1

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

MISC

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

FOX_PZ4782K_274M_41_478P

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#

DATA GRP 2DATA GRP 3

D41#
D42#
D43#
D44#
D45#
D46#

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

1

2

R657

OPEN

11-,21-,33-

H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)

H_D#(48)
H_D#(49)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)

2

1

27.4_1%R741

12

54.9_1%R742

12

R661 27.4_1%

12

54.9_1%R660

H_DPRSTP#

CLOSED TO CPU

33­23-

23­11-

+VCCP

Place series resistor (R602 = 1K ohm) on H_PWRGD_XDP without stub

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

23­23­23-

H_DPSLP#

H_DPWR#

H_CPUSLP#
PSI#

H_DSTBN#3
H_DSTBP#3
H_DINV#3

17-,23-

17-,23-

23­23­23-

H_D#(63:0)

H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#(63:0)H_D#(63:0)

R658

12

1K_5%

33-

H_PWRGD

19-

H_PWRGD_XDP

INVENTEC

TITLE

DD08

MEROM-2

DOC. NUMBER REV

CODE

SIZE

CHANGE by OF

EDI CHEN 26-Oct-2007

A3

Model_No AX1

CS

SHEET

6917

PLACE THESE INSIDE SOCKET
CAVITY ON L8 (NORTH SIDE
SECONDARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L8 (SOUTH SIDE
SECONDARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L1 (NORTH SIDE
PRIMARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L1 (SOUTH SIDE
PRIMARY)

SOUTH SIDE SECONDARY

NORTH SIDE SECONDARY

C624

1
2

10uF_6.3v

C199

1
2

10uF_6.3v

C633

1
2

10uF_6.3v

C661

1
2

10uF_6.3v

C198

1
2

10uF_6.3v

C194

2

10uF_6.3v

12

C662

330uF_2v_6mR

12

C177

330uF_2v_6mR

1
2

1
2

C622

1
2

10uF_6.3v

C625

1

10uF_6.3v

2

C193

1
2

10uF_6.3v

C631

1
2

10uF_6.3v

C174

10uF_6.3v

C170

10uF_6.3v

12

12

1
2

1
2

1
2

1
2

C176

1
2

10uF_6.3v

C167

11
2

10uF_6.3v

C165

330uF_2v_6mR

C178

330uF_2v_6mR

C656

10uF_6.3v

C621

10uF_6.3v

C630

10uF_6.3v

C632

10uF_6.3v

C172

1
2

10uF_6.3v

C166

1
2

10uF_6.3v

C655

1
2

10uF_6.3v

C623

1
2

10uF_6.3v

C660

1
2

10uF_6.3v

C629

1
2

10uF_6.3v

1
2

1
2

C173

10uF_6.3v

C169

10uF_6.3v

C658

1
2

10uF_6.3v

C657

1

10uF_6.3v

2

C635

1
2

10uF_6.3v

C634

1
2

10uF_6.3v

C175

1
2

10uF_6.3v

C168

1
2

10uF_6.3v

+VCC_CORE

11-,18-

CN16-3

A7

VCC001

A9

VCC002

A10

VCC003

A12

VCC004

A13

VCC005

A15

VCC006

A17

VCC007

A18

VCC008

A20

VCC009

B7

VCC010

B9

VCC011

B10

VCC012

B12

VCC013

B14

VCC014

B15

VCC015

B17

VCC016

B18

VCC017

B20

VCC018

C9

VCC019

C10

VCC020

C12

VCC021

C13

VCC022

C15

VCC023

C17

VCC024

C18

VCC025

D9

VCC026

D10

VCC027

D12

VCC028

D14

VCC029

D15

VCC030

D17

VCC031

D18

VCC032

E7

VCC033

E9

VCC034

E10

VCC035

E12

VCC036

E13

VCC037

E15

VCC038

E17

VCC039

E18

VCC040

E20

VCC041

F7

VCC042

F9

VCC043

F10

VCC044

F12

VCC045

F14

VCC046

F15

VCC047

F17

VCC048

F18

VCC049

F20

VCC050

AA7

VCC051

AA9

VCC052

AA10

VCC053

AA12

VCC054

AA13

VCC055

AA15

VCC056

AA17

VCC057

AA18

VCC058

AA20

VCC059

AB9

VCC060

AC10

VCC061

AB10

VCC062

AB12

VCC063

AB14

VCC064

AB15

VCC065

AB17

VCC066

AB18

VCC067

FOX_PZ4782K_274M_41_478P

VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099

VCC0100

VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16

VCCA01
VCCA02

VCCSENSE

VSSSENSE

+VCC_CORE

11-,18-

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF3

VID5

AE2

VID6

AF7

AE7

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

1

C171

2

220uF_2v_15mR_Panasonic

11-

H_VID0

11-

H_VID1

11-

H_VID2

11-

H_VID3

11-

H_VID4

11-

H_VID5

11-

H_VID6

LAYOUT NOTE:
ROUTE VCCSENSE AND VSSSENSE TRACE AT

24.7 OHM WITH 50 MIL SPACEING
PLACE PU AND PD WITHIN I INCH OF CPU

+VCC_CORE

11-,18-

1

R717

100_1%

2

1

R716

100_1%

2

11-

11-

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

C626

1
2

0.1uF_16v

VCCSENSE

VSSSENSE

C627

1
2

0.1uF_16v

LAYOUT NOTE:
PLACE C2461 NEAR PIN B26

PLACE THESE INSIDE SOCKET
CAVITY ON L8 (NORTH SIDE
SECONDARY)

C197

C628

1

1

2

2

0.1uF_16v

10-,13-,26-,36-,41-,47-,52-

0.1uF_16v 0.1uF_16v

0.01uF_16v

C654

1
2

+V1.5S

1
2

C196

C195

1
2

0.1uF_16v

1

C653

10uF_6.3v

2

INVENTEC

TITLE

DD08

MEROM-3

CHANGE by

EDI CHEN

26-Oct-2007

SIZE

A3

DOC. NUMBER

CODE

Model_No AX1

CS

SHEET

REV

OF

6918

XDP CONNECTOR

[e-mail]

CN16-4

A4

VSS001

A8

VSS002

A11

VSS003

A14

VSS004

A16

VSS005

A19

VSS006

A23

VSS007

AF2

VSS008

B6

VSS009

B8

VSS010

B11

VSS011

B13

VSS012

B16

VSS013

B19

VSS014

B21

VSS015

B24

VSS016

C5

VSS017

C8

VSS018

C11

VSS019

C14

VSS020

C16

VSS021

C19

VSS022

C2

VSS023

C22

VSS024

C25

VSS025

D1

VSS026

D4

VSS027

D8

VSS028

D11

VSS029

D13

VSS030

D16

VSS031

D19

VSS032

D23

VSS033

D26

VSS034

E3

VSS035

E6

VSS036

E8

VSS037

E11

VSS038

E14

VSS039

E16

VSS040

E19

VSS041

E21

VSS042

E24

VSS043

F5

VSS044

F8

VSS045

F11

VSS046

F13

VSS047

F16

VSS048

F19

VSS049

F2

VSS050

F22

VSS051

F25

VSS052

G4

VSS053

G1

VSS054

G23

VSS055

G26

VSS056

H3

VSS057

H6

VSS058

H21

VSS059

H24

VSS060

J2

VSS061

J5

VSS062

J22

VSS063

J25

VSS064

K1

VSS065

K4

VSS066

K23

VSS067

K26

VSS068

L3

VSS069

L6

VSS070

L21

VSS071

L24

VSS072

M2

VSS073

M5

VSS074

M22

VSS075

M25

VSS076

N1

VSS077

N4

VSS078

N23

VSS079

N26

VSS080

P3

VSS081

FOX_PZ4782K_274M_41_478P

VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

H_BPM5_PREQ#

H_BPM4_PRDY#

H_BPM3_XDP#
H_BPM2_XDP#

H_BPM1_XDP#
H_BPM0_XDP#

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

+VCCP

H_PWRGD_XDP

C659

1
2

0.1uF_16v

16­16-

16­16-

16­16-

17- 15-

12

R758

54.9_1%

H_TCK

JTAG DEBUG CONNECTOR

5-,13-,14-,15-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

H_TDO

H_TCK

H_TMS

TDI_FLEX

CN24

12

GND0

3

OBSFN_A0

5

OBSFN_A1

78

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4 GND5

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6 GND7

21

OBSFN_B0

23

OBSFN_B1

25 26

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12 GND13

39

PWRGOOD_HOOK0

41

HOOK1

43

VCC_OBS_AB VCC_OBS_CD

45

HOOK2

47

HOOK3

49 50

GND14

51

SDA

53

SCL

55 56

TCK1

57

TCK0

59

GND16 GND17

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

ITPCLK_HOOK4

ITPCLK#_HOOK5

RESET#_HOOK6

DBR#_HOOK7

GND15

TRSTn

4
6

10
12
14
16
18
20
22
24

28
30
32
34
36
38
40
42
44
46
48

52

TDO

54

TDI

58

TMS

60

SAMTEC_BSH_030_01_L_D_A_TR_60P

+V3S

+VCCP

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

PAD100

1

1

2

2

3

3

4

4

16-,19­16-,19­16-,19­16-,19-

5

5

6

6

7

7

8

8

SMDPAD_8P_30X81

+V3A

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

+VCCP

C665

1
2

0.1uF_16v

1K_5%

12

R757

8-,15-,16-,17-,18-,19-,21-,22-,23-,25-,26-,33-,36-

5-,7-,9-,13-,14-,32-,34-,35-,36-,41-,42-,43-,47-,50-,52-,53-,54-

+VCCP

2

1

R759

1K_5%

R760

54.9_1%

2

1

CLK_XDP

15-

CLK_XDP#

16-,23-

H_CPURST#

16-,34-

XDP_DBRESET#

16-,19-

H_TDO

16-

H_TRST#

16-,19-

TDI_FLEX

16-,19-16-,19-

H_TMS

CHANGE by

EDI CHEN 2-Nov-2007

INVENTEC

TITLE

DD08

MEROM-4

DOC. NUMBER

CODE

A3

Model_No AX1

CS

REVSIZE

OFSHEET

6919

5-,11-,13-,14-,22-,31-,34-,36-,38-,39-,46-,47-,48-,53-

11/02

PWM_3S_FAN#

THERM_3S_WARN#

H_THERMDA

THERM_MINUS

THERM_3S_WARN#

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

16-

16-

20-

+V3S

44-

20-

2

2.2K_5%

R219

+V5S

C7

1uF_10v

C6

1

0.1uF_16v

2

FAN_FG

CN6

1

1

2

2

3

G1

G

3

4

G

G2

4

ACES_85205_0400_4P

1
2

5

3

U1

4

NC7SZ00M5

1
2

+V3S

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

C201

1

0.1uF_16v

C200

1000pF_50v

12

2

U28

1

VDD

2

DP

3

4

THERM

SMSC_EMC1402_1_ACZL_MSOP_8P

SMCLK

SMDATA

ALERTDN

8

7

6

5

GND

15-,28-,29-,34-,43-

15-,28-,29-,34-,43-

34-,35-

ICH_3S_SMCLK
ICH_3S_SMDATA

THERM_SCI#

LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU

1

CHANGE by

EDI CHEN

26-Oct-2007

INVENTEC

TITLE

DD08

THERMAL&FAN CONTROLLER

A3

Model_No AX1

CS

SHEET

OF

REVSIZE CODE DOC. NUMBER

6920

MCH_CFG(5)

[e-mail]

MCH_CFG(13:12)

XOR/ALLZ

NOTE: CFG[2:0] STRP : 010b : 800 MT/S

LOW=DMIx2
HIGH=DMIx4

00=PARTIAL CLOCK GATING DISABLE

01=XOR MODE ENABLE
10=ALL-Z MODE ENABLE
11=NORMAL OPERATION

011b : 667 MT/S

MCH_CFG(19)
MCH_CFG(20)

MCH_CFG(7)

(CPU Strap)

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

21-

21-

+V3S

5-,13-,14-,15-,19-,20-,21-,22-,26-,27-,28-,29-,31-,32-,33-,34-,35-,36-,37-,41-,42-,43-,44-,46-,47-,48-,49-,50-,56-

R143 10K_5%

+V1.8

8-,12-,21-,25-,26-,28-,29-

1

R206

1K_1%

2

1

R208

3K_1%

2

1

R209

1K_1%

2

MCH_CFG(20)
DIGITAL DISPLAY
PORT(SDVO/DP/iHDMI)
CONCURRENT WITH PCIE

12

10K_5%R142

12

PM_PWROK

C179

1
2

1
2

1
2

0.01uF_16v

C183

1
2

0.01uF_16v

LOW=ONLY DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)OR PCIEIS OPERATIONAL
HIGH= DIGITAL DISPLAY PORT
(SDVO/DP/iHDMI)AND PCIE ARE OPERATING

VIA THE PEG PORT

C181

2.2uF_6.3v

C182

2.2uF_6.3v

PM_EXTTS#0_R
PM_EXTTS#1_R

11-,21-,34-,44-

21-

SM_RCOMP_VOH

21-

SM_RCOMP_VOL

LOW=RSVD
HIGH=Mobile CPU

MCH_CFG(16)
(FSB Dynamic
ODT)

+V3S

1

R650

OPEN

2

R168

0_5%

1

R649

OPEN

2

MCH_CFG(17:3)

12

MCH_CFG(9)
PCIE Graphics
Lane

LOW=Dynamic ODT

Disable

HIGH=Dynamic ODT

Enable

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

MCH_CFG(18)
MCH_CFG(19)
MCH_CFG(20)

PM_SYNC#

H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1

PLT_RST#

PM_THRMTRIP#

PM_DPRSLPVR

MCH_CFG(19)
(DMI LANE
REVERSAL)

LOW=Reverse Lane

HIGH=Normal operation

21­21-

34­11-,17-,33­28­29-

35-,47­16-,33­11-,34-

12

R731

12

R732

12

R735
R141 0_5%

R224

R707

15-,17-

15-,17-

15-,17-

21-

LOW=NORMAL

HIGH=LANES REVERSED

1K_5%R730

1K_5%

1K_5%

MCH_CFG(3)
MCH_CFG(4)
MCH_CFG(5)
MCH_CFG(6)
MCH_CFG(7)
MCH_CFG(8)
MCH_CFG(9)
MCH_CFG(10)
MCH_CFG(11)
MCH_CFG(12)
MCH_CFG(13)
MCH_CFG(14)
MCH_CFG(15)
MCH_CFG(16)
MCH_CFG(17)

12
12
12
12

12
12

NOTE :

USE 4K-OHM RESISTOR WHEN INSTALLING
PULL-UP/PULL-DOWN RESISTOR ON ANY
MCH-CFG CONNECTION/PINS.

U17-2

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

AJ6

RSVD16

M1

RSVD17

AY21

RSVD20

A47

RSVD21

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

PM_EXTTS#0_R
PM_EXTTS#1_R

R29

N33

P32

AT40

AT11

T20

R32

BG48

BF48

BD48

BC48

BH47

BG47

BE47

BH46

BF46

BG45

BH44

BH43

BH6

BH5

BG4

BH3

BF3

BH2

BG2

BE2

BG1

BF1

BD1

BC1

B7

F1

PM_SYNC#

PM_DPRSTP#

PM_EXT_TS#_0

PM_EXT_TS#_1

PWROK

RSTIN#

THERMTRIP#

DPRSLPVR

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

NC_8

NC_9

NC_10

NC_11

NC_12

NC_13

NC_14

NC_15

NC_16

NC_17

NC_18

NC_19

NC_20

NC_21

NC_22

NC_23

NC_24

NC_25

0_5%R164
0_5%

0_5%R145
100_5%

0_5%

ITL_CANTIGA_FCBGA_1329P

SA_CK_0

SA_CK_1

SB_CK_0

SB_CK_1

SA_CK#_0

SA_CK#_1

SB_CK#_0

SB_CK#_1

SA_CKE_0

SA_CKE_1

SB_CKE_0

SB_CKE_1

SA_CS#_0

SA_CS#_1

SB_CS#_0

SB_CS#_1

SA_ODT_0

SA_ODT_1

SB_ODT_0

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0

DMI_RXN_1

DMI_RXN_2

DMI_RXN_3

DMI_RXP_0

DMI_RXP_1

DMI_RXP_2

DMI_RXP_3

DMI_TXN_0

DMI_TXN_1

DMI_TXN_2

DMI_TXN_3

DMI_TXP_0

DMI_TXP_1

DMI_TXP_2

DMI_TXP_3

GFX_VID_0

GFX_VID_1

GFX_VID_2

GFX_VID_3

GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

AP24

AT21

AV24

AU20

AR24

AR21

AU24

AV20

BC28

AY28

AY36

BB36

BA17

AY16

AV16

AR13

BD17

AY17

BF15

AY13

BG22

BH21

BF28

BH28

AV42

AR36

BF17

BC36

B38

A38

E41

F41

F43

E43

AE41

AE37

AE47

AH39

AE40

AE38

AE48

AH40

AE35

AE43

AE46

AH42

AD35

AE44

AF46

AH43

B33

B32

G33

F33

E33

C34

AH37

AH36

AN36

AJ35

AH34

N28

M28

G36

E36

K36

H36

B12

B28

B30

B29

C29

A28

12

R684 10K_5%
R225 499_1%12

TP1048

DMI_TXN(0)
DMI_TXN(1)
DMI_TXN(2)
DMI_TXN(3)

DMI_TXP(0)
DMI_TXP(1)
DMI_TXP(2)
DMI_TXP(3)

DMI_RXN(0)
DMI_RXN(1)
DMI_RXN(2)
DMI_RXN(3)

DMI_RXP(0)
DMI_RXP(1)
DMI_RXP(2)
DMI_RXP(3)

12

R167

0_5%

TP11005

TP11006

48­48­15­34-

CHANGE by

MCH_CFG(16)

MCH_CFG(9)
MCH_CFG(7)
MCH_CFG(5)

28­28­29­29-

28­28­29­29-

28-,30­28-,30­29-,30­29-,30-

28-,30­28-,30­29-,30­29-,30-

28-,30­28-,30­29-,30­29-,30-

21­21-

21­21-

15-

CLK_DREF

15-

CLK_DREF#

15-

SSCLK1_DREF

15-

SSCLK1_DREF#

15-

CLK_PEG_MCH

15-

CLK_PEG_MCH#

34-

DMI_TXN(3:0)

34-

DMI_TXP(3:0)

34-

DMI_RXN(3:0)

34-

DMI_RXP(3:0)

9-

DFGT_VID_0

9-

DFGT_VID_1

9-

DFGT_VID_2

9-

DFGT_VID_3

9-

DFGT_VID_4

9-

DFGT_VR_EN

34-

CL_CLK0

34-

11-,21-,34-,44-

TMDS_C_SCLK
TMDS_C_SDATA
CLKREQ_MCH#
MCH_ICH_SYNC#

CL_DATA0

PM_PWROK

34-

CL_RST#0

+VCCP

8-,15-,16-,17-,18-,19-,22-,23-,25-,26-,33-,36-

12

R734

56_5%

EDI CHEN

21­21­21­21-

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR0#
M_CLK_DDR1#
M_CLK_DDR2#
M_CLK_DDR3#

M_CKE0
M_CKE1
M_CKE2
M_CKE3

M_CS0#
M_CS1#
M_CS2#
M_CS3#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP

SM_RCOMP#
SM_RCOMP_VOH

SM_RCOMP_VOL

C112

0.1uF_16v

1

R715

OPEN

2

+V1.25_TEENAH

25-,26-

1

2

1
2

26-Oct-2007

1

R708

OPEN

2

+V1.8

8-,12-,21-,25-,26-,28-,29-

12

R207

80.6_1%

12

R205

80.6_1%

12-,28-,29-

C113

1
2

0.1uF_16v

R165

1K_1%

12

R166

499_1%

INVENTEC

TITLE

DD08

CANTIGA-1

SIZE

CODE

A3

CS

SHEET

1

R713

OPEN

2

21-

SM_RCOMP

21-

SM_RCOMP#

M_VREF

DOC. NUMBER

OF

21 69

1

2

R710

OPEN

REV

AX1Model_No