DDD UMA
SI Build(Final)
2007.03.30
DATE
POWER
VER :
DATE
INVENTEC
TITLE
DDD UMA
DOC. NUMBER
CODE
SIZE
A3
CS
SHEET
14 8
REV
AX1 Model_No
OF
DATE CHANGE NO.
REV
DRAWER
DESIGN
CHECK
RESPONSIBLE
SIZE =
FILE NAME :
XXXXXXXXXXXX
P/N
EE
3
XXXX-XXXXXX-XX
TABLE OF CONTENTS
PAGE
5- DC& BATTERY CHARGER
6- SELECT & BATTERY CONN
7- SYSTEM POWER(3V/5V)
8- SYSTEM POWER(+V1.8/+V1.25S)
9- SYSTEM POWER(+VGFX/+VCCP)
10- SYSTEM POWER(+V1.5S)
11- CPU POWER(VCC_CORE)
12- DDR TERMINATION VOLTAGE
13- POWER(SLEEP)
14- POWER(SEQUENCE)
PAGE
15- CLOCK_GENERATOR
16- PENRYN-1
17- PENRYN-2
18- PENRYN-3
19- THERMAL&FAN CONTROLLER
20- Crestline-1
21- Crestline-2
22- Crestline-3
23- Crestline-4
24- Crestline-5
25- Crestline-6
26- DDR2-DIMM0
27- DDR2-DIMM1
28- DDR2-DAMPING
29- VGA CONN
30- LCM CONN
31- ICH8-1
32- ICH8-2
33- ICH8-3
34- ICH8-4
35- ICH8-5
PAGE
36- SYSTEM BIOS&ODD EXTEND/B
37- HDD&ODD CONN
38- USB CONN
39- KBC
40- KB&TP CONN
41- AUDIO CODEC
42- MDC CONN & AUDIO JACK
43- NIC 10/100- CONTROLLER
44- NIC 10/100- RJ45 CONN
45- MINICARD & BT CONN
46- NEW CARD & SD/MMC
47- LED & BUTTON
48- SCREW HOLE
INVENTEC
TITLE
DDD UMA
CODE
CHANGE by
Smit
23-Mar-2007
SIZE
A3
DOC. NUMBER
Model_No AX1
CS
SHEET
REV
OF
48 2
Clock Generator
ICS9LPRS355
P.15
LCM
VGA
P.30
P.29
SYSTEM
BIOS
LVDS
CRT
P.36
SPI
Penryn
(478 uFCPGA)
FSB
Crestline
965GM
(1299 PCBGA)
DMI
P.16
P.20
SATA
DDR2
DDR2
HDD
DDR II _SODIMM0
P.26
DDR II _SODIMM1
P.27
P.37
MAIN BATT
System Charger &
DC/DC System power
SD/MMC
Conn
P.46
MDC V1.5
CONNECTOR
RJ11
FIXED ODD
USB0
Conn
USB1
Conn
USB2
Conn
CARD READER
ALCOR AU6371
(USB3)
P.46
P.42
P.42
P.38
P.38
P.38
PATA
P.37
USB2.0
AUDIO CODEC
AD_1981HD
Mic IN
Headphone
P.41
BlueTooth
CNTR
(USB6)
P.41
ICH8-M
676 BGA
P.46
HDA
P.41
Speaker
P.41
LPC
LCI
PCI_EXPRESS
P.31
SMSC KBC1070
Keyboard
P.40
MINI CARD
CONN
(WLAN)
KBC
TouchPad
P.39
P.40
P.45
CHANGE by
New Card
CONN
(USB7)
Smit
P.46
NIC 10/100
INTEL
82562GT
RJ45
28-Mar-2007
P.43
P.44
INVENTEC
TITLE
DDD UMA
DOC. NUMBER
CODE
SIZE
A3
Model_No AX1
CS
SHEET
REV
OF
48 3
Adapter
+VADP2
OCP
OCP_OC#
+VBATR
KBC_PW_ON
SLP_S3#_3R
ADP_PRES
5/3.3V
(TPS51120)
+V5A
+V3A
+V5AL
+V3AL
+V5S
+V3S
ADP_PRES
BATSELB
AC_AND_CHG
CHGCTRL_3
Charger
(BQ24703)
Selector
(Discrete)
+VBDC
+VBATA
CHGCTRL_3
ADP_PRES
AC_AND_CHG
BATCON
Main Battery
PWR_GOOD_3
PM_DPRSLPVR
PSI#
H_DPRSTP#
SLP_S4#_3R
SLP_S3#_3R
V1.25S_PG
IO POWER
(TPS51124)
GPU POWER
(TPS51117)
IMVP VI
(ADP3208)
SLP_S3#_3R
+V1.8
V1.8_PG
+V1.25S
V1.25S_PG
VCCP_PG
+VCC_CORE
(APL5913)
+VCCP
+VCCP
+VGFX_CORE
LR
(G2997)
LR
VR_PWRGD_CK505
+V0.9S
M_VREF
+V1.5S
V1.5S_PG
INVENTEC
TITLE
DDD UMA
DOC. NUMBER
CODE
CHANGE by
SIZE
A3
CS
SHEET
15-Mar-2007 Smit
44 8
REV
AX1 Model_No
OF
DC JACK
JACK500
4
3.3A_150mil
1
2
3
G1
G2
0.1uF_25v
FOX_JPD1041_NB073_7F_4P
1
R16
1.5K_5%
2
1
R503
2
1 2
R501
8.25K_1%
1
R502
14.3K_1%
2
2VREF
7-,14-
+VBDC
5-,6-
+VADPTR
C5 1
2
10pF_50v
100K_0.5%
L1
NFM60R30T222
3
C6
1
2
270K_5%
3
2
C501
1
2
0.022uF_16v
+VADP
R15
12
100K_1%
3.3A_150mil
1 2
4
0.1uF_25v
PDS540_5A_40V
R505
12
+V5AL
5-,7-
C500
0.1uF_16v
8
U8-A
+
1
OUT
-
ON_LM393DR2G_SOP_8P
4
R500
1M_5%
12
+V5AL
5-,7-
8
U8-B
5
+
7
OUT
6
-
ON_LM393DR2G_SOP_8P
4
CHGCTRL_3
5-,6-
R7
12
100K_1%
R45
12
24K_1%
+VADP
5-,6-
C3
C4 1
10pF_50v
2
D501
Q21
8
7
6
5
AM4825P_AP
1
2
6-
AC_AND_CHG
SSM3K7002F
Q6
SSM3K7002F
12
1M_5%
1
R13
23.7K_0.1%
2
MICREL_LMC7101BIM5_SOT23_5P
Q9
6-,39-
1
2
D
R14
1
2
G
S
1
1
+V5AL
3 4
IN+
IN-
3
1
2
3
4
G
G
5-,7-
2
V+
LM324A
ADP_PRES
+V3AL
2
S
D
3
3
D
S
2
OUT
V-
4
U500-A
+
1
OUT
-
11
12
20K_5%
5-,6-,7-,14-,31-,39-,40-,47-
1
R19
4.7K_5%
ALARM
2
R535
1
100K_5%
2
1
R34
191K_1%
C15
0.1uF_16v
C503
12
0.1uF_16v
1
U6
5
3
2
+VADP1
5-
R9
5-,6-,7-,39-,43-
R504
10K_5%
2
24703VREF
1
2
1
2
R18
1
100_5%
C513
1
2
0.1uF_25v
1
R521
0_5%
2
Kevin sense
5-
1
R508
150K_1%
2
2
1 2
R32
140K_1%
1N4148
1
R30
10K_1%
2
3
U7
ANPEC_APL431LBAC_SOT23_3P
1
R522
0_5%
2
+VBATR
12
0.015_1%_1W
1
R31
2
100_1%
2
1
D2
C504
1uF_6.3v
R27
12
100K_1%
2
CATHODE
ANODE
1
REF
ADP_PRES
5-,7-,8-,9-,11-,13-,30-,39-
+VADP2 +VADP1
6-
R509
C16
12
1uF_6.3v
R35
12
1.62K_1%
12
1K_1%
R507
100K_5%
12
1
R539
60.4K_1%
2
1
2
1
2
R538
60.4K_1%
1 2
R28
221_1%
3
1
2
R26
9.53K_1%
2
Q2001
SSM3K7002F
R513
0.018_1%_1W
12
Kevin sense
R536
1
C7
2
1
2
4.7uF_6.3v
1
R9589
13.7K_1%
2
Q519
D
G
1
S
SSM3K7002F
3
3
D
G
1
5-,6-,7-,39-,43-
S
2
2
2
R33
100_1%
1
U1
ACN
9
ACP
26
ACDET
5
ENABLE
28
ACSEL
19
ALARM
2
SRSET
3
ACSET
27
ACPRES
13
IBAT
4
VREF
7
COMP
NC
23
NC
TI_BQ24703_QFN_28P
1
R537
150_1%
2
C510
C23
1
150pF_50v
2
4.7uF_6.3v
1
R9590
1M_5%
2
1
R9591
1M_5%
2
Q520
D
S
1
2
ACDRV#
BATDRV#
BATSET
BATDEP
THERMAL
5
+
6
-
+V3AL
G
1
3
1
SSM3K7002F
4.7uF_25v
25 8
22
VCC
21
PWM#
16
SRP
15
SRN
12
BATP
24
18
VS
20
VHSP
6
1
17
GND
11 14
NC
10
NC
29
C511
2200pF_50v
12
4
U500-B
7
OUT
LM324A
11
Q18
1
B
5-,6-,7-,14-,31-,39-,40-,47-
1
R9592
220K_5%
2
Q521
D
G
2
S
BSS138
6-
+VBATR
5-,7-,8-,9-,11-,13-,30-,39-
C502
2
1uF_25v
1
1
2
2
D500
RLZ18C
1
R541
10K_5%
2
2
E
C
MMBT3906
3
1
R511
47K_5%
2
BATT_2P#
1
R512
12
237K_1%
R506
1K_5%
4
U500-C
10
+
OUT
9
-
LM324A
11
SSM3K7002F
Q13
1
1
R510
10K_5%
2
1
Q11
SSM3K7002F
1
13
1
R8
174K_1%
2
1
R10
20K_1%
2
C2
180pF_50v
1
R11
7.87K_1%
2
2
D502
CHENMKO_BAT54_3P
1
2
R518
12
100K_5%
4
U500-D
12
+
14
OUT
13
-
LM324A
11
12
C512
383K_1%
6800pF_25v
1908GND
OCP_OC#
5-,11-,13-,14-,19-,30-,32-,34-,37-,40-,41-,42-
1
B
1
R4
215K_1%
2
1
R5
80.6K_1%
2
L2
12
R520
8
G
G
C19
0.1uF_25v
Q17
1
B
2
S
D
3
3
D
S
2
1
2
1
R25
4.7K_5%
2
2
E
C
MMBT3906
3
AP_AM4835P_T1_PF
C20
1
22uF_25v
2
1
2
3
4
R39
0_5%
S
1
R516
133K_1%
2
1
R517
80.6K_1%
2
5-
R12
12
412K_1%
Q20
8
D
7
6
5
G
1
2
H_STPCLK
32-
PLFC1045R_10uH
1
D504 2
SSM34_3A40V
Kevin sense
1
R17
13.7K_1%
2
1
R37
300K_0.1%
2
1
R36
Q12
3
D
1
G
S
2
SSM3K7002F
C18
OPEN
1
2
CHANGE by SHEET
2
1
2
Smit
24K_0.1%
R38
8.87K_0.5%
Q10
3
D
G
1
S
2
SSM3K7002F
26-Mar-2007
5-,11-,13-,14-,19-,30-,32-,34-,37-,40-,41-,42-
D506
2
R519
12
36.5K_1%
1
3
2
D503
3
BAT54S_30V_0.2A
C524
1
BAT54C_30V_0.2A
2
C505
1
2
1uF_16v
1
R553
10_5%
2
7-
1uF_25v
Place near L19
+V5S
1
2
E
Q14
MMBT3906
C
SSM3K7002F
3
1
R6
330K_5%
2
SSM3K7002F
R42
0.015_1%_1W
12
1 2
R44
1K_1%
0.033uF_16v
12
+V3AL
6CELLSEL#=0,Vcharger=12.6V
6CELLSEL#=1,Vcharger=16.8V
G
1
Q8
Q5
1
1
G
R2
2
1M_5%
1 2
R43
1K_1%
C17
5-,6-,7-,14-,31-,39-,40-,47-
1
R41
10K_5%
2
Q7
3
D
G
1
S
2
SSM3K7002F
2
S
D
3
3
D
S
2
1
2
C21
10uF_25v_K_X5R
6-
6CELLSEL#
R3
220K_5%
2
5-
+VBDC
C22
10uF_25v_K_X5R
C8 C13
1
1
2
2
4.7uF_25v
Note:
high power trace
INVENTEC
TITLE
DDD UMA
DC &BATTERY CHARGER
CODE REV SIZE
DOC. NUMBER
A3
Model_No AX1
CS
OF
+V5S
1
MAX_LX5
H_STPCLK
5-,6-
48 5
CHGCTRL_3
CHENKO_LL4148_2P
1000pF_50v
5-,39-
FIX39
FIX_MASK
FIX40
FIX_MASK
FIX41
FIX_MASK
FIX42
FIX_MASK
C514
2
D4
EX17_BAT_GND
0.047uF_10v
1
R543
12
1K_5%
1
2
+VBATA_EX17_BAT
CN4001
TYCO_1746707_1_6P
EX17_BAT_GND
1
1
2
2
3
3
4
4
G1
5
G
5
G2
6
6
G
SCREW2.8_7_1P
S26
17.0’W BATTERY EXTEND/B
1
1
C515
1
R544
470K_5%
2
R546
470K_5%
2
2
3
D
1
G
S
2
Q3
SSM3K7002F
CN4000
SYN_200046MR006G101ZR_6P
1
1
2
2
3
3
4
4
5
5
6
6
SCREW2.8_7_1P
S27
EX17_BAT_GND
+V3AL
5-,6-,7-,14-,31-,39-,40-,47-
5
U5
24
74HC1G14GV
3
AC_AND_CHG
ADP_PRES
G1
G
G2
G
EX17_BAT_GND
SCREW2.8_7_1P
S28
EX17_BAT_GND
+VADP
5-
5-,7-,39-,43-
5-
R1
12
3K_5%
1
R545
10K_5%
2
+VBATA
D1
1
2
RLZ18C
Q16
SSM3K7002F
3
2
D
S
G
1
6-
+VADP2
5-
+V3AL
5-,6-,7-,14-,31-,39-,40-,47-
1
R24
220K_5%
2
Q2
1
S
2
3
G
AM4825P_AP
21
8
D
7
6
5 4
D3CHENKO_LL4148_2P
12
1.5M_5%
+V3AL
5-,6-,7-,14-,31-,39-,40-,47-
5-
SSM3K7002F
R40
SSM3K7002F
1
Q15
8
1
D
S
7
2
6
3
54
G
AM4825P_AP
3
Q19
D
G
1
S
2
3
Q1
D
G
S
2
1
Q4
G
1
R22
470K_5%
2
1
R21
4.7K_5%
2
3
D
SSM3K7002F
S
2
+VBATA +VBDC
6-
C14
1
2
OPEN
SDA_MAIN
SCL_MAIN
CHENMKO_CHPZ6V2_3P
1
R9595
100K_5%
2
THM_MAIN#
39-
3
SSM3K7002F
D2004
CHENKO_LL4148_2P
D
S
2
2 1
Q523
G
1
+V3AL
R550
10K_5%
3939-
D505
+V3AL
5-,6-,7-,14-,31-,39-,40-,47-
Q522
2
E
1
B
C
3
MMBT3906
1
R9594
220K_5%
2
1
R9623
220K_5%
2
5-,6-,7-,14-,31-,39-,40-,47-
1
1
R549
10K_5%
2
2
12
C1 C2
A
1
R552
100K_5%
2
1
R9593
47K_5%
2
+V3AL
5-,6-,7-,14-,31-,39-,40-,47-
5
U7001
2
74HC1G14GV
3
R9625
10_5%
4
R9624
10_5%
12
12
1
C523
2
47pF_50v
5-
1
R23
10K_5%
2
SYN_200046MR006G100ZU_6P
R551
100_5%
BATT_2P#
39-
BATCON
5-
MAIN BATT
CN500
1
1
2
2
3
3
4
4
5
5
6
6
C516
1
2
0.1uF_25v
6CELLSEL#
7
7
8
8
INVENTEC
TITLE
DDD UMA
SELECT & BATTERY CONN
SIZE
CODE
CHANGE by
Smit
21-Mar-2007
DOC. NUMBER
A3
Model_No AX1
CS
SHEET
REV
OF
48 6
ADP_PRES
KBC_PW_ON
5-,6-,39-,43-
39-
R761
17.4K_1%
C760
OPEN
+VBATR
5-,8-,9-,11-,13-,30-,39-
PAD503
3
4
R762
POWERPAD_4A
4
1 2
51120GND
+V5AL
5-,7-
5
U520
1
2
TC7SET32FU
3
1 2
7.32K_1%
12
7-
+VBATP
5-,7-,14-
C761
1000pF_50v
2VREF
1
2
51120GND
R763
12
0_5%
51120GND
7.32K_1%
R765
12
30K_1%
R766
12
C762
2
1
OPEN
9-,13-,14-,30-,32-,33-,34-,36-,43-,45-,46-,47-
+V3A
PAD504
POWERPAD_2_0610
C770 1
1uF_10v
1
2
2
+VBATP
7-
C776
1
1
2
4.7uF_25v
CYNTEC_PCMC063_3R3
L521
2
1 2
C771
330uF_4v
C773
4.7uF_25v
8765
D
876
D
S
123
FDS8884
G
4S123
5
G
FDS6690AS
4
Q514
Q513
POWERPAD_2_0610
C763
0.1uF_16v
12
+V3AL
5-,6-,14-,31-,39-,40-,47-
PAD555
R771
4.7_5%
12
1
C764
4.7uF_6.3v
2
6
8
7
VO2
VFB2
COMP2
TI_TPS51120_QFN_32P
9
EN5
10
EN3
11
PGOOD2
12
EN2
13
VBST2
14
DRVH2
15
LL2
16
DRVL2
VREG3
PGND2
CS2
19
17
18
1
R772
10K_1%
2
+V5AL
5-,7-
C767 1
4.7uF_6.3v
2
4
5
GND
VREF2
VREG5
V5FILT
21
20
C766
1
0.1uF_16v
2
VFB1
VIN
U519
3
1
2
VO1
COMP1
SKIPSEL
TONSEL
PGOOD1
EN1
VBST1
DRVH1
LL1
DRVL1
PGND1
CS1
22
24
23
1
R413
10K_1%
2
R774
12
10_5%
33
32
31
30
29
28
27
26
25
51120GND
R414
0_5%
12
C765
1
2
1uF_10v
32-,39-
RSMRST#
1
2
4.7_5%
12
C774
4.7uF_25v
R767
OPEN
2
1
8-,9-,12-,13-,14-,30-,32-,39-,43-,46-
R764
OPEN
R773
C768
12
0.1uF_16v
+VBATP
1
C775
1
2
2
4.7uF_25v
12
SLF10040_4R7N7R0
7-
C772
L522
4.7uF_25v
220uF_6.3v
C777
1
1
2
1uF_10v
2
8-,9-,10-,11-,12-,13-,14-,29-,30-,34-,38-
+V5A
PAD505
POWERPAD_2_0610
C778
SLP_S3#_3R
8
2VREF
5-,7-,14-
1 2
5-
MAX_LX5
765
D
G
S
Q515
23
1
4
SI4800DY
8D765
G
Q516
FDS6690AS
41S23
INVENTEC
TITLE
DDD UMA
SYSTEM POWER(3V/5V/12V)
CODE
Smit 29-Mar-2007
DOC. NUMBER SIZE
A3
Model_No AX1
CS
SHEET OF CHANGE by
REV
48 7
R564
1
43.2K_1%
C548
12
OPEN
2
R563
12
30K_1%
51124GND
51124GND
R561
12
30K_1%
R565
12
20.5K_1%
C547
1
2
OPEN
+V1.8
10-,12-,20-,23-,24-,26-,27-
PAD3
POWERPAD_2_0610
1
C81
2
220uF_2.5v
+VBATR
5-,7-,8-,9-,11-,13-,30-,39-
C46
1
2
4.7uF_25v
12
PCMC063T_2R2MN
L4
C45
1
2
4.7uF_25v
FDS6690AS
SI4800DY
Q28
Q27
8
D
S
123
8765
D
765
G
4
G
3
4 1S2
V1.8_PG
SLP_S4#_3R
SLP_S5#_3R
0.1uF_16v
12-,32-
32-,38-
C52
R562
OPEN
12
14-
1
2
R114
12
4.7_5%
R96
2
1
OPEN
6
VO2
7
8
9
10
11
12
12
VFB2
PGOOD2
EN2
VBST2
DRVH2
TI_TPS51124RGER_QFN_24P
LL2
DRVL2
TRIP2
PGND2
13
1
2
R97
0_5%
51124GND
4
5
TONSEL
V5FILT
14
15
R94
15.4K_1%
GND
V5IN
3
16
2
VO1
VFB1
PGOOD1
TRIP1
PGND1
17
1
R93
15.4K_1%
2
1
18
U11
GND
EN1
VBST1
DRVH1
LL1
DRVL1
R91
2
OPEN
C51
+V5A
1
2
OPEN
25
24
23
22
21
20
19
7-,8-,9-,10-,11-,12-,13-,14-,29-,30-,34-,38-
C54
1
2
1uF_10v
R92
12
4.7_5%
R95
12
10_5%
1
2
C49
0.1uF_16v
1
SLP_S3#_3R
7-,9-,12-,13-,14-,30-,32-,39-,43-,46-
7-,8-,9-,10-,11-,12-,13-,14-,29-,30-,34-,38-
R9585
100K_5%_OPEN
9-,14-
V1.25S_PG
12
+V5A
C53
1
2
4.7uF_6.3v
+VBATR
5-,7-,8-,9-,11-,13-,30-,39-
5
8
76
D
G
S
4
123
8
76
5
D
G
4S123
Q24
FDS8884
Q25
FDS6690AS
1
2
PCMC063T_2R2MN
C47
1
2
4.7uF_25v
L3
12
C50
4.7uF_25v
POWERPAD_2_0610
1
C48
220uF_2.5v_R35
2
PAD2
+V1.25S
10-,20-,24-,34-
INVENTEC
TITLE
DDD UMA
Smit
19-Mar-2007
SYSTEM POWER(+V1.8/+V1.25S)
CODE
DOC. NUMBER SIZE
A3
Model_No AX1
CS
SHEET
REV
OF CHANGE by
48 8
+V3A
VCCP_PG
8-,14-
20-
14-
V1.25S_PG
7-,8-,12-,13-,14-,30-,32-,39-,43-,46-
SLP_S3#_3R
DFGT_VR_EN
7-,13-,14-,30-,32-,33-,34-,36-,43-,45-,46-,47-
1
R117
10K_5%_OPEN
2
R9586
0_5%_OPEN
12
R9568
0_5%
12
12
0_5%_OPEN
R46
+V5A
7-,8-,10-,11-,12-,13-,14-,29-,30-,34-,38-
1
R9569
10_5%
1
2
1
1uF_6.3v
2
C1024
R9570
200K_1%
2
U521
1
EN_PSV
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
7
GND
TI_TPS51117_QFN_14P
VCCPGND
VBST
DRVH
TRIP
V5DRV
DRVL
PGND
TML
R9575
0_5%
12
+VBATR
5-,7-,8-,11-,13-,30-,39-
8
765
G
0_5%
VCCPGND
0.1uF_16v
1
R9572
12.1K_1%
2
C1025
12
123
4
8
765
G
3
12
4
R9571
12
14
13
12
LL
11
10
9
8
15
C1026
1
1uF_6.3v
2
D
Q517
FDS8884
S
SLF10155T_2R0N8R4
D
Q518
FDS6676AS
S
C1023
1
2
4.7uF_25v
12
L527
C1022
1
2
4.7uF_25v
VCCPGND
1
R9574
12.1K_1%
2
1
R9573
30K_1%
2
2
PAD4
3
1
4
POWERPAD_4A
1
C1027
2
220uF_2v_15mR_Panasonic
+VCCP
10-,15-,16-,17-,18-,19-,21-,23-,24-,31-,34-
2
PAD506
3
1
4
POWERPAD_4A
+VGFX_CORE
23-
INVENTEC
TITLE
DDD UMA
CHANGE by
Smit
15-Mar-2007
GRAPHIC POWER (+VGFX_CORE)
A3
Model_No AX1
CS
SHEET
REV SIZE DOC. NUMBER CODE
OF
48 9
+V1.25S
8-,20-,24-,34-
+VCCP
9-,15-,16-,17-,18-,19-,21-,23-,24-,31-,34-
R525
12
OPEN
1
2
R523
0_5%
+V5A
7-,8-,9-,11-,12-,13-,14-,29-,30-,34-,38-
C519
1
2
1uF_10v
U501
6
VCNTL
7
POK
82
EN
VIN
GND
9
1
ANPEC_APL5913_KAC_TRL_SOP_8P
14-
VOUT
VOUT
VIN
FB
V1.5S_PG
+V1.8
8-,12-,20-,23-,24-,26-,27-
C506
1
2
5
3
4
22uF_6.3v
C517
1
2
22uF_6.3v
1
2
C518
1uF_10v
1
2
39pF_50v
C520
PAD500
POWERPAD_2_0610
1
R548
27.4K_1%
2
1
R547
30K_1%
2
+V1.5S
13-,18-,24-,34-,45-,46-
INVENTEC
TITLE
DDD UMA
CHANGE by
Smit
15-Mar-2007
SYSTEM POWER(+VCCP/+V1.5S)
A3
DOC. NUMBER
CODE SIZE REV
Model_No AX1
CS
SHEET
OF
48 10
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
VR_PWRGD_CK505
PWR_GOOD_3
VR_PWRGD_CK505
C83
330pF_50v
12
R128
1.65K_1%
0.012uF_16v
11-,15-
H_DPRSTP#
PM_DPRSLPVR
14-
11-,15-
12
C103
+V3S
R134
1K_5%
PSI#
C82
220pF_25v
1
2
1
2
17-
17-,20-,31-
20-,32-
R130
0_5%
12
12
R115
12
68.1K_1%
C102
680pF_50v
+V5S
R638
OPEN
R637
OPEN
R601
0_5%
VCOREGND
CSREF
18-
18-
11-
VCCSENSE
VSSSENSE
1
VCOREGND
5-,13-,14-,19-,30-,32-,34-,37-,40-,41-,42-
12
2
12
C592
1000pF_50v
12
R132
12
OPEN
1
C104
18pF_50v
2
1
2
12
R136
12
1K_5%
12
R131
12
499_1%
VCOREGND
C591
4700pF_25v
R577
0_5%
1000pF_50v
CHENKO_LL4148_2P
D7
R135
1
0_5%_OPEN
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
R133
OPEN
1
EN
2
PWRGD
12
3
PGDELAY
4
CLKEN
5
FBRTN
6
FB
7
COMP
8
SS
9
ST
10
VARFREQ
11
VRTT
12
TTSEN
115K_1%
1
C98
2
VCOREGND
2 1
R147
12
665K_1%
1
C126
0.1uF_16v
2
2
18181818181818-
45
44
42
47
DPRSLP
DPRSTP
PMON
PMONFS
14
2
41
46
PSI
VID0
VID1
VID243VID3
VID4
RAMP20RPM22RT
CSFEF19CSSUM
CLIM
CSCOMP
LLINE
15
17
18
16
49
48
TML
U12
ADI_ADP3208_LFCSP_48P
13
R127
1
VCOREGND
2
R124
0_5%
1
1
C101
1000pF_50v
2
+V3S
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
1 2
C127
0.1uF_16v
5
U16
20-,32-
4
2
3
TI_SN74LVC1G17DCKR_SC70_5P
SB_3S_VRMPWRGD
+V5A
7-,8-,9-,10-,12-,13-,14-,29-,30-,34-,38-
2
R614
10_5%
C123
1
1
2
2.2uF_6.3v
C590
1
2
R600
100K_5%
VCOREGND
37
VCC
36
BST1
35
DRVH1
34
SW1
33
PVCC1
32
DRVL1
31
PGND1
30
PGND2
29
DRVL2
28
PVCC2
27
SW2
26
DRVH2
25
BST2
GND
24
R144
215K_1%
12
12
C100
0.01uF_16v
VCOREGND
1
1
C121
2
1000pF_50v
VCOREGND
R615
1
169K_1%
R616
12
169K_1%
R119
12
220K_1%
1
C99
2
330pF_50v
2.2uF_6.3v
2
2
R121
76.8K_1%
1
R146
4.7_5%
12
12
R145
4.7_5%
+VBATR
R120
12
100_5%
40
39
VID5
VRPM
21
2
1
2
1
SP
VID6
23 38
R143
150K_1%
R122
274K_1%
2
D507
3
BAT54A
2
1
C125
12
1uF_16v
12
C122
1uF_16v
5-,7-,8-,9-,11-,13-,30-,39-
1
R599
220K_5%
2
NTC thermistor, place near L16
1
2
C230
100uF_25v
0.01uF_50v
C623
+VBATR
1
2
5-,7-,8-,9-,11-,13-,30-,39-
C106
1
1
2
2
4.7uF_25v
C170
1
2
4.7uF_25v
C169
4.7uF_25v
X 3
FDS6676AS
C168
1
2
4.7uF_25v
X 3
1
2
Q31
1
2
C167
4.7uF_25v
C166
4.7uF_25v
Q34
FDS6676AS
CHANGE by
1
2
G
4
G
41S23
C171
4.7uF_25v
765
8
D
1S23
8765
D
G
43 21
9
G
43 21
G
4
G
4
56789
Q33
SI7686DP_T1_E3
Q30
765
8
FDS6676AS
D
S
123
5678
Q32
SI7686DP_T1_E3
8765
D
Q35
FDS6676AS
S
23
1
R150
OPEN
C129
OPEN
R149
OPEN
C128
OPEN
ETQP4LR36WFC_PANASONIC
1
2
1
2
1
2
1
2
23-Mar-2007 Smit
L503
1 2
2
R613
10_1%
1
11-
CSREF
2
R612
10_1%
1
L504
1 2
ETQP4LR36WFC_PANASONIC
INVENTEC
TITLE
DDD UMA
CPU POWER(VCC_CORE)
CODE
SIZE
A3
CS
SHEET
11 48
+VCC_CORE
OF
18-
REV DOC. NUMBER
AX1 Model_No
SLP_S4#_3R
SLP_S3#_3R
8-,32-
7-,8-,9-,13-,14-,30-,32-,39-,43-,46-
+V1.8
8-,10-,20-,23-,24-,26-,27-
1
2
C27
4.7uF_6.3v
+V5A
7-,8-,9-,10-,11-,13-,14-,29-,30-,34-,38-
U9
GMT_G2997F6U_MSOP10_10P
11
TML1VDDQSNS
10
VIN VLDOIN
9
S5
8
GND4PGND
7
S3
6
C29
1uF_10v
1
2
VTTREF
C28
0.1uF_16v
1
2
NOTE: DDR2 REGULATOR
20-,26-,27-
VTTSNS
VTT
2
3
5
M_VREF
+V0.9S
1
2
28-
C26
10uF_6.3v
1
2
C25
10uF_6.3v
INVENTEC
TITLE
DDD UMA
DDR TERMINATION VOLTAGE
CHANGE by
SIZE
15-Mar-2007 Smit
A3
DOC. NUMBER CODE
CS
12 48
REV
AX1 Model_No
OF SHEET
7-,9-,13-,14-,30-,32-,33-,34-,36-,43-,45-,46-,47-
+V3A
6
5
2
C441
1
2
0.047uF_16v
1
FDC655BN
R417
120K_1%
12
13-
GATE_3S GATE_5S
+V3S
11-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
Q41
4
D
S
3
G
1
1
R418
47_5%
C442
10uF_6.3v
2
2
7-,8-,9-,10-,11-,12-,14-,29-,30-,34-,38-
R415
120K_1%
12
13-
+V5A
6
D
5
2
13
FDC655BN
C439
1
2
0.047uF_16v
Q40
+V5S
5-,11-,14-,19-,30-,32-,34-,37-,40-,41-,42-
4
S
G
1
C440
2
10uF_6.3v
1
R416
100_5%
2
R426
100_5%
+V1.5S
10-,18-,24-,34-,45-,46-
1
2
SLP_S3#_3R
Q44
3
D
G
1
S
2
SSM3K7002F
1
C769
0.033uF_16v
2
SLP_S3#_3R
7-,9-,13-,14-,30-,32-,33-,34-,36-,43-,45-,46-,47-
7-,8-,9-,12-,13-,14-,30-,32-,39-,43-,46-
7-,8-,9-,12-,13-,14-,30-,32-,39-,43-,46-
SSM3K7002F
+VBATR
Q52
1
G
+V3A
D
S
5-,7-,8-,9-,11-,13-,30-,39-
1
R770
47K_5%
2
1
B
Q54
MMBT3904
1
R769
100K_5%
2
SSM3K7002F
3
2
3
C
E
2
1
R768
130K_1%
2
+VBATR
Q43
1
B
MMBT3906
Q53
G
1
D
S
5-,7-,8-,9-,11-,13-,30-,39-
1
R781
2.7K_5%
2
2
E
C
3
R780
12
0_5%
3
2
D19
1
RLZ18C
2
R775
12
1K_5%
Q42
1
G
SSM3K7002F
3
D
S
2
1
0_5%
2
13- 13-
GATE_5S GATE_3S
1
R776
2
CHANGE by
Smit 15-Mar-2007
1
2
1
2
R779 R778
0_5%
R777
0_5% 0_5%
Q51
1
G
SSM3K7002F
3
D
S
2
INVENTEC
TITLE
DDD UMA
POWER(SLEEP)
CODE
SIZE
A3
CS
SHEET
DOC. NUMBER
Model_No AX1
REV
OF
48 13
5-,6-,7-,14-,31-,39-,40-,47-
1
R419
100K_1%
2
C432
1
2
0.1uF_16v
TI_SN74LVC1G17DBVR_SOT_5P
+V3AL +V3AL
5-,6-,7-,14-,31-,39-,40-,47-
1
2
5
2
3
C429
0.1uF_16v
U25
4
1
R397
100K_5%
2
39-
VCC1_POR#_3
PWR_GOOD_3
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
SLP_S3#_3R
+V3S
5-,11-,13-,19-,30-,32-,34-,37-,40-,41-,42-
+V5S
11-,14-
8-,9-
V1.25S_PG
10-
V1.5S_PG
8-
V1.8_PG
9-
VCCP_PG
7-,8-,9-,12-,13-,30-,32-,39-,43-,46-
R390
12
68.1K_1%
R380
12
102K_1%
12
10K_5%
12
10K_5%
12
10K_5%
12
10K_5%
12
R396
CHENKO_LL4148_2P
1K_5%
D18 CHENKO_LL4148_2P
2 1
R399
12
140K_1%
1
2
C431
0.1uF_16v
R382
R391
R392
R389
D17
2 1
1
1
R393
49.9K_1%
2
2
R394
12
20K_5%
C428
1000pF_50v
1
2
R398
OPEN
R386
12
20K_5%
ON_LM393DR2G_SOP_8P
R383
12
100K_5%
C422
1
2
0.1uF_16v
R385
2
1
1M_5%
+V5A
7-,8-,9-,10-,11-,12-,13-,14-,29-,30-,34-,38-
U24-A
8
3
+
1
OUT
2
4
R395
1
1M_5%
2VREF
1
2
5-,7-
2
+V5A
7-,8-,9-,10-,11-,12-,13-,14-,29-,30-,34-,38-
8
U24-B
5
+
7
OUT
6
-
ON_LM393DR2G_SOP_8P
4
+V3A
7-,9-,13-,30-,32-,33-,34-,36-,43-,45-,46-,47-
1
R384
10K_5%
2
32-,39-
C430
PWR_GOOD_KBC
0.1uF_16v
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
+V3S
1
R401
0_5%_OPEN
1
R400
10K_5%
2
2
11-,14-
PWR_GOOD_3
CHANGE by
Smit 15-Mar-2007
INVENTEC
TITLE
DDD UMA
POWER(SEQUENCE)
SIZE CODE
A3
DOC. NUMBER
Model_No AX1
CS
SHEET
REV
OF
48 14
+V3S
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
L512
BLM18AG471SN1D
1
2
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
CLKREQ_R_SATA#
15-,32-
+VCCP
9-,10-,15-,16-,17-,18-,19-,21-,23-,24-,31-,34-
2
10K_5%
R249
1
CLKREQ_R_MCH#
FSA
FSB
1 1
1
0
17-,2017-,2015-
R662
C302
1
2
OPEN
CLK_PWRGD
VR_PWRGD_CK505
FSC
FSB CLOCK
FREQUENCY
0
0
R663
12
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
20-
10K_5%
+V3S
R701
32-
11-
667
800
CPU_BSEL1
CPU_BSEL2
CLK_3S_REF
*CLKREQ# pin controls SRC Table.
Byte5: bit6 =0(PWD)
SRC0
CR#_A
Byte5: bit7=0, disable CR#_A; 1,enable CR#_A
Byte5: bit2 =0(PWD)
SRC0
CR#_C
Byte5: bit3=0, disable CR#_C; 1,enable CR#_C
Byte5: bit6 =1
SRC2
Byte5: bit2 =1
SRC2
Layout note: All decoupling 0.1uF disperse closed to pin
1
2
C715
10uF_10v
1
2
0.1uF_16v
1
2
0.1uF_16v
C324
1
2
C325
+V3S
10K_5%R267
12
CPU_BSEL0
12
CLK_R3S_ICH48
CLKREQ_R_SATA#
ICH_3S_SMCLK
ICH_3S_SMDATA
C714
33pF_50v
15-,32-
39-
CLK_R3S_MINICARD
C371
1
OPEN
2
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
19-,26-,27-,3219-,26-,27-,32-
1
2
12
10K_5%
1
R700
475_1%
2
12
R665
12
0_5%_OPEN
R664
12
0_5%
HOST CLOCK
FREQUENCY
166
200
10K_5%
C358
22pF_50v
CLK_R3S_DEBUG
Please place close to CLKGEN within 500mils
Byte5: bit4 =0(PWD)
CR#_B
SRC1
Byte5: bit5=0, disable CR#_B; 1,enable CR#_B
Byte5: bit0 =0(PWD)
CR#_D
SRC1
Byte5: bit1=0, disable CR#_D; 1,enable CR#_D
C319
C322
1
2
0.1uF_16v
0.1uF_16v
9-,10-,15-,16-,17-,18-,19-,21-,23-,24-,31-,34-
10K_5%_OPEN
R708
12
17-,20-
2.2K_5%
12
R302
32-
33_5%
12
12
R305
45-
X501
14.31818MHZ
12
1
2
C713
33pF_50v
30PPM
C321
1
2
0.1uF_16v
+VCCP
R709
R301
OPEN
33_5%
12
Byte5: bit4 =1
SRC4
Byte5: bit0 =1
SRC4
1
2
0.1uF_16v
1
2
2
1
475_1%R266
R9607
33_5%
+V3S
12
10K_5%
C318
R702
CLK_3S_ICH48
CLKREQ_SATA#
CLKREQ_MCH#
CLK_3S_DEBUG
CR#_E
CR#_F
CR#_G
CR#_H
+V3S
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
Layout note: All decoupling 0.1uF disperse closed to pin
L510
BLM18AG471SN1D
2
1
U509
26
VDDSRC_IO
45
VDDSRC_IO
36
VDDSRC_IO
12
VDD96_IO
39
VDDSRC
61
VDDREF
20
VDDPLL3_IO
49
VDDCPU_IO
9
VDD48
2
VDDPCI
55
VDDCPU
16
VDD
10
SUB_48MHZ_FSLA
57
FSLB_TEST_MODE
62
REF0_FSLC_TEST_SEL
1
PCI0_CR#_A
3
PCI1_CR#_B
4
CLK_3S_KBPCI
PCI2_TME
5
PCI3
56
CK_PWRGD_PD#
64
SCLK
63
SDTAT
60
X1
59
X2
8
GNDPCI
11
GND48
15
GND
19
GND
23
GNDSRC
29
GNDSRC
42
GNDSRC
58
GNDREF
52
GNDCPU
ICS_ICS9LPRS355BGLFT_TSSOP_64P
Byte6: bit7=0, disable CR#_E; 1,enable CR#_E
SRC6
Byte6: bit6=0, disable CR#_F; 1,enable CR#_F
SRC8
Byte6: bit5=0, disable CR#_G; 1,enable CR#_G
SRC9
Byte6: bit4=0, disable CR#_H; 1,enable CR#_H
SRC10
C722
1
2
10uF_10v
27MHz_NonSS_SRCT1_SE1
27MHz_SS_SRCC1_SE2
C699
1
2
10uF_10v
CPU_STOP#
CPUT2_ITP_SRCT8
CPUC2_ITP_SRCC8
SRCT11_CR#_H
SRCC11_CR#_G
SRCT7_CR#_F
SRCC7_CR#_E
PCI4_27_Select
PCI_F5_ITP_EN
SRCT3_CR#_C
SRCC3_CR#_D
SRCT2_SATAT
SRCC2_SATAC
SRCC0_DOTT_96
SRCT0_DOTC_96
C328
C326
1
2
0.1uF_16v
48
NC
38
PCI_STOP#
37
51
CPUT1_F
50
CPUC1_F
54
CPUT0
53
CPUC0
47
46
33
32
34
SRCT10
35
SRCC10
30
SRCT9
31
SRCC9
44
43
41
SRCT6
40
SRCC6
6
7
27
SRCT4
28
SRCC4
24
25
21
22
17
18
13
14
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
C327
1
1
2
2
0.1uF_16v
0.1uF_16v
CLK_MCHBCLK
CLK_MCHBCLK#
CLK_CPUBCLK
CLK_CPUBCLK#
CLK_XDP
CLK_XDP#
CLK_REQH#
CLK_REQG#
CLK_PCIE_NEWCARD
CLK_PCIE_NEWCARD#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_3S_KBPCI
CLK_3S_ICHPCI
CLK_PEG_MCH
CLK_PEG_MCH#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_SATA1
CLK_SATA1#
SSCLK1_DREF
SSCLK1_DREF#
CLK_DREF
CLK_DREF#
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
C323
1
2
0.1uF_16v
CLK_3S_REF
CHANGE by
+V3S
11-,13-,14-,15-,19-,20-,21-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,45-,46-,47-
C329
1
2
0.1uF_16v
R248
ITP_EN =0
SRC8/SRC8#
ITP_EN =1
ITP/ITP#
15-
1
1
2
2
10K_5%_OPEN
0_5%
12
0_5%
12
12
0_5% R667
0_5%
12
12
0_5%
12
0_5%
475_1%
2
475_1%
12
12
0_5% R677
0_5% R718
12
12
12
33_5%
0_5%
12
0_5%
0_5%
2
0_5%
0_5%
2
0_5%
0_5%12
0_5% 1
2
0_5%
2
R250
R251
R247
12
12
1
2
C320
0.1uF_16v
10K_5%_OPEN
LAYOUT NOTES : THE R250 , R251 CLOSED TO U509
Smit
15-Mar-2007
R720
10K_5%
R669
R670
R668
R672
R673
R245 1
1 2
R686
R6780_5%
R7190_5%
R70433_5% 12
R707
1 2
R716
R7170_5%
1 2
R714
R715
1
1 2
R712
1
R713
1 2
R9565
R9566
R710
1
R711
R303
10K_5%
R706
OPEN
22_5%
22_5%
1
1
R246
10K_5%
2
2
4646-
1 2
1 2
R304
12
OPEN
R703
12
10K_5%
39-
32-
INVENTEC
TITLE
DDD UMA
CLOCK_GENERATOR
SIZE
CODE
A3
CS
SHEET
32-
PCISTOP#_3
32-
CPUSTOP#_3
21-
CLK_R_MCHBCLK
21-
CLK_R_MCHBCLK#
16-
CLK_R_CPUBCLK
16-
CLK_R_CPUBCLK#
19-
CLK_R_XDP
19-
CLK_R_XDP#
46-
CLK_R_REQH#
45-
CLK_R_REQG#
CLK_R_PCIE_NEWCARD
CLK_R_PCIE_NEWCARD#
45-
CLK_R_PCIE_MINI2
45-
CLK_R_PCIE_MINI2#
39-
CLK_R3S_KBPCI
33-
CLK_R3S_ICHPCI
20-
CLK_R_PEG_MCH
20-
CLK_R_PEG_MCH#
32-
CLK_R_PCIE_ICH
32-
CLK_R_PCIE_ICH#
31-
CLK_R_SATA1
31-
CLK_R_SATA1#
20-
SSCLK1_R_DREF
20-
SSCLK1_R_DREF#
20-
CLK_R_DREF
20-
CLK_R_DREF#
+V3S +V3S
27_Selet =0
LCD_SST 100MHZ
27_Selet =1
27MHZ non-spread clock
CLK_R3S_KBC14
CLK_R3S_ICH14
DOC. NUMBER
OF
15 48
REV
AX1 Model_No