How it Works
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5310M
User Manual
26 pgs1.75 Mb0
User Manual [fr]
110 pgs3.51 Mb0
Schematics
45 pgs1.07 Mb0

HP 5310M Schematics

A
1 1
B
C
D
E
Compal confidential
Schematics Document
Mobile Penryn uFCPGA with Intel
2 2
Cantiga_GM+ICH9-M SFF core logic
Fossil
2009-02-03
3 3
4 4
Secur ity Classification
Issued Date
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
LA-5221P
E
1 45Tues day, February 03, 2009
0.1
A
Compal confidential
File Name : LA-5221P
B
C
D
E
Fossil
Thermal Se nsor
1 1
EMC 1 402
Mobile Penym
LV/ULV Dual Core
uFCPGA-956 CPU - SFF
page 4
page 4,5,6,7
CK505
Clock Generator ICS9LPRS397
page 15
Accelerometer
LI S30 2DLTR
page 25
Fan C onn
page 4
Display Port
page 16
LC D conn
page 17
2 2
WWAN Card
USB x1
page 25
USB2.0
H_ A#( 3.. 35) H_ D#( 0..6 3)
Intel Cantiga GS
FCBGA 1363 - SFF
page 8,9,10,11,12,13
FSB
667/800/10 66MHz 1 .05V
DM I X4
DDR3 800MHz 1.5V
Singal Channel
DD R3-SO-DIMM X 1
BANK 0 , 1, 2, 3
BT(SoftBreeze) Conn USB x 1
page 14
page 30
USB conn x 1(For I/O)
PCI-E BUS
Intel ICH9-M
WB MMAP-569 - SFF
page 19,20,21,22
10/100/1 000 LAN
Marvelle 88E8072
page 23
WLAN Card
PCIE x1
page 26
USB2.0
CardReader Controller
RealT e k RTS5159
SPI
24HST 104 1A-3
3 3
RJ45 CONN
LED
page 18
page 24
SD/MM C Slot
LPC BUS
SPI ROM
MXIC/MX25L1605AM2C-12G SO8 (2MB)
or
WINBOND/W25X16-VSSIG(2MB)
USB2.0
Azalia
SATA0
page 31
page 30
USB conn x 2(For I/O)
page 28
USB x1(Camara)
page 17
Audio CKT
92HD75B2
2.5" SAT A HDD Connector
NAND F lash module(SSD)
page 27
OR
page 20
daughter board
TPA6047
AMP & Audio Jack
page 28
RTC CKT.
page 20
daughter board
SMSC KBC 1091
page 32
Power OK CKT.
page 33
4 4
Power On/Off CKT.
page 34
DC/DC Interface CKT.
page 34
A
B
Touch Pad CONN.
Secur ity Classification
Issued Date
Int.KBD
C
page 29page 29
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
LA-5221P
E
2 45Tues day, February 03, 2009
0.1
A
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
1 1
( O MEANS ON X MEANS OFF )
+B
+3VL
power plane
O
O
O
O
O
X
+5VALW
+3VALW
+1.8V
O
O
O
O
X
O
X X
X
X X X
+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
OO
OO
X
X
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build CONN@ : means ME part. 45@ : means install after SMT.
ULV723@ mean CPU ULV723 (U1) for L01
SU9300@ mean CPU SU9300 (U1) for L02
ZZZ 1
PCB-MB
U1
CPU
SU9300@
I2C / SMBUS ADDRESSING
DE VI CE
DD R S O- DI MM 0
CL OCK GENE RATO R (E XT .)
HEX AD DR ES S
A 0
D2
1 0 1 0 0 0 0 0
1 1 0 1 0 0 1 0
SMBUS Control Table
SOURCE
SMB_EC_CK1 SMB_EC_DA1
SMB_EC_CK2 SMB_EC_DA2
SMB_CK_CLK1 SMB_CK_DAT1 ICH9
LCD_CLK LCD_DAT
Secur ity Classification
Issued Date
A
2005/03/10 2006/03/10
KB926
KB926
Can tig a
Compal Secret Data
Deciphered Date
INVERTER BATT EEPROM
X
V V
X
X X
X
X
X X
SERIAL
X
X X
THERMAL SENSOR (CPU)
SODIMM CLK CHIP
X X
V
X
X
V V V
X X
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Notes List
LA-5221P
X X
MINI CARD
X X X
X
3 45Tues day, February 03, 2009
LCD
X
X
V
0.1
5
4
3
2
1
XDP Connector
XDP_TDI
TP16PAD
0_0603_5% R892
C3
1 2
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK
XDP_DBRESET#
0.1U_0402_10V6K@
1 2 3
R8 1K_0402_5%
XDP_BPM#4
XDP_BPM#3 XDP_BPM#2
XDP_BPM#1 XDP_BPM#0
TP15PAD
H_PW RGOOD_R
12
FAN_PWM_R
12
R890 3K_0402_5%
+3VS
R896 10K_0402_5%
1 2
1
2
+3VS
+3VS
5
U50
P
INB
O
INA
G
TC7SH00FU_ SSOP5
3
TP21PAD
XDP_PRE#
12/ 22 Fol low consum er des ign
+5VS
4
12
R891 2.2K_0402_5%
for R F, HP 12/10
12
TP10PAD
TP11PAD TP12PAD
TP13PAD
D D
H_A#[ 3..16]<8>
H_ADSTB#0<8>
H_A#[ 17..35]<8>
C C
H_ADSTB#1<8>
H_FER R#<20>
B B
12/22 HP review Rem ove te st point
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
H_REQ#0<8> H_REQ#1<8> H_REQ#2<8>
H_REQ#4<8>
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A20M#<20>
H_IGNN E#<20>
H_STPCLK#<20> H_INT R<20>
H_NMI<20> H_SMI#<20>
U1A
P2
A[3]#
V4
A[4]#
W1
A[5]#
T4
A[6]#
AA1
A[7]#
AB4
A[8]#
T2
A[9]#
AC5
A[10]#
AD2
A[11]#
AD4
A[12]#
AA5
A[13]#
AE5
A[14]#
AB2
A[15]#
AC1
A[16]#
Y4
ADSTB[0]#
R1
REQ[0]#
R5
REQ[1]#
U1
REQ[2]#
P4
REQ[3]#
W5
REQ[4]#
AN1
A[17]#
AK4
A[18]#
AG1
A[19]#
AT4
A[20]#
AK2
A[21]#
AT2
A[22]#
AH2
A[23]#
AF4
A[24]#
AJ5
A[25]#
AH4
A[26]#
AM4
A[27]#
AP4
A[28]#
AR5
A[29]#
AJ1
A[30]#
AL1
A[31]#
AM2
A[32]#
AU5
A[33]#
AP2
A[34]#
AR1
A[35]#
AN5
ADSTB[1]#
C7
A20M#
ICH
D4
FERR#
F10
IGNNE#
F8
STPCLK#
C9
LINT0
C5
LINT1
E5
SMI#
V2
RSVD01
Y2
RSVD02
AG5
RSVD03
AL5
RSVD04
J9
RSVD05
F4
RSVD06
H8
RSVD07
PENR YN SFF_UFC BGA956
ULV723@
ADDR GROUP 0
DEFER#
CONTROL
RESET#
ADDR GR OUP 1
BPM[0]# BPM[1]# BPM[2]# BPM[3]#
XDP /ITP SI GNALS
TH ERMAL
PROCHOT#
THERMDA THERMDC
THERMTRIP#
H CLK
BCLK[0] BCLK[1]
ADS# BNR# BPRI#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]# RS[1]# RS[2]#
TRDY#
HIT#
HITM#
PRDY# PREQ#
TCK
TDO TMS
TRST#
DBR#
TP22 PAD
M4 J5 L5
N5 F38 J1
M2
B40 D8
N1
H_RESET#
G5 K2 H4 K4 L1
H2 F2
XDP_BPM#0
AY8
XDP_BPM#1
BA7
XDP_BPM#2
BA5
XDP_BPM#3
AY2
XDP_BPM#4
AV10
XDP_BPM#5_R
AV2
XDP_TCK
AV4
XDP_TDI
AW7
TDI
XDP_TDO
AU1
XDP_TMS
AW5
XDP_TRST#
AV8
XDP_DBRESET#
J7
H_PROCH OT#
D38 BB34 BD34
H_THERMTRIP#
B10
H_THERMDA, H_THERMDC routing together, Trace width / Sp acing = 10 / 10 mil
A35 C35
RESERVED
Place close to U1.
+VCCP
H_ADS# <8> H_BNR # <8>
H_BPR I# <8>
H_DEF ER# <8>
H_D RDY# <8> H_DB SY# <8>
H_BR0# <8>
H_INIT# <20>
H_LOCK# <8>
H_RS#0 <8> H_RS#1 <8> H_RS#2 <8>
H_TR DY# <8>H_REQ#3<8>
H_HIT# <8> H_HITM# <8>
1 2
R9
1 2
56_0402_5%
R13 0_0402_5%
1 2
XDP_DBRESET# <21>
Place Close to U1.
R14 68_0402_5%
1 2
H_THERMTRIP# <8,20>
CLK_CP U_BCLK <15> CLK_CP U_BCLK# <15>
01/11 HP review Del R1 5 and R16(s hort short net)
02/03 instal l-->@
R10 51_0402_1%
@
XDP_BPM#5
+VCCP
H_THERMDA H_THERMDC
H_PROCH OT#<42>
H_PW RGOOD<5,20>
H_RESET# <8>
H_PROCH OT#
TP14PAD
PWM Fan Control circuit
FAN_PWM<32>
+VCCP
Q21
CBE
123
PMBT3904_SOT23
External Thermal Sensor EMC1402
R1 54.9_0402_1%
R2 54.9_0402_1%
R3 54.9_0402_1%
R4 54.9_0402_1%
R5 54.9_0402_1%@
R6 54.9_0402_1%
R7 54.9_0402_1%
TP17 PAD
TP18 PAD
R12 0_0402_5%
1 2
JP2
1
4
2
G1
5
3
G2
ACES_85204-03001
conn@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
This s hall place n ear CPU
TP19 PAD
R11 1K_0402_5%
1 2
TP20 PAD
+VCCP
CLK_CPU_XDP <15> CLK_CPU_XDP# <15>
H_RESET#H_RESET#_R
2
C4
0.1U_0402_16V4Z
C5 2200P_0402_50V7K
1 2
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
MAINPW ON
H_THERMTRIP#
2006/02/13 2006/03/10
1 2
R18 0_0402_5%@
Compal Secret Data
1
H_THERMDA
H_THERMDC
Deciphered Date
U2
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
Put the sensor colse to CPU
2
SMCLK
SMDATA
ALERT#
GND
8
7
6
5
1 2
R17 10K_0402_5%
Title
Size Doc ument Number Re v
Cus tom
LA-5221P
Date: Sheet of
ICH_SM_CLK <14,15,21,25>
ICH_SM_DA <14,15,21,25>
THERM_SCI# <21>
+3VS
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
1
4 45Tues day, February 03, 2009
0.1
5
4
3
2
1
H_D #[0..15]<8>
D D
H_DSTBN#0<8> H_DSTBP#0<8> H_DIN V#0<8> H_D#[ 16..31]<8>
C C
layo ut n ote : Route TE ST3 & TEST 5 traces o n grou nd r eferenc ed layer t o the TPs
H_DSTBN#1<8> H_DSTBP#1<8> H_DIN V#1<8>
12/17 HP
review
Re move t est point
CPU_BSEL0<15> CPU_BSEL1<15> CPU_BSEL2<15>
H_D#0 H_D#1
H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DIN V#0
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DIN V#1
V_CPU_GTLREF
CPU_BSEL CPU_BSEL2 CPU_BSEL1
B B
166
200
0 1
0
1
U1B
F40
D[0]#
G43
D[1]#
E43
D[2]#
J43
D[3]#
H40
D[4]#
H44
D[5]#
G39
D[6]#
E41
D[7]#
L41
D[8]#
K44
D[9]#
N41
D[10]#
T40
D[11]#
M40
D[12]#
G41
D[13]#
M44
D[14]#
L43
D[15]#
K40
DSTBN[0]#
J41
DSTBP[0]#
P40
DINV[0]#
P44
D[16]#
V40
D[17]#
V44
D[18]#
AB44
D[19]#
R41
D[20]#
W41
D[21]#
N43
D[22]#
U41
D[23]#
AA41
D[24]#
AB40
D[25]#
AD40
D[26]#
AC41
D[27]#
AA43
D[28]#
Y40
D[29]#
Y44
D[30]#
T44
D[31]#
U43
DSTBN[1]#
W43
DSTBP[1]#
R43
DINV[1]#
AW43
GTLREF
E37
TEST1
D40
TEST2
C43
TEST3
AE41
TEST4
AY10
TEST5
AC43
TEST6
A37
BSEL[0]
C37
BSEL[1]
B38
BSEL[2]
PENR YN SFF_UFC BGA956
ULV723@
CPU_BSEL0
1
0
D[32]# D[33]# D[34]#
DAT A GROUP 0
D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#
DAT A GROUP 2DAT A GROUP 3
D[45]# D[46]#
D[47]# DSTBN[2]# DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
DATA GROUP 1
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]# DSTBN[3]# DSTBP[3]#
DINV[3]#
COMP[0]
MI SC
COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP# PSI#
Cause CPU core power change to 1 phas e, and not need support the pi n, leave it as TP. 10/02
H_D#33
AR43
H_D#34H_D#2
AH40
H_D#35
AF40
H_D#36
AJ43
H_D#37
AG41
H_D#38
AF44
H_D#39
AH44
H_D#40
AM44
H_D#41
AN43
H_D#42
AM40
H_D#43
AK40
H_D#44
AG43
H_D#45
AP40
H_D#46
AN41
H_D#47
AL41
H_DSTBN#2
AK44
H_DSTBP#2
AL43
H_DIN V#2
AJ41
H_D#48
AV38
H_D#49
AT44
H_D#50
AV40
H_D#51
AU41
H_D#52
AW41
H_D#53
AR41
H_D#54
BA37
H_D#55
BB38
H_D#56
AY36
H_D#57
AT40
H_D#58
BC35
H_D#59
BC39
H_D#60
BA41
H_D#61
BB40
H_D#62
BA35
H_D#63
AU43
H_DSTBN#3
AY40
H_DSTBP#3
AY38
H_DIN V#3
BC37
COMP0
AE43
COMP1
AD44
COMP2
AE1
COMP3
AF2
G7 B8 C41 E7 D10 BD10
12/22 HP review Rem ove te st point
H_D#32
AP44
H_DPRSTP# <8,20,42>
H_DPSLP# <20> H_DPW R# <8> H_PW RGOOD <4,20>
H_CPUSLP # <8>
H_D# [32..47] <8>
H_DSTBN#2 <8> H_DSTBP#2 <8> H_DIN V#2 <8> H_D# [48..63] <8>
H_DSTBN#3 <8> H_DSTBP#3 <8> H_DIN V#3 <8>
R21
R22
R19
R20
12
12
12
12
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
Resistor placed within
0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
266 0 0 0
+VCC_ CORE +VCC_ CORE
U1C
F32
VCC[001]
G33
VCC[002]
H32
VCC[003]
J33
VCC[004]
K32
VCC[005]
L33
VCC[006]
M32
VCC[007]
N33
VCC[008]
P32
VCC[009]
R33
VCC[010]
T32
VCC[011]
U33
VCC[012]
V32
VCC[013]
W33
VCC[014]
Y32
VCC[015]
AA33
VCC[016]
AB32
VCC[017]
AC33
VCC[018]
AD32
VCC[019]
AE33
VCC[020]
AF32
VCC[021]
AG33
VCC[022]
AH32
VCC[023]
AJ33
VCC[024]
AK32
VCC[025]
AL33
VCC[026]
AM32
VCC[027]
AN33
VCC[028]
AP32
VCC[029]
AR33
VCC[030]
AT34
VCC[031]
AT32
VCC[032]
AU33
VCC[033]
AV32
VCC[034]
AY32
VCC[035]
BB32
VCC[036]
BD32
VCC[037]
B28
VCC[038]
B30
VCC[039]
B26
VCC[040]
D28
VCC[041]
D30
VCC[042]
F30
VCC[043]
F28
VCC[044]
H30
VCC[045]
H28
VCC[046]
D26
VCC[047]
F26
VCC[048]
H26
VCC[049]
K30
VCC[050]
K28
VCC[051]
M30
VCC[052]
M28
VCC[053]
K26
VCC[054]
M26
VCC[055]
P30
VCC[056]
P28
VCC[057]
T30
VCC[058]
T28
VCC[059]
V30
VCC[060]
V28
VCC[061]
P26
VCC[062]
T26
VCC[063]
V26
VCC[064]
Y30
VCC[065]
Y28
VCC[066]
AB30
VCC[067]
PENR YN SFF_UFC BGA956
ULV723@
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016
VCCA[01] VCCA[02]
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
VCCSENSE
VSSSENSE
AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30
J11 E11 G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37
B34 D34
BD8 BC7 BB10 BB8 BC5 BB4 AY4
VCCSENS E
BD12
VSSSENSE
BC13
Length match within 25 mils. The trace width/space/other is 20/7/25.
12/22 HP review Rem ove 0 oh m
+VCCP
1
+
C6
330U_D2E_2.5VM_R9
2
CPU_V ID0 <42> CPU_V ID1 <42> CPU_V ID2 <42> CPU_V ID3 <42> CPU_V ID4 <42> CPU_V ID5 <42> CPU_V ID6 <42>
VCCSENS E <42>
VSSSENSE <42>
1
C7
2
10U_0805_6.3V6M
0.01U_0402_16V7K
Near pin B34
Change to 330u_R9, casue high limitation. 12/14
+1.5VS
1
C8
Near pin D34
2
+VCC_ CORE
R23
+VCCP
12
R25 1K_0402_1%
V_CPU_GTLREF
A A
12
R26 2K_0402_1%
1 2
100_0402_1%
R24
1 2
100_0402_1%
Close to CPU pin within 500mils.
VCCSENS E
VSSSENSE
Close to CPU pin AW43 within 500mils.
5
4
Secur ity Classification
Issued Date
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
LA-5221P
1
5 45Tues day, February 03, 2009
0.1
5
D D
AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
C C
VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
ULV723@
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
F24
F22
B22
B24
BB26
BD28
BD26
K24
D22
D24
H24
H22
VCCP_039
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
T24
T22
K22
P24
P22
V24
M24
M22
AJ35
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
V22
Y24
Y22
AB24
AB22
AD24
AD22
4
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
F18
F16
B16
B18
B20
AF24
AF22
AH24
AH22
AT24
AK24
AT22
AK22
AP24
AP22
AV24
AV22
AY24
AY22
AM24
AM22
BB24
D16
BB22
BD24
BD22
F20
K18
D18
K16
H18
H16
D20
H20
3
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC_182
VCC_183
VCC_184
VCC_185
VCC_186
VCC_187
VCC_188
VCC_189
VCC_190
VCC_191
VCC_192
VCC_193
VCC_194
VCC_195
T18
T16
K20
P18
M18
M16
M20
T20
P16
V18
V16
P20
V20
Y18
Y16
Y20
AF18
AF16
AB18
AB16
AD18
AD16
AF20
AB20
AD20
AK18
AK16
AP18
AP16
AH18
AH16
AH20
AK20
AM18
AM16
2
AU11
VCCP_116
VCCP_117
VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128
VCC_196
VCC_197
VCC_198
VCC_199
VCC_200
VCC_201
VCC_202
AT18
AT16
AP20
AV18
AV16
AY18
AM20
1
+VCCP
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13
U1F PENR YN SFF_UFC BGA956
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145
VCC_203
VCC_204
VCC_205
VCC_206
VCC_207
VCC_208
VCC_209
VCC_210
VCC_211
VCC_212
VCC_213
VCC_214
VCC_215
VCC_216
VCC_217
VCC_218
VCC_219
VCC_220
VCCP_020
VCCP_018
VCCP_019
VCCP_017
AT20
AY16
AV20
AY20
BB18
BB16
AT14
BB20
AP14
BD18
AV14
BD16
BD20
AM14
AJ37
AF38
AY14
BB14
AK38
BD14
AG37
+VCC_C ORE +VCCP
B B
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
Penryn(3/3)-Power
LA-5221P
1
6 45Tues day, February 03, 2009
0.1
5
U1D
B42
VSS[001]
F44
VSS[002]
D44
VSS[003]
D42
VSS[004]
F42
VSS[005]
H42
VSS[006]
K42
VSS[007]
M42
VSS[008]
P42
VSS[009]
T42
VSS[010]
V42
VSS[011]
Y42
D D
C C
B B
A A
VSS[012]
AB42
VSS[013]
AD42
VSS[014]
AF42
VSS[015]
AH42
VSS[016]
AK42
VSS[017]
AM42
VSS[018]
AP42
VSS[019]
AY44
VSS[020]
AV44
VSS[021]
AT42
VSS[022]
AV42
VSS[023]
AY42
VSS[024]
BA43
VSS[025]
BB42
VSS[026]
C39
VSS[027]
E39
VSS[028]
G37
VSS[029]
H38
VSS[030]
J39
VSS[031]
L39
VSS[032]
M38
VSS[033]
N39
VSS[034]
R39
VSS[035]
T38
VSS[036]
U39
VSS[037]
W39
VSS[038]
Y38
VSS[039]
AA39
VSS[040]
AC39
VSS[041]
AD38
VSS[042]
AE39
VSS[043]
AG39
VSS[044]
AH38
VSS[045]
AJ39
VSS[046]
AL39
VSS[047]
AM38
VSS[048]
AN39
VSS[049]
AR39
VSS[050]
AR37
VSS[051]
AT38
VSS[052]
AU39
VSS[053]
AU37
VSS[054]
AW39
VSS[055]
AW37
VSS[056]
BA39
VSS[057]
BC41
VSS[058]
BD40
VSS[059]
BD38
VSS[060]
B36
VSS[061]
H34
VSS[062]
D36
VSS[063]
K34
VSS[064]
M34
VSS[065]
M36
VSS[066]
P34
VSS[067]
T34
VSS[068]
V34
VSS[069]
T36
VSS[070]
Y34
VSS[071]
AB34
VSS[072]
AD34
VSS[073]
Y36
VSS[074]
AD36
VSS[075]
AF34
VSS[076]
AH34
VSS[077]
AH36
VSS[078]
AK34
VSS[079]
AM34
VSS[080]
AP34
VSS[081]
PENR YN SFF_UFC BGA956
ULV723@
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
5
AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21
U1E
G25
VSS_164
G23
VSS_165
G21
VSS_166
J25
VSS_167
J23
VSS_168
J21
VSS_169
L25
VSS_170
L23
VSS_171
L21
VSS_172
N25
VSS_173
N23
VSS_174
N21
VSS_175
R25
VSS_176
R23
VSS_177
R21
VSS_178
U25
VSS_179
U23
VSS_180
U21
VSS_181
W25
VSS_182
W23
VSS_183
W21
VSS_184
AA25
VSS_185
AA23
VSS_186
AA21
VSS_187
AC25
VSS_188
AC23
VSS_189
AC21
VSS_190
AE25
VSS_191
AE23
VSS_192
AE21
VSS_193
AG25
VSS_194
AG23
VSS_195
AG21
VSS_196
AJ25
VSS_197
AJ23
VSS_198
AJ21
VSS_199
AL25
VSS_200
AL23
VSS_201
AL21
VSS_202
AN25
VSS_203
AN23
VSS_204
AN21
VSS_205
AR25
VSS_206
AR23
VSS_207
AR21
VSS_208
AU25
VSS_209
AU23
VSS_210
AU21
VSS_211
AW25
VSS_212
AW23
VSS_213
AW21
VSS_214
BA25
VSS_215
BA23
VSS_216
BA21
VSS_217
BC25
VSS_218
BC23
VSS_219
BC21
VSS_220
C17
VSS_221
C19
VSS_222
E19
VSS_223
E17
VSS_224
G19
VSS_225
G17
VSS_226
J19
VSS_227
J17
VSS_228
L19
VSS_229
L17
VSS_230
N19
VSS_231
N17
VSS_232
R19
VSS_233
R17
VSS_234
U19
VSS_235
U17
VSS_236
W19
VSS_237
W17
VSS_238
AA19
VSS_239
AA17
VSS_240
AC19
VSS_241
AC17
VSS_242
AE19
VSS_243
AE17
VSS_244
AG19
VSS_245
AG17
VSS_246
AJ19
VSS_247
AJ17
VSS_248
AL19
VSS_249
AL17
VSS_250
AN19
VSS_251
AN17
VSS_252
AR19
VSS_253
AR17
VSS_254
AU19
VSS_255
AU17
VSS_256
AW19
VSS_257
AW17
VSS_258
BA19
VSS_259
BA17
VSS_260
BC19
VSS_261
BC17
VSS_262
C11
VSS_263
C15
VSS_264
E15
VSS_265
G15
VSS_266
H10
VSS_267
M12
VSS_268
J15
VSS_269
L15
VSS_270
N15
VSS_271
M10
VSS_272
T12
VSS_273
R15
VSS_274
U15
VSS_275
W15
VSS_276
T10
VSS_277
Y12
VSS_278
AD12
VSS_279
PENR YN SFF_UFC BGA956
ULV723@
VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395
AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4
4
+VCC_C ORE
10U_0805_6.3V6M
1
C9
2
+VCC_C ORE
1U_0402_6.3V6K
1
C33
2
Mid Frequence Decoupling
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C11
C10
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C35
C34
2
2
3
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C13
C12
2
High Frequence Decoupling
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C37
C36
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C15
C14
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C38
C39
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
1
2
1
1
C17
C16
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C41
C40
2
2
2
10U_0805_6.3V6M
C18
1U_0402_6.3V6K
C42
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C19
2
1U_0402_6.3V6K
1
C43
2
10U_0805_6.3V6M
1
1
C20
C21
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C44
C45
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C23
C22
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C46
2
C47
2
10U_0603_6.3V6M
1
1
C24
C25
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C48
C49
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C26
2
1U_0402_6.3V6K
1
C50
2
10U_0603_6.3V6M
1
1
2
1
2
1
C27
C28
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C51
C52
2
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C30
C29
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C54
C53
2
10U_0603_6.3V6M
1
1
2
1
2
1
C31
C32
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C56
C55
2
2
6/14 : Replac e 12pc s 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.
ESR <= 1.5m ohm
Near CPU CORE regulator
+VCC_ CORE
220U_D2_2VK_R 9
1
1
+
+
C58
C57
2
2
Del C3 7 to improve power plan. 6/14
+VCCP
1U_0603_10V4Z
1U_0603_10V4Z
1
C60
C61
2
Secur ity Classification
Issued Date
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
1U_0603_10V4Z
1
1
C62
2
2
Compal Secret Data
1U_0603_10V4Z
1U_0603_10V4Z
1
1
C63
C64
2
2
Deciphered Date
1U_0603_10V4Z
C65
220U_D2_2VK_R 9
220U_D2_2VK_R 9
1
+
C59
2
1U_0603_10V4Z
1
C66
2
1U_0603_10V4Z
1
C67
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1
1
C68
C69
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1
2
1
1
C71
C70
2
2
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Penryn(3/3)-GND/Bypass
LA-5221P
1
7 45Tues day, February 03, 2009
0.1
5
H_D #[0..63]<5>
D D
C C
H_RESET#<4>
H_CPUSLP #<5>
B B
layo ut note:
Rout e H_ SCO MP and H_S COMP# with trace wid th, spac ing and impedan ce (55 ohm ) same as FSB data traces
Layout Note: H_RC OMP / H_VREF / H_SWNG
tra ce w idth and s pacing is 10/20
+VCCP
12
R44
1K_0402_1%
12
A A
R482K_0402_1%
with in 100 mils from NB
Trace < = 500mils
H_VRE F
1
C79
2
0.1U_0402_16V4Z
@
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_SW NG H_RCOMP
H_VRE F
H_RCOMP
12
R49
24.9_0402_1%
5
U4A
J7
H_D#_0
H6
H_D#_1
L11
H_D#_2
J3
H_D#_3
H4
H_D#_4
G3
H_D#_5
K10
H_D#_6
K12
H_D#_7
L1
H_D#_8
M10
H_D#_9
M6
H_D#_10
N11
H_D#_11
L7
H_D#_12
K6
H_D#_13
M4
H_D#_14
K4
H_D#_15
P6
H_D#_16
W9
H_D#_17
V6
H_D#_18
V2
H_D#_19
P10
H_D#_20
W7
H_D#_21
N9
H_D#_22
P4
H_D#_23
U9
H_D#_24
V4
H_D#_25
U1
H_D#_26
W3
H_D#_27
V10
H_D#_28
U7
H_D#_29
W11
H_D#_30
U11
H_D#_31
AC11
H_D#_32
AC9
H_D#_33
Y4
H_D#_34
Y10
H_D#_35
AB6
H_D#_36
AA9
H_D#_37
AB10
H_D#_38
AA1
H_D#_39
AC3
H_D#_40
AC7
H_D#_41
AD12
H_D#_42
AB4
H_D#_43
Y6
H_D#_44
AD10
H_D#_45
AA11
H_D#_46
AB2
H_D#_47
AD4
H_D#_48
AE7
H_D#_49
AD2
H_D#_50
AD6
H_D#_51
AE3
H_D#_52
AG9
H_D#_53
AG7
H_D#_54
AE11
H_D#_55
AK6
H_D#_56
AF6
H_D#_57
AJ9
H_D#_58
AH6
H_D#_59
AF12
H_D#_60
AH4
H_D#_61
AJ7
H_D#_62
AE9
H_D#_63
B6
H_SWING
D4
H_RCOMP
J11
H_CPURST#
G9
H_CPUSLP#
L17
H_AVREF
K18
H_DVREF
CANTI GA GMCH S FF_FCBGA1363
+VCCP
12
R45
221_0603_1%
12
R50
100_0402_1%
H_SW NG
1
C80
2
0.1U_0402_16V4Z
Near B6 pin
H_ADSTB#_0 H_ADSTB#_1
H_BREQ#
H_DEFER#
HOST
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
layo ut note:
Plac e th em close to U4 pin BC51.
Layout Note : V_DDR_MCH_REF trace width and s pacing is 20/20.
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8
H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_DBSY#
H_HIT#
H_HITM#
H_LOCK# H_TRDY#
H_RS#_0 H_RS#_1 H_RS#_2
4
H_A#3
L15
H_A#4
B14
H_A#5
C15
H_A#6
D12
H_A#7
F14
H_A#8
G17
H_A#9
B12
H_A#10
J15
H_A#11
D16
H_A#12
C17
H_A#13
D14
H_A#14
K16
H_A#15
F16
H_A#16
B16
H_A#17
C21
H_A#18
D18
H_A#19
J19
H_A#20
J21
H_A#21
B18
H_A#22
D22
H_A#23
G19
H_A#24
J17
H_A#25
L21
H_A#26
L19
H_A#27
G21
H_A#28
D20
H_A#29
K22
H_A#30
F18
H_A#31
K20
H_A#32
F20
H_A#33
F22
H_A#34
B20
H_A#35
A19
F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8
L9 N7 AA7 AG3
K2 N3 AA3 AF4
L3 M2 Y2 AF2
J13 L13 C13 G13 G15
F4 F2 G7
01/05 HP review Del PM_EXT TS#0 and contact J39 L39
V_DDR _MCH_REF<14>
PM_EXTTS#0
R52 10K_0402_5%
4
V_DDR _MCH_REF
1 2
H_A#[ 3..35] <4>
H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR # <4> H_BPR I# <4> H_BR0# <4> H_DEF ER# <4> H_D BSY# <4> CLK_MCH_BCLK <15> CLK_MCH_BCLK# <15> H_DPW R# <5> H_D RDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_T RDY# <4>
H_DIN V#0 <5> H_DIN V#1 <5> H_DIN V#2 <5> H_DIN V#3 <5>
H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>
H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>
H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>
H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>
H_THERMTRIP#<4,20>
PM_DPRSLPVR<21,42>
02/02 DDR3 power
C78
1
2
0.1U_0402_16V4Z
+3VS
3
TCK TDI TDO TMS
+3VS
R28
1 2
R27
1 2
R29 4.7K_0402_5%@
1 2
R30 1K_0402_5% @
1 2
1K_0402_5% @
4.7K_0402_5%@
Close to U4
02/02 DDR3 power
+1.5V
1
1
C73
0.01U_0402_25V7K
2
1
C75
2
0.01U_0402_25V7K
MCH_CLKSEL0<15> MCH_CLKSEL1<15> MCH_CLKSEL2<15>
3
12
R31 1K_0402_1%
12
R34
3.01K_0402_1%
12
R37 1K_0402_1%
CFG20<10>
PM_EXTTS#0
R38 0_0402_5%
1 2
R39 100_0402_1%
1 2
C760.1U_0402_16V4Z @
1
2
2006/02/13 2006/03/10
C72
2.2U_0 603_6.3V4Z
2
SMRCOMP_VOH
SMRCOMP_VOL
1
C74
2
2.2U_0 603_6.3V4Z
12/29 HP review Rem ove so me CFG net
PM_BMBUSY#<21>
H_DPRSTP#<5,20,42>
PM_EXTTS#0<14>
PM_PWROK<21,32,42> PLT_RST#<19,23,25,31>
1 2
R40 0_0402_5%
Add R428 in 9/26
+1.5V
12
R43 10K_0402_1%
12
R46 10K_0402_1%
Secur ity Classification
Issued Date
U4B
J43
RSVD1
L43
RSVD2
J41
RSVD3
L41
RSVD4
AN11
RSVD5
AM10
RSVD6
AK10
RSVD7
AL11
RSVD8
F12
RSVD9
AN45
RSVD10
AP44
RSVD11
AT44
RSVD12
AN47
RSVD13
C27
RSVD14
D30
RSVD15
J9
RSVD17
AW42
RSVD20
BB20
RSVD22
BE19
RSVD23
BF20
RSVD24
BF18
RSVD25
K26
CFG_0
G23
CFG_1
G25
CFG_2
J25
CFG_3
L25
CFG_4
L27
CFG_5
F24
CFG_6
D24
CFG_7
D26
CFG_8
J23
CFG_9
B26
CFG_10
A23
CFG_11
C23
CFG_12
B24
CFG_13
B22
CFG_14
K24
CFG_15
C25
CFG_16
L23
CFG_17
L33
CFG_18
K32
CFG_19
K34
CFG_20
J35
PM_SYNC#
F6
PM_DPRSTP#
J39
PM_EXT_TS#_0
L39
PM_EXT_TS#_1
AY39
PWROK
BB18
RSTIN#
K28
THERMTRIP#
K36
DPRSLPVR
A7
NC_1
A49
NC_2
A52
NC_3
A54
NC_4
B54
NC_5
D55
NC_6
G55
NC_7
BE55
NC_8
BH55
NC_9
BK55
NC_10
BK54
NC_11
BL54
NC_12
BL52
NC_13
BL49
NC_14
BL7
NC_15
BL4
NC_16
BL2
NC_17
BK2
NC_18
BK1
NC_19
BH1
NC_20
BE1
NC_21
G1
NC_22
Compal Secret Data
CANTI GA GMCH S FF_FCBGA1363
Deciphered Date
CFGRSVD
PM
NC
2
CLK
DMI
GRA PHICS VID
ME
MISC
2
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
HDA
1
BB32 BA25 BA33 BA23
BA31 BC25 BC33 BB24
BC35 BE33 BE37 BC37
BK18 BK16 BE23 BC19
BJ17 BJ19 BC17 BE17
SMRCOMP
BL25
SMRCOMP#
BK26
SMRCOMP_VOH
BK32
SMRCOMP_VOL
BL31
V_DDR _MCH_REF
BC51
SM_PWROK
AY37
SM_REXT
BH20
SM_DRAMRST#
BA37
B42 D42 B50 D50
R49 P50
AG55 AL49 AH54 AL47
AG53 AK50 AH52 AL45
AG49 AJ49 AJ47 AG47
AF50 AH50 AJ45 AG45
G33 G37 F38 F36 G35
G39
AK52 AK54 AW40 AL53
CL_VRE F
AL55
F34 F32 B38 A37 C31 K42
TSATN#
D10
C29 B30 D28 A27 B28
R47 54.9_0402_1%
Title
Cantiga(1/6)-AGTL/DMI/DDR
Size Doc ument Number Re v
Cus tom
LA-5221P
Date: Sheet of
M_CLK_DD R0 <14> M_CLK_DD R1 <14>
M_CLK_DD R#0 <14> M_CLK_DD R#1 <14>
DDR_CKE 0_DIMMA <14> DDR_CKE 1_DIMMA <14>
DDR_CS0_D IMMA# <14> DDR_CS1_D IMMA# <14>
M_ODT0 <14> M_ODT1 <14>
R32 80.6_0402_1%
1 2
R33 80.6_0402_1%
1 2
R35 10K_0402_1%
1 2
R36 499_0402_1%
1 2
CLK_M CH_DREFCLK <15> CLK_M CH_DREFCLK# <15> MCH_ SSCDREFCLK <15> MCH_ SSCDREFCLK# <15>
CLK_MCH_3GPLL <15> CLK_MCH_3GPLL# <15>
DMI_TXN0 <21> DMI_TXN1 <21> DMI_TXN2 <21> DMI_TXN3 <21>
DMI_TXP0 <21> DMI_TXP1 <21> DMI_TXP2 <21> DMI_TXP3 <21>
DMI_RXN0 <21> DMI_RXN1 <21> DMI_RXN2 <21> DMI_RXN3 <21>
DMI_RXP0 <21> DMI_RXP1 <21> DMI_RXP2 <21> DMI_RXP3 <21>
DFGT_ VID_0 <44> DFGT_ VID_1 <44> DFGT_ VID_2 <44> DFGT_ VID_3 <44> DFGT_ VID_4 <44>
GFXVR_EN <44>
1 2
SM_DRAMRST# <14>
CL_CLK0 <21> CL_DATA0 <21> PM_PWROK <21,32,42> CL_RST# <21>
0.1U_0402_16V4Z
CLKREQ#_B <15> MCH _ICH_SYNC # <21>
12/12 HP review +1.05V M-->+VCCP
1
C77
2
02/02 DDR3 power
+1.5V
+VCCP
12
R41 1K_0402_1%
12
R42 511_0402_1%
+VCCP
Compal Electronics, Inc.
8 45Tues day, February 03, 2009
1
0.1
5
D D
DDR_ A_D[0..63 ]<14>
C C
B B
DDR_A _D0 DDR_A _D1 DDR_A _D2 DDR_A _D3 DDR_A _D4 DDR_A _D5 DDR_A _D6 DDR_A _D7 DDR_A _D8 DDR_A _D9 DDR_A _D10 DDR_A _D11 DDR_A _D12 DDR_A _D13 DDR_A _D14 DDR_A _D15 DDR_A _D16 DDR_A _D17 DDR_A _D18 DDR_A _D19 DDR_A _D20 DDR_A _D21 DDR_A _D22 DDR_A _D23 DDR_A _D24 DDR_A _D25 DDR_A _D26 DDR_A _D27 DDR_A _D28 DDR_A _D29 DDR_A _D30 DDR_A _D31 DDR_A _D32 DDR_A _D33 DDR_A _D34 DDR_A _D35 DDR_A _D36 DDR_A _D37 DDR_A _D38 DDR_A _D39 DDR_A _D40 DDR_A _D41 DDR_A _D42 DDR_A _D43 DDR_A _D44 DDR_A _D45 DDR_A _D46 DDR_A _D47 DDR_A _D48 DDR_A _D49 DDR_A _D50 DDR_A _D51 DDR_A _D52 DDR_A _D53 DDR_A _D54 DDR_A _D55 DDR_A _D56 DDR_A _D57 DDR_A _D58 DDR_A _D59 DDR_A _D60 DDR_A _D61 DDR_A _D62 DDR_A _D63
U4D
AP46
SA_DQ_0
AU47
SA_DQ_1
AT46
SA_DQ_2
AU49
SA_DQ_3
AR45
SA_DQ_4
AN49
SA_DQ_5
AV50
SA_DQ_6
AP50
SA_DQ_7
AW47
SA_DQ_8
BD50
SA_DQ_9
AW49
SA_DQ_10
BA49
SA_DQ_11
BC49
SA_DQ_12
AV46
SA_DQ_13
BA47
SA_DQ_14
AY50
SA_DQ_15
BF46
SA_DQ_16
BC47
SA_DQ_17
BF50
SA_DQ_18
BF48
SA_DQ_19
BC43
SA_DQ_20
BE49
SA_DQ_21
BA43
SA_DQ_22
BE47
SA_DQ_23
BF42
SA_DQ_24
BC39
SA_DQ_25
BF44
SA_DQ_26
BF40
SA_DQ_27
BB40
SA_DQ_28
BE43
SA_DQ_29
BF38
SA_DQ_30
BE41
SA_DQ_31
BA15
SA_DQ_32
BE11
SA_DQ_33
BE15
SA_DQ_34
BF14
SA_DQ_35
BB14
SA_DQ_36
BC15
SA_DQ_37
BE13
SA_DQ_38
BF16
SA_DQ_39
BF10
SA_DQ_40
BC11
SA_DQ_41
BF8
SA_DQ_42
BG7
SA_DQ_43
BC7
SA_DQ_44
BC9
SA_DQ_45
BD6
SA_DQ_46
BF12
SA_DQ_47
AV6
SA_DQ_48
BB6
SA_DQ_49
AW7
SA_DQ_50
AY6
SA_DQ_51
AT10
SA_DQ_52
AW11
SA_DQ_53
AU11
SA_DQ_54
AW9
SA_DQ_55
AR11
SA_DQ_56
AT6
SA_DQ_57
AP6
SA_DQ_58
AL7
SA_DQ_59
AR7
SA_DQ_60
AT12
SA_DQ_61
AM6
SA_DQ_62
AU7
SA_DQ_63
CANTI GA GMCH S FF_FCBGA1363
DDR SYSTEM MEMORY A
SA_BS_0 SA_BS_1 SA_BS_2
SA_RAS# SA_CAS#
SA_WE#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8
SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
4
BC21 BJ21 BJ41
BH22 BK20 BL15
AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9
AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9
BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25
DDR_A_DM 0 DDR_A_DM 1 DDR_A_DM 2 DDR_A_DM 3 DDR_A_DM 4 DDR_A_DM 5 DDR_A_DM 6 DDR_A_DM 7
DDR_A _DQS0 DDR_A _DQS1 DDR_A _DQS2 DDR_A _DQS3 DDR_A _DQS4 DDR_A _DQS5 DDR_A _DQS6 DDR_A _DQS7 DDR_A _DQS#0 DDR_A _DQS#1 DDR_A _DQS#2 DDR_A _DQS#3 DDR_A _DQS#4 DDR_A _DQS#5 DDR_A _DQS#6 DDR_A _DQS#7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_BS 0 <14> DDR_A_BS 1 <14> DDR_A_BS 2 <14>
DDR_A _RAS# <14> DDR_A _CAS# <14>
DDR_A_W E# <14>
DDR_A _DM[0..7] <14>
DDR_ A_DQS[0.. 7] <14>
DDR_A _DQS#[0.. 7] <14>
DDR_A _MA[0..14] <14>
3
U4E
AP54 AM52 AR55
AV54 AM54 AN53
AT52 AU53 AW53
AY52
BB52 BC53
AV52 AW55 BD52 BC55
BF54
BE51 BH48
BK48
BE53 BH52
BK46
BJ47
BL45
BJ45
BL41 BH44 BH46
BK44
BK40
BJ39
BK10 BH10
BK6 BH6
BJ9
BL11
BG5
BJ5 BG3 BF4 BD4 BA3 BE5 BF2 BB4 AY4 BA1 AP2 AU1 AT2 AT4 AV4 AU3 AR3 AN1 AP4
AL3
AJ1 AK4 AM4 AH2 AK2
CANTI GA GMCH S FF_FCBGA1363
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
2
BJ13
SB_BS_0
BK12
SB_BS_1
BK38
SB_BS_2
BE21
SB_RAS#
BH14
SB_CAS#
BK14
SB_WE#
AP52
SB_DM_0
AY54
SB_DM_1
BJ49
SB_DM_2
BJ43
SB_DM_3
BH12
SB_DM_4
BD2
SB_DM_5
AY2
SB_DM_6
AJ3
SB_DM_7
AR53
SB_DQS_0
BA53
SB_DQS_1
BH50
SB_DQS_2
BK42
SB_DQS_3
BH8
SB_DQS_4
BB2
SB_DQS_5
AV2
SB_DQS_6
AM2
SB_DQS_7
AT54
SB_DQS#_0
BB54
SB_DQS#_1
BJ51
SB_DQS#_2
BH42
SB_DQS#_3
BK8
SB_DQS#_4
BC3
SB_DQS#_5
AW3
SB_DQS#_6
AN3
SB_DQS#_7
BJ15
SB_MA_0
BJ33
SB_MA_1
BH24
SB_MA_2
BA17
SB_MA_3
BF36
SB_MA_4
BH36
SB_MA_5
BF34
SB_MA_6
BK34
SB_MA_7
BJ37
SB_MA_8
BH40
SB_MA_9
BH16
SB_MA_10
BK36
SB_MA_11
BH38
SB_MA_12
BJ11
SB_MA_13
BL37
SB_MA_14
DDR SYSTEM MEMORY B
1
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
LA-5221P
1
9 45Tues day, February 03, 2009
0.1
5
4
3
2
1
Strap Pin Table
Plac e R5 3 <500m ils to U4 pin U45&T4 4.
U4C
BLON_PWM<17> ENABLT<17>
+3VS
D D
1/2 Fol low intel ch eck list
4.22K-->2.4K
C C
B B
DDC2_ CLK<17> DDC2_DAT A<17>
ENAVDD<17>
TXCLK_L-<17> TXCLK_L+<17>
TXOUT_L0-<17> TXOUT_L1-<17> TXOUT_L2-<17>
TXOUT_L0+<17> TXOUT_L1+<17> TXOUT_L2+<17>
For ma ke layout clearance, del TP for channel B. 10/18
12/219 HP review No TV out and contact to GND
12/19 HP review CMOS bu ffers and c an be left as NC
12/ 19 HP rev iew No CR T o ut an d conta ct t o GN D
12/19 HP review CMOS bu ffers and c an be left as NC
Close to pin D32 and keep 30mil space to other part/trace.
R54 10K_0402_5%
1 2
1 2
1 2
T4
R55 10K_0402_5%
R56 2.4K_0402_1%
10/18
10/19
10/19
1.02K_0402_1%
D38
L_BKLT_CTRL
C37
L_BKLT_EN
K38
L_CTRL_CLK
L37
L_CTRL_DATA
J37
L_DDC_CLK
L35
L_DDC_DATA
B36
L_VDD_EN
F50
LVDS_IBG
H46
LVDS_VBG
P44
LVDS_VREFH
K46
LVDS_VREFL
D46
LVDSA_CLK#
B46
LVDSA_CLK
D44
LVDSB_CLK#
B44
LVDSB_CLK
G45
LVDSA_DATA#_0
F46
LVDSA_DATA#_1
G41
LVDSA_DATA#_2
C45
LVDSA_DATA#_3
F44
LVDSA_DATA_0
G47
LVDSA_DATA_1
F40
LVDSA_DATA_2
A45
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
F42
LVDSB_DATA#_2
D48
LVDSB_DATA#_3
D40
LVDSB_DATA_0
C41
10/18
LVDSB_DATA_1
G43
LVDSB_DATA_2
B48
LVDSB_DATA_3
J27
TVA_DAC
E27
TVB_DAC
G27
TVC_DAC
F26
TVA_RTN
B34
TV_DCONSEL_0
D34
TV_DCONSEL_1
J29
CRT_BLUE
G29
CRT_GREEN
F30
CRT_RED
E29
CRT_IRTN
D36
CRT_DDC_CLK
C35
CRT_DDC_DATA
J33
CRT_HSYNC
D32
CRT_TVO_IREF
G31
CRT_VSYNC
R62
CANTI GA GMCH S FF_FCBGA1363
1 2
LVDS
TV
PEG_COMPI
PEG_COMPO
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8
PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8
PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9
PEG_TX#_10
PCI-EXPRESS GRAPHICS
PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
VGA
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
layo ut note:
PEGCOMP trace width and sp acing i s 20/25 mils.
PEGCOMP
U45 T44
D52 G49
DPB_AUX#
K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54
E51 F48
DPB_AUX
J55
DPB_HPD
J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52
DPB_LANE0#
L47
DPB_LANE1#
F52
DPB_LANE2#
P46
DPB_LANE3#
H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54
DPB_LANE0
J47
DPB_LANE1
F54
DPB_LANE2
N47
DPB_LANE3
H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52
R53 49.9_0402_1%
R885 100K_0402_5%
R886 100K_0402_5%
12/22 +VCC_PEG-->+VCCP
1 2
1 2
TR 2N 7002DW-7-F 2N SOT-363
1 2
TR 2N 7002DW-7-F 2N SOT-363
4
C83 0.1U _0402_16V7K
1 2
C84 0.1U _0402_16V7K
1 2
C85 0.1U _0402_16V7K
1 2
C86 0.1U _0402_16V7K
1 2
C87 0.1U _0402_16V7K
1 2
C88 0.1U _0402_16V7K
1 2
C89 0.1U _0402_16V7K
1 2
C90 0.1U _0402_16V7K
1 2
1 2
4
1 2
Q72B
5
+VCCP
Q71B
5
3
+3VS
C81 0.1U_0402_16V7K
TR 2N 7002DW-7-F 2N SOT-363
3
+3VS
C82 0.1U_0402_16V7K
TR 2N 7002DW-7-F 2N SOT-363
6 1
DP_DATA0_N DP_DATA1_N DP_DATA2_N DP_DATA3_N
DP_DATA0_P DP_DATA1_P DP_DATA2_P DP_DATA3_P
DPD_C_AUXR#
Q71A
6 1
2
DPD_C_AUXR
Q72A
2
DP_DATA0_N <16> DP_DATA1_N <16> DP_DATA2_N <16> DP_DATA3_N <16>
DP_DATA0_P <16> DP_DATA1_P <16> DP_DATA2_P <16> DP_DATA3_P <16>
DDC1_ EN
DDC1_ EN
DPD_C_AUXR# <16>
DPD_C_AUXR <16> DPB_HPD <16>
DDC1_ EN <16>
CFG[2:0] FSB Freq select
CFG[4:3] Reserved
CFG5 (DMI select)
CFG6
CFG6
CFG7 (Intel Management Engine Crypto strap)
CFG8
CFG9
(PCIE Graphics Lane Reversal)
CFG10 (PCIE Lookback enable)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
CFG19 (DMI Lane Reversal)
CFG20 (PCIE/SDVO concurrent)
000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved
0 = DMI x 2 1 = DMI x 4 0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
*
*
1 =(TLS)chiper suite with confidentiality
Reserved
0 = Re verse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order
0 = Enable
1 = Disable
Reserved
00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled
ReservedCFG[15:14]
*
(Default)11 = Normal Operation
*
0 = Disabled
1 = Enabled
*
ReservedCFG[18:17]
0 = Normal Operation
(Lane number in Order)
*
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
*
*
*
12/29 HP review Rem ove so me res erved R for CF G net
+3VS
R67 4.02K_0402_1% @
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
CFG20<8>
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Cantiga(3/6)-VGA/LVDS/TV
LA-5221P
1 2
1
10 45Tues day, February 0 3, 2009
0.1
5
12/22 HP review Pin J31 L31 contact t o GND
12/24 HP review Pin J31 L31 contact t o GND
D D
12/17 HP review +1.05VM -->+VCCP
C C
B B
+1.05VM_HPLL
1
C125
2
0.1U_0402 _16V4Z
12/22 HP review DPLLA c ontact with DPLLB PWR
12/22 HP review Rem ove 0 ohm
+1.5VS
0.1U_0402_16 V4Z
+VCCP
1
+
2
C108
+1.05VM_PEGPLL
9/27
1
C101
2
100U_D2_6.3VM
12/17 HP review Rem ove 0 ohm
1
C126
2
0.1U_0402 _16V4Z
+1.05VM_DPLLA
+1.8V
1 2
BLM18PG181SN1D_0603
1
C98 1000P_0402_50V7K
2
9/27
+1.05VM_PEGPLL
4.7U_0805 _10V4Z
10U_0805_6.3V6M
1
2
C109
10U_0805_6.3V6M
+1.8V
12/17 HP review Rem ove 0 ohm
+1.05VM_HPLL
+1.05VM_MPLL
L1
720mA
1U_0603_10V4Z
1
2
C110
0.1U_0402_16V4Z
1
C119
2
+1.8V_TXLVDS
1
2
C111
1
C120
2
1U_0603_10V4Z
1
C127
2
4
U4H
VTT_1
VCCA_TV_DAC
TVD TV/CRT
HDA
VCCD_QDAC
VCCD_TVDAC
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
AXF
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4
PEG
DMI
VTTLF
VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8
VTT_9 VTT_10 VTT_11 VTT_12 VTT_13
VTT
VCC_HDA
VCC_HV_1 VCC_HV_2
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3
VTTLF1 VTTLF2 VTTLF3
J31
VCCA_CRT_DAC
L31
VCCA_DAC_BG
M33
VSSA_DAC_BG
J45
VCCA_DPLLA
L49
VCCA_DPLLB
AF10
VCCA_HPLL
AE1
VCCA_MPLL
U43
VCCA_LVDS1
U41
VCCA_LVDS2
V44
VSSA_LVDS
AJ43
VCCA_PEG_BG
AG43
VCCA_PEG_PLL
AW24
VCCA_SM_1
AU24
VCCA_SM_2
AW22
VCCA_SM_3
AU22
VCCA_SM_4
AU21
VCCA_SM_5
AW20
VCCA_SM_6
AU19
VCCA_SM_7
AW18
VCCA_SM_8
AU18
VCCA_SM_9
AW16
VCCA_SM_10
AU16
VCCA_SM_11
AT16
VCCA_SM_12
AR16
VCCA_SM_13
AU15
VCCA_SM_14
AT15
VCCA_SM_15
AR15
VCCA_SM_16
AW14
VCCA_SM_17
AT24
VCCA_SM_NCTF_1
AR24
VCCA_SM_NCTF_2
AT22
VCCA_SM_NCTF_3
AR22
VCCA_SM_NCTF_4
AT21
VCCA_SM_NCTF_5
AR21
VCCA_SM_NCTF_6
AT19
VCCA_SM_NCTF_7
AR19
VCCA_SM_NCTF_8
AT18
VCCA_SM_NCTF_9
AR18
VCCA_SM_NCTF_10
AU27
VCCA_SM_CK_4
AU28
VCCA_SM_CK_3
AU29
VCCA_SM_CK_2
AU31
VCCA_SM_CK_1
AT31
VCCA_SM_CK_NCTF_1
AR31
VCCA_SM_CK_NCTF_2
AT29
VCCA_SM_CK_NCTF_3
AR29
VCCA_SM_CK_NCTF_4
AT28
VCCA_SM_CK_NCTF_5
AR28
VCCA_SM_CK_NCTF_6
AT27
VCCA_SM_CK_NCTF_7
AR27
VCCA_SM_CK_NCTF_8
AH12
VCCD_HPLL
AE43
VCCD_PEG_PLL
M46
VCCD_LVDS_1
L45
VCCD_LVDS_2
CANTI GA GMCH SFF _FCBGA1363
CRTPLLA PEGA SM
A LVDS
POWER
LVDS
R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1
K30
A31
N34
N32
M25 N24 M23
BK24 BL23 BJ23 BK22
T41
C33 A33
AB44 Y44 AC43 AA43
AM44 AN43 AL43
K14 Y12 P2
0.47U_0603_10V7K
3
+1.5VS_Q DAC
1
C128
2
+VCCP
+VCCP
0.47U_0603_10V7K
0.47U_0603_10V7K
C94
10U_0805_10V4Z
1
C129
2
+VCCP
4.7U_0805_10V4Z
2.2U_0805_16V4Z
4.7U_0805_10V4Z
1
1
2
2
C95
1U_0603_10V4Z
1
1
C103
C102
2
2
1
1
1
+
C96
12/22 HP review +3VS-->GND
01/10 HP review Del R6 9 0ohm and contact GND directly
12/22 HP review +1.5VS-->GND
C93
2
2
2
C97
01/10 C93 (330u D2 ESR9-->220u B2 ESR25M@)
Nea r AXF PIN
02/02 Del 10u andR73 0ohm-->1ohm
01/10 HP review 3VS_HV-- >+3VS
12/22 HP review +1.05VM -->+VCCP
0.47U_0603_10V7K
1
C130
2
R73
1_0603_5%
+3VS
0.1U_0402_16V4Z
1 2
10U_0805_6.3V6M
+1.5V_SM_CKG
1
1
C118
2
2
C121
852mA
220U_B2_2.5V M_R25M
@
+VCCP
0.1U_0402 _16V4Z
10U_0805_6.3V6M
1
1
C114
C115
2
2
+VCCP
+3VS
2
+1.05VM_DPLLA
9/27
1
C92
2
0.1U_0402 _16V4Z
+1.05VM_HPLL
1
2
C99
0.1U_0402 _16V4Z
+1.05VM_MPLL
1
C104
2
0.1U_0402 _16V4Z
+1.5V
2 1
D3 CH751H- 40_SC76
1
2
C112
1000P_0402_50V7K
+1.05VM_PEGPLL
0.1U_0402 _16V4Z
10U_0805_10V4Z
1
C122
2
+VCCP_ D
+1.5VS_Q DAC
0.1U_0402 _16V4Z
0.01U_0402_16V7K
1
C131
2
12/12
+VCCP
+VCCP
+VCCP
12/22 HP review +1.05VM -->+VCCP
12/22 HP review +1.05VM -->+VCCP
+1.8V
R68
1 2
BLM18PG181SN1D_0603
@
1
+
C91
220U_B2_2.5V M_R25M
2
01/10 C91(D2 ESR15M@-->B2 ESR25M@)
12/22 HP review +1.05VM -->+VCCP Rem ove 0 ohm
R70
1 2
BLM18PG181SN1D_0603
1
2
C100
4.7U_0805 _10V4Z
BLM18PG181SN1D_0603
1
C105
2
10U_0805_6.3V6M
12/22 HP review Rem ove 0 ohm
R71
1 2
12/22 HP review +1.05VM -->+VCCP
Nea r T41 Pin
12/22 HP review +1.05VM -->+VCCP
+VCCP
L2
1 2
BLM18PG121SN1D_0603
1
C123
2
R74 10_0402_5%
1 2
01/10 HP review Del R7 5 0ohm and +3VS_HV-->+3VS
+1.5VS
R76
1 2
BLM18PG181SN1D_0603
4.7U_0603_6.3V
1
1
C132
C133
2
2
1
12/22 HP review +1.05VM -->+VCCP Rem ove 0 ohm
12/22 HP review Rem ove 0 ohm
12/22 HP review +1.5VS-->GND
12/22 HP review +1.05VM -->+VCCP Rem ove 0 ohm
10U_0805_6.3V6M
4.7U_0805 _10V4Z
1
1
1
+
C113
220U_B2_2.5V M_R25M
C117
C116
2
2
2
01/10 C113(D2 ESR15M@-->B2 ESR25M)
12/22 HP review +1.05VM -->+VCCP Rem ove 0 ohm
0.1U_0402 _16V4Z
1
C124
2
01/02 Near U4 Pin AM44
+VCCP
+VCCP
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cust om
2
Date : Sheet of
Compal Electronics, Inc.
Cantiga(4/6)-PWR
LA -5 22 1P
1
11 45Tuesday, Febru ary 03, 2009
0.1
5
Extnal Graphic: 1210.34mA integr ated Graphic: 1930.4mA
12/12 HP review +1.05V M-->+VCCP
D D
0.22U_0402_10V4 Z
0.22U_0402_10V4 Z
1
+
C141
220U_B2_2.5VM_R25M
2
10U_0805_6.3V6M
C142
C143
1
2
1853mA (VCC and VCC_NCTF)
1
1
2
2
+VCCP
0.1U_0402_16V4Z
C145
C144
1
2
01/10 C141(D2 ESR15M-->B2 ESR25M)
C C
B B
A A
5
U4F
AT41
VCC_1
AR41
VCC_2
AN41
VCC_3
AJ41
VCC_4
AH41
VCC_5
AD41
VCC_6
AC41
VCC_7
Y41
VCC_8
W41
VCC_9
AT40
VCC_10
AM40
VCC_11
AL40
VCC_12
AJ40
VCC_13
AH40
VCC_14
AG40
VCC_15
AE40
VCC_16
AD40
VCC_17
AC40
VCC_18
AA40
VCC_19
Y40
VCC_20
AN35
VCC_21
AM35
VCC_22
AJ35
VCC_23
AH35
VCC_24
AD35
VCC_25
AC35
VCC_26
W35
VCC_27
AM34
VCC_28
AL34
VCC_29
AJ34
VCC_30
AH34
VCC_31
AG34
VCC_32
AE34
VCC_33
AD34
VCC_34
AC34
VCC_35
AA34
VCC_36
Y34
VCC_37
W34
VCC_38
AM32
VCC_39
AL32
VCC_40
AJ32
VCC_41
AH32
VCC_42
AE32
VCC_43
AD32
VCC_44
AA32
VCC_45
AM31
VCC_46
AL31
VCC_47
AJ31
VCC_48
AH31
VCC_49
AM29
VCC_50
AL29
VCC_51
AM28
VCC_52
AL28
VCC_53
AJ28
VCC_54
AM27
VCC_55
AL27
VCC_56
AM25
VCC_57
AL25
VCC_58
AJ25
VCC_59
AM24
VCC_60
N36
VCC_61
CANTI GA GMCH S FF_FCBGA1363
4
01/10 C137(330u D2 ESR9M-->220u B2 ESR25M)
02/02 Change to DDR3 power
0.1U_0402_10V7K~D C1103
1
VCC CORE
12/12 HP review +1.05V M-->+VCCP
+VCCP
AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34
POWER
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8
VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31
VCC NCTF
VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38
2
0.1U_0402_10V7K~D C1105
1
2
330U_D2E_2.5VM _R9
Secur ity Classification
Issued Date
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C137
0.1U_0402_10V7K~D
1
+
2
C1102
3000mA
1
2
+1.5V
+VCC_CM_BB36 +VCC_CM_BE35
0.1U_0402_10V7K~D C1104
1
2
+VCC_CM_BF24 +VCC_CM_BL19
0.1U_0402_10V7K~D C1106
1
2
220U_B2_2.5VM_R25M
CRB use
+VCCGFX
5739mA (VCC_AXG and VCC_AXG_NCTF)
1
1
C148
C147
2
C149
2
10U_0805_6.3V
10U_0805_6.3V
2006/02/13 2006/03/10
C146
1
+
2
3
10U_0805_6.3V6M
1
2
+VCC_CM_BB16 +VCC_CM_BC29
0.1U_0402_10V7K~D
1
2
1
2
1U_0603_10V4Z
10U_0805_6.3V6M
C138
1
2
C1110
1
C150
2
0.1U_0402_16V4Z
C139
+VCC_CM_BC29
+VCC_CM_BB36 +VCC_CM_BE35
0.01U_0402_16V7K
+VCC_CM_BF24 +VCC_CM_BL19 +VCC_CM_BB16
01/10 HP review Del T5 and T6
BB36
BE35 AW34 AW32
BK30 BH30
BF30
C140
2
BD30
BB30 AW30
1
BL29
BJ29
BG29
BE29 BC29
BA29
AY29
BK28 BH28
BF28 BD28
BB28
BL27
BJ27
BG27
BE27 BC27
BA27
AY27 AW26
BF24
BL19
BB16
W32
AG31
AE31 AD31 AC31
AA31
Y31
W31 AH29 AG29
AE29 AD29 AC29
AA29
Y29
W29 AH28 AG28
AE28
AA28 AH27 AG27
AE27 AD27 AC27
AA27
Y27
W27 AH25 AD25 AC25
W25
AJ24 AH24 AG24
AE24 AD24 AC24
AA24
Y24
W24
AM22
AL22
AJ22 AH22 AG22
AE22 AD22 AC22
AA22 AM21
AL21
AJ21 AH21 AD21 AC21
AA21
Y21
W21
AM16
AL16
AG13
AE13
Compal Secret Data
Deciphered Date
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61
VCC_AXG_SENSE VSS_AXG_SENSE
2
POWER
VCC SMVCC GFX
2
U4G
CANTI GA GMCH S FF_FCBGA1363
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8
VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39
VCC GFX NCTF
VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44
VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74
VCC GFX
VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC SM LF
1
+VCCGFX
T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18
AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15
AU45 BF52 BB38 BA19 BE9 AU9 AL9
Title
Size Doc ument Number Re v
Cus tom
LA-5221P
Date: Sheet of
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
1
2
C134
0.1U_0402_16V4Z
0.22U_0402_10V4 Z
C156 0.1 U_0402_16V4Z
1
1
2
2
1
1
2
2
C136
C135
4.7U_0805_10V4Z
C151 0.22U_0603 _10V7K
C152 0.22U_0603 _10V7K
1
1
C157 0.1 U_0402_16V4Z
2
2
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
1
C153 0 .47U_0402_6.3V6K
C154 1U_06 03_10V4Z
1
1
1
2
2
2
12 45Tues day, February 0 3, 2009
C155 1U_06 03_10V4Z
0.1
5
U4I
BA55
VSS_1
AU55
VSS_2
AN55
VSS_3
AJ55
VSS_4
AE55
VSS_5
AA55
VSS_6
U55
VSS_7
N55
VSS_8
BD54
VSS_9
BG53
VSS_10
AJ53
VSS_11
AE53
D D
C C
B B
A A
VSS_12
AA53
VSS_13
U53
VSS_14
N53
VSS_15
J53
VSS_16
G53
VSS_17
E53
VSS_18
K52
VSS_19
BG51
VSS_20
BA51
VSS_21
AW51
VSS_22
AU51
VSS_23
AR51
VSS_24
AN51
VSS_25
AL51
VSS_26
AJ51
VSS_27
AG51
VSS_28
AE51
VSS_29
AC51
VSS_30
AA51
VSS_31
W51
VSS_32
U51
VSS_33
R51
VSS_34
N51
VSS_35
L51
VSS_36
J51
VSS_37
G51
VSS_38
C51
VSS_39
BK50
VSS_40
AM50
VSS_41
K50
VSS_42
BG49
VSS_43
E49
VSS_44
C49
VSS_45
BD48
VSS_46
BB48
VSS_47
AY48
VSS_48
AV48
VSS_49
AT48
VSS_50
AP48
VSS_51
AM48
VSS_52
AK48
VSS_53
AH48
VSS_54
AF48
VSS_55
AD48
VSS_56
AB48
VSS_57
Y48
VSS_58
V48
VSS_59
T48
VSS_60
P48
VSS_61
M48
VSS_62
K48
VSS_63
H48
VSS_64
BL47
VSS_65
BG47
VSS_66
E47
VSS_67
C47
VSS_68
A47
VSS_69
BD46
VSS_70
AY46
VSS_71
AM46
VSS_72
AK46
VSS_73
AH46
VSS_74
BG45
VSS_75
AE45
VSS_76
AC45
VSS_77
AA45
VSS_78
W45
VSS_79
R45
VSS_80
N45
VSS_81
E45
VSS_82
BD44
VSS_83
BB44
VSS_84
AV44
VSS_85
AK44
VSS_86
AH44
VSS_87
AF44
VSS_88
AD44
VSS_89
K44
VSS_90
H44
VSS_91
BL43
VSS_92
BG43
VSS_93
AY43
VSS_94
AR43
VSS_95
W43
VSS_96
R43
VSS_97
M43
VSS_98
E43
VSS_99
CANTI GA GMCH S FF_FCBGA1363
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25
4
3
U4J
AN25
VSS_199
AG25
VSS_200
AE25
VSS_201
AA25
VSS_202
Y25
VSS_203
E25
VSS_204
A25
VSS_205
BD24
VSS_206
AN24
VSS_207
AL24
VSS_208
H24
VSS_209
BG23
VSS_210
AY23
VSS_211
E23
VSS_212
BD22
VSS_213
BB22
VSS_214
AN22
VSS_215
Y22
VSS_216
W22
VSS_217
H22
VSS_218
BL21
VSS_219
BG21
VSS_220
AY21
VSS_221
AN21
VSS_222
AG21
VSS_223
AE21
VSS_224
M21
VSS_225
E21
VSS_226
A21
VSS_227
BD20
VSS_228
H20
VSS_229
BG19
AY19
M19
BD18
BL17
BG17
AY17
M17
BD16 AN16 AG16 AE16
W16
BG15
AY15 AN15 AD15 AC15
M15
BD14
BL13 BG13
AY13 AU13 AR13
AJ13 AC13 AA13
W13
M13
BD12 AV12 AP12
AM12
AK12 AB12
BG11 AG11
BD10
AY10 AP10
BG9
BD8
E19
N18 H18
E17 A17
Y16
N16 H16
R15
E15
H14
U13
E13 A13
V12 P12 H12
E11
H10 BL9
E9 A9
BB8 AY8 AV8 AT8 AP8
VSS
VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299
CANTI GA GMCH S FF_FCBGA1363
VSS NCTF
VSS SCB
VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23
VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358
VSS_359 VSS_360 VSS_361 VSS_362
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9
VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7
2
AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13
N42 N40 N38 M39
AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18
BL55 BL1 A55 D1 B55 B2 A4
12/12 FOR NO CRA CK DE TECT FUNCTION
1
Secur ity Classification
12/12 FOR NO CRA CK DE TECT FUNCTION
5
4
Issued Date
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
LA-5221P
1
13 45Tues day, February 0 3, 2009
0.1
5
DDR_A _DQS#[0.. 7]<9>
DDR _A_D[0..6 3]<9>
DDR_A _DM[0..7]<9>
DDR_ A_DQS[0.. 7]<9>
DDR_A _MA[0..14]<9>
D D
Layou t Note: Plac e near JP 3
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C166
1
2
C C
B B
Layou t Note: Plac e near JP3 203,2 04
+0.75VS
A A
+1.5V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1113
1
2
1U_0603_10V4Z~D
1U_0603_10V4Z~D
1
1
C1120
C1121
2
2
0.1U_0402_16V4Z
C167
1
2
10U_0603_6.3V6M~D
C1114
1
2
1U_0603_10V4Z~D
1
C1122
2
0.1U_0402_16V4Z
C168
C169
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1115
C1116
1
2
1
2
C1117
1
1
2
2
10U_0603_6.3V6M~D
1U_0603_10V4Z~D
10U_0603_6.3V6M~D
1
C1153
C1123
2
4
V_DDR _MCH_REF<8>
DDR_CKE 0_DIMMA<8>
330U_ D2_2.5VY_R15M
1
C1119
C1118
1
+
2
2
10U_0603_6.3V6M~D
1
1
C1154
C1155
2
2
+3VS
2.2U_06 03_6.3V6K~D
1
2
3
+1.5V +1.5V
2.2U_06 03_6.3V6K~D
0.1U_0402_16V4Z ~D
DDR_A _D0
1
C158
2
DDR_A_BS 2<9>
M_CLK_DD R0<8>
M_CLK_DD R#0<8>
DDR_A _BS0<9>
DDR_A_W E#<9>
DDR_A _CAS#<9>
DDR_CS1_D IMMA#<8>
C183
0.1U_04 02_16V4Z~D
+0.75VS
C184
1
2
DDR_A _D1
1
DDR_A_DM 0
C159
DDR_A _D2
2
DDR_A _D3
DDR_A _D8 DDR_A _D13
DDR_A _DQS#1 DDR_A _DQS1 SM_DRAMRST#
DDR_A _D10 DDR_A _D11
DDR_A _D20 DDR_A _D17
DDR_A _DQS#2 DDR_A _DQS2
DDR_A _D18 DDR_A _D19
DDR_A _D25 DDR_A _D30
DDR_A_DM 3
DDR_A _D26 DDR_A _D27
DDR_CKE 0_DIMMA DDR_CKE 1_DIMMA
DDR_A_BS 2
DDR_A_MA12 DDR_A_MA9
DDR_A_MA8
DDR_A_MA3 DDR_A_MA1
M_CLK_DD R0 M_CLK_DDR#0
DDR_A_MA10 DDR_A_BS 0
DDR_A_W E# DDR_A _CAS#
DDR_A_MA13
DDR_C S1_DIMMA#
DDR_A _D32 DDR_A _D39
DDR_A _DQS#4 DDR_A _DQS4
DDR_A _D34 DDR_A _D35
DDR_A _D40 DDR_A _D41
DDR_A_DM 5
DDR_A _D42 DDR_A _D43
DDR_A _D54 DDR_A _D49
DDR_A _DQS#6 DDR_A _DQS6
DDR_A _D50 DDR_A _D51
DDR_A _D56 DDR_A _D57
DDR_A_DM 7
DDR_A _D58 DDR_A _D59
1 2
R128 10K_04 02_5%~D
1 2
R129 10K_0402_5%~D
3 5 7
9 11 13 15 17 19 21 23 25 27
33 35
39 41
45 47 49 51 53 55 57 59
63
67 69
73 75 77 79 81 83 85 87 89 91 93 95 97 99
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
205
2
JP3
VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
G1
DQS#0
VSS10
VSS17
VSS19
VSS21
VDD10
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30
VSS31
VSS33
VSS35
DQS#5
VSS38
VSS40
VSS42
VSS43
VSS45
VSS47
DQS#7
VSS50
VSS52
EVENT#
FOX_AS0A626-U4RN -7F
VSS3
DQS0
VSS6
VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3
DQ30 DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1#
RAS#
ODT0
ODT1
NC2
DQ36 DQ37
DM4
DQ38 DQ39
DQ44 DQ45
DQS5
DQ46 DQ47
DQ52 DQ53
DM6
DQ54 DQ55
DQ60 DQ61
DQS7
DQ62 DQ63
SDA
VTT2
DQ4 DQ5
DQ6 DQ7
A15 A14
A11
CK1
BA1
S0#
SCL
1
2
DDR_A _D4
4
DDR_A _D5
6 8
DDR_A _DQS#0
10
DDR_A _DQS0
12 14
DDR_A _D6
16
DDR_A _D7
18 20
DDR_A _D14
22
DDR_A _D15
24 26
DDR_A_DM 1
28 30 32
DDR_A _D9
34
DDR_A _D12
36 38
DDR_A _D22
40
DDR_A _D21
42 44
DDR_A_DM 2
46 48
DDR_A _D16
50
DDR_A _D23
52 54
DDR_A _D28
56
DDR_A _D29
58 60
DDR_A _DQS#3
62
DDR_A _DQS3
64 66
DDR_A _D24
68
DDR_A _D31
70 72
74 76 78
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86
A7
88
DDR_A_MA6
90
A6 A4
A2 A0
G2
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DDR_A_MA4DDR_A_MA5
DDR_A_MA2 DDR_A_MA0
M_CLK_DD R1 M_CLK_DDR#1
DDR_A_BS 1 DDR_A _RAS#
DDR_C S0_DIMMA# M_ODT0
M_ODT1
DDR_A _D36 DDR_A _D37
DDR_A_DM 4
DDR_A _D33 DDR_A _D38
DDR_A _D47 DDR_A _D45
DDR_A _DQS#5 DDR_A _DQS5
DDR_A _D46 DDR_A _D44
DDR_A _D52 DDR_A _D53
DDR_A_DM 6
DDR_A _D48 DDR_A _D55
DDR_A _D60 DDR_A _D61
DDR_A _DQS#7 DDR_A _DQS7
DDR_A _D62 DDR_A _D63
PM_EXTTS#0 MEM_SDATA MEM_SCLK
+0.75VS
SM_DRAMRST# <8>
T161PAD~D
M_CLK_DDR1 <8> M_CLK_DDR#1 <8>
DDR_A_BS 1 <9> DDR_A _RAS# <9>
DDR_CS0_D IMMA# <8> M_ODT0 <8>
M_ODT1 <8>
PM_EXTTS#0 <8>
ICH_SMBDATA < 4,15,21,25> ICH_SMBCLK <4,15,21,25>
DDR_C KE1_DIMMA <8>
V_DDR _MCH_REF <8>
0.1U_0402_16V4Z ~D
2.2U_06 03_6.3V6K~D
C1089
C1088
1
1
2
2
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
2
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT
LA-5221P
14 45Tues day, February 0 3, 2009
1
0.1
of
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