HP 4415s, 4416s Schematics

THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC

THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC

THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC

THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR

CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR

CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR

CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT

IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT

IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT

IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED

WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED

WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED

WRITTEN PERMISSION, INVENTEC CORPORATION 2009 ALL RIGHT RESERVED

HSF Property :

RoHS

RoHS

RoHS

PIAGET-Discrete

P09C2.0D

REV

DATE CHANGE NO.

DATE

DATE

DATE CHANGE NO. REV

DATE

CHANGE NO. REV

CHANGE NO.

CHANGE NO.

REV

REV

MV Build

DRAWER

DRAWER

DRAWER

DRAWER

DRAWER
DESIGN

DESIGN

DESIGN

DESIGN

DESIGN
CHECK

CHECK

CHECK

CHECK

CHECK
RESPONSIBLE

RESPONSIBLE

RESPONSIBLE

RESPONSIBLE

RESPONSIBLE

SIZE =

SIZE =

SIZE = 3 REV

SIZE =
FILE NAME : XXXX-XXXXXX-XX

FILE NAME :

FILE NAME : XXXX-XXXXXX-XX

FILE NAME : XXXX-XXXXXX-XX

FILE NAME :

P/N XXXXXXXXXXXX

P/N

P/N XXXXXXXXXXXX

P/N

P/N

EE

EE

3

3

3

XXXX-XXXXXX-XX

XXXX-XXXXXX-XX

XXXXXXXXXXXX

XXXXXXXXXXXX

XXXXXXXXXXXX

2009/08/12

DATEEE

DATEEE

POWER

POWER

POWER

VER :SIZE =

VER :

DATE

DATEDATE

DATEPOWER

DATEDATEEE POWER

DATEDATE

TITLE

TITLE

TITLE

TITLE

TITLE

SIZE CODE DOC. NUMBER REVVER :

SIZE CODE DOC. NUMBER

SIZE CODE

SIZE

SIZE CODE

A3

A3

A3

INVENTEC

INVENTEC

INVENTEC

INVENTEC

INVENTEC

Piaget 2.0 Discrete

Piaget 2.0 Discrete

Piaget 2.0 Discrete

DOC. NUMBER

DOC. NUMBER

CODE3

DOC. NUMBER REVVER :

CS

1310A22683-0-MTR

CS

CS 1310A22683-0-MTR

1310A22683-0-MTR

SHEET OF

SHEET OF

SHEET

SHEET OF

SHEET

OF

OF

1 60

1 60

1 60

REV

REVVER :

A02

A02

A02

TABLE OF CONTENTS

PAGE
5- DC& BATTERY CHARGER
6- SELECT & BATTERY CONN
7- +V5A,+V3A & +V2.5S
8- OCP

9- +VCC_NB & +V1.2A
11- POWER

12- DDR2 POWER
13- POWER(SLEEP)
14- POWER(SEQUENCE)

PAGE
15- CLOCK_GENERATOR
16- CPU-1
17- CPU-2
18- CPU-3

19- CPU-4
20- DDR2-DIMM010- +VCC_CORE
21- DDR2-DIMM1
22- DDR2-DAMPING
23- THERMAL&FAN CONTROLLER
24- RS780-1
25- RS780-2
26- RS780-3
27- RS780-4
28- GPU-AMD-M92S2-1
29- GPU-AMD-M92S2-2
29- GPU-AMD-M92S2-3
30- GPU-AMD-M92S2-4
32- Video RAM(GDDR2)-1
33- Video RAM(GDDR2)-2
34- CRT

35- LCD CONN & WEBCAM CONN
36- SB700-1
37- SB700-2
38- SB700-3
39- SB700-4

PAGE
40- KBC
41- KB & TP CONN
42- SPI & ACCELEROMETER
43- HDD & ODD CONN

44- USB CONN
45- TCM CONN

46- FLASH MEDIA CARD
47- AZALIA CODEC
48- Earphone & MIC JACK
49- AUDIO AMP & HP JACK
50- MDC CNTR
51- Giga-LAN- CONTROLLER
52- NIC-10/100/1000-RJ45 CONN
53- MINICARD & BT CONN

54- NEW CARD & SIM CONN
55- W/B & SW/B & LED/B CONN
56- SCREW
57- Power Plan CAP

58- HDMI
59- 15’’ ODD Extend Board

60- Switch Board & LID Switch & QL

CHANGE by

Jason Chiu 20-Jul-2009

INVENTEC

TITLE

Piaget 2.0 Discrete

Table OF Content

CODE

SIZE

A3

DOC. NUMBER

1310A22683-0-MTRA02

CS

SHEET

REV

OF

602

Clock Generator

ICS9LPR476KLFT

LCM

CRT

VRAM

LVDS

RGB

M92S2

GDDR2

PCIE-GFX

AMD Caspian

Turion/Sempron

SIG2 Socket/638pin

Hyper Transport

AMD

RS881

(FCBGA)

A-LINK

PCIE0
PCIE2
PCIE3

DDR2

DDR2

DDR II _SODIMM0

DDR II _SODIMM1

Giga-Lan

Marvell 8072

MINI CARD

CONN

(WLAN)

NEW CARD

USB1

CONN

RJ45

MAIN BATT

System Charger &

DC/DC System power

4 in 1

Slot

HDMI

USB11

Bluetooth

USB0

Conn

USB2

Conn

USB4

Conn

USB5

Conn

USB3

Flash media

ALCOR AU6371

USB7

CAMERA

USB6

WWAN

USB2.0

Azalia interface

mdc v1.5v/3

CONNECTOR

RJ11

AMD

SB710

(FCBGA)

Mic IN

AUDIO CODEC

IDT_92HD75

Headphone

SATA1

SATA0

SM Bus

LPC interface

Speaker

Accelerometer

SMSC KBC1098

Keyboard

CHANGE by

FIXED ODD

HDD

KBC

TouchPad

Jason Chiu 20-Jul-2009

SPI

TCM

SYSTEM

BIOS

INVENTEC

TITLE

Piaget 2.0 Discrete

Block Diagram

DOC. NUMBER

CODE

SIZE

A3

1310A22683-0-MTRA02

CS

SHEET

REV

OF

603

Adapter

+VBAT

OCP

OCP_OC#

+VBATR

ADP_PRES

KBC_PW_ON

POWER_GOOD_3

SYS_PWRGD

POWER_GOOD_3

5/3.3V

(TPS51125)

+VCC_NB&+V1.2

(TPS51124)

+V5A
+V3A

+V5AL

+V3AL

+V1.2S

SYS_PWRGD

RICH

(RT9194PE)

+VCC_NB

+V1.1S

+V3S

+V5S

ANPEC

(APL5315)

+V2.5S

Charger

(BQ24740)

CHGCTRL_3

ADP_PRES

AC_AND_CHG

PWR_GOOD3

NB_SKIP#

SLP_S5#_5R

V18_GOOD

PWR_GOOD_3

NB_SKIP

NBV_BUF

SYS_PWRGD

VGA_ALTV0
VGA_ALTV1

V1.5S_PG

SYS_PWRGD

MAXIM

(MAX8792ETD)

DDR2 POWER

(MAX17000ETG)

+V1.8

VCC_CORE

(MAX17009)

VDD_CORE

(SC471A)

GMT

(G966)

PWR_GOOD_3

CHANGE by

+VCC_CORE_NB

+V1.5S

+V0.9S

Jason Chiu 20-Jul-2009

+V1.8S

+VCC_CORE

+VCC_CORE_VDD1

+VDD_CORE

INVENTEC

TITLE

Piaget 2.0 Discrete

DOC. NUMBER

CODE

SIZE

A3

1310A22683-0-MTRA02

CS

SHEET

REV

OF

604

1

R1044
15K_5%

2

+VADPBL

+VBDC

5-,6-,7-

0402_OPEN

5-,7-

R1052

1 2

100K_1%

R1043

1

R5012

200K_1%

2

1

R1039

41.2K_1%

2

R1048

1 2

100K_1%

1 2

24K_1%

12

1

R1040

10K_1%

2

R1051

2VREF

12

R5063

76.8K_1%

1
2

7-,8-,14-

C70

0.022uF_16V

1

R1047

2

23.7K_1%

R1042

604K_1%

1 2

+V5AL

5-,7-,8-,55-

8

3

+

OUT

2

-

TI_LMV393IDGKR_SOP_8P

U1002-A

4

R1045

1 2

255K_1%

+V5AL

5-,7-,8-,55-

8

5

+

OUT

6

­U1002-B

4

+V5AL

5-,7-,8-,55-

1
2

C1034

0.1uF_16V

1

+

3

-

TI_LMV331IDBVR_SOT23_5P

+V3AL

1

7

TI_LMV393IDGKR_SOP_8P

CHGCTRL_3

R1049

1 2

1M_5%

R1050

1 2

100K_5%

U1004

5

4

OUT

2

C1036

0.1uF_25V

1 2

1

1 2

2
3

R1057
220K_5%

4

FAIR_FDMC6675BZ_8P

R5011

1 2

150K_5%

6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

1

R1027
22K_5%

2

AC_ADP_PRES

1

R5013

22K_5%

2

40-,51-

ADP_PRES

R1002

1 2

6-,40-

210K_1%

R1003
147K_1%

VCTRL_3

5-

Q1007

3

D

1

G

S

2

2N7002W

Q1009

S

1

2

40-

ADPDRV#

3.3A_150mil

C1037

1
2

10pF_50V

+VADPBL

5-,7-

2 1

D

D

8

8

7

7

6

6

5

5 4

G

1

S1

Q1053

G1

2

6

3

D1

ACDET

D2

G2

5

4

S2

2N7002DW

40­40-

6-40-

G

BQREF

SLP_S3#_3R

7-,9-,13-,14-,35-,37-,38-,39-,51-,53-,55-,57-

CELLS

CHGEN#

8-

I_SET

C1002

1

1uF_6.3V

2

R1021

1 2

422K_1%

1

C1013

1uF_6.3V

2

+VADP

7-,8-

C1040

1
2

0.1uF_25V

D1009

B140_SMA

Q1003

R1029

1 2

S

1
2

47K_5%

3

FAIR_FDMC6675BZ_8P

ADP_EN
KBC_VCC1_PWRGD

R184

1

2

47K_5%

8-

7-,13-,14-,38-,40-,49-,51-,54-

40-

6-

1

R1006

100K_5%

2

1

R1024

453K_1%

2

1

R1022
1M_1%

2

L1002

NFM60R30T222

1 2

4

R1030

1

4.7K_5%

R185

1 2

300K_5%

+V3A

12

R1023
20K_5%

C1014
1uF_6.3V

+VADPTR

+VADPTR

3

C1038

1
2

10pF_50V

2

5-

ADPDRV#

1

1

2

2

5A

C1039

1

0.1uF_25V

2

+VBAT +VBATR

5-

1
2

U1003

2

ACN

3

ACP

5

ACDET

9

AGND

13

EXTPWR

16

SRSET

6

ACSET

10

VREF

8

IADSLP

21

DPMDET

4

LPMD

20

CELLS

1

CHGEN

11

VDAC

12

VADJ

15

IADAPT

TI_BQ24740_QFN_28P

8-

PVCC

HIDRV

BTST

REGN

LODRV

PGND

LPREF

ISYNSET

PowerPad

ICS

28

26

25

PH

27

0_5%

24

23

22

19

SRP

18

SRN

17

BAT

7

14

29

C1001

100pF_50V

DC JACK

1
2
3
4

ACES_91302_0047L_1_4P

R1053

1 2

0.01_1%

C1015

1uF_25V

C1016

1 2

0.1uF_16V

C1019

1
2

1uF_25V

C1018

R1028

1 2

1 3

0.1uF_16V

1

D1003

BAT54_30V_0.2A

2

C1020
1uF_10V

1

R1001

24.9K_1%

2

JACK1001

1
2

G

3

G

4

C1017

1
2

12

G1
G2

7-,9-,10-,11-,12-,13-,14-,35-,57-

1uF_25V

C1035

1

1

2

2

0.1uF_25V

C1003

1
2

0.1uF_25V

C1023

1
2

C1022

C1021

1
2

4.7uF_25V

4.7uF_25V

4.7uF_25V

CHANGE by

5-

5-,7-

R1008

1 2

3K_5%

8

765

D

Q1002

G

FDMC8884

S

123

4

8D765

G

4

123

PCMB0603T_8R2MS

Q1052

FDMC8884

S

L1001

1 2

C1007
C1008

4.7uF_25V

4.7uF_25V

1
2

Icharger=3A

CELLSEL#=0,Vcharger=12.6V
CELLSEL#=1,Vcharger=16.8V

Jason Chiu 20-Jul-2009

+VBDC+VBAT+VADPBL

5-,6-,7-

Q1004

8

1

D

S

7

2

6

3

D1004

1

RLZ18C2

4

G

AM4825P_AP

5

+VBDCR

+VBDC

R1007

0.01_1%

1 2

1

R1005
0_5%

2

C1005

0.033uF_16V
2

1

1

R1004
0_5%

2

1
2

5-,6-,7-

C1010

1

1

C1009

2

2

4.7uF_25V

4.7uF_25V

Kevin sense

C1006

1uF_25V

1
2

C1004

1uF_25V

1
2

Note:

high power trace

INVENTEC

TITLE

Piaget 2.0 Discrete

DC & BATTERY CHARGER

CODE

SIZE

A3

DOC. NUMBER

1310A22683-0-MTRA02

CS

SHEET

REV

OF

605

CHGCTRL_3

5-,40-

1

1K_5%

R57

2

D10

1SS355W

2 1

C52

0.047uF_16V

+V3AL

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

+V3AL

1

R1013
10K_5%

2

D1007

3

DIODE_BAV99

1 2

100_5%

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

1

R1014
10K_5%

2

R1012

THM_MAIN#

1

D1005

3

2

DIODE_BAV99

1

R142

100K_5%

2

1

R61
220K_5%

2

3

D

Q10

1

G

2N7002W

S

2

1

1

R58
470K_5%

2

2

MMBT3906

5-

Q1059

CHGEN#

+VBDC +VBATA

2

E

1

B

C

3

5-

ACDET

5-,7-

POWERPAD_2_0610

PAD1001

SDA_MAIN
SCL_MAIN

40­40-

+V3AL

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

1

D1006

2

DIODE_BAV99

100K_5%

R1015

1 2

100_5%

40-

470pF_50V

1

3

2

+V3AL

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

1

R1010

2

1

1

C1011

2

2

C5018

100pF_50V

R1009

1 2

1K_5%

1
2

C5017

100pF_50V

1
2

C1012

0.1uF_25V

SYN_081006_TK001_6P

1

1

2

2

3

3

4

4

5

5

6

6

1

C5016

0402_OPEN

2

CN1001

G
G

G1
G2

INVENTEC

TITLE

Piaget 2.0 Discrete

SELECT & BATTERY CONN

SIZE

CODE DOC. NUMBER

A3

CHANGE by SHEET

20-Jul-2009Jason Chiu

CS

OF

6 60

REV

A021310A22683-0-MTR

+V3A

5-,9-,13-,14-,35-,37-,38-,39-,51-,53-,55-,57-

PAD8

POWERPAD_2_0610

C811 1

1uF_6.3V

2

C5013

1uF_16V

R472

2

6.8K_1%

C723

0402_OPEN

1

C810

220uF_6.3V

DEBUG_KBCRST

7-,40-

+VADPBL

1

R5040

2

11.5K_1%

1 2

DEBUG_KBCRST

R426

2

1

10K_1%

0402_OPEN

L56

1

0402_OPEN

5-

1

R5039

255K_1%

2

1

1

2
3

2

FAIR_LMV321AS5X_SOT23_5P

2

R1274

R5042

220K_5%

R5043

470K_5%

U5002

+IN

-VS

-IN

CYNTEC_PCMC063_3R3

KBC_PWR_ON

1

51125GND

+VBATR

1

C1455

2

1

2

C1454

1
2

0402_OPEN

+V5AL

5-,7-,8-,55-

1

1
2

2

1

2

5

+VS

4

OUT

R470

1 2

40-

330K_5%

D5006

1SS355W

7-,40-

21

+V3AL

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

1

1
2

C1456

0603_OPEN

C5015

10uF_6.3V

ANPEC_APL5325_BI_TRG_SOT23_5P

12

+V5AL

1 2

680K_5%

4.7uF_25V

2

U5003

3 4

VIN

2

GND

1

C5021

0.1uF_16V

5-,7-,8-,55-

R5041

2 1

1SS355W

C1457

Q1048

FDMC8296

VOUT

5

SETSHDN

R5044

16.5K_1%

D5013

5-,13-,14-,38-,40-,49-,51-,54-

R424
100K_5%

2N7002W

1

C721

2

0.1uF_16V

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

PAD5002

1

POWERPAD1x1m

2

C667
10uF_6.3V

8 7 6 5

D

Q1039

G

FDMC8884

C724

41S2 3

G

2 3

41

0.1uF_16V

+VBATR

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

D

S

8 7 6 5

1SS355W

SLP_S3#_3R

+V3ALP

1

R5045

64.9K_1%

2

1
2

1

R5046

20K_1%

1

2

2

+V5AL

5-,7-,8-,55-

1

2

Q66

3

D

1

G

S

2

R473

75K_1%

R474

1 2

12

4.7_5%

2VREF

5-,7-,8-,14-

R5014

1 2

0402_OPEN

D5012

2 1

2 1
D5007

1SS355W_OPEN

+V3AL

PAD5003

POWERPAD1x1m_OPEN

C5014

2.2uF_6.3V

2

5

G2

G1

S2

D1

D2

S1

4

6

3

2N7002DW

1

2

25

ENTRIP2

EN0

1

0402_OPEN

2

5

6

VFB2

13

14 SKIPSEL

R5015

4

VREF

TONSEL

VIN

15 GND

1

ROHM_RLZ242

3

VFB1

VREG5

16

D5009

51125GND

2

1

ENTRIP1

PGOOD

VBST1
DRVH1

DRVL1

VCLK

17

18

51125GND

TML

7

VO2

8

VREG3

9

VBST2
DRVH2

11

LL2

12

DRVL2

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

Q57

1

1

R425

68.1K_1%

2

2VREF

5-,7-,8-,14-

C661

1

0.22uF_6.3V

2

R423

12

0_5%

51125GND

24

VO1

R429

12

23
22
2110
20

LL1

19

TI_TPS51125_QFN_24P

+V5AL

1
2

33_5%

U31

5-,7-,8-,55-

C666

10uF_6.3V

1 2

R5016

1 2

100_5%

1

C665

2

4.7uF_25V

38-,40-

R430

4.7_5%

5-,6-

D5008

DAN202K

1 2

3

RSMRST#

C664

0.1uF_16V

1 2

+VADP+VBDC

40-

5-,8-

+VADP_DEBUG

10uF_6.3V

R427

1 2

10K_1%

51125GND

8765

C1388

4.7uF_25V

D

Q1033

G

FDMC8884

4 1S23

8765

D

Q1047

G

FDMC8296

4 1S23

+V3S

10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

1

R1210

C1341

1 2

2

10K_5%

R1257

2

1

15.4K_1%

C1413

1 2

0402_OPEN

1

1

2

2

C1386

4.7uF_25V

1

R1246

10_5%

2

C1384

1
2

2200pF_50V

U1013

ANPEC_APL5315_12BI_TRL_SOT23_5P

3

VIN4VOUT

SHDN

2

SET

GND

1
2

C1387

0402_OPEN

51

+VBATR

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

1
2

0603_OPEN

C1385

L38

1 2

CYNTEC_PCMC063_3R3

200mA

+V2.5S

18-

1

R1208
22K_1%

2

1
2

1

R1209
10K_1%

2

1

2

330uF_6.3V

C1340

10uF_6.3V

C601

PAD3

POWERPAD_2_0610

C662

1
2

1uF_6.3V

+V5A

9-,10-,11-,12-,13-,14-,35-,44-,57-

5A

DEBUG_KBCRST SCHEMATIC , MV OPEN

CHANGE by

INVENTEC

TITLE

Piaget 2.0 Discrete

+V5A,+V3A&+V2.5S

CS

SHEET

DOC. NUMBERSIZE

7 60

12-Aug-2009Jason Chiu

A3

REVCODE

A021310A22683-0-MTR

OF

+V5S

13-,14-,23-,29-,34-,35-,37-,38-,41-,43-,48-,49-,53-,57-,58-

BQREF

LIMITsignal

R1058

1 2

ICS

5-,8-

10K_5%

5-

55-

1 2

R1060

169K_1%

R1062

1 2

100_5%

VBIAS

BSS84_3P

8-

OCP_IN_ADC ICS

U1006

1
2
3

TI_LMV321IDBVR_SOT23_5P

1

R1059
100K_1%

2

Q1014

2

3

D

S

1SS355W

G

1

40-

Vcc+

1IN+
GND

OUT

1IN-

1 2

C1044

0.22uF_10V

D1014

2 1

1
2

D5010

1

RLZ4.7B

2

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

5

4

1SS355W 2

D1013

C1046

3900pF_16V

1

R1087
2K_1%

2

1

1

R1070

3.9K_1%

2

+V3AL

R1068

1 2

100K_5%

1

R5017

100_5%

2

1
2

C1045

0.1uF_10V

1

1

B

3

C

Q1015

B

E

D_MMST3904

2

2

E

Q1054

C

MMBT3906

3

5-

1

R1074

8.06K_1%

2

12

R1072

8.66K_1%

1

R1054

45.3K_1%

2

I_SET

+VADP

2

1

OCP_OC

5-,7-

R1076
68K_1%

1

R1075

33.2K_1%

2

1

R1085

4.7K_1%

2

2 1

1SS355W

D1015

40-

8-

1

R5048

27.4K_1%

2

C5019

1
2

0.01uF_16V

VBIAS

2VREF

5-,7-,14-

1

R1078
130K_1%

2

1

2

R5049

1 2

100K_1%

R1077
10K_1%

1

R5051

100K_1%

2

1

R1083
10K_1%

2

R5047

1 2

0402_OPEN

R5054

1 2

200K_1%

3

+

OUT

2

-

R5050

1 2

100K_1%

+V5AL

5-,7-,8-,55-

8

U1007-A

1

AS393MTR_E1

4

+V3AL

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

5

+

OUT

6

-

R5052

0_5%

1
2

R1079

1 2

1M_5%

8

U1007-B

7

AS393MTR_E1

4

C1049

1uF_25V

40-

2N7002W

1

2

R1061

1 2

0_5%

Q1013

3

D

G

1

S

2

+V3AL

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

1

R5053

10K_5%

2

ADP_ID_ADC

+V3AL

5-,6-,7-,8-,36-,38-,40-,41-,42-,53-,55-

1

R1080
47K_5%

2

18-,23-

R5029

1 2

0_5%

PROCHOT#

40-

5-,8-

ADP_DET#

R5037

1 2

11K_5%

1uF_10V

C5006

+V5AL

5-,7-,8-,55-

U5001

1

1IN+

2

GND

3
1
2

1IN-

TI_LMV321IDBVR_SOT23_5P

1

R5018

49.9K_1%

2

2

39.2K_1%

Vcc+

OUT

R5019

5

4

1

40-

PMC

Jason Chiu 20-Jul-2009

INVENTEC

TITLE

Piaget 2.0 Discrete

OCP

CODE

SIZE DOC. NUMBER REV

A3

1310A22683-0-MTRA02

CS

SHEETCHANGE by OF

608

+VCC_NB

27-

PAD2

POWERPAD_2_0610

51124GND

1

R272

4.64K_1%

2

1

R304
10K_5%

2

C1337

4.7uF_25V

1

2

+VBATR

C1336

4.7uF_25V

1
2

PCMC063T_1R5MN

C5010

330uF_2.5V

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

C1334

0402_OPEN

1

1

1

2

2

2

C1335

0.1uF_25V

L22

1

2

R1185

10_5%

1

C1272

2200pF_50V

2

1

2

8 7 6 5

9

D

8 7 6 5

D

1S2 3

G

41S2 3

G

4

Q1020

FDMC8884

Q1019

FDMS8670S

PWR_GOOD_3

R313

1 2

0_5%

R273

R274

1 2

0_5%

10K_5%

12

1
2

9-,10-,11-,14-

C416

1 2

0.1uF_16V

TI_TPS51124RGER_QFN_24P

R316

51124GND

1 2

0_5%_OPEN

4

3

GND

VFB12VFB2

U20

TRIP1

V5IN

17

15

16

1

R317

2

5.1K_1%

5

TONSEL

V5FILT

14

51124GND

TRIP2

1

R315

2

10K_1%

6

VO2

PGOOD2

PGND2

13

1

VO1

25

GND

24

PGOOD1

23

EN1

22

VBST1

21

DRVH1

20 11

LL1

19

DRVL1

C415

PGND1

1000pF_50V

18

VBST2

DRVH2

DRVL2

+VBATR

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

C1369

C1366

C1368

1

Q1023

FDMC8884

Q1058

FDMC8296

4.7uF_25V

1
2

0402_OPEN

1

2

2

L33

1 2

PCMC063T_1R5MN

1

R1239

0402_OPEN

2

330uF_2.5V

C1370

4.7uF_25V

7

R307

8

EN2

R309

9

10

LL2

12

1 2

C500

1
2

0402_OPEN

0_5%

V1.2S_PG

9-,10-,11-,14-

0_5%

12

PWR_GOOD_3

C502

0_5%

1 2

0.1uF_16V

12

R306

G

4 1

G

4 1S23

8765

D

S

23

8765

D

+V5A

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

R314

1 2

1
2

C506

1uF_6.3V

10_5%

C1331

1
2

4.7uF_6.3V

1
2

C1332

0.1uF_10V

1
2

0402_OPEN

C5011

1
2

1

2

C1367

0.1uF_25V

R305

6.04K_1%

51124GND

1

2

0402_OPEN

1

R303
10K_1%

2

+V1.2S

11-,15-,18-,19-,27-,36-,37-,57-

PAD7

POWERPAD_2_0610

C499

1
2

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

ANPEC_APL5930KAI_TRL_SOP_8P

R629

1

10K_5%

C1552

1
2

0.1uF_10V

5-,7-,13-,14-,35-,37-,38-,39-,51-,53-,55-,57-

U51

7

POK

2

8 2

EN

+V3A+V5A

+V1.2A

1

C874

10uF_6.3V

VOUT
VOUT

VIN

FB

5

3
4

10uF_6.3V

2

C1496

6

VCNTL

VIN

GND

9

1

37-

1

R628

4.75K_1%

2

1

R548

1

2

2

10K_1%

INVENTEC

TITLE

Piaget 2.0 Discrete

+VCC_NB & +V1.2A

CHANGE by

SIZE REVDOC. NUMBERCODE

A3

CS

14-Aug-2009Jason Chiu

SHEET

9 60

A021310A22683-0-MTR

OF

PWR_GOOD_3

VDD1_FB#

VDD1_FB

SYS_PWRGD

NBV_BUF

CPU_SVC_R
CPU_SVD_R

18-

18-

NB_GNDS
NB_SKIP#

11-,40-

11-

9-,11-,14-

18­18-

11-

1

R32
10K_5%

2

COREFB

COREFB#

0402_OPEN

R3

1 2

100K_1%

100_1%

18­18-

+V3S

R43

1

2

7-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

1

R41

4.7K_5%

2

R39

1 2

1000pF_50V

R44

C37

1
2

0.0047uF_50V

MAX17009

MAX_MAX17009GTL+_TQFN_40P

R40 100_1%

1

36.5K_1%

1 2

1 2

R37

154K_1%

1

C34

2

+VCC_CORE

+V1.8

10-,18-,19-,57-

1

C29

1 2

0.0047uF_50V

R28

1 2

10_1%

1

R1019

11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

51_5%

2

R31

R29

1
2

MAX17009

R1018

2

MAX17009

MAX17009

C35

1 2

R42

2

2

0.0047uF_50V

2

C9

0.22uF_6.3V

1

1 2

2

2

C32

1 2

2

C31

1000pF_50V

R78

1000pF_50V

1.2K_1%

1

100_1%

1

C36

2

R36

121K_1%

R34

10K_1%

C8

0.0047uF_50V

100_1%

1

1.2K_1%R30

1

1000pF_50V

1.5K_1%

1

+V5A

1.5K_1%

1

2

1

2

MAX17009

4011

FBDC1FBDC2

GNDS1

1

PERGD

2

NV_BUF

3

SHDN#

4

REF

5

ILIM

6

OSC

7

TIME

8

SVC

9

SVD

10

THRM

GNDS215GNDS_NB

1
2

MAX17009

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

R73

1 2

10_5%

39

12

38

FBAC1FBAC2

13

37

PGD_IN

OPTION

VDDIO

14

C1026

1
2

1

SBR3U40P1

2

C1024

1
2

C1030

1
2

D1012

C1029

1
2

0603_OPEN

1

R105
1K_5%

2

C84

220pF_50V

+VBATR

1

C69

2

47uF_25V

1

R79
22_5%

2

C66

1
2

1000pF_50V

ETQP4LR45XFC

1 2

1

R106

2.4K_1%

2

R104

1 2

4.02K_1%

1

R110
1K_5%

2

C89

1
2

220pF_50V

L3

R103

1 2

10K_1%_THER_NTC

C33

1 2

0.22uF_10V

C63

R109

1 2

4.02K_1%

1

R107

2.4K_1%

2

ETQP4LR45XFC

0.22uF_10V

1 2

R108

1 2

10K_1%_THER_NTC

L4

1 2

C108

330uF_2V_6mR

1

C1055

2

330uF_2V_6mR

+VCC_CORE

1

1

2

2

+VCC_CORE

1

2

10-,18-,19-,57-

C1056

330uF_2V_6mR

10-,18-,19-,57-

C106

330uF_2V_6mR

(Should routed in 5/5/5 pair and need to
have 10mil clearance to other traces.)

C1025

C1028

1

1

2

2

0603_OPEN

38-,40-

SB_PWRGD

0402_OPEN

G

4

R45

1 2

0_5%

R77

1 2

0_5%

MAX17009

2

C57

0.1uF_16V

1

1

2

R75

4.7_5%

R1020

0_5%

12

+V5A

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

C1027

1
2

4.7uF_6.3V

MAX17009

32

3120

36

33

35

3417

DH1

CSP1

CSN1CSN2

PRO#

TMLPAD

VRHOT#

LX1
BST1
VDD1

DL1

GND1

U2

GND2

DL2
VDD2
BST2

LX2

VCC

NBSKP#

DH2

CSP2

18

19

16

MAX17009

41
30
29
28
27
26
25
24
23
22
21

1

R74

4.7_5%

2

C56

1
2

0.1uF_16V

4

Q1012

G

FDMS7660

4

1
2

+VBATR

C1041

1

8D765

2

Q1010

G

FDMS8692

S

12

3

8765

D

1

2

1
2

1uF_6.3V

C55

FDMS7660

(Should routed in 5/5/5 pair and need to
have 10mil clearance to other traces.)

Q1011

G

4S123

C1054

1
2

4700pF_25V

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

C1032

1

8D765

2

Q1005

S

FDMS8692

123

8D765

S

123

C1043

4700pF_25V

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

C1042

C1031

1

1

2

2

4.7uF_25V

0402_OPEN

4.7uF_25V

4.7uF_25V

1

R76
22_5%

D1011

2

SBR3U40P1

C87

1
2

1000pF_50V

4.7uF_25V

4.7uF_25V

4.7uF_25V

1
2

MAX17009

CHANGE by

Jason Chiu 20-Jul-2009

INVENTEC

TITLE

Piaget 2.0 Discrete

+VCC_CORE

SIZE CODE

A3

DOC. NUMBER

1310A22683-0-MTRA02

CS

SHEET

REV

OF

6010

+VCC_CORE_NB

19-

PAD5

POWERPAD_2_0610

220uF_2.5V

C599

R339

12

10-,11-,40-

NB_SKIP#

1
2

8792GND

SYS_PWRGD

C1344

100pF_50V

8792GND

1

R1211
0402_OPEN

2

R1213

1 2

0_5%

1

R1214
0402_OPEN

2

R333

80.6K_1%

1

2

10-

C524
12

1000pF_50V

R332

1

0402_OPEN

NBV_BUF

2

8792GND

0_5%

C531

1
2

1uF_6.3V

14

8792GND

13
12
11
10
9
8

FB

15

10-

8792GND

1
2

0402_OPEN

R331

R1215

12

+V5A

C1383
1

2

4.7uF_25V

1

2

1
2

C1343

1
2

1uF_6.3V

C1342

1
2

0402_OPEN

5
6
7

4

C1346

0402_OPEN

1

0603_OPEN

2

Q1024

S1_D2

S2

FDS6900AS

C1345

D1 1

G1 8

PWR_GOOD_3

R328

12

0_5%

0.22uF_16V

R1212

100K_1%

2

3G2

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

5-,7-,9-,10-,12-,13-,14-,35-,57-

+VBATR

C1382

4.7uF_25V

L37

2

1

1

2

CYNTEC_PCMC063_3R3

R330

12

C525
12

5.76K_1%

1.5K_1%

0.22uF_16V

9-,10-,11-,14-

C526

12

12

R338

1 2

0_5%

U24

1

EN

PGOOD

2

VCCVDD

3

SKIP

DL

4

LX

REF

5

DH

REFIN

6

BST

ILIM

7

TON

MAX_MAX8792ETD+T_DFN_14P

TML-PAD

R324

1 2

0_5%

PWR_GOOD_3

9-,10-,11-,14-

9-,15-,18-,19-,27-,36-,37-,57-

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

U1008

1

2

3

RICH_RT9194PE_05P_SOT23_6P

6

EN

VCC

5

GND

DRI

4

FB

PGOOD

+V5A

1
2

1 2

C1053

0.1uF_10V

10-,11-,40-

R1086

0_5%

+V1.2S

1
2

Q1018

8

D

7

6

5 4

G

FDMC8296

SYS_PWRGD

C1062

4.7uF_10V

1

S

2
3

24-,25-,26-,27-,28-,29-,30-,57-

1

R1088

4.12K_1%

2

1

R1089

10K_1%

2

+V1.1S

1

2

C1061

220uF_2.5V

+V1.8

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

+V5A

C1574

1

1
2

2

0.1uF_10V

10-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

ANPEC_APL5910KAI_TRL_SOP_8P

1

PWR_GOOD_3

C635

10uF_10V

2

9-,10-,11-,14-

3
4

CHANGE by

POK
EN FB

U33

VIN6VOUT
VCNTL

+V1.5S

54-

9

GND

8

GND

7

5

NC

1

R411

9.1K_1%

2

1

R449
10K_1%

2

1

2

C633

10uF_10V

INVENTEC

TITLE

Piaget 2.0 Discrete

POWER

SIZE CODE

20-Jul-2009Jason Chiu

A3

CS

SHEET

DOC. NUMBER

11 60

REV

A021310A22683-0-MTR

OF

+VBATR

5-,7-,9-,10-,11-,13-,14-,35-,57-

V18_GOOD

SLP_S5#_5R

+V5A

7-,9-,10-,11-,13-,14-,35-,44-,57-

R397

1 2

10_5%

U27

MAX_MAX17000ETG+_TQFN_24P

1

OVP

17000GND

2

PGOOD1

3

PGOOD2

19

VDD

23

VCC

21

AGND

4

STDBY

24

SHDN

22

SKIP

10

REFIN

25

GND

13-

R398

1 2

13-

0_5%

1

1uF_6.3V

C614

3300pF_50V12

2

C613

R396

0_5%

PGND1

PGND2

12

VTTR

VTTS

14

TON

17

BST

15

DH

16

LX

18

DL

20

13

CSH

12

CSL

11

FB

9

VTTI

7
8

VTT

5
6

R395

1 2

0_5%

C539
2

1uF_6.3V

10uF_6.3V

C611

2

1

C542

17000GND

1

0.1uF_16V

1
2

+V0.9S

19-,22-

C541
1
2

10uF_6.3V

1

R394
200K_5%

2

M_VREF

20-,21-

1
2

FDMS8670S

C615

0.033uF_16V

Q47

FDMC8884

Q48

1

8D76

5

2

4.7uF_25V

G

4.7uF_25V

S

4

123

9

8765

D

G

1

4 1S23

2

C609

C607

1
2

0603_OPEN

PCMC063T_2R2MN

1

R1258

0402_OPEN

1

R1218

2

10K_1%

2

C1415

0603_OPEN

C612

0.22uF_16V

C610
1
2

L1024

1 2

R1217

1 2

806_1%

1 2

1

C606

2

0402_OPEN

17000GND

1

R347

8.45K_1%

2

1

R346
10K_5%

2

1

C1414

2

330uF_2V_9mR_Panasonic

10-,11-,13-,18-,19-,20-,21-,22-,23-,38-,57-

POWERPAD_2_0610

+V1.8

PAD1002

NOTE: DDR2 REGULATOR

CHANGE by

INVENTEC

TITLE

Piaget 2.0 Discrete

DDR2 POWER

SIZE

CODE DOC. NUMBER

A3

CS

20-Jul-2009Jason Chiu

SHEET

12 60

REV

A021310A22683-0-MTR

OF

GATE_5S

+V5A

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

Q38

6

D

5
2

1

G

FDC655BN

13-

+V5S

8-,14-,23-,29-,34-,35-,37-,38-,41-,43-,48-,49-,53-,57-,58- 7-,10-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

4

S

3

47_5%

R401

1

Q37

G

1
2

1

2

3

D

S

2

SSM3K7002F

C616
10uF_6.3V

+V3A

5-,7-,9-,14-,35-,37-,38-,39-,51-,53-,55-,57-

Q1041

6

D

5
2

1 3

G

FDC655BN

C1517

1 2

13- 13-

1000pF_50V_OPEN

+V3S

+V1.8

Q1022

8

4

S

R1256

47_5%

Q1025

1

G

1

2

1

2

3

D

S

2

SSM3K7002F

C1411

100uF_6.3V

GATE_3SGATE_5S

D

S

7

6
5 4

G

SI7230DN

1
2
3

2

C1348

1

1000pF_50v

Q1026

1

+V1.8S

G

14-,18-,24-,26-,27-,30-,38-,57-10-,11-,12-,18-,19-,20-,21-,22-,23-,38-,57-

1
2

1

R1216
47_5%

2

3

D

S

2

SSM3K7002F

C1347
10uF_6.3V

13-,14-,58-

SLP_S3_5R

SLP_S3#_3R

V18_GOOD

SLP_S3_5R

5-,7-,13-,14-,38-,40-,49-,51-,54-

12-

13-,14-,58-

R437

1 2

4.7K_5%

+VBATR +VBATR

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

1

R436
100K_5%

2

1

R438
470K_5%

2

Q60

1

S1

2

G1

6

D1

3

D2

5

G2

4

S2

2N7002DW

5-,7-,9-,10-,11-,12-,13-,14-,35-,57-

E

E

Q59

B

B

D-MMST3906

C

C

R402

1 2

100K_5%

R399

1 2

470_5%

1

C617

2200pF_50V

2

1

R400
20K_5%

2

13-

GATE_5S SLP_S5#_3R

13-

GATE_3S

38-,44-

SSM3K7002F

SSM3K7002F

SLP_S3#_3R

+V5A

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

1

R567
10K_5%

3

D

S

2

3

D

S

2

5-,7-,13-,14-,38-,40-,49-,51-,54-

2

1

R568

100K_5%

2

Q79

1

G

Q74

G

1

CHANGE by SHEET

+V5A

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

1

R566
3K_5%

2

20-Jul-2009Jason Chiu

12-

51-

SLP_S5#_5R

SLP_S5_FPR

INVENTEC

TITLE

Piaget 2.0 Discrete

POWER(Sleep)

SIZE

CODE DOC. NUMBER

A3

CS

OF

13 60

REV

A021310A22683-0-MTR

POW_SW1
POW_SW0

SLP_S3#_3R

28-

28-

95.3K_1%

R1233

1 2

5-,7-,13-,38-,40-,49-,51-,54-

0_5%

C1365

0.022uF_16V_OPEN

1
2

R1235

1

2

C1330

0.1uF_16V

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

+VDD_FB

14-

R1238

14.7K_1%

R1232

75K_1%

1

2

1

2

VGAP_AGND

R1236
10K_1%

1

2

1
2

+V5A

1

2

C1333

1
2

470pF_50V

1

R1234
100K_5%

2

R1237

37.4K_1%

1
2

1

R1204

75K_1%

2

1 2

75K_1%

C1329

220pF_50V

1 2

37.4K_1%

12

11

9

R1202

R1203

EN

PGOOD

VOUT

FB

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

SEMTECH_SC471A_MLPQ_16P

13

14G015

16

U1014

G1

DH

ILIM

GND

RTN

D08D1

5

6

7

VGAP_AGND

R1231

1 2

5.11K_1%

LX

BST

VCC

DL

PAD

17

1

2

310

4

1

R1201

0_5%

DAP202K

R1230

1

2

0_5%

+V5A

2

3

12

D1017

C1363

0.1uF_16V

1 2

Q1030

FDMC8884

+V5A

7-,9-,10-,11-,12-,13-,14-,35-,44-,57-

C1362

1
2

1uF_6.3V

1
2

C1063

2200pF_50V

G

4 1S23

G

4 1

8765

8765

23

C1081

4.7uF_25V

D

9

D

Q1029

FDMS8670S

S

+VBATR

5-,7-,9-,10-,11-,12-,13-,35-,57-

C1364

4.7uF_25V

1

1
2

2

C1398

1
2

4.7uF_25V
L42

1 2

PCMC104T_1R0MN

10uF_6.3V_OPEN

+VDD_FB

14-

C629

+VDD_CORE

30-,57-

PAD6

POWERPAD_2_0610

1

1
2

C631

330uF_2v_9mR_Panasonic

2

+V1.8S

13-,18-,24-,26-,27-,30-,38-,57-

8-,13-,23-,29-,34-,35-,37-,38-,41-,43-,48-,49-,53-,57-,58-

+V5S

R1242

1 2

100K_1%

R1241

1 2

280K_1%

C1371

1000pF_50V

SLP_S3_5R

+V3S

R1205

1 2

1M_5%

5-,7-,9-,13-,35-,37-,38-,39-,51-,53-,55-,57-

R1207

1 2

U1012

1
3

+

OUT

-

R1240

20K_5%

2

1

1

1

R1243

2

54.9K_1%

2

13-,58-

SSM3K7002F

Q1021

1

2VREF

5-,7-,8-

R1244

1 2

100K_1%

3

D

G

S

2

1
2

100K_1%

C1372
4700pF_25V

+V3A

5

4

TI_LMV331IDBVR_SOT23_5P

2

C1339

1
2

0.1uF_16V

7-,10-,13-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

1

R1206

1.2K_1%

2

9-,10-,11-

PWR_GOOD_3

INVENTEC

TITLE

Piaget 2.0 Discrete

POWER(Sequence)

CHANGE by

Jason Chiu 14-Aug-2009

CODE

A3

1310A22683-0-MTRA02

CS

SHEET

REVDOC. NUMBERSIZE

OF

6014

7-,10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

CLK_R_PCIE_NEWCARD#
CLK_R_PCIE_NEWCARD

CLK_R_PCIE_MINICARD1#
CLK_R_PCIE_MINICARD1

CLK_R_PCIE_LAN#
CLK_R_PCIE_LAN

7-,10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

7-,10-,13-,14-,15-,20-,21-,23-,26-,27-,29-,30-,35-,36-,37-,38-,39-,40-,41-,42-,45-,46-,47-,49-,50-,51-,53-,54-,55-,57-,58-

Q1031

CPPE_NC#

38-,54-

3

SSM3K7002F

+V3S

SB_3S_SMCLK

SB_3S_SMDATA

54­54-

53­53-

51­51-

+V3S

1

G

S

D

2

CLK_R_PCIE_ALINK#

CLK_R_PCIE_ALINK

L1023

1 2

600OHM_25%

20-,21-,23-,29-,38-,42­20-,21-,23-,29-,38-,42-

+V3S

1

R392
10K_5%

2

CLK_R_PCIE_SB#
CLK_R_PCIE_SB

1
2

26­26­36­36-

C1381

22uF_6.3V

+V3S_CLK

VGA_PCIE_CLK#
VGA_PCIE_CLK

15-

1
2

R414

1 2

10K_5%

C1377

0.1uF_16V

CLK_DVI#
CLK_DVI

WL_OFF

C1403

1
2

0.047uF_10V

+V3S_CLK

29-

TP24

29-

TP25

26-

TP27

26-

TP26

53-

CLK_R_PCIE_ALINK#
CLK_R_PCIE_ALINK
CLK_R_PCIE_SB#

CLK_R_PCIE_SB

CLKGEN_X1
CLKGEN_X2

C1378

1
2

0.047uF_10V

+V3S_CLK

L1022

15-

BLM11A121S

1 2

L35

15-

BLM11A121S

45
46

10
13
14
15
16
20
21
22
23

42
43
50
51
24

25
26
30
31
32
33

34
35
39
40
41
67
68

1 2

C596

0.1uF_16V

U30

1

SMBCLK

2

SMBDAT

4

SRC7C_LPRS_27MHZ_NS

5

SRC7T_LPRS_27MHZ_SS
SRC6C_SATAC_LPRS
SRC6T_SATAT_LPRS

7

SRC5C_LPRS

8

SRC5T_LPRS

9

SRC4C_LPRS
SRC4T_LPRS
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS

CLKREQ4#
CLKREQ3#
CLKREQ2#
CLKREQ1#
CLKREQ0#

ATIG2C_LPRS
ATIG2T_LPRS
ATIG1C_LPRS
ATIG1T_LPRS
ATIG0C_LPRS
ATIG0T_LPRS

SB_SRC1C_LPRS
SB_SRC1T_LPRS
SB_SRC0C_LPRS
SB_SRC0T_LPRS
SB_SRC_SLOW#
X1
X2

+V3S_CLK_VDDA

1
2

ICS_ICS9LPRS476KLFT_MLF_72P

1
2

+V3S_CLK_VDDREF
C1376

2.2uF_6.3V

C595

10uF_6.3V

VDDA

VDD48
VDDDOT
VDDREF
VDDHTT
VDDCPU

VDDSB_SRC

VDDATIG

VDDSRC

VDDSATA

VDDCPU_IO

VDDSB_SRC_IO

VDDATIG_IO

VDDSRC_IO
VDDSRC_IO

48MHZ_0

48MHZ_1
HTT0T_LPRS_66M
HTT0C_LPRS_66M

CPUKG0T_LPRS
CPUKG0C_LPRS

PD#

REF0_SEL_HTT66

REF1_SEL_SATA

REF2_SEL_27

GND48
GNDREF
GNDHTT

GNDCPU

GNDA

GNDSATA

GNDSB_SRC

GNDATIG
GNDSRC
GNDSRC
GNDDOT

THERMAL-PAD

+V3S_CLK

C1374

47pF_50V_OPEN

1
2

1
2

49
69
3
62
61
54
38
29
17
44
53
37
28
18
12

71
70

NBHT_CLK

60

NBHT_CLK#

59

CLK_R_CPUBCLK

56
55

CLK_R_CPUBCLK#

57
65
64
63

72
66
58
52
48
47
36
27
19
11
6

73

15-

1
2

C1399

1
2

0.1uF_16V

C590

12pF_50V_OPEN

C1375

0.1uF_16V

1
2

CLK_48M

CLK_48M_1

C1373

1
2

0.1uF_16V

C636

1
2

0.1uF_16V

R382

1 2

33_5%

R383

1 2

33_5%

26­26-

C589

1
2

12pF_50V_OPEN

C641

1
2

0.047uF_10V

1
2

C582

1
2

4.7pF_50V_OPEN

NBHT_CLK
NBHT_CLK#

SB700_R_J21

CLK_R3S_NB14

CLK_KBC&SB14

C1400

1
2

0.1uF_16V

+V1.2S_CLK_IO

C584

4.7pF_50V

1

R385

8.2K_5%

2

1
2

C1402

1
2

0.047uF_10V

1

2

R389

1 2

1

R388

8.2K_5%_OPEN

2

C1401

0.1uF_16V

1
2

38-

CLK_R3S_SB48

46-

CLK_R3S_FM48

R1245
261_1%_OPEN

33_5%

C1380

47pF_50V_OPEN

18-

CLK_R_CPUBCLK

18-

CLK_R_CPUBCLK#

36-

15-

40-

+V1.2S_CLK_IO

C1379

1
2

1uF_10V

SB700_R_J21
CLK_R3S_NB14
CLK_R3S_KBC14

+V1.2S

9-,11-,18-,19-,27-,36-,37-,57-

L43

BLM11A121S

12

C637

1
2

10uF_6.3V

+V3S_CLK

1

1K_5%

15-

2

R390

X1

2

1

1
2

C516

27pF_50V

14.31818MHZ

30PPM

1
2

C515

27pF_50V

Place close to CLKGEN within 500mils

NBGFX_CLK

R387

1

R386

90.9_1%

2

1 2

158_1%

15-

CLK_R3S_NB14

26-

INVENTEC

TITLE

Piaget 2.0 Discrete

CLOCK_GENERATOR

SIZE

CHANGE by SHEET OF

12-Aug-2009Jason Chiu

A3

CS

DOC. NUMBER

15 60

REVCODE

A021310A22683-0-MTR

L0_CLKIN1
L0_CLKIN1#
L0_CLKIN0
L0_CLKIN0#

L0_CTLIN1

L0_CTLIN1#
L0_CTLIN0
L0_CTLIN0#

L0_CADIN15
L0_CADIN15#
L0_CADIN14
L0_CADIN14#
L0_CADIN13
L0_CADIN13#
L0_CADIN12
L0_CADIN12#

L0_CADIN11

L0_CADIN11#

L0_CADIN10

L0_CADIN10#

L0_CADIN9
L0_CADIN9#
L0_CADIN8
L0_CADIN8#

L0_CADIN7
L0_CADIN7#
L0_CADIN6
L0_CADIN6#
L0_CADIN5
L0_CADIN5#
L0_CADIN4
L0_CADIN4#
L0_CADIN3
L0_CADIN3#
L0_CADIN2
L0_CADIN2#
L0_CADIN1
L0_CADIN1#
L0_CADIN0
L0_CADIN0#

CN12-1

24­24­24­24-

24­24­24­24-

24­24­24­24­24­24­24­24­24­24­24- 24­24­24­24­24­24-

24­24­24­24­24­24­24- 24­24­24­24­24­24­24­24­24- 24­24-

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

N5

L0_CADIN_H15

P5

L0_CADIN_L15

M3

L0_CADIN_H14

M4

L0_CADIN_L14

L5

L0_CADIN_H13

M5

L0_CADIN_L13

K3

L0_CADIN_H12

K4

L0_CADIN_L12

H3

L0_CADIN_H11

H4

L0_CADIN_L11

G5

L0_CADIN_H10

H5

L0_CADIN_L10

F3

L0_CADIN_H9

F4

L0_CADIN_L9

E5

L0_CADIN_H8

F5

L0_CADIN_L8

N3

L0_CADIN_H7

N2

L0_CADIN_L7

L1

L0_CADIN_H6

M1

L0_CADIN_L6

L3

L0_CADIN_H5

L2

L0_CADIN_L5

J1

L0_CADIN_H4

K1

L0_CADIN_L4

G1

L0_CADIN_H3

H1

L0_CADIN_L3

G3

L0_CADIN_H2

G2

L0_CADIN_L2

E1

L0_CADIN_H1

F1

L0_CADIN_L1

E3

L0_CADIN_H0

E2

L0_CADIN_L0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

HYPERTRANSPORT

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8

L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

Y4
Y3
Y1
W1

T5
R5
R2
R3

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3

T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

FOX_PZ63823_284S_41F_TEMP_638P

24-

L0_CLKOUT1

24-

L0_CLKOUT1#

24-

L0_CLKOUT0

24-

L0_CLKOUT0#

24-

L0_CTLOUT1

24-

L0_CTLOUT1#

24-

L0_CTLOUT0

24-

L0_CTLOUT0#

24-

L0_CADOUT15

24-

L0_CADOUT15#

24-

L0_CADOUT14

24-

L0_CADOUT14#

24-

L0_CADOUT13

24-

L0_CADOUT13#

24-

L0_CADOUT12

24-

L0_CADOUT12#

24-

L0_CADOUT11

24-

L0_CADOUT11#
L0_CADOUT10

24-

L0_CADOUT10#

24-

L0_CADOUT9

24-

L0_CADOUT9#

24-

L0_CADOUT8

24-

L0_CADOUT8#

24-

L0_CADOUT7

24-

L0_CADOUT7#

24-

L0_CADOUT6

24-

L0_CADOUT6#

24-

L0_CADOUT5

24-

L0_CADOUT5#
L0_CADOUT4

24-

L0_CADOUT4#

24-

L0_CADOUT3

24-

L0_CADOUT3#

24-

L0_CADOUT2

24-

L0_CADOUT2#

24-

L0_CADOUT1

24-

L0_CADOUT1#
L0_CADOUT0

24-

L0_CADOUT0#

A1

AF1

S1

Top View

A26

Layout: Add stitching caps if crossing plane split.

INVENTEC

TITLE

Piaget 2.0 Discrete

CPU-1

SIZE

CODE

CS

SHEET

DOC. NUMBER

16 60

CHANGE by OF

20-Jul-2009Jason Chiu

A3

REV

A021310A22683-0-MTR

MA_CLK_DDR2

MA_CLK_DDR2#

MA_CLK_DDR1

MA_CLK_DDR1#

MA_CS1#
MA_CS0#

MA_ODT1
MA_ODT0

MA_CAS#

MA_WE#

MA_RAS#

MA_BA2
MA_BA1
MA_BA0

MA_CKE1
MA_CKE0

MA_A(15:0)

MA_DQS(7)

MA_DQS#(7)

MA_DQS(6)

MA_DQS#(6)

MA_DQS(5)

MA_DQS#(5)

MA_DQS(4)

MA_DQS#(4)

MA_DQS(3)

MA_DQS#(3)

MA_DQS(2)

MA_DQS#(2)

MA_DQS(1)

MA_DQS#(1)

MA_DQS(0)

MA_DQS#(0)

MA_DM(7:0)

CN12-2

P19

MA_CLK_H3

N19

MA_CLK_H0

N20

MA_CLK_L0

P20

MA_CLK_L3

20­20­20­20-

20-,22­20-,22-

20-,22­20-,22-

20-,22­20-,22­20-,22-

20-,22­20-,22­20-,22-

20-,22­20-,22­20-,22- 21-,22-

MA_A(15)
MA_A(14)
MA_A(13)
MA_A(12)
MA_A(11)
MA_A(10)
MA_A(9)
MA_A(8)
MA_A(7)
MA_A(6)
MA_A(5)
MA_A(4)
MA_A(3)
MA_A(2)
MA_A(1)
MA_A(0)

20-

MA_DQS(7)

20-

MA_DQS#(7)

20-

MA_DQS(6)

20-

MA_DQS#(6)

20-

MA_DQS(5)

20-

MA_DQS#(5)

20-

MA_DQS(4)

20-

MA_DQS#(4)

20-

MA_DQS(3)

20-

MA_DQS#(3)

20-

MA_DQS(2)

20-

MA_DQS#(2)

20-

MA_DQS(1)

20-

MA_DQS#(1)

20-

MA_DQS(0)

20-

MA_DQS#(0)

20-

MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)

Y16

MA_CLK_H2

AA16

MA_CLK_L2

E16

MA_CLK_H1

F16

MA_CLK_L1

V20

MA1_CS_L1

U20

MA1_CS_L0

U19

MA0_CS_L1

T20

MA0_CS_L0

V22

MA0_ODT1

T19

MA0_ODT0

V19

MA1_ODT1

U21

MA1_ODT0

T22

MA_CAS_L

T24

MA_WE_L

R19

MA_RAS_L

J21

MA_BANK2

R23

MA_BANK1

R20

MA_BANK0

J20

MA_CKE1

J22

MA_CKE0

K19

MA_ADD15

K24

MA_ADD14

V24

MA_ADD13

K20

MA_ADD12

L22

MA_ADD11

R21

MA_ADD10

K22

MA_ADD9

L19

MA_ADD8

L21

MA_ADD7

M24

MA_ADD6

L20

MA_ADD5

M22

MA_ADD4

M19

MA_ADD3

N22

MA_ADD2

M20

MA_ADD1

N21

MA_ADD0

W12

MA_DQS_H7

W13

MA_DQS_L7

Y15

MA_DQS_H6

W15

MA_DQS_L6

AB19

MA_DQS_H5

AB20

MA_DQS_L5

AD23

MA_DQS_H4

AC23

MA_DQS_L4

G22

MA_DQS_H3

G21

MA_DQS_L3

C22

MA_DQS_H2

C21

MA_DQS_L2

G16

MA_DQS_H1

G15

MA_DQS_L1

G13

MA_DQS_H0

H13

MA_DQS_L0

Y13

MA_DM7

AB16

MA_DM6

Y19

MA_DM5

AC24

MA_DM4

F24

MA_DM3

E19

MA_DM2

C15

MA_DM1

E12

MA_DM0

FOX_PZ63823_284S_41F_TEMP_638P

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54

MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32

MEMORY INTERFACE

MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15

AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)

MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)

MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)

MB_CS1#
MB_CS0#

MB_ODT1
MB_ODT0

MB_CAS#

MB_WE#

MB_RAS#

MB_BA2
MB_BA1
MB_BA0

MB_CKE1
MB_CKE0

21­21­21­21-

21-,22­21-,22-

21-,22­21-,22-

21-,22­21-,22­21-,22-

21-,22­21-,22­21-,22-

21-,22­21-,22-

21­21­21­21­21­21­21­21­21­21­21­21­21­21­21­21­21-

20- 21-

MA_DATA(63:0)

MB_CLK_DDR2

MB_CLK_DDR2#

MB_CLK_DDR1

MB_CLK_DDR1#

MB_A(15:0)

MB_DQS(7)

MB_DQS#(7)

MB_DQS(6)

MB_DQS#(6)

MB_DQS(5)

MB_DQS#(5)

MB_DQS(4)

MB_DQS#(4)

MB_DQS(3)

MB_DQS#(3)

MB_DQS(2)

MB_DQS#(2)

MB_DQS(1)

MB_DQS#(1)

MB_DQS(0)

MB_DQS#(0)

MB_DM(7:0)

MB_A(15)
MB_A(14)
MB_A(13)
MB_A(12)
MB_A(11)
MB_A(10)

MB_A(9)
MB_A(8)
MB_A(7)
MB_A(6)
MB_A(5)
MB_A(4)
MB_A(3)
MB_A(2)
MB_A(1)
MB_A(0)

MB_DQS(7)
MB_DQS#(7)
MB_DQS(6)
MB_DQS#(6)
MB_DQS(5)
MB_DQS#(5)
MB_DQS(4)
MB_DQS#(4)
MB_DQS(3)
MB_DQS#(3)
MB_DQS(2)
MB_DQS#(2)
MB_DQS(1)
MB_DQS#(1)
MB_DQS(0)
MB_DQS#(0)

MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)

CN12-3

R26

MB_CLK_H3

P22

MB_CLK_H0

R22

MB_CLK_L0

R25

MB_CLK_L3

AF18

MB_CLK_H2

AF17

MB_CLK_L2

A17

MB_CLK_H1

A18

MB_CLK_L1

U22

MB1_CS_L0

W25

MB0_CS_L1

V26

MB0_CS_L0

W23

MB0_ODT1

W26

MB0_ODT0

Y26

MB1_ODT0

U24

MB_CAS_L

U23

MB_WE_L

U25

MB_RAS_L

J26

MB_BANK2

U26

MB_BANK1

R24

MB_BANK0

H26

MB_CKE1

J25

MB_CKE0

J24

MB_ADD15

J23

MB_ADD14

W24

MB_ADD13

L25

MB_ADD12

L26

MB_ADD11

T26

MB_ADD10

K26

MB_ADD9

M26

MB_ADD8

L24

MB_ADD7

N25

MB_ADD6

L23

MB_ADD5

N26

MB_ADD4

N23

MB_ADD3

P26

MB_ADD2

N24

MB_ADD1

P24

MB_ADD0

AF12

MB_DQS_H7

AE12

MB_DQS_L7

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AC25

MB_DQS_H4

AC26

MB_DQS_L4

F26

MB_DQS_H3

E26

MB_DQS_L3

A24

MB_DQS_H2

A23

MA_DQS_L2

D16

MB_DQS_H1

C16

MA_DQS_L1

C12

MB_DQS_H0

B12

MA_DQS_L0

AD12

MB_DM7

AC16

MB_DM6

AE22

MB_DM5

AB26

MB_DM4

E25

MB_DM3

A22

MB_DM2

B16

MB_DM1

A12

MB_DM0

FOX_PZ63823_284S_41F_TEMP_638P

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54

MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31

MEMORY INTERFACE

MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10

MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16

AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)

MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)

MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)

MB_DATA(63:0)

INVENTEC

TITLE

Piaget 2.0 Discrete

CPU-2

SIZE CODE DOC. NUMBER REV

CHANGE by SHEET OF

Jason Chiu 20-Jul-2009

A3

1310A22683-0-MTRA02

CS

6017

CPU_VDDA

C1087

1
2

3300pF_50V

1
2

C1086

4.7uF_6.3V

1

C1088

2

L1008

BLM11A221S

1

0.22uF_6.3V

+V2.5S

7-

2

10-

COREFB

10-

COREFB#

Routing differential pair type

To put pull high resistors near switching power source

Keep trace to resistor less than 600mils from CPU pin
and trace to AC caps less than 1250mils.

CLK_R_CPUBCLK

CLK_R_CPUBCLK#

+V1.8

+VCC_CORE

10-,19-,57-

Routing differential pair type

1

R47
51_5%

2

1

R46
51_5%

2

CPU_TDI

R341

300_5%

+V1.8

1

2

18-

18-

18-

18-

18-

18-

18-

18-,36-

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

CPU_DBREQ#

CPU_DBRDY

CPU_TCK
CPU_TMS

CPU_TRST#

CPU_TDO

LDT_RST#

15-

15-

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

38­38-

C436

100pF_50V

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

1

R340

0_5%_OPEN

2

HDT Header

C120

3900pF_16V

1 2

1

R149

169_1%

2

1 2

C119

3900pF_16V

1 2

R283

1 2

R284

C435

1

1

2

2

100pF_50V

+V1.8

1 2

R285

1 2

R286

Keep trace to resistors less
than 1" from CPU pin.

+V1.8

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

SAMTEC_ASP_68200_26P_OPEN

604_1%
604_1%

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

CN1003

CPUBCLKIN_H
CPUBCLKIN_L

LDT_PG

LDTSTOP#

LDT_RST#

CPU_TDI

CPU_TRST#

CPU_TCK

CPU_TMS

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

39.2_1%

39.2_1%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

18-,36­18-,26-,36­18-,36-

18­18­18­18­18-

+V1.8

CPU_MVREF

18-

300_5%
300_5%

10-

VDD1_FB

VDD1_FB#

Routing differential pair type

10-

CN12-4

F8

VDDA

F9

VDDA

A9

CLKIN_H

A8

CLKIN_L

A7

PWROK
LDTSTOP_L

B7

RESET_L

AF4

SIC

AF5

SID

AF9 AE9

TDI

AD9

TRST_L

AC9

TCK

AA9

TMS

E10

DBREQ_L

F6

VDD_FB_H

E6

VDD_FB_L

H6

TP1008

VDDNB_FB_H

G6

TP1009

VDDNB_FB_L

Y10

TP1017

VTT_SENSE

W17

M_VREF

AE10

M_ZN

AF10

M_ZP

TP1015

AA8

MEMHOT_L

R1531 2

E9

TEST25_H

R150

1 2

E8

TEST25_L

G9

TP1010

TEST19

TP1011

H10

TEST18

C2

TEST9

TP1001

D7

TEST17

TP1004

E7

TEST16

TP1007

F7

TEST15

TP1002

C7

TEST14

TP1019

AC8

TEST12

C3

TEST7

AA6

TEST6

TP1014

W7

THERMDC

TP1012

W8

THERMDA

Y6

VDD1_FB_H

AB6

VDD1_FB_L

FOX_PZ63823_284S_41F_TEMP_638P

+V1.8

MISC

LDTREQ_L

SVC
SVD

THERMTRIP_L

PROCHOT_L

TDO

DBRDY

VDDIO_FB_H
VDDIO_FB_L

HTREF1
HTREF0

TEST29_H
TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST28_H
TEST28_L

TEST27

ALERT_L

TEST10

TEST8

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

1

R1176
1K_1%

2

1

2

R1175
1K_1%

1
2

+V1.8

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

1

R147
1K_1%

2

C6F10
A6
A4

AF6
AC7

G10

TP1013

W9
Y9

TP1016

P6
R6

C9

TP1005
TP1003

C8

AE7
AD7

TP23

AE8
AB8
AF7

J7
H8

TP22

AF8
AE6
K8
C4

C1207
1000pF_50V

+V1.8S

13-,14-,18-,24-,26-,27-,30-,38-,57-

1

R148
1K_1%

2

18-,26-,36-

THERMTRIP#

18-

CPU_DBRDYCPU_DBREQ#

44.2_1% R1186

1 2

R281

1 2

1 2
1 2

CPU_THERM_SCI#

CPU_MVREF

18-

1

C1208

0.22uF_6.3V

2

2

300_5%
300_5%R280

300_5%R277
300_5%R282

10­10-

LDT_REQ#
CPU_SVC_R
CPU_SVD_R

+V1.2S

R118744.2_1%

12
1

LDT_PG

LDT_RST#

LDTSTOP#

LDT_REQ#

CHANGE by

+V1.8

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

R323

1

2

R322
300_5%

1

300_5%

2

9-,11-,15-,19-,27-,36-,37-,57-

Keep trace to resistors less
than 1" from CPU pin.

+V1.8

R1111

18-,36-

18-,36-

18-,26-,36-

18-,26-,36-

1 2

300_5%

R1113

1 2

300_5%

R1112

1 2

300_5%

R1114

1 2

470_5%

Jason Chiu 20-Jul-2009

1

R327
1K_5%

2

1

Q35

B

MMBT3904

C32E

+V1.8S

10-,11-,12-,13-,18-,19-,20-,21-,22-,23-,38-,57-

1

R151
1K_5%

2

1

2

1

B

C32E

Q31

MMBT3904

+V1.8S

13-,14-,18-,24-,26-,27-,30-,38-,57-

23-,29-,38-

H_THERMTRIP#CPU_SIC

8-,23-

PROCHOT#CPU_SID

18-

CPU_TDO

13-,14-,18-,24-,26-,27-,30-,38-,57-

R152
30K_5%

23-,29-,38-

Therm_SCI#

INVENTEC

TITLE

Piaget 2.0 Discrete

CPU-3

SIZE

A3

DOC. NUMBER REV

CODE

1310A22683-0-MTRA02

CS

SHEET

OF

6018