HP 4411s, 4510S maintenance and service guide

S-SERIES 2009

INVICTA (Intel-Discrete)

MV Build (A03) - Final

2009.03.18

DATE

CHANGE NO.

REV

DRAWER DESIGN CHECK RESPONSIBLE

FILE NAME :

XXXXXXXXXXXX

P/N

EE

3

XXXX-XXXXXX-XX

DATE

POWER

DATE

TITLE

VER : SIZE

A3

INVENTEC

INVICTA Cycle1

DOC. NUMBER

CODESIZE =

CS

1310A22527-0-MTR

SHEET

OF

541

REV

A03

Table Of Contents

Page

5- DC & Battery Charger & OCP. 6- Select & Battery CONN. 7- System Power (+V3A/+V5A).

8- System Power (+V1.8/+VCCP) .

9- Graphic Power (+VDD_CORE & +VPCIE). 10- System Power (+V1.5S) . 11- CPU Power (+VCC_CORE).

12- DDR Termination Voltage(+V0.9S). 13- Power (Sleep: +V5S/+V3S/+V1.8S).

14- Power (Sequence).

Page

15- Clock Generator. 16- CPU Penryn-1. 17- CPU Penryn-2.

18- CPU Penryn-3. 19- XDP & Thermal & Fan. 20- N/B Cantiga-1.

21- N/B Cantiga-2. 22- N/B Cantiga-3. 23- N/B Cantiga-4.

24- N/B Cantiga-5. 25- N/B Cantiga-6. 26- DDR2-DIMM0.

27- DDR2-DIMM1. 28- DDR2-Termination. 29- VGA CONN.

30- LCD,WebCam,HDMI CONN. 31- S/B ICH9-1. 32- S/B ICH9-2.

33- S/B ICH9-3. 34- S/B ICH9-4. 35- S/B ICH9-5.

Page

36- Power, LID, APP SW/B.

37- HDD & ODD,Accelerometer,15" ODD EXT/B.

38- USB CONN. 39- KBC, BIOS ROM, Debug Port. 40- Internal Keyboard & TouchPad CONN. 41- Audio CODEC & Earphone & Speaker. 42- Audio MIC & MDC CONN.

43- Giga LAN controller. 44- Magnetic & RJ45 CONN.

45- Mini Card(WLAN/WWAN), BT. 46- New Card & 4 in 1 Card (SD/MMC/MS/XD). 47- LEDs, TCM CONN.

48- Screws, Crack testing circuit. 49- AMD M92S2-1. 50- AMD M92S2-2.

51- AMD M92S2-3. 52- AMD M92S2-4. 53- Video RAM-1 (DDR2).

54- Video RAM-2 (DDR2).

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

Contents

SIZE

A3

DOC. NUMBERCODE

1310A22527-0-MTR A03

CS

SHEET

REV

OF

542

(NewCard)

7 IN 1

CONN

P.46

USB3

Card Reader

ALCOR_AU6433

BlueTooth

USB7

Mini Card

WWAN+SIM Card

USB8 (& PCIE2)

Mini Card

WLAN

Web CAM

USB0

CONN

USB1

CONN

USB2

USB4

CONN

USB5

CONN

USB6

CONN

USB10

CONN

P.38

P.46

P.38

P.45

V-RAM

LCM VGA

HDMI

DDR2 500

P.53

LVDS

P.30

CRT

P.29

P.30

Accelerometer

STMicro LIS302DL

MDC V1.5

CONN

RJ11

AMD M92S2

P.49

P.37

P.42

Audio CODEC

ADI_1984A

P.42

MIC

-phone

INT.MIC

PCI_EXPRESS

SM bus

USB I/F

Headphone

P.41

-phone

(478 uFCPGA)

Cantiga

(1329 FCBGA)

ICH9-M

676 mBGA

IHDA

P.41

Speaker

P.41

Penryn

FSB 1067/800

PM45

DMI

LPC

TCM

P.41

P.16-19

P.20-25

SATA

PCIE I/F

P.31-35

SPI

KBC

SMSC KBC1091

P.40

TouchPad

Keyboard

DDR2 800

HDD & Fixed ODD

SPI

P.39

System

BIOS

P.39

P.40

(PC2-6400)

DDR II _SODIMM0

P.26

DDR II _SODIMM1

P.27

P.37

Mini Card

Slot1

(WLAN/WLAN+WiMAX)

(PCIE2+USB8)

Express Card 34

CONN

(PCIE3+USB2)

Giga LAN

Marvell

88E8072

(PCIE-6)

CHANGE by

P.43

Drawer_Name

MAIN BATT

6 Cell / 8 Cell

System Charger &

DC/DC System power

Clock Generator

ICS9LPRS397

P.45

P.46

RJ45

CONN

P.44

TITLE

17-Mar-2009

P.15

INVENTEC

INVICTA Cycle1

SIZE

CODE

DOC. NUMBER

A3

1310A22527-0-MTR A03

CS

SHEET

OF

P.5

REV

543

BATSELB

AC_AND_CHG

CHGCTRL_3

Adapter

(90W)

LIMIT_SIGNAL

Selector

(Discrete)

+VBATR

+VBDC

OCP

Charger

(BQ24740)

+VBATA

BATCON

ADP_EN OCP_OC# ADP_PS0 ADP_PS1

CHGCTRL_3

ADP_PRES

AC_AND_CHG

Main Battery

ADP_PRES

KBC_PW_ON

SLP_S4#_3R

SLP_S3#_3R

5/3.3V

(TPS51120)

IO POWER

(TPS51124)

+V1.8

+V5A +V3A

+V5AL +V3AL

V1.8_PG

VCCP_PG

+VCCP

(5.8A)

(6.1A)

(13.7A)

SLP_S3#_3R

SLP_S4#_3R

SLP_S3#_3R

LR

(G2997)

LR

(APL5913)

M_VREF

V1.5S_PG

+V5S

+V3S

+V3_LAN

+V0.9S

+V1.5S

+V1.8S

(3.7A)

(4.2A)

(647mA)

(3.5A)

(5A)

SLP_S3#_3R

PWR_GOOD_3

PM_DPRSLPVR

PSI#

H_DPRSTP#

ATI

GPU POWER

(TPS51511)

IMVP VI

(ADP3208)

+VDD_CORE +VPCIE

VGA_PG

+VCC_CORE

PM_PWROK

(12A)

(2.6A)

CHANGE by

(36A)

Drawer_Name 17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

SIZE

A3

DOC. NUMBER

CODE

1310A22527-0-MTR A03

CS

SHEET

REV

OF

544

+VADPBL

5-,6-

FAIR_FDMC6675BZ_8P

ADP_EN#

1

R150 15K_5%

2

2VREF

7-,14-

R143

14.3K_1%

+VBDC

5-,6-

R137

12

100K_1%

Q25

D

S

8

1

7

2

6

3

5

4

G

D1010

14-

21

CHENKO_LL4148_2P

1

R147 100K_1%

2

1

R146

8.25K_1%

2

1

2

+VADPBL

5-,6-

R131

12

100K_1%

23.7K_1% R134

12

24K_1%

220K_5%

R1075

100K_5%

12

C1067

R138

R1072

3

2

12

3 2

C125

0.22uF_16V

12

0.1uF_16V

1

2

1

2

D

S

SSM3K7002F

12

270K_5%

+V5AL

+

-

5 6

+VADP

14-

1

C1112

2

0.1uF_16V

1

R1074 220K_5%

2

Q1018

1

14-

G

R145

OUT

R144 1M_5%

12

+V5AL

+

OUT

-

BATCAL#

+V3AL

5-,7-,14-

R1030

8

12

U1006-A

1

ON_LM393DR2G_SOP_8P

4

5-,7-,14-

8

U1006-B

7

1

C84

4

0.1uF_16V

2

ON_LM393DR2G_SOP_8P

+V5AL

5-,7-,14-

R133

12

1M_5%

1

1IN+

2

U1008

GND

TI_LMV321IDBVR_SOT23_5P

3

1IN-

NFM60R30T222

C1070

C1069

1

2

10pF_50V

0.1uF_25V

B140_SMA

D

8 7 6 5

FAIR_FDMC6675BZ_8P

5-,6-,7-,14-,31-,39-,40-,45-,47-

22K_5%

6-,39-,43-

6-

AC_AND_CHG

R129

12

100K_5%

5

Vcc+

4

OUT

L1005

4.73A(180mils)

12

3

4

C1115

10pF_50V

D1009

21

Q26

S

1 2 3 4

G

ADPDRV# ADP_PRES

CHGCTRL_3

6-,39-

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

2

R35

10K_5%

1

Q1015

1

S1

2

G1

6

D1

3

D2

5

G2

4

S2

2N7002DW

DC JACK

VADP_IN

C1113

1

2

0.1uF_25V

ACES_91302_0047L_1_4P

7A(280mils)

12

R83

47K_5%

1

R36

4.7K_5%

2

5-

R1029

12

47K_5%

R71

294K_1%

12

1

R78

2

200K_1%

SLP_S3#_3R

+V3A

7-,13-,19-,30-,32-,33-,34-,43-,45-,47-

5-

ADPDRV#

VCTRL_3

39-

P2U

8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

R76

453K_1%

R1028 422K_1%

12

R1027 1M_1%

CN1003

1

2

3

4

C1046

1uF_25V

C1038

1uF_6.3V

CELLS

1

2

1

2

G G

+VBAT

6-

12

1

2

G1 G2

P2U

R84

12

300K_5%

R80

BQREF

12

39-

R77

100K_5%

C1042

1uF_6.3V

R87

0.01_1%

12

C1043

12

0.1uF_16V

20K_5%

1

R72

0_5%

1

2

C1044

1uF_6.3V

ICS

BQREF

+VBATR

7-,8-,9-,11-,13-,30-,39-,40-

C1045

12

1uF_25V

2

3

5

9

13

16

6

2

5-

10

8

21

4

20

1

11

12

15

TI_BQ24740_QFN_28P

1 2

5-

R1070

12

5-

169K_1%

LIMIT_SIGNAL

U1005

ACN

ACP

ACDET

AGND

EXTPWR

SRSET

ACSET

VREF

IADSLP

DPMDET

LPMD

CELLS

CHGEN

VDAC

VADJ

IADAPT

5-

ICS

P2U

C1039

100pF_50V

100K_1%

LS_100R

PVCC

HIDRV

BTST

REGN

LODRV

PGND

SRP

SRN

BAT

LPREF

ISYNSET

PowerPad

R1071

100_5%

12

47-

28

26

25

PH

P_CG_BST

27

24

23

22

19

18

17

7

14

29

C1111

1

2

14-

R140

VBIAS

1

2

P_CG_REG

C1004

1 2

0.22uF_16V

12

R1069

12

10K_5%

Q1017

BSS84_3P

2

S

14-

C1006 1uF_25V

P2U

P_CG_PH

12

13

1uF_10V

P_CG_LD

1

R79

24.9K_1%

2

G

1

0_5%R32 D1003

BAT54

1 2

5-,11-,13-,14-,19-,29-,30-,32-,34-,37-,40-,41-

U14

1

1IN+

2

GND

3

1IN-

Vcc+

OUT

5

4

TI_LMV321IDBVR_SOT23_5P

D12

DAN202K

2

3

D

R1060

3.9K_1%

C27

C25

0.1uF_25V

P_CG_HD

1

2

C1005

0.1uF_16V

12

4.7uF_25V

1

2

P2U

Kelvin sense

C1040

0.1uF_25V

P2U

+V3S

+V5S

11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

U1007-A

2

1

2

5

+

4

-

5-,11-,13-,14-,19-,29-,30-,32-,34-,37-,40-,41-

1

R158 10K_5%

2

3

2

OUT

12

R142

80.6K_1%

1

R162 133K_1%

2

1

C124

1

2

0.027uF_10V

2

3

U1007-B

7

+

OUT

6

12

+V5S

ON_LM339DR2G_SOP_14P

R159

330K_5%

R160

3.9K_5%

1

2

R1073 2K_1%

1 2

C127

0.1uF_16V

1

D11

1

2

1

2

C28

4.7uF_25V

Vout sense

R1061

12

100K_5% C1068

3900pF_16V

C26

4.7uF_25V

1

2

C2O

1

B

41S23

4

3

C

E

Q1016

2

D_MMST3904

8765

D

G

8

765

D

G

S

123

Q1008

FDMC8884

Q1007

FDMC8884

OCP_OC

L1001

PCMB0603T_8R2MS

12

4.7uF_25V

14-

SSM3K7002F

1

C1009

2

21

CHENKO_LL4148_2P

Q1014

3

D

G

1

S

2

+VBDCR

C1008

1 2

4.7uF_25V

1 2

3.6A(140mils)

R1031

0.01_1%

12

Kelvin sense

C1037

0.033uF_16V 2

1

C1002

1uF_25V

P2U

Layout Rule 1>Noisy driver(BST, SW node, DH & DL) keep trace short and wide 2>Don’t route sensitive signal(Current&Voltage Sense, FB, REF, AGND...) close noisy driver area 3>Layout Kelvin sense as a differential pair to device

4>Layout Vout sense connect to output terminal(c2o) 5>Place Cap. and filter close to IC(p2u)

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

DC & Battery Charger

CODE

SIZE

A3

CS

SHEET

R161

1

2

10K_5%

R141

12

100K_5%

1

ON_LM339DR2G_SOP_14P

R139

12

604K_1%

11-,14-,39-,50-

PWR_GOOD_3

32-

OCP_OC#

OCP

+VBDC

5-,6-

C1007

1

2

4.7uF_25V

C1047

4.7uF_25V

C1041

1 2

1uF_25V

DOC. NUMBER

OF

554

1

2

REV

A031310A22527-0-MTR

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

CHGCTRL_3

CHENKO_LL4148_2P 2

1000pF_50V

2

5-,39-

D1

C16

1

0.047uF_16V

R14

12

1K_5%

1

C15

1

R13 470K_5%

2

1 2

G

1

R1002 470K_5%

2

3

D

S

2

Q1003

SSM3K7002F

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

5

U1001

24

74HC1G14GV

3

AC_AND_CHG

ADP_PRES

5-

5-,39-,43-

+VADPBL

5-

1

R20 10K_5%

2

R1032

3K_5%

SSM3K7002F

2

MMGZ2548B

Q1004

S

D

G

1

D1008

2

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

220K_5%

3

+VBAT

1

12

R12

5-

AM4825P_AP

+VBATA

Q17

1

S

2 3

6-

5-

8

D

7 6 54

G

12

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

R1003

1.5M_5%

SSM3K7002F

Q13

1

8

S

D

7

2

6

3

54

G

AM4825P_AP

2N7002DW

G2

5

G1

2

Q1001

3

Q1002

D

G

1

S

2

+VBATA+VBDC

6-

1

R1009

R1007 10K_5%

10K_5%

2

7A(280mils)

1

C29

SDA_MAIN

1

R37

2

470K_5%

1

R38

4.7K_5%

2

S2

4

D2

3

D1

6

S1

1

SCL_MAIN

2

0402_OPEN

6-

CFET#

THM_MAIN#

D2

6-

CFET# BATCON

21

CHENKO_LL4148_2P

+V3AL

39-

1

2

3939-

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

3

D1004

2

BAV99

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

R1011 100K_5%

2

+V3AL

5

2

3

U2

5-,6-,7-,14-,31-,39-,40-,45-,47-

R1001 220K_5%

74HC1G14GV

3

BAV99

4

1

D1005

D1006

2

39-

R1008

1

2

R1010

100_5%

12 12

100_5%

1

C1012

2

470pF_50V

3

BAV99

1 2

R1005

12

1K_5%

C1001

0.1uF_16V

1

R1006 10K_5%

2

6CELL#

SYN_081006_TK001_6P

CN1001

1

2

3

4

5

G1

G

5

6

G2

G

6

MAIN BATT

C1010

1 2

0.1uF_25V

R11

12

0_5%_OPEN

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

Selector & Battery CONN & Extend/B

CODE

SIZE

A3

DOC. NUMBER

1310A22527-0-MTR A03

CS

SHEET

OF

546

REV

KBC_PW_ON

VCC1_POR#_3

39-

14-,39-

Q54

S1

2

G1

D1 D2

5

G2

S2

2N7002DW

+V5AL

5-,7-,14-

1

R1226

330K_5%

2

1 6

3 4

Q53 S1

2

G1

D1 D2

5

G2

S2

2N7002DW

1

6 3

4

R1246

R1252

80.6K_1%

1

2

1

2

68K_1%

+VBATR +VBATR

7-

5-,8-,9-,11-,13-,30-,39-,40-

5A(200mils)

P2U

+V3A

6A(240mils)

5-,13-,19-,30-,32-,33-,34-,43-,45-,47-

1uF_6.3V

C564

1 2

R1249

12

C2O

6.49K_1%

+VBATR

7-

C1327

1

2

4.7uF_25V

CYNTEC_PCMC063_3R3

1

C565

330uF_6.3V

2

L37

1

0_5%_OPEN

0402_OPEN

EMI OPTION

C1325

4.7uF_25V

Q1026

SI7326DN

2

R385

C537

R1251

12

10K_1%

P2U

8765

D

S

123

765

8

D

1

S

123

SI7726DN

2

1

51125GND

G

4

G

Q43

4

1 2

C1333

2200pF_50V

C563

0.1uF_16V

RF option

1 2

12

C538

0.1uF_25V

P2U

R423

4.7_5%

12

+V3AL

5-,6-,14-,31-,39-,40-,45-,47-

1

C562

2

4.7uF_6.3V

P_3A_FB

0_5%_OPEN

R1250

12

P_3A_BST

P_3A_DH P_3A_LL P_3A_DL

P2U

R1253

12

0_5% R414

12

0_5%

25

TML

7

VO2

8

VREG3 VBST2

10 11

DRVL2

5

6

VFB2

ENTRIP2

SKIPSEL

EN0

14

13

4

VREF

TONSEL

VIN

GND

15

1 2

3

2

VFB1

PGOOD

VREG5

16

17

P2U

C529

2.2uF_25V

51125GND

P2U

POWERPAD1x1m

1

U26

ENTRIP1

24

VO1

23 229

VBST1

21

DRVH1DRVH2

20

LL1LL2

1912

DRVL1

TI_TPS51125_QFN_24P

VCLK

18

P2U

PAD1005

P_5A_BST

P_5A_DH P_5A_LL P_5A_DL

+V5AL

P_5A_FB

2VREF

1 2

51125GND

32-,39-

5-,7-,14-

1

C1326

4.7uF_6.3V

2

5-,14-

C1342

1uF_6.3V

RSMRST#

4.7_5%

C526

R413

12

C1330

2200pF_50V

P2U

0.1uF_16V

51125GND

RF option

1 2

R1248

12

10K_1%

C1328

1

0.1uF_25V

2

Q42

SI7726DN

R1247

12

15K_1%

P2U

765

8

D

G

4

1S23

SI7326DN

8

765

D

G

41S23

C1329

1

2

4.7uF_25V

Q1025

CYNTEC_PCMC063_3R3

1

0_5%_OPEN R383

2

0402_OPEN C533

1

EMI OPTION

+VBATR

C1331

1

C1332

1

2

4.7uF_25V

2

4.7uF_25V

L36

12

C525

1uF_6.3V

C2O

7-

+V5A

8-,9-,10-,11-,12-,13-,30-,34-,38-,40-

5A(200mils)

1

C524

1

330uF_6.3V

2

CHANGE by

Drawer_Name 17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

System Power(+V5A/+V3A)

DOC. NUMBER

CODE

SIZE

A3

1310A22527-0-MTR A03

CS

REV

OFSHEET

547

P_1.8_FB P_VCCP_FB

+V1.8

9-,10-,12-,13-,20-,23-,24-,26-,27-,40-

12A(480mils)

330uF_2v_9mR_Panasonic

C1318

C2O

C556

0.1uF_25V_OPEN

1

2

PCMC063T_1R0MN

1

2

+VBATR

C557

2200pF_50V_OPEN

1

2

L1019

12

R410

10_5%

C552

2200pF_50V

EMI OPTION

5-,7-,8-,9-,11-,13-,30-,39-,40-

C555

4.7uF_25V

1

2

C554

4.7uF_25V

Q48

SI7326DN

1

2

1

2

12-,32-

14-

12

R526

12

30K_1%

P2U

1

R459 0_5%

2

R457

12

4.7_5%

51124GND

0_5%_OPEN

P_1.8_BST

P_1.8_DH

P_1.8_LL

P_1.8_DL

P2U

R461

12

7

PGOOD2

8

EN2

9

VBST2

10

DRVH2

LL2

12

DRVL2

8.87K_1%

R463

12

0_5%

2

5

6

4

3

VO2

GND

VFB1

VFB2

TONSEL

TI_TPS51124RGER_QFN_24P

PGND2

13

17

14

15

16

TRIP1

TRIP2

V5FILT

V5IN

P_1.8_V5F

1

R460

51124GND

1

R464 12K_1%

2

51124GND

U1015

1

VO1

25

GND

24

PGOOD1

23

EN1

P_VCCP_BST

22

VBST1

21

DRVH1

2011

LL1

19

DRVL1

PGND1

18

7-,9-,10-,11-,12-,13-,30-,34-,38-,40-

P2U

R528

1

30K_1%

P_VCCP_DH

P_VCCP_LL

P_VCCP_DL

C1371

1

1uF_10V

2

C1373

1 2

0.022uF_16V

14-

R465

12

4.7_5%

R462

12

10_5%

R527

12

12.1K_1%

P2U

5-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

R1272

12

100K_5%

VCCP_PG

P2U

C1374

12

0.1uF_16V

+V5A

C1372

1

4.7uF_6.3V

2

SLP_S3#_3R

G

4

Q1030

FDS6690AS

P2U

C2O

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-,40-

C550

4.7uF_25V

8

765

1

D

2

S

Q50

SI7326DN

123

6

54

8D7

G

S

123

1

2

C553

4.7uF_25V

L1020

12

PCMC063T_2R2MN

1

R1245

10_5%

2

1

C1369

2200pF_50V

2

1

2

EMI OPTION

C551

4.7uF_25V

1

2

C549

2200pF_50V_OPEN

1

2

C548

0.1uF_25V_OPEN

1

C1375

220uF_2v_15mR_Panasonic

2

+VCCP

10-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

8A(320mils)

R525

12

43.2K_1%

V1.8_PG

SLP_S4#_3R

8

765

D

G

S

3

12

765

8

D

G

4

Q1031

FDS6676AS

C1370

0.1uF_16V

P2U

41S23

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

System Power(+V1.8/+VCCP)

DOC. NUMBER

CODE

SIZE

A3

1310A22527-0-MTR A03

CS

SHEET

REV

OF

548

POW_SW1

0 0 1

POW_SW0

0 1 0

+VDD_CORE

1.0V

0.95V

0.9V

+VPCIE

50-,51-

2A(80mils)

C39

1uF_6.3V

P2U

1

2

SLP_S3#_3R

C1015 22uF_6.3V

R1017

1

0_5%

POW_SW0

+VPCIE

1

R1013

9.31K_1%

2

1

R1014 20K_1%

2

VGAP_AGND

49-

5-,8-,10-,12-,13-,14-,32-,39-,41-,43-,46-

1

R1015 120K_1%

2

P2U

R1019

12

10K_1%

P2U

C8

12

10uF_6.3V

U5

2

NC

3

VLDO

4

VLDOFB

5

GND

6

ODOFF

7

OD

8

COMP

9

VOSW

21

TML-PAD

12

1

C1016

0.1uF_16V

2

+V1.8

8-,10-,12-,13-,20-,23-,24-,26-,27-,40-

1

VLDOIN

VSWFB

10

TI_TPS51511_RHL_20P

R58

0_5%

P_VDDC_BST

20

VBST

19

DRVH

18

LL

17

DRVL

16

PGND

15

CS

14

V5IN

13

PGOOD

12

ENSW

ENLDO

11

R56

12

0_5%

R1020

12

0_5%

P_VDDC_DH P_VDDC_LL P_VDDC_DL

R1021

12

6.04K_1% R1018

12

10K_1%

14-

C44

0.1uF_16V

12

P2U

+VDD_CORE P_VDDC_FB

VGA_PG

C1017

0.1uF_16V

12

+V5A

7-,8-,10-,11-,12-,13-,30-,34-,38-,40-

C45

1

2

4.7uF_6.3V

P2U

Q1009

SI7230DN

5

4

G

3

G

2

3

8D7654

1

2

Q1

FDMS8670S

+VBATR

5-,7-,8-,11-,13-,30-,39-,40-

1.2A(50Mils)

C1021

1

2

4.7uF_25V

C1022

876

1

2

4.7uF_25V

1

9

S

1

R3

0_5%_OPEN

2

C9

1

(0402)

2

0.1uF_25V_OPEN

C1020

1

2

4.7uF_25V

1

MPLC0730_1R0_10.6A

C40

1 2

1000pF_50V

P2U

C1019

1

2

2200pF_50V

L2

VGAP_AGND

2

1

R50

8.06K_1%

2

1

2

RF option

R1016 30K_1%

C2O

1

2

C49

0.1uF_25V

R53

1

12K_1% C42

2

1000pF_50V

1 2

Q18

D

S

SSM3K17FU

VGAP_AGND

G

1 2

R1041

12

1K_5%

C1049

1000pF_50V

49-

POW_SW1

+VDD_CORE

12A(power plane)

1

C56

330uF_2v_9mR_Panasonic

2

1

2

40-,51-

C1018

22uF_6.3V

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

Graphic Power (+VDD_CORE & +VPCIE)

CODESIZE

CS

SHEET

DOC. NUMBER

OF

954

A3

REV

A031310A22527-0-MTR

+V5A

7-,8-,9-,11-,12-,13-,30-,34-,38-,40-

+V1.8

8-,9-,12-,13-,20-,23-,24-,26-,27-,40-

SLP_S3#_3R

5-,8-,9-,12-,13-,14-,32-,39-,41-,43-,46-

+VCCP

8-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

R1244

12

0_5%

1

R1243 0402_OPEN

2

ANPEC_APL5930KAI_TRG_SOP_8P

C1341

1 2

1uF_10v

6

7 8 9

1 2

VIN

VCNTL

POK EN VIN

C1366

22uF_6.3v

VOUT

U514

3A(120mils)

3.5A (140mils)

+V1.5S

13-,18-,24-,34-,45-,46-

+V1.5S

C1368

22uF_6.3v

1 2

C601

1uF_10v

1 2

39pF_50V

C1367

1

R1269

27.4K_1%

2

1

R1270

30K_1%

2

1 2

45

3

FB

2

GND

1

14-

V1.5S_PG

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

System Power (+V1.5S)

CODESIZE REVDOC. NUMBER

A3

1310A22527-0-MTR A03

CS

SHEET

OF

5410

P2U

2

P2U

2

AGND_VCORE

VSSSENSE

Kelvin sense

VCCSENSE

CSP1

C1172

1

47pF_50V

C1173

1

47pF_50V

CSN1

CSN2

C1175

1

47pF_50V

C1177

1

47pF_50V

CSP2

11-

18-

5-,13-,14-,19-,29-,30-,32-,34-,37-,40-,41-

R1113

12

332_1%

1

C1174 47pF_50V

2

R1114

12

332_1%

R1115

12

332_1%

1

C1176 47pF_50V

2

R1116

2

1

332_1%

P2U

R1117

12

0_5%

R1120

12

0_5%

VR_PWRGD_CK505#

C1214

0.22uF_6.3V

1

2

P2U

AGND_VCORE

1

C1179

2

0402_OPEN

C1178

1

2

0402_OPEN

C1180

1

2

0402_OPEN

AGND_VCORE

5-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

R278

PM_PWROK

PM_DPRSLPVR

PWR_GOOD_3

R1159

0_5%_OPEN

R1160

0_5%

AGND_VCORE

H_DPRSTP#

H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0

20-,32-,39-

20-,32-

32-

5-,14-,39-,50-

+V5S

1

2

POWERPAD1x1m

AGND_VCORE

C1171

330pF_50V

1

2

R1118

12

20K_1%

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

R1164

0402_OPEN

17-,20-,3117-

PSI#

1818181818-

1818-

12

0_5% R1162

12

499_1%

R1156

12

0_5% R280

2

1 12

0_5%

R279

2

1

124K_1%

P2U

C1170

1

2

2.2uF_6.3V

PAD4

R1112

5.1K_1%

1

2

1

DROOP

2

VREF

3

GND

4

CSP1

5

CSN1

6

CSN2

7

CSP2

8

GNDSNS

9

VSNS

10

THERM

TP7

37

36

40

39

38

35

41

PwPd

ISLEW

V5FILT

TONSEL

OSRSEL

TRIPSEL

PWRMON

U1011

TI_TPS51620RHAR_QFN_40P

VR_TT#

PSI#

VID5

VID6

DPRSTP#

11

13

16

15

14

12

+VCCP

1

R1119 56_5%

1

2

Senstive signal

34

VR_ON

VID317VID4

32

33

CLK_EN#

19

DPRSLPVR

VID118VID2

R1161

12

10K_5%_OPEN

R1157

12

10K_5%_OPEN

31

DRVH1

PGOOD

VBST1

LL1

DRVL1

V5IN

PGND

DRVL2

LL2

VBST2

DRVH2

VID0

20

30

P_CORE_BST1

29 28 27 26 25 24 23

P_CORE_BST2

22 21

P_CORE_DL2

+V3S

P_CORE_DH1

P2U

R1163

12

3.3_5%

R282

12

3.3_5%

C1215

12

0.22uF_16V

C1217

12

0.22uF_16V

P_CORE_LL1

+V5A

7-,8-,9-,10-,12-,13-,30-,34-,38-,40-

1 2

2200pF_50V_OPEN

P_CORE_DH2

P_CORE_LL2

1

C363

2

P_CORE_DL1

C1216

P2U

2.2uF_6.3V

C1218

1

2

0.1uF_25V_OPEN

68uF_25V

C1219

1

2

C1249

1 2

4.7uF_25V

C1250

1

2

4.7uF_25V

C1246

1 2

4.7uF_25V

C1248

1

2

4.7uF_25V

4A(160mils)

2200pF_50V_OPEN

0.1uF_25V_OPEN

C417

C1252

1

2

C1251

C1247

1

2

4.7uF_25V

+VBATR

C1253

1 2

FDMS8660S

1

2

5-,7-,8-,9-,13-,30-,39-,40-

89

567

G 4321

8

9

765

D

G

Q34

S

123

4

9

5678

Q1022

SI7686DP_T1_E3

G

4321

65

9

87

Q35

D

FDMS8660S

G

41S23

CHANGE by

CSN1

Kelvin sense

CSP1

Q1021

SI7686DP_T1_E3

R1202

0_5%_OPEN

C1254

0.1uF_25V_OPEN

(0402)

0_5%_OPEN

C360

0.1uF_25V_OPEN

(0402)

CSP2

Kelvin sense

CSN2

11-

R284

C880

1 2

2

R334

0_5%

C409 12

0.01uF_16V R335

2

549K_1%

220K_5%

12

R336

0.01uF_16V_OPEN

1

2

R720

0402_OPEN

R337

1

37.4K_1%

12

1

2

1

2

1

2

1

2

11-

CYNTEC_PCMC104T_R36MN_2P

NTC_Thermistor, place near L021

R340

12

37.4K_1%

R719

0402_OPEN

1

C879

2

0.01uF_16V_OPEN

17-Mar-2009Drawer_Name

P2L

1

63.4K_1%

12

R338

L29

Ensure trace/via isolated other signal

44A <35W>

L30

12

R341

R342

R285

2

549K_1%

C364 12

0.01uF_16V R286

0_5%

12

63.4K_1%

1

12

P2L

12

220K_5%

INVENTEC

TITLE

INVICTA Cycle1

CPU Power (+VCC_CORE)

CODE

SIZE

A3

CS

SHEET

11 54

+VCC_CORE

18-,40-

Ensure trace/via isolated other signal

REVDOC. NUMBER

A031310A22527-0-MTR

OF

SLP_S4#_3R

SLP_S3#_3R

8-,32-

5-,8-,9-,10-,13-,14-,32-,39-,41-,43-,46-

+V1.8

8-,9-,10-,13-,20-,23-,24-,26-,27-,40-

2A(80mils)

1

C1321

2

4.7uF_6.3V

+V5A

7-,8-,9-,10-,11-,13-,30-,34-,38-,40-

U1012

GMT_G2997F6U_MSOP10_10P

TML11VDDQSNS

10 2

VIN

9

S5

8

GND

7

S3

6

VTTREF

C1323

1

2

1uF_10V

1

C1324

2

0.1uF_16V

NOTE: DDR2 REGULATOR

20-,26-,27-

VLDOIN

PGND

VTTSNS

VTT

1

3 4 5

M_VREF

+V0.9S

28-

2A(80mils)

1

C1320

2

10uF_6.3V

1 2

C1322 10uF_6.3V

CHANGE by

Drawer_Name 17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

DDR Termination Voltage (+V0.9S)

SIZE

A3

DOC. NUMBERCODE REV

1310A22527-0-MTR A03

CS

SHEET

OF

5412

5-,7-,13-,19-,30-,32-,33-,34-,43-,45-,47-

13-

GATE_3S

D18

BAT54

13

12

R424 120K_1%

+V3A

12

6

D

5 2

1

G

FDC655BN

C619

0.01uF_16V

4.2A(160mils)

Q55

4

S

3

R477 47_5%

Q56

1

G

SSM3K7002F

+V3S

5-,11-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

+V5A

7-,8-,9-,10-,11-,12-,30-,34-,38-,40-

Q51

6

D

5 2

13

C559

12

0.01uF_16V

G

FDC655BN

SSM3K7002F

R411 120K_1%

12

13-

GATE_3S

1

C622

10uF_6.3V

2

3

D

S

2

3.7A(160mils)

+V5S

5-,11-,14-,19-,29-,30-,32-,34-,37-,40-,41-

4

S

1

R412

100_5%

2

Q52

3

D

1

G

S

2

Added for VGA

+V1.8

8-,9-,10-,12-,20-,23-,24-,26-,27-,40-

Q1019

R1101

120K_1%

13-

GATE_3S

1

C560

2

10uF_6.3V

12

1 2

C1161

0.022uF_16V

8 7

6

5

D

FDMC8884

S

G

R1098 100_5%

SSM3K7002F

5A(200mils)

+V1.8S

40-,49-,50-,51-,52-,53-,54-

1 2 3 4

Q29

3

D

1

G

S

2

(3A)

R1271 100_5%

Q59

1

G

SSM3K7002F

+V1.5S

10-,18-,24-,34-,45-,46-

1

2

3

D

S

2

1

C1163

2

10uF_6.3V

1

2

SLP_S3_3R

30-

SLP_S3#_3R

C1337

0402_OPEN

SLP_S3#_3R

5-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

5-,7-,13-,19-,30-,32-,33-,34-,43-,45-,47-

12

Q1024

G

1

SSM3K7002F

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-,40-

1

R1238 47K_5%

2

+V3A

1

R1240 100K_5%

2

3

D

S

2

3

C

1

B

E

2

SSM3K7002F

+VBATR

Q1028

1

MMBT3906

Q1027

D_MMST3904

1

R1236 130K_1%

2

Q1029

1

G

5-,7-,8-,9-,11-,13-,30-,39-,40-

1

R1239

2.7K_5%

2

E

B

C

3

D

S

2

D1013

1

MMGZ2548B

2

R1225

12

1K_5%

1

2

1

2

R1222 0_5%

R1224 0_5%

13-

GATE_3S

INVENTEC

TITLE

INVICTA Cycle1

Power (Sleep: +V5S/+V3S/+V1.8S)

SIZE

CHANGE by OF

Drawer_Name 17-Mar-2009

A3

DOC. NUMBER

CODE

1310A22527-0-MTR A03

CS

SHEET

REV

5413

SLP_S3#_3R

LS_100R

9-

68.1K_1%

102K_1%

12

R30

1K_5%

R19

12

1K_5%

10-

V1.5S_PG

8-

V1.8_PG

8-

VCCP_PG

R24

1

2

R23

12

1

R132 137K_1%

2

1

R135 10K_1%

2

D1001

DAP202K

12

10K_5%

12

10K_5%

12

10K_5%

R70

12

1M_5%

R130

29.4K_1%

R136

10K_1%

5-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

VGA_PG

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

+V5S

5-,11-,13-,14-,19-,29-,30-,32-,34-,37-,40-,41-

R15

R22

R18

+VADP

12

R16

49.9K_1%

5-,14-

1

R74

22.6K_1%

2

1

R69 10K_1%

2

5-,14-

2

1

2

3

R27

12

20K_5%

1

C17

1

1000pF_50V

2

ON_LM393DR2G_SOP_8P

U1004-B

2VREF

R21

100K_5%

5-5-

VBIAS

U1004-A

3

+

OUT

2

4

R33

12

1M_5%

8

5

+

OUT

6

4

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

R17

5-,14-

1

2

C1003

5-

R29 1_5%

1uF_25V

D1002

1

ADP_EN#

12

1M_5%

+V5AL

5-,7-,14-

8 U1002-B

5

+

OUT

6

-

ON_LM393DR2G_SOP_8P

4

1

R73 10K_5%

2

39-

ADP_ID

+VADP

5-,14-

2

R1004

220K_5%

7

1

R28 220K_5%

2

Q1005

1

SSM3K7002F

2

5-,7-,14-

2

1

C19

1 2

0.1uF_16V

+VADP

1 2

8

1

ON_LM393DR2G_SOP_8P

11

R68 47K_5%

2

CHENKO_LL4148_2P

7

+V3S

1

R25 10K_5%

2

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

R34 47K_5%

2

5-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

12

100K_5%

3

D

G

S

2

5-,11-,39-,50-

1 2

R31

C18

1000pF_50V

1

B

PWR_GOOD_3

5-

3

C

Q1006

E

D_MMST3904

2

39-

23.7K_1%

51.1K_1%

SLP_S3#_3R BATCAL#

ADP_EN

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

R1088

R1087

2200pF_50V

D1011

1

2

DAN202K

3

1

R1106

57.6K_1%

2

R1107

12

2

3

D

1

G

S

2

R190

12

10K_5%

R1090

12

21K_1%

12

470K_5%

2 1

1M_5%

+V5AL

5-,7-,14-

8

3

+

OUT

2

-

U1002-A

4

ON_LM393DR2G_SOP_8P

2VREF

5-,7-,14-

+V5S

R195

2 1

5-,11-,13-,14-,19-,29-,30-,32-,34-,37-,40-,41-

12

R1089

1

OCP_OC

12

C1165

23.7K_1%

+V5AL

5-,7-,14-

R82

1

1M_5%

12

R1108

Q1020

100K_5%

SSM3K7002F

1 2

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R184

71.5K_1%

2

1

R1092

21K_1%

2

1

R1091

3.48K_1%

2

R188

5-

12

47K_5%

C216

1uF_6.3V

12

C1135

0.1uF_16V

R1104

115K_1%

1

9 8

U1007-C

11 10

U1007-D

C217

0.1uF_16V

12

1M_5%

+

-

12

1M_5%

+

-

1

2

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

R1105 10K_5%

2

7-,39-

R189

OUT

R193

OUT

1

R191 10K_5%

3

2

14

ON_LM339DR2G_SOP_14P

12

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R186 10K_5%

3

2

13

ON_LM339DR2G_SOP_14P

12

VCC1_POR#_3

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

2

1

2

39-

ADP_PS0

39-

ADP_PS1

R1103

10.5K_1%

R1102 100K_5%

Thermistor

_NTC

INVENTEC

TITLE

INVICTA Cycle1

Power (Sequence)

CHANGE by

SIZE CODE

17-Mar-2009Drawer_Name

A3

CS

SHEET

DOC. NUMBER

14 54

REV

A031310A22527-0-MTR

OF

(500mA)

+VCCP

8-,10-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

L1022

BLM18AG471SN1D

1

2

C1396

1

10uF_6.3V

2

Layout note: All decoupling 0.1uF disperse closed to pin

C569

1 2

C1343

0.1uF_16V

1 2

0.1uF_16V

1 2

C1401

0.1uF_16V

1 2

C1398

0.1uF_16V

1

0.1uF_16V

2

C570

1 2

C1344

47pF_50V

(351mA)

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

L1023

BLM18AG471SN1D

2

C1400

1 2

10uF_6.3V

1 2

0.1uF_16V

C1399

1 2

0.1uF_16V

C1345

1 2

0.1uF_16V

C1349

1 2

0.1uF_16V

C1336

Layout note: All decoupling 0.1uF disperse closed to pin

1 2

0.1uF_16V

C1404

RF option

C1348

1 2

47pF_50V

CPU_BSEL1

CPU_BSEL2

FSA

1 0 0

FSB

17-,2017-,20-

FSC

1

0

1

0

R438

12

FSB CLOCK FREQUENCY

667 800

1067

10K_5%_OPEN

10K_5%

R437

10K_5%

*CLKREQ# pin controls SRC Table.

Byte5:bit7=0 , disable CR#_A ; enable CR#_A

CR#_A

Byte5:bit6=0 (PWD)

SRC0

Byte5:bit4=0 (PWD) , disable CR#4 ; 1, enable CR#4

CR#_4

SRC4

+VCCP

8-,10-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

1

R431

2

CPU_BSEL2_R_14M

2

1

R432

10K_5%

1

2

HOST CLOCK FREQUENCY

166 200 266

Byte5:bit6=1

SRC2

8-,10-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

CPU_BSEL0

17-,20-

RF option

12pF_50V_OPEN

CLK_R3S_ICH48

CLK_R3S_CR48

CLK_R3S_ICH14

CLK_R3S_KBC14

CLK_R3S_MINICARD

CLK_R3S_TCM

CLK_R3S_KBPCI

32-

46-

3239454739-

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

C1402

C1350

2

12pF_50V

RF option

ICH_3S_SMCLK

ICH_3S_SMDATA

C1347 27pF_50V

CLK_PWRGD

1 2

3219-,26-,27-,32-,37-,5019-,26-,27-,32-,37-,50-

X1001

12

1

14.318MHz

2

30PPM

C1346 27pF_50V

Please place close to CLKGEN within 500mils

Byte5:bit5=0 (PWD) , disable CR#3 ; 1, enable CR#3

CR#_3

SRC3

Byte5:bit3=0 (PWD) , disable CR#6 ; 1, enable CR#6

CR#_6

SRC6

12

2.2K_5%

12

C1403

R1286 22_5%

1

C578

2

12pF_50V

CLKREQ_MCH#

CLKREQ_SATA#

10K_5%_OPEN

R1289

10K_5%

R1287 33_5%

1

C574

2

5.6pF_50V

CLKREQ_NC#

RF option

+VCCP

1

R1288

2

1

R1290

2

12

2

12

R439

12

R1261

12

R487

12

+V3S

1

2

0402_OPEN

15-,2015-,32-

15-,46-

22_5%R1259 22_5% 33_5%

33_5%_OPEN

R1260 33_5%

R430

12

10K_5%

R715

12

CR#_7

CR#_9

CR#_10

CR#_11

U1013

62

VDDSRC_IO

52

VDDSRC_IO

38

VDDSRC_IO

23

VDD96_IO

55

VDDSRC

6

VDDREF

31

VDDPLL3_IO

66

VDDCPU_IO

CPUC2_ITP_LPR_SRCC8_LPR

19

VDD48

CPUT2_ITP_LPR_SRCT8_LPR VDDPCI VDDCPU VDDPLL3

USB_48MHZ_FSLA

2

FSLB_TEST_MODE

7

FSLC_TEST_SEL_REF0

8

REF1

PCI1 PCI2_TME PCI3

1

CK_PWRGD_PD#

SCLK

9

SDATA

5

X1

4

X2

GNDPCI GND48

3

GND GND GNDSRC GNDSRC GNDCPU GNDREF GNDSRC

NC CR#7

CR#3 CR#4 TML-PAD TML-PAD TML-PAD TML-PAD

SRCT2_LPR_SATAT_LPR

SRCC2_LPR_SATAC_LPR

27MHz_NonSS_SRCT1_LPR_SE1

27MHz_SS_SRCC1_LPR_SE2

SRCT0_LPR_DOTT_96_LPR

SRCC0_LPR_DOTC_96_LPR

ICS_ICS9LPRS397_MLF_72P

CLK_3S_ICH48

12 72 27

20

13 14 15

10

18 22 26 30 42 59 69

34

11 65 21 37 41 73 74 75 76

Byte5:bit2=0 (PWD) , disable CR#7 ; 1, enable CR#7

SRC8

Byte5:bit1=0 (PWD) , disable CR#9 ; 1, enable CR#9

SRC9

Byte5:bit0=0 (PWD) , disable CR#10 ; 1, enable CR#10

SRC10

Byte6:bit7=0 (PWD) , disable CR#11 ; 1, enable CR#11

SRC11

PCI_STOP#

CPU_STOP#

CPUT1_LPR_F

CPUC1_LPR_F

CPUT0_LPR_F

CPUC0_LPR_F

SRCT11_LPR SRCC11_LPF

SRCT10_LPR SRCC10_LPR

SRCT9_LPR SRCC9_LPR

SRCT7_LPR SRCC7_LPR

SRCT6_LPR SRCC6_LPR

PCI4_27_Select

PCI_F5_ITP_EN

SRCT4_LPR SRCC4_LPR

SRCT3_LPR SRCC3_LPR

CR#11 CR#10

CR#9CR#A

CR#6

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R1257 10K_5%

2

33_5% 33_5%

R1255

ITP_EN =0 SRC8/SRC8#

ITP_EN =1 ITP/ITP#

CLKREQ_MCH#

CLKREQ_SATA#

CLKREQ_MINI_WLAN#

12

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

CLKREQ_NC#

54 53

68 67

71 70

63 64

48 47

50 51

44 45

61 60

57 56

16 17

39 40

35 36

32 33

28 29

24 25

43 46 49 58

10K_5%

R1258

CLK_3S_DEBUG CLK_3S_ICHPCI

CLKREQ_LAN#_R

CHANGE by

+V3S

R12921

2

R1291

0_5%

R491

2

10K_5%

Drawer_Name

15-,2015-,3215-,4615-,45-

1

+V3S

R433

12

10K_5%

12

R1237

R1254 1 2

12

R1256

32-

PCISTOP#_3

32-

CPUSTOP#_3

21-

CLK_MCHBCLK

21-

CLK_MCHBCLK#

16-

CLK_CPUBCLK

16-

CLK_CPUBCLK#

19-

CLK_XDP#

19-

CLK_XDP

45-

CLK_PCIE_MINI_WLAN

45-

CLK_PCIE_MINI_WLAN#

43-

CLK_PCIE_LAN

43-

CLK_PCIE_LAN#

20-

CLK_PEG_MCH

20-

CLK_PEG_MCH#

39-

CLK_R3S_DEBUG

33-

CLK_R3S_ICHPCI

46-

CLK_PCIE_NC

46-

CLK_PCIE_NC#

32-

CLK_PCIE_ICH

32-

CLK_PCIE_ICH#

31-

CLK_SATA1

31-

CLK_SATA1#

50-

CLK_PEG_REF

50-

CLK_PEG_REF#

43-

CLKREQ_LAN#

15-,45-

CLKREQ_MINI_WLAN#

27_Selet =0

LCD_SST 100MHZ

27_Selet =1

27MHZ non-spread clock

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,40-,41-,42-,43-,45-,46-,47-,48-,50-,51-

10K_5% 10K_5%R1285 1 2 10K_5% 10K_5%

INVENTEC

TITLE

INVICTA Cycle1

Clock Generator

SIZE

CODE DOC. NUMBER

A3

CS

17-Mar-2009

SHEET

OF

15 54

REV

A031310A22527-0-MTR

H_A#(35:3)

21-

H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16)

H_REQ#(4:0) H_RS#(2:0)

H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31) H_A#(32) H_A#(33) H_A#(34) H_A#(35)

21-

H_ADSTB#0

H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4)

H_ADSTB#1

H_STPCLK#

21-

31-

H_A20M#

31-

H_FERR#

31-

H_IGNNE#

3131-

H_INTR

31-

H_NMI

31-

H_SMI# CLK_CPUBCLK#

CN14-1

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

ADDR GROUP 0

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

ADDR GROUP 1

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

ICH

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RESERVED

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD010

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

CONTROL

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#

TCK

TDI TDO TMS

XDP/ITP SIGNALS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

H CLK

BCLK0 BCLK1

H1 E2 G5

H5 F21 E1

F1

D20 B3

H4

C1 F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

12

R345

D21

PROCHOT#

A24 B25

10mils/10mils

C7

A22 A21

21-

H_ADS#

21-

H_BNR#

21-

H_BPRI#

21-

H_DEFER#

21-

H_DRDY#

21-

H_DBSY#

21-

H_BREQ#0

31-

H_INIT#

21-

H_LOCK#

21-

H_TRDY#

21-

H_HIT#

21-

H_HITM#

19-

H_BPM0_XDP#

19-

H_BPM1_XDP#

19-

H_BPM2_XDP#

19-

H_BPM3_XDP#

19-

H_BPM4_PRDY#

19-

H_BPM5_PREQ#

19-

H_TCK

19-

TDI_FLEX

19-

H_TDO

19-

H_TMS

19-,32-

XDP_DBRESET#

+VCCP

8-,10-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

56_5%

19-

H_THERMDA

19-

H_THERMDC

20-,31-

PM_THRMTRIP#

15-

CLK_CPUBCLK

15-

+VCCP

8-,10-,11-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-,40-

1

2

51 ohm +/-1% pull-up to +VCCP

R1167

R343

51_5%

56_5%

2

(VCCP) if ITP is implemented.

1

Close to CPU.

H_CPURST#

19-

H_TRST#

1

R1230

54.9_1%

2

H_RS#(0) H_RS#(1) H_RS#(2)

FOX_PZ4782K_274M_41_478P

21-19-,21-

PMCH CPU

ICH8

+VCCP

0"~2"

1"~6"

1"~10"

0"~2"

PM_THRMTRIP# should be T at CPU

CHANGE by

Drawer_Name

17-Mar-2009

INVENTEC

TITLE

INVICTA Cycle1

CPU Penryn-1

DOC. NUMBER

CODE REV

SIZE

A3

1310A22527-0-MTR A03

CS

SHEET

OF

5416

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

H_D#(63:0)

H_DSTBN#0 H_DSTBP#0

H_DINV#0

H_D#(63:0)

+VCCP

8-,10-,11-,15-,16-,18-,19-,20-,21-,23-,24-,31-,34-,40-

1

R387

1K_1%

R386

2K_1%

H_DSTBN#1 H_DSTBP#1

2

1

2

H_DINV#1

CPU_BSEL0 CPU_BSEL1 PSI# CPU_BSEL2

GTLREF

17-,21-

2121-

17-,21-

212121-

15-,2015-,2015-,20-

H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15)

H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31)

TP1014 TP1013

1 2

C464

0.1uF_16V_OPEN

CN14-2

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

DATA GRP 0

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

DATA GRP 1

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

MISC

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

FOX_PZ4782K_274M_41_478P

C366

1 2

0.1uF_16V_OPEN

Place the capacitance close to the TEST3,TEST5 pin. Make sure TEST3,TEST5 routing is reference to GND and away from other noisy signals.

D32# D33# D34# D35# D36# D37# D38# D39# D40#

DATA GRP 2DATA GRP 3

D41# D42# D43# D44# D45# D46#

D47# DSTBN2# DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63# DSTBN3# DSTBP3#

DINV3#

COMP0 COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

CPU_COMP0

R26

CPU_COMP1

U26

CPU_COMP2

R1165 27.4_1%

AA1

CPU_COMP3

Y1

E5 B5 D24 D6 D7 AE6

H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47)

H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)

12

27.4_1%R389

12

54.9_1%R388

12 12

54.9_1%R1166

11-,20-,31-

17-,21-

H_D#(63:0)

21-

H_DSTBN#2

21-

H_DSTBP#2

21-21-

H_DINV#2

17-,21-

H_D#(63:0)

21-

H_DSTBN#3

21-

H_DSTBP#3

21-

H_DINV#3

Close to CPU. COMP0, 2: 18mils.

H_DPRSTP#

31-

H_DPSLP#

21-

H_DPWR#

21-

H_CPUSLP#

11-

31-

R344

12

1K_5%

Place the 1K series resistor on H_PWRGD_XDP without stub.

CPU

0.5" ~ 6" 0.5" ~ 11" 0.5" ~ 11" (L3) (L2) (L1)

H_PWRGD

19-

H_PWRGD_XDP

ICH9M

L1 + L2: 1 ~ 15"

+VCC_CORE

MCH

H_DPRSTP# topology

INVENTEC

TITLE

INVICTA Cycle1

CPU Penryn-2

SIZE

CHANGE by OF

Drawer_Name 17-Mar-2009

A3

DOC. NUMBER

CODE

1310A22527-0-MTR A03

CS

SHEET

REV

5417