Honeywell HX6656 User Manual

Military & Space Products

32K x 8 ROM—SOI HX6656

FEATURES

RADIATION

• Fabricated with RICMOS™ IV Silicon on Insulator (SOI) 0.75 µm Process (L

= 0.6 µm)

eff

• Total Dose Hardness through 1x106rad(SiO2)

• Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s

• Dose Rate Survivability through 1x1011 rad(Si)/s

-2

• Neutron Hardness through 1x10

• SEU Immune

• Latchup Free

OTHER

• Read Cycle Times < 17 ns (Typical) ≤ 25 ns (-55 to 125°C)

• Typical Operating Power <15 mW/MHz

• Asynchronous Operation

• CMOS or TTL Compatible I/O

• Single 5 V ± 10% Power Supply

• Packaging Options

- 28-Lead Flat Pack (0.500 in. x 0.720 in.)

- 28-Lead DIP, MIL-STD-1835, CDIP2-T28

- 36-Lead Flat Pack (0.630 in. x 0.650 in.)

GENERAL DESCRIPTION

The 32K x 8 Radiation Hardened ROM is a high performance 32,768 word x 8-bit read only memory with industrystandard functionality. It is fabricated with Honeywell’s radiation hardened technology, and is designed for use in systems operating in radiation environments. The ROM operates over the full military temperature range and requires only a single 5 V ± 10% power supply. The ROM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 15 mW/MHz in operation, and less than 5 mW when de-selected. The ROM operation is fully asynchronous, with an associated typical access time of 14 ns.

Honeywell’s enhanced SOI RICMOS™IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOS™ IV process is a 5-volt, SIMOX CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of 0.75 µm (0.6 µm effective gate length—L tungsten via plugs, Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability.

). Additional features include

eff

HX6656

FUNCTIONAL DIAGRAM

A:0-8,12-13

NCS

NOE

A:9-11,14

Ro w Decoder

•

CS • CE • OE

(0 = high Z)

32, 768 x 8

Memory

Array

• • •

Column Decoder

Data Output

Signal

1 = enab l ed

Q:0-7

Signal

All controls must b e enabled for a signal to pass. (#: numbe r of

buffers, default = 1)

SIGNAL DEFINITIONS

A: 0-14 Address input pins which select a particular eight-bit word within the memory array. Q: 0-7 Data Output Pins. NCS Negative chip select, when at a low level allows normal read operation. When at a high level NCS forces the

ROM to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers except CE. If this signal is not used it must be connected to VSS.

NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When

at a low level, the data output driver state is defined by NCS and CE. If this signal is not used it must be connected to VSS.

CE* Chip enable, when at a high level allows normal operation. When at a low level CE forces the ROM to a

precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input buffer. If this signal is not used it must be connected to VDD.

TRUTH TABLE

NCS CE* NOE MODE Q

L H L Read Data Out H X XX Deselected High Z

X L XX Disabled High Z

Notes: X: VI=VIH or VIL XX: VSS≤VI≤VDD NOE=H: High Z output state maintained

for NCS=X, CE=X

*Not Available in 28-lead DIP or 28-Lead Flat Pack

RADIATION CHARACTERISTICS

Total Ionizing Radiation Dose

HX6656

The ROM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T =125°C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and ROM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments.

Transient Pulse Ionizing Radiation

The ROM is capable of reading and retaining stored data during and after exposure to a transient ionizing radiation pulse of ≤1 µs duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation (timing degradation during transient pulse radiation is ≤10%), it is suggested that stiffening capacitance be placed on or near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through requirements, typical circuit board mounted de-coupling capacitors are recommended.

The ROM will meet any functional or electrical specification after exposure to a radiation pulse of ≤50 ns duration up to 1x1011 rad(Si)/s, when applied under recommended operating conditions.

Neutron Radiation

The ROM will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm-2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV.

Single Event Phenomena

All storage elements within the ROM are immune to single event upsets. No access time or other performance degradation will occur for LET 190 MeV/cm/mg

Latchup

The ROM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs.

RADIATION HARDNESS RATINGS (1)

Parameter

Total Dose ≥1x10 Transient Dose Rate Upset (3) ≥1x10 Transient Dose Rate Survivability (3) ≥1x10 Neutron Fluence ≥1x10

(1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C. (3) Not guaranteed with 28–Lead DIP.

Limits (2)

Units

rad(SiO2)

rad(Si)/s rad(Si)/s

N/cm

Test Conditions

TA=25°C Pulse width ≤1 µs

Pulse width ≤50 ns, X-ray, VDD=6.0 V, TA=25°C

1 MeV equivalent energy, Unbiased, TA=25°C

HX6656

ABSOLUTE MAXIMUM RATINGS (1)

Rating

Symbol

VDD Positive Supply Voltage (2) -0.5 7.0 V VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V TSTORE Storage Temperature (Zero Bias) -65 150 °C TSOLDER Soldering Temperature • Time 270•5 °C•s PD Total Package Power Dissipation (3) 2.5 W IOUT DC or Average Output Current 25 mA VPROT ESD Input Protection Voltage (4) 2000 V

ΘJC

TJ Junction Temperature 175 °C

(1)Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not

implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2)Voltage referenced to VSS. (3)ROM power dissipation (IDDSB + IDDOP) plus ROM output driver power dissipation due to external loading must not exceed this specification. (4)Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.

Thermal Resistance (Jct-to-Case)

Parameter

Min

28 FP/36 FP 2 28 DIP 10

Max

Units

°C/W

RECOMMENDED OPERATING CONDITIONS

Symbol

VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V TA Ambient Temperature -55 25 125 °C VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V

Parameter

Min

Description

MaxTyp

CAPACITANCE (1)

Symbol

CI Input Capacitance 7 pF CO Output Capacitance 9 pF VIO=VDD or VSS, f=1 MHz

Parameter

Typical

(1)

Worst Case

Min

Max

Units

Test Conditions

VI=VDD or VSS, f=1 MHz

Units

(1) This parameter is tested during initial design characterization only.

+ 8 hidden pages