Honeywell HX6408 User Manual
HX6408
Advanced Information
HX6408
512k x 8 STATIC RAM
The 512K x 8 Radiation Hardened Static RAM is a high
performance 524,288 word x 8-bit static random access
memory with optional industry-standard functionality. It is
fabricated with Honeywell’s radiation hardened Silicon On
Insulator (SOI) technology, and is designed for use in low
voltage systems operating in radiation environments. The
RAM operates over the full military temperature range and
requires only a single 3.3 V ± 0.3V power supply. Power
consumption is typically <30 mW @ 1MHz in write mode,
<14 mW @ 1MHz in read mode, and is less than 5 mW
when in standby mode.
Honeywell’s enhanced RICMOS™(Radiation Insensitive
CMOS) SOI V technology is radiation hardened through the
use of advanced and proprietary design, layout and process
hardening techniques.
FEATURES
Fabricated with RICMOS™ V
Silicon On Insulator (SOI)
0.35 mm Process (Leff = 0.28 µm)
Total Dose ≥ 3x105 and 1X106 rad(SiO2)
Neutron ≥1x1014 cm-2
Dynamic and Static Transient Upset
≥1x10
Dose Rate Survivability ≥1x1012 rad(Si)/s
Soft Error Rate
≤1x10
10
rad(Si)/s (3.3 V)
-10
Upsets/bit-day (3.3 V)
No Latchup
Read/Write Cycle Times
≤20 ns, (3.3 V), -55 to 125°C
Typical Operating Power (3.3 V)
<14 mW @ 1MHz Read
<30 mW @ 1MHz Write
<5 mW Standby mode
Asynchronous Operation
CMOS Compatible I/O
The RICMOS™ V low power process is a SOI CMOS
technology with an 80 Å gate oxide and a minimum
drawn feature size of 0.35 µm. Additional features
include tungsten via and contact plugs, Honeywell’s
proprietary SHARP planarization process and a lightly
doped drain (LDD) structure for improved short
channel reliability. A seven transistor (7T) memory cell
is used for superior single event upset hardening,
while three layer metal power busing and the low
collection volume SOI substrate provide improved
dose rate hardening.
Single Power Supply,
3.3 V ± 0.3 V
Operating Range is
-55°C to +125°C
36-Lead Flat Pack Package
Optional Low Power Sleep
Mode
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HX6408
y
Advanced Information
FUNCTIONAL DIAGRAM 36 LEAD FLAT PACK PINOUT
Address
Decoder
Memory
Arra
NWE
NSL
NCS
NOE
WE • CS
NWE • CS
Timing \ Control
All controls must be enabled
for signal to pass.
# = number of buffers,
Default = 1
1 = enabled
Signal
Signal
#
DQ(0:7)
NCS 6
VDD 9
VSS 10
NWE 13
SIGNAL DEFINITIONS
A: 0-18 Address input pins, which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins, which serve as data outputs during a read operation and as data inputs
during a write operation.
NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level
NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance
state. If this signal is not used it must be connected to VSS.
NWE Negative write enable, when at a low level activates a write operation and holds the data output
drivers in a high impedance state. When at a high level NWE allows normal read operation.
NOE Negative output enable, when at a high level holds the data output drivers in a high impedance
state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This
signal is asynchronous.
NSL Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM
to a precharge condition, holds the data output drivers in a high impedance state and disables all the
input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected
to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option
and pin 36 is then a NC.
A0 1
A1 2
A2 3
A3 4
A4 5
D0 7
D1 8
D2 11
D3 12
A5 14
A6 15
A7 16
A8 17
A9 18
HX6408
Top View
36 (NSL)
35 A18
34 A17
33 A16
32 A15
31 NOE
30 D4
29 D5
28 VSS
27 VDD
26 D6
25 D7
24 A14
23 A13
22 A12
21 A11
20 A10
19 NAS
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HX6408
Advanced Information
TRUTH TABLE
NCS NSL NWE NOE Mode DQ
L H H L Read Data Out
L H L X Write Data In
H X X X Deselected High Z
X L X X Sleep High Z
X: VI = VIH or VIL,
NOE=H: High Z output state maintained for NCS=X, NWE=X
RADIATION
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will
remain within specifications. Total dose hardness is
assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray.
Transistor gate threshold shift correlations have been
made between 10 KeV X-rays applied at a dose rate of
5
1x10
rad(SiO
(Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD voltage levels during transient events.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating conditions.
Note that the current conducted during the pulse by the
RAM inputs, outputs, and power supply may
2
)/min at T= 25°C and gamma rays
significantly exceed the normal operating levels. The
application design must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes an equivalent neutron energy
of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft
Error Rate (SER), under recommended operating
conditions.
This hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with
the SOI substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and
n-channel substrates are made to ensure no
source/drain snapback occurs.
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HX6408
Advanced Information
RADIATION HARDNESS RATINGS (1)
Parameter Limits (2) Units Test Conditions
Total Dose
Transient Dose Rate Upset
Transient Dose Rate Survivability
Soft Error Rate
Neutron Fluence
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0V to 3.6V, TA=-55
ABSOLUTE MAXIMUM RATINGS (1)
VDD Supply Voltage Range (2) -0.5 4.6 V
VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V
TSTORE Storage Temperature (Zero Bias) -65 150 °C
TSOLDER Soldering Temperature (5 seconds) 270 °C
PD Maximum Power Dissipation (3) 2.5 W
IOUT DC or Average Output Current 25 mA
VPROT EST Input Protection Voltage (4) 2000 V
TJ Junction Temperature 175 °C
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is
not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DSEC certified lab.
RECOMMENDED OPERATING CONDITIONS
VDD Supply Voltage (referenced to VSS) 3.0 3.3 3.6 V
TA Ambient Temperature -55 25 125 °C
VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V
VDDRAMP VDD Turn on ramp time 50 ms
≥3X105
6
≥1X10
rad(SiO
) TA=25°C
2
≥1X1010 rad(Si)/s Pulse width ≤50 ns
≥1X10
12
VDD>3.6V, T
rad(Si)/s Pulse width ≤50 ns, X-
=25°C
A
ray,VDD=3.6V,
T
=25°C
A
<1X10
-10
Upsets/bit-day TA= 85°C, Adams 90%
worst case environment
≥1X1014 N/cm2 1MeV equivalent
energy, Unbiased,
T
=25°C
A
o
C to 125oC
Rating Symbol Parameter
Units
Min Max
36 Pin FP 2 ΘJC Thermal Resistance (Jct-to-Case)
Description Symbol Parameter
°C/W
Units
Min Typ Max
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