PACKAGE LIST AND PARTS.......6AMP BIAS ADJUSTMENT128
DISASSEMBLY7SCHEMATIC DIAGRAMS.......129
UNIT EXPLODED VIEW AND PARTS11
Released 2007
Discontinued XXXXRev 0, 10/2007
harman/kardon, Inc.
250 Crossways Park Dr.
Woodbury, New York, 11797
Page 2
harman/kardon
AVR 145/230 service manual
Page 2 of 135
2
ELECTROSTATICALLY SENSITIVE DEVICES
AVR145
harman/kardon
Some semiconductor (solid state) devices can be damaged easily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES devices are integrated circuits and some field effect transistors and
semiconductor "chip" components.
The following techniques should be used to help reduce the incidence of component damage caused by static electricity.
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on
your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device,
which should be removed for potential shock reasons prior to applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to
prevent electrostatic charge build-up or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as "anti-static" can generate electrical charges
sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical change sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement
ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material.)
7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the
chassis or circuit assembly into which the device will be installed.
CAUTION :
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together
or your clothes fabric or the lifting of your foot from a carpeted floor can generate static electricity sufficient to damage an ES devices.
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
Each precaution in this manual should be followed during servicing.
Components identified with the IEC symbolin the parts list are special significance to safety. When replacing a component identified with
, use only the replacement parts designated, or parts with the same ratings or resistance, wattage, or voltage that are designated in the
parts list in this manual. Leakage-current or resistance measurements must be made to determine that exposed parts are acceptably
insulated from the supply circuit before retuming the product to the customer.
Page 3
SAFETY PRECAUTIONS
The following check should be performed for the continued
protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Measure leakage current to a known earth ground (water
pipe, conduit, etc.) by connecting a leakage current tester
between the earth ground and all exposed metal parts of the
appliance (input/output terminals, screwheads, metal
overlays, control shaft, etc.). Plug the AC line cord of the
appliance directly into a 120V AC 60Hz outlet and turn the
AC power switch on. Any current measured must not exceed
o.5mA.
ANY MEASUREMENTS NOT WITHIN THE LIMITS
OUTLINED ABOVE ARE INDICATIVE OF A
POTENTIAL SHOCK HAZARD AND MUST BE
CORRECTED BEFORE RETURNING THE APPLIANCE
TO THE CUSTOMER.
harman/kardon
AVR 145/230 service manual
Page 3 of 135
Reading should
not be above
0.5mA
Earth
ground
Device
under
test
Test all
exposed metal
surfaces
Also test with
plug reversed
(Using AC adapter
plug as required)
Leakage
current
tester
AC Leakage Test
Page 4
Technical Specifications AVR145/230
harman/kardon
AVR 145/230 service manual
Page 4 of 135
Audio Section
Stereo Mode
Continuous Average Power (FTC)
50 Watts per channel, 20Hz–20kHz,
@ < 0.07% THD, both channels driven into 8 ohms
5 Channel Surround Modes
Power Per Individual Channel
Front L&R channels:
40 Watts per channel,
@ < 0.07% THD, 20Hz–20kHz into 8 ohms
Center channel:
40 Watts, @ < 0.07% THD, 20Hz–20kHz into 8 ohms
Surround channels:
40 Watts per channel,
@ < 0.07% THD, 20Hz–20kHz into 8 ohms
Input Sensitivity/Impedance
Linear (High Level)200mV/47kohms
Signal-to-Noise Ratio (IHF-A)100dB
Surround System Adjacent Channel Separation
Video FormatPAL/NTSC
Input Level/Impedance1Vp-p/75 ohms
Output Level/Impedance1Vp-p/75 ohms
Video Frequency Response
(Composite and S-Video)10Hz–8MHz (-3dB)
Video Frequency
Response (Component)10Hz–100MHz (-3dB)
Frequency Response
@ 1W (+0dB, –3dB)10Hz–130kHz
High Instantaneous
Current Capability (HCC)±25 Amps
Transient Intermodulation
Power RequirementAC 220–240V/50Hz
Power Consumption65W idle, 540W maximum
(5 channels driven)
Dimensions (Max)
Width440mm
Height165mm
Depth382mm
Weight9.7 kg
Depth measurement includes knobs, buttons and terminal connections.
Height measurement includes feet and chassis.
All features and specifications are subject to change without notice.
Harman Kardon, The Bridgeand Logic 7 are
registered trademarks of Harman International Industries, Incorporated.
*Manufactured under license from Dolby Laboratories.
“Dolby,”“Pro Logic” and the Double-D symbol are trademarks of Dolby Laboratories.
"DTS" and "DTS Neo:6" are registered trademarks of DTS,
Inc. "96/24" is a trademark of DTS,Inc.
SA-CD is a trademark of Sony Electronics, Inc.
Apple and iPod are registered trademarks of Apple Computer,Inc.
Cirrus is a registered trademark of Cirrus Logic Corp.
**Without input anti slewing and output isolation networks.
TM
is a trademark of Harman International Industries, Inc.
Page 5
45
TROUBLESHOOTING GUIDE
SYMPTOMCAUSESOLUTION
Unit does not function when Main• No AC Power• Make certain AC power cord is plugged into
Power Switch is pusheda live outlet
• Check to see whether outlet is switch-controlled
Display lights,but no sound• Intermittent input connections• Make certain that all input and speaker connections
or pictureare secure
• Mute is on• Press Mute Button
• Volume control is down• Turn up volume control
No sound from any speaker;• Amplifier is in protection mode • Check speaker wire connections for shorts at receiver and
light around power switch is reddue to possible shortspeaker ends
• Amplifier is in protection mode • Contact your local Harman Kardon service center
due to internal problems
No sound from surround or• Incorrect surround mode• Select a mode other than Stereo
center speakers• Input is monaural• There is no surround information from mono sources
• Stereo or Mono program material• The surround decoder may not create center- or rear-channel
information from nonencoded programs
Unit does not respond to• Weak batteries in remote• Change remote batteries
remote commands• Wrong device selected• Press the AVR selector
• Remote sensor is obscured• Make certain front panel sensor is visible to remote
or connect an optional remote sensor
Intermittent buzzing in tuner• Local interference• Move unit or antenna away from computers,fluorescent
lights,motors or other electrical appliances
Letters flash in the channel indicator• Digital audio feed paused• Resume play for DVD
display and digital audio stops• Check that Digital Input is selected
In addition to the items shown above,additional information on troubleshooting possible problems with your AVR 145,or installation-related issues, may
be found in the list of "Frequently Asked Questions" which is located in the Product Support section of our Web site at www.harmankardon.com.
harman/kardon
AVR 145/230 service manual
Page 5 of 135
Page 6
1. Instruction manual ass'y - Accessories
harman/kardon
AVR 145/230 service manual
Page 6 of 135
2. Package Drawing
AVR145/230
1
5
9
POLY BAG
COVER ASS'Y
POLY BAG
2
AM LOOP ANTENNA ASS'Y
6
IMAGE BROCHURES
10
BOOKLET,INFORMATION
3
BATTERY ASS'Y
7
REMOCON
TRANSMITTER ASS'Y
11
MANUAL INSTRUCTION
4
FM 1 POLE ANT
8
STAPLE
12
MANUAL SETUP CODE
2
SNOW PAD (L)
SET
4
ACCESSORY-1
1
SNOW PAD (R)
3
BOX ,OUT CARTON
5
ACCESSORY-1
NO
1
2
3
4
5
6
7
8STAPLECPL09053
DESCRIPTION
POLY BAG
AM LOOP ANTENNA ASS'Y
BATTERY3
FM 1 POL ANT
COVER ASS'Y
1
COVER A
2
COVER B
SHEET,FRONT COVER
3
PAD , COVER
4
5
BAG , POLY
IMAGE BROCHURES
REMOCON ASS'YCARTAVR145/2301
PARTS NO.Q,ty
CPB1061Y
CSA1A027Z
CABR03P3
CSA1A018Z1
CGRAVR130/230ZA
CGR1A331M7H431
CQE1A220Z
CPS1A6761
CPB1A176Z1
HQE1A273Z
13
1
1
STAPLE
1
1
NO
1CGR1A332M7H43
1
1
9
BOOKLET,INFORMATION
10
11
12
MANUAL ,SETUP GUIDE
13
STAPLECPL09053
ACCESSORY-2
DESCRIPTION
PARTS NO.Q,ty
CQE1A180Z1
CQX1A1135YMANUAL,INSTRUCTION
CQX1A1138X
DESCRIPTIONNO
ACCESSORY-1
1CPB1061YPOLY BAG
1
1
1
SNOW,PAD(L)
2
3
SNOW,PAD(R)
4
SET
BOX,OUT CARTON5
6
ACCESSORY-2CQXAVR145/230
CQXAVR145/230
CPS4A564
CPS4A565
AVR145/230SET
CPG1A820W
Q,tyPARTS NO.
1
1
1
1
6
1
1
ACCESSORY-2
Page 7
DISASSEMBLY
harman/kardon
AVR 145/230 service manual
Page 7 of 135
AVR145/230
1. Removing the Top Cabinet
Remove the Screws
6
4
5
3. Removing the Rear Panel
13
1
~
10
9
11
7
8
12
13
3
1
2
Remove the Screws
6
7
8
9
10
19
5
432
202122
25
1
~
11
23
12
24
13
25
1
14
15
16
1718
9
8
7
4. Removing the Main PCB
17
Remove the Screws
~
2. Removing the Front Panel
Remove the Screws
6
5
1
4
2
3
19
~
1
5
2
6
3
4
7
Page 8
Page 8 of 135
AVR145
harman/kardon
AVR145 DISASSEMBLY PROCEDURE
1 TOP-CABINET (21) REMOVAL
1. Remove 13 screws (S1,S7) and then remove the Top-cabinet.
2 FRONT PANEL ASS’Y REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Disconnect the card cable between connector (CN72-17p) on the FIP PCB (37-1) and connector (CN72) on the Input PCB (39-1).
3. Disconnect the lead wire (BN81-8P) on the FIP PCB (37-1) from connector (CN81) on the Trans PCB (40-4).
4. Disconnect the lead wire (BN22-6P) on the Phone PCB (37-5) from connector (CN22) on the Input PCB (39-1).
5. Disconnect the lead wire (BN18-5P) on the Phone PCB (37-5) from connector (CN18) on the Input PCB (39-1)
6. Disconnect the lead wire (BN10-4P) on the Volume PCB (37-6) from connector (CN10) on the Input PCB (39-1)
7. Disconnect the lead wire (BN41-6P) on the Volume PCB (37-6) from connector (CN41) on the Video PCB (41)
8. Remove 1 screw (S10) and then lead wire (JW82-1P,JW83-1P) on the Phone PCB (37-5).
9 .Remove 1screw (S10) and then lead wire (JW84-1P) on the Volume PCB (37-3).
10. Remove 10 screws (S1) and then remove the Front Panel ASS’Y.
3 VOLUME PCB (37-6) REMOVAL
1. Remo ve the Top-cabinet, r eferring to t he prev iou s step 1.
2. Remove the Front Panel ASS’Y, referring to the previous step 2.
3. Pull out the Volume Knob ASS’Y.
4. Disconnect connector (CN84) on the Volume PCB (37-6) from the lead wire (BN84-5P) on the FIP PCB (37-1).
5. Remove 8 screws (S2,S14), and then remove the Volume PCB (37-6).
4 PHONE PCB (37-5) REMOVAL
1. Remo ve the Top-cabinet, r eferring to t he prev iou s step 1.
2. Remove the Front Panel ASS’Y, referring to the previous step 2.
3.. Disconnect connector (CN85)on the Phone PCB (37-5) from the lead wire (BN85-2P) on the FIP PCB (37-1).
4. Remove 2 screws (S2) and then remove the Phone PCB (37-5).
5 POWER LED PCB (37-3) REMOVAL
1. Remo ve the Top-cabinet, r eferring to t he prev iou s step 1.
2. Remove the Front Panel ASS’Y, referring to the previous step 2.
3. Disconnect connector (CN88) on the Power Led PCB (37-3) from the lead wire (BN88-4P) on the FIP PCB (37-1) .
4. Remove 2 screws (S2) and then remove the Power led PCB (37-3).
6 FIP PCB (37-1) REMOVAL
1. Remo ve the Top-cabinet, r eferring to t he prev iou s step 1.
2. Remove the Front Panel ASS’Y, referring to the previous step 2.
3. Disconnect the lead wire (BN84-5P) on the FIP PCB (37-1) from connector (CN84) on the Volume PCB (37-6).
4. Disconnect the lead wire (BN85-2P) on the FIP PCB (37-1) from connector (CN85) on the Phone PCB (37-5).
5. Disconnect the lead wire (BN88-4P) on the FIP PCB (37-1) from connector (CN88) on the Power Led PCB (37-3).
6. Disconnect the connector (CN89) on the FIP PCB (37-1) from lead wire (BN89-4P) on the Key PCB (37-2).
7. Remove 3 screws (S2) and then remove the Guide PCB (37-8) & the FIP PCB (37-1).
7 KEY PCB (37-2) REMOVAL
1. Remo ve the Top-cabinet, r eferring to t he prev iou s step 1.
2. Remove the Front Panel ASS’Y, referring to the previous step 2.
3. Remove the FIP PCB (37-1), referring to the previous step6.
4. Remove 10 screws (S2) and then remove the Key PCB (37-2).
Page 9
Page 9 of 135
AVR145
harman/kardon
8 TUNER MODULE (42) REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Disconnect the card cable between connector (CON1-13p) on the Tuner module (42) and connector (CN13) on Input PCB (39-1).
3. Remove 2 screws (S8) and then remove the Tuner Module (42).
9 VIDEO PCB (41) REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Disconnect the card cable between connector (BN14-13p) on the Video PCB (41) and connector (CN14) on the Input PCB (39-1).
3. Disconnect connector (CN43 ) on the Vide o PCB (41 ) from the lead wire (BN43-4P ) on the Re gulator PCB (A)(40 -2) .
4. Disconnect the card cable between connector (CN42) on the Video PCB (41) and connector (BN44-7p) on the I-Pod PCB (39-2).
5. Disconnect connector (CN41) on the Video PCB (41) from the lead wire (BN41-6P) on the Volume PCB (37-6).
6. Remove 6 screws (S8) and then remove the Video PCB (41).
10 I-POD PCB (39-2) REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Remove the Video PCB (41), referring to the previous step9
3. Disconnect connector (CN46) on the I-Pod PCB (39-2) from the lead wire (BN46-3P) on the Input PCB (39-1).
4. Disconnect the card cable between connector (BN19-9p)) on the I-Pod PCB (39-2) and connector (CN19) on the Input PCB (39-1).
5. Disconnect the card cable between connector (BN44-7p)) on the I-Pod PCB (39-2) and connector (CN42) on the Video PCB (41).
6. Disconnect the card cable between connector (CN47-7p)) on the I-Pod PCB (39-2) and connector (CN47) on the RS232 PCB (37-7).
7. Remove 2 screws (S13) and then remove the I-Pod PCB (39-2).
11 RS232 PCB (37-7) REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Remove the Video PCB (41), referring to the previous step9
3. Disconnect the card cable between connector (CN47) on the RS232 PCB (37-7) and connector (CN47-7) on the RS232 PCB (37-7).
4. Remove 2 screws and then remove the RS232 PCB (37-7).
12 INPUT PCB (39-1) REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Remove the Tuner module (42), referring to the previous step8
3. Remove the Video PCB (41), referring to the previous step9
4. Disconnect connector (CN20) on the the Input PCB (39-1) from the lead wire (BN20-5P) on the Regulator PCB (B)(40-5).
5. Disconnect connector (CN22) on the Input PCB (39-1) from the lead wire (BN22-6P) on the Phone PCB (37-5).
6. Disconnect connector (CN18) on the Input PCB (39-1) from the lead wire (BN18-5P) on the Phone PCB (37-5)
7. Disconnect connector (CN10) on the Input PCB (39-1) from the lead wire (BN10-4P) on the Volume PCB (37-6).
8. Disconnect the card cable between connector (CN14) on the Input PCB (39-1) and connector (BN14-13p)) on the Video PCB (41).
9. Disconnect the card cable between connector (CN19) on the Input PCB (39-1) and connector (BN19-9p) on the I-Pod PCB (39-2)
10. Disconnect the lead wire (BN46-3P) on the Input PCB (39-1) from connector (CN46) on the I-Pod PCB (39-2).
11. Disconnect the card cable between connector (CN12-21p) on the Input PCB (39-1) and connector (CN12-21p)
on the main PCB (38-1)
12. Disconnect the card cable between connector (CN11-13p) on the Input PCB (39-1) and connector (CN11) on the main PCB (38-1)
13. Disconnect the card cable between connector (CN72) on the Input PCB (39-1) and connector (CN72-17p) on the FIP PCB (37-1)
14. Remove 11 screws (S8,S15) and then remove the Input PCB (39-1).
13 POWER TRANS (36) & POWER PCB ASS’Y(40) REMOVAL
1. Remove the Top-cabinet, referring to the previous step 1.
2. Disconnect lead wire of the Power Trans (36) from connector (CN91-3P) on the Main PCB (38-1)
3. Disconnect connector (CN19-3P,CN20-4P) on TRANS PCB (40-3) from the lead wire (BN19-3P,BN20-4P) on the Main PCB (38-1).
4. Disconnect the lead wire (BN96-8P) on the Power PCB (40-4) from connector (CN96) on the Regulator PCB (B)(40-5).
5. Disconnect the lead wire (BN99-8P) on the Power PCB (40-4) from connector (CN99) on the Regulator PCB (A)(40-2).
6. Disconnect connector (CN81) on the Trans PCB (40-4) from the lead wire (BN81-8P) on the FIP PCB (37-1).
7. Remove 4 Trans screws (S9) and then remove the Power Trans (36)& Power PCB ASS’Y(40) REMOVAL .
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AVR145
harman/kardon
14 MAIN PCB AS S ’Y (38 -1 ) REMOVA L
1. Remove the Top-cabinet, referring to the previous step 1.
2. Remove the Tuner module (42), referring to the previous step8.
3. Remove the Video PCB (41) referring to the previous step9.
4. Remove the I-Pod PCB (39-2), referring to the previous step 10.
5. Remove the RS232 PCB (37-7), referring to the previous step 11.
6. Remove the Input PCB (39-1), referring to the previous step 12.
7. Remove the AC Cord(35) on the Main PCB (38-1)
8. Disconnect the lead wire (BN90-2P) on the Main PCB (38-1) from connector (CN86) on Moms PCB (37-4).
9. Disconnect connector (CN91-3P) on the Main PCB (38-1) from lead wire of the Power Trans (36)
10. Disconnect the lead wire (BN89-2P) on the Main PCB (38-1) from connector (CN89) on Regulator PCB (A)(40-2).
11. Disconnect the lead wire (BN19-3P,BN20-4P) on the Main PCB (38-1) from connector (CN19-3P,CN20-4P) on TRANS PCB (40-4).
12. Remove 11screws (S13-1EA, S4-2EA, S6-2EA, S8-6EA) and then remove the Main PCB ASS’Y (38-1).
The NJM2595 is a 5-input 3-output video switch. Its switches
select one from five signals received from VTR,TV,DVD,
TV-GAME and others.
The NJM2595 is designed for audio items, such as AV amplifier
and others.
NJM2595D NJM2595M
■ FEATURES
● 5-input 3-output
● Operating Voltage ±4.0 to ±6.5V
● Operating current ±15mAtyp. at Vcc=±5V
● Crosstalk -65dBtyp.
● Internal 6dB Amplifier
● Internal 75Ω Driver
● Bipolar Technology
● Package Outline DIP16,DMP16
■ PIN CONFIGURATION and BLOCK DIAGRAM
16
+
SW2V
10 14 2
SW1
SW5
Vin1
Vin2
Vin3
Vin4
Vin5
13
20k
20k
20k
S5
S6
S7
6dB
Amp
6dB
Amp
6dB
Amp
8 12 6 4
-
75Ω
Driver
75Ω
Driver
75Ω
Driver
1
15
11
Vout1
Vout2
Vout3
9
20k
7
20k
5
20k
3
20k
S2
S3
SW3
S4
SW4
S1
GND V
Page 49
harman/kardon
AVR 145/230 service manual
Page 49 of 135
■EQUIVA LENT CIRCUIT
PIN No. PIN NAME INSIDE EQUIVALENT CIRCUIT VOLTAGE
16 V+ 5V
8 V- -5V
12 GND -
NJM2595
13
9
7
5
3
1
15
11
Vin1
Vin2
Vin3
Vin4
Vin5
Vout1
Vout2
Vout3
Vin
Vcc
260
2.1k
20k
Gnd
Vcc
Vee
Vout
0V
0V
4
6
2
SW3
SW4
SW5
Vee
SW
16k
8k
20k
Gnd
Vcc
4k
Vee
-
Page 50
harman/kardon
AVR 145/230 service manual
Page 50 of 135
NJM2595
■EQUIVA LENT CIRCUIT
PIN No. PIN NAME INSIDE EQUIVALENT CIRCUIT VOLTAGE
14
10
■TEST CIRCUIT
V
SW1
SW2
+
Vout2.2 Vout2.1
SW
32k
16k
20k
Gnd
Vout3.2
Vcc
4k
Vee
Vout3.1
-
0.1µF
75
Ω
V
CL
V
CH
75
Ω
Vin1
+
100µF
75
Ω
SW1
10µF
+
16 15 14 1312 11
+
V
Vout1
Vout2
SW5
SW1
Vin5
Vin1
SW3
1
+
75
Ω
SW5
+
10µF
SW3
Vin5
75
Ω
V
V
CL
CH
75
Ω
V
V
CL
CH
GND
Vin4
10µF
Vin4
75
Ω
75
75
V
Ω
V
CL
V
CH
75
Ω
Vin2
SW2
Ω
10µF
+
9
Vin2
-
V
Vout3
SW4
10
SW2
Vin3
8765432
+
10µF
SW4
0.1µF
Vin3
+
100µF
75
Ω
V
CL
CH
Vout1.2Vout1.1
-
V
Page 51
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Page 63
ANALOG MULTIPLEXER/DEMULTIPLEXER
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Page 63 of 135
■ LOW "O N" RESISTANCE : 125Ω(Typ.)
OVER 15V p.p SIGNA L-INPU T R A N GE FOR
V
DD-VEE
■ HIGH "OFF" RESISTANCE : CHANNEL
LEAKAGE ± 100pA (Typ.) at V
■ BINARY A DDRES S DECO DING ON CHIP
■ HIG H DEGREE OF LINEARITY : < 0. 5 %
DISTORTION TYP.at f
V
DD-VSS
■ VERY LOW QUIESCENT POWER
DISSIPATION UNDER ALL DIGITAL
CONTROL INPUT A ND SUPPLY
CONDITIONS : 0.2
at V
■ MATCHED SWITCH CHARACTERISTICS :
R
ON
■ WIDE RANGE OF DIGITAL AND ANALOG
SIGNAL LEVELS : DIGITAL3 to 20,
ANALOG TO 20V p.p.
■ QUIESCENT CURRENT SPECIF. UP TO 20V
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD=18VTA= 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARDSPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4053B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
= 15V
DD-VEE
=1KHz,VIS=5Vpp,
IS
> 10V, RL = 10KΩ
µW(Typ.)
DD-VSS=VDD-VEE
=10V
=5Ω (Typ.) FOR VDD-VEE= 15V
=18V
HCF4053B
TRIPLE 2-CHANNEL
DIPSOP
ORDER CODES
PACKAGETUBET & R
DIPHCF4053BEY
SOPHCF4053BM1HCF4053M013TR
technology available in DIP and SOP packages.
The HCF4053B analog multiplexer/demultiplexer
is a digitally controlled analog switch having low
ON impedance andvery low OFF leakagecurrent.
This multiplexer circuit dissipate extremely low
quiescent power over the full V
V
supply voltage rang e, independent of the
EE
DD-VSS
logic state of the control signal s.
When a logic "1" is present at the inhibit input
terminal all channel are off. This device is a triple
2-channel multiplexer having three separate
digital control inputs, A, B, and C, and an inhibit
input. Eac h control input selects one of a pair of
channels which are connected in a single pole
double-throw configuration.
and VDD-
PIN CONNECTION
1/10October 2002
Page 64
HCF4053B
harman/kardon
AVR 145/230 service manual
Page 64 of 135
INPUT EQUIVALENT CIRCUITPIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
11, 10, 9A, B, CBinary Control Inputs
6INHInhibit Inputs
12, 13, 2,1,
5, 3
14OUT/INax or ay
15OUT/INbx or by
4OUT/INcx or cy
7
8
16
TRUTH TABLE
INHIBITC or B or A
00ax or bx or cx
01ay or by or cy
1XNONE
X : Don’t Care
IN/OUT
V
V
V
EE
SS
DD
ax,ay,bx,by,cx,cy Input/
Output
Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
“H” during first 40 flames.
Output Buffer Power Supply Pin, 2.7V∼5.25V
Digital Power Supply Pin, 4.75V∼5.25V
5 DVSS - Digital Ground Pin
6 XTO O X'tal Outp ut Pin
7 XTI I X'tal Input Pin
8 TEST3 I
Test 3 Pin
This pin should be connected to DVSS.
9 MCKO2 O Master Clock Output 2 Pin
10 MCKO1 O Master Clock Output 1 Pin
11 COUT O C-bit Output Pin for Receiver Inpu t
12 UOUT O U-bit Output Pin for Receiver Input
13 VOUT O V-bit Output Pin for Receiver Inpu t
14 SDTO2 O Audio Serial Data Output Pin (DIR/DIT part)
15 BICK2 I/ O Audio Serial Data Clock Pin (DIR/DIT part)
16 LRCK2 I/O Channel Clock Pin (DIR/DIT part)
17 SDTO1 O Audio Serial Data Output Pin (ADC/ DAC part)
18 BICK1 I/ O Audio Serial Data Clock Pin (ADC/DAC part)
19 LRCK1 I/O Input Channel Clock Pin
20 CDTO O Control Data Output Pin in Serial Mode, I2C= “L”.
CCLK I Control Data Clock Pin in Serial Mode, I2C= “L”
21
SCL I Control Data Clock Pin in Serial Mode, I2 C= “H”
CDTI I Control Data Input Pin in Serial Mode, I2C= “L”.
22
SDA I/O Control Data Pin in Serial Mode, I2C= “H”.
23 CSN
I Chip Select Pin in Serial Mode, I2C= “L”.
I This pin should be connected to DVSS, I 2C = “H” .
24 DAUX1 I AUX Audio Serial Data Input Pin (ADC/DAC part)
25 SDTI4 I DAC4 Audio Serial Data Input Pin
26 SDTI3 I DAC3 Audio Serial Data Input Pin
27 SDTI2 I DAC2 Audio Serial Data Input Pin
28 SDTI1 I DAC1 Audio Serial Data Input Pin
29 XTL1 I X’tal Frequency Select 0 Pin
30 XTL0 I X’tal Frequency Select 1 Pin
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ASAHI KASEI [AK4589]
harman/kardon
AVR 145/230 service manual
Page 83 of 135
No. Pin Name I/O Function
Power-Down Mode Pin
31 PDN I
When “L”, the AK4589 is powered-down, all digital output pins go “L”, all registers
are reset. When CAD1/0 pins are changed, the AK4589 should be reset by PDN pin.
32 MASTER I
Master Mode Select Pin
“H”: Master mode, “L”: Slave mode
Zero Input Detect 2 Pin (Table 13)
DZF2 O
33
OVF O
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN bit is “0”, this pin
goes to “H”. It always is in “L” when P/S pin is “H”.
Analog Input Overflow Detect Pin
This pin goes to “H” if the analog input of Lch or Rch overflows.
Zero Input Detect 1 Pin (Table 13)
34 DZF1 O
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN bit is “0”, this pin
goes to “H”. Output is selected by setting DZFE pin when P/S pin is “H”.
35 LOUT4- O DAC4 Lch Negative Analog Output Pin
36 LOUT4+ O DAC4 Lch Positive Analog Output Pin
37 ROUT4- O DAC4 Rch Negative Analog Output Pin
38 ROUT4+ O DAC4 Rch Positive Analog Output Pin
39 LOUT3- O DAC3 Lch Negative Analog Output Pin
40 LOUT3+ O DAC3 Lch Positive Analog Output Pin
41 ROUT3- O DAC3 Rch Negative Analog Output Pin
42 ROUT3+ O DAC3 Rch Positive Analog Output Pin
43 LOUT2- O DAC2 Lch Negative Analog Output Pin
44 LOUT2+ O DAC2 Lch Positive Analog Output Pin
45 ROUT2- O DAC2 Rch Negative Analog Output Pin
46 ROUT2+ O DAC2 Rch Positive Analog Output Pin
47 LOUT1- O DAC1 Lch Negative Analog Output Pin
48 LOUT1+ O DAC1 Lch Positive Analog Output Pin
49 ROUT1- O DAC1 Rch Negative Analog Output Pin
50 ROUT1+ O DAC1 Rch Positive Analog Output Pin
470pF capacitor should be connected
between L O UT4- a nd LOUT4+ .
470pF capacitor should be connected
between ROUT4- an d RO UT4+ .
470pF capacitor should be connected
between L O UT3- a nd LOUT3+ .
470pF capacitor should be connected
between ROUT3- an d RO UT3+ .
470pF capacitor should be connected
between L O UT2- a nd LOUT2+ .
470pF capacitor should be connected
between ROUT2- an d RO UT2+ .
470pF capacitor should be connected
between L O UT1- a nd LOUT1+ .
470pF capacitor should be connected
between ROUT1- an d RO UT1+ .
51 LIN I Lch Analog Input Pin
52 RIN I Rch Analog Input Pin
53 VCOM 54 VREFH -
Common Voltage Output Pin
2.2µF capaci tor shoul d be con nected to AVSS externally.
Positive Voltage Reference Input Pin, AVDD
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ASAHI KASEI [AK4589]
harman/kardon
AVR 145/230 service manual
Page 84 of 135
No. Pin Name I/O Function
55 AVDD - An alog Power Supply Pin, 4.75V ∼5.25V
56 AVSS -
Analog Ground Pin, 0V
57 RX0 I Receiver Chann el 0 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
58 NC -
No Connect pin
No internal bonding. This pin should be connected to PVSS.
59 RX1 I Receiver Chann el 1 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
60 TEST1 I
Test 1 Pin
This pin should be connected to PVSS.
61 RX2 I Receiver Chann el 2 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
62 NC -
No Connect pin
No internal bonding. This pin should be connected to PVSS.
63 RX3 I Receiver Chann el 3 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
64 PVSS - PLL Ground pin
65 R 66 PVDD -
External Resist or Pin
12kΩ +/-1% resistor sh ould be conn ect ed to PVSS external ly.
PLL Power supply Pin, 4.75V∼5.25V
67 RX4 I Receiver Chann el 4 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
68 TEST2 I
Test 2 Pin
This pin should be connected to PVSS.
69 RX5 I Receiver Chann el 5 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
70 CAD0 I
Chip Address 0 Pin (ADC/DAC part)
71 RX6 I Receiver Chann el 6 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
72 CAD1 I
Chip Address 1 Pin (ADC/DAC part)
73 RX7 I Receiver Chann el 7 Pin (Intern al biased pin. Internally biased at PVDD/ 2)
74 I2C I
Control Mode Select Pin .
“L”: 4-wire Serial, “H”: I
2
C Bus
75 DAUX2 I Auxiliary Audio Data Input Pin (DIR/DIT part)
76 VIN I V-bit Input Pin for Transmitter Output
77 MCLK I
Master Clock Input Pin
78 TX0 O Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
79 TX1 O
When DI T bit = “0 ”, Through Data.
When DIT bit = “1”, DAUX2 Data.
The M29W800D is a 8 Mbit (1Mb x8 or 512Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently s o i t is po ss ib le to p re se rve
valid data while old data is erased. Each block can
be protected independen tly to prevent accidental
Program or Erase comman ds from modifying the
memory. Program and Erase co mmands are written to the Command Int erface o f the memo ry. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation c an be
detected and any error conditions identified. The
M29W800DT, M29W800DB
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memo ry are asymmet rically arranged, see Figures 6 and 7, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in SO44, TSOP48 (12 x
20mm), TFBGA48 6 x 9mm (0.8mm pitch) and
TFBGA48 6 x 8mm (0.8mm pitch ) packages. T he
memory is supplied with all the bits er ased (set to
’1’).
Figure 2. Logic DiagramTable 1. Signal Names
A0-A18Address Inputs
DQ0-DQ7Data Inputs/Outputs
DQ8-DQ14Data Inputs/Outputs
DQ15A–1Data Input/Output or Address Input
E
G
W
RP
Note: Also see APPENDIX A., Tables 21 and 22 for a full listing of the Block Addresses.
AI05463
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Figure 7. Block Addresses (x16)
harman/kardon
AVR 145/230 service manual
Page 91 of 135
M29W800DT, M29W800DB
Top Boot Block Addresses (x16)
7FFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
78000h
77FFFh
70000h
0FFFFh
08000h
07FFFh
00000h
M29W800DT
8 KWord
4 KWord
4 KWord
16 KWord
32 KWord
32 KWord
32 KWord
Total of 15
32 KWord Blocks
Bottom Boot Block Addresses (x16)
7FFFFh
78000h
77FFFh
70000h
0FFFFh
08000h
07FFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
M29W800DB
32 KWord
32 KWord
32 KWord
16 KWord
4 KWord
4 KWord
8 KWord
Total of 15
32 KWord Blocks
Note: Also see APPENDIX A., Tables 21 and 22 for a full listing of the Block Addresses.
AI05464
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Page 92
M29W800DT, M29W800DB
harman/kardon
AVR 145/230 service manual
Page 92 of 135
SIGNAL DESCRIPTIONS
See Figure 2.,Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A18). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When r eading th e Status Re gister
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-
1). When BYTE
a Data Input/Output pin (as DQ8-DQ14). When
BYTE
is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include th is pin when
BYTE
is High and references to t he Address Inputs to include this pin when BYT E
when stated explicitly otherwise.
Chip Enable (E
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
, all other pins are ignored.
IH
Output Enable (G
trols the Bus Read operation of the memory.
Write Enable (W
the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP
Reset/Block Temporary Unprotect pin can be
used to ap p ly a Ha r d wa r e R es et t o t h e m e mo ry or
to temporarily unprote ct all Bl ock s th at h av e be en
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unpr otect Low, V
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, V
Read and Bus Write operations after t
is High, VIH, this pin behaves as
is Low except
). The Chip Enable, E, activates
). The Out put Enable, G, con-
). The Write Ena bl e, W, controls
). The
, for at least
IL
, the memory will be ready fo r Bus
IH
PHEL
or
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Tabl e 15. and Figure 15., Reset/
Block Temporary Unprotect AC Waveforms, for
more details.
Holding RP
at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
PHPHH
.
Ready/Busy Output (RB
to VID must be slower than
IH
). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
. Ready/Busy is hig h-im-
OL
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 15., Reset/
Block Temporary Unprotect AC Characteristics
and Figure 15., Reset/Block Temporary Unprotect
AC Waveforms.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE
). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Select is Low, V
it is High, V
V
Supply Voltage. The VCC Supply Voltage
CC
, the memory is in 8-bit mode, when
IL
, the memory is in 16-bit mode.
IH
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is le ss than the Lockout Vo ltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacito r should be connected between
the V
Supply Voltage pin and the VSS Ground
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
V
Ground. The VSS Ground is the reference for
SS
CC3
.
all voltage measurements.
Page 93
BUS OPERATIONS
harman/kardon
AVR 145/230 service manual
Page 93 of 135
There are five standard bus operations that control
the device. These are Bus Read, Bus Writ e, Output Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Oper ations, for a summary.
Typically glitches of les s than 5ns on Chip Enab le
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low s ignal , V
and Output Enable and keeping Write Enable
High, V
. The Data Inputs/Outputs will ou tput the
IH
value, see Figure 12., Read Mode AC Waveforms,
and Table 12., Read AC Characteristics for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operati on
begins by setting the desired address on the Address Inputs. The Ad dress Inputs are latched b y
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs ar e latched by the Com mand Interface on the rising ed ge of Chip Enab le
or Write Enable, whichever occurs first. Output Enable must remain High, V
IH
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
.
IH
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
, to Chip Enable
IL
, during the whole Bus
, the
IH
M29W800DT, M29W800DB
ance state. To reduce the Su pply Current to the
Standby Supply Current, I
be held within V
± 0.2V. For the Standby current
CC
level see Table 11., DC Characteristics.
During program or eras e operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC3
til the operation completes.
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the interna l Supply Current is reduced to the Stan dby Supply Current, I
Data Inputs/Outputs wi ll still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment an d are not u sually used in applicatio ns. They require V
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can b e read b y apply ing the s ignals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blo cks, one for use on programming equipment and t he other for in-system
use. Block Protect a nd Chi p Un protec t o perations
are described in APPENDIX C.
, Chip Enable should
CC2
CC
CC2
± 0.2V)
. The
to be
ID
Table 2. Bus Operations, BYTE
OperationEGW
Bus Read
Bus Write
Output DisableX
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VIL or VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
= V
IL
Address Inputs
DQ15A–1, A0-A1 8
V
IL
V
IH
V
IH
XXXHi-ZHi-Z
V
IL
V
IL
V
Cell AddressHi- ZData Outpu t
IH
V
Command AddressHi-ZData Input
IL
V
XHi-ZHi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID,
V
IH
Others V
A0 = VIH, A1 = VIL, A9 = VID,
V
IH
Others V
IL
IL
or V
or V
IH
IH
Data Inputs/Outputs
DQ14-DQ8DQ7-DQ0
Hi-Z20h
Hi-Z
D7h (M29W800DT)
5Bh (M29W800DB)
11/42
Page 94
M29W800DT, M29W800DB
harman/kardon
AVR 145/230 service manual
Page 94 of 135
Table 3. Bus Operations, BYTE = V
OperationEGW
Bus Read
Bus Write
Output DisableX
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VIL or VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
IH
V
IL
V
IH
V
IH
XXXHi-Z
V
IL
V
IL
V
Cell AddressData Output
IH
V
Command AddressData Input
IL
V
XHi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID,
V
IH
Others V
A0 = VIH, A1 = VIL, A9 = VID,
V
IH
Others VIL or V
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operation s will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memor y is in 16-bit or 8bit mode. See either Table 4, or 5, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless otherwise stated. It also resets the error s in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. Once th e pro gram or erase operati on
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select command is used to read t he Manu facturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Sel ect command. Once
the Auto Select comman d is issued the memory
remains in Auto Sele ct mode until a Read/Res et
command is issue d. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignor ed.
Address Inputs
A0-A18
or V
IL
IH
IH
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
0020h
22D7h (M29W800DT)
225Bh (M29W800DB)
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V
and A1 = VIL. The other address bits
IL
or VIH. The Manufacturer
IL
Code for STMicroelectronics is 0020h.
The Device Code ca n be read using a Bu s Read
operation with A0 = V
address bits may be s et to either V
and A1 = VIL. The other
IH
or VIH. The
IL
Device Code for the M29W800DT is 22D7h and
for the M29W800DB is 225Bh.
The Block Protection Status of each block can be
read using a Bus Read oper ation with A0 = V
A1 = V
, and A12-A18 specifying the address of
IH
the block. The other address bits may be set to either V
or VIH. If the addressed block is protected
IL
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protect ed block then the
Program command is ignored, the data remain s
unchanged. The Status Register is never read and
no error condition is given.
During the program operation th e memory will ig nore all commands. It is no t possib le to is sue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the p rogram operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
,
IL
Page 95
M29W800DT, M29W800DB
harman/kardon
AVR 145/230 service manual
Page 95 of 135
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back t o ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bu s Write operations are r equired
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program com mand and the Unlock B ypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to
program one address in memory at a time. The
command requires tw o Bus Write operati ons, the
final write operati on lat ches the addr ess and d ata
in the internal state machine and starts the Program/Erase Controller.
The Program operation us ing the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be progra mme d; the op er ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leav es the device in Unlock Bypass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset comm and can b e used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unc hanged . No er ror con dition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read operations during the Chi p Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase o per at ion has c om ple ted the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a l ist of one or more
blocks. Six Bus W rite operations are required to
select the first block in the list. Each additional
block in the list can be select ed by repeating the
sixth Bus Write operation using the address of the
additional block. The Bl ock Er as e op er ation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the sel ected blocks are prot ected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase o per at ion the me mor y will
ignore all comman ds except the Erase Suspe nd
command. Typical bloc k erase times are give n in
Table 6. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. S ee the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error conditio n and return to Read mode.
The Block Erase Comma nd sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
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AVR 145/230 service manual
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Erase Suspend Command . The Erase Suspend
Command may be used to tempor arily suspend a
Block Erase operation a nd return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Control ler will sus pend with in
the Erase Suspend Latency Time (refer to Table 6.
for value) of the Erase Suspen d Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additiona l block (before
the Program/Erase Controller starts) then the
Erase is suspende d i mme di atel y and wil l sta rt im mediately when the Eras e Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend i t is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. I f any atte mpt is made to
program in a protected bloc k or in the su spended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error c ondit ion is gi ven. Read ing from blocks that are being erased will output
the Status Register.
It is also possible to is sue the Auto Select, Re ad
CFI Query and Unloc k Bypass com mands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be accepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Fl ash Inter face (CFI) Memo ry Are a. Th is
command is valid when the device is in the Read
Array mode, or when the device is in Auto Se lect
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. O nce the command is issued subsequent Bus Read operations r ead from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Aut o Select mode ). A second Re ad/
Reset command would be needed if the d evic e is
to be put in the Read Array mode from Auto Select
mode.
See APPENDIX B. , Tables 23, 24, 25, 26, 27 and
28 for details on the informati on contained in the
Common Flash Interface (CFI) memory area.
Block Protect and Chip Unprotect Commands.
Each block can be separately protected against
accidental Program or Er ase. The wh ole chi p can
be unprotected to allow th e da ta in si de the b lock s
to be changed.
Block Protect an d Chip Unprotect ope rations are
described in APPENDIX C.
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MITSUMI
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AVR 145/230 service manual
Page 97 of 135
Video Switch · 75Ω driver · Y/C mix MM1501
Video Switch · 75Ω driver · Y/C mix
Monolithic IC MM1501 Series
Outline
This IC extends the series of ICs for video/audio signal switching, with a 2-input 1-output single video switch,
video signal/chroma signal 75Ω driver, and Y/C mixing circuit in one small package (SOT-26).
Features
(1) Low power consumption achieved.
(2) Low power supply voltage realized.
(3) Frequency bandwidthwithout 75Ω driver: 10MHzwith 75Ω driver: 7MHz
(4) Cross talk 70dB When 4.43MHz
(5) With SAG measures pin (75Ω driver and Y/C mix driver)