Preliminary
GS88218/36B-11/11.5/100/80/66
119-Bump BGA |
512K x 18, 256K x 36 ByteSafe™ |
100 MHz–66 MHz |
Commercial Temp |
8Mb S/DCD Sync Burst SRAMs |
3.3 V VDD |
Industrial Temp |
3.3 V and 2.5 V I/O |
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Features
•FT pin for user-configurable flow through or pipeline operation
•Single/Dual Cycle Deselect Selectable
•IEEE 1149.1 JTAG Compatible Boundary Scan
•On-chip write parity checking; even or odd selectable
•ZQ mode pin for user-selectable high/low output drive strength
•x16/x32 mode with on-chip parity encoding and error detection
•3.3 V +10%/–5% core power supply
•2.5 V or 3.3 V I/O supply
•LBO pin for Linear or Interleaved Burst mode
•Internal input resistors on mode pins allow floating mode pins
•Default to SCD x18/x36 Interleaved Pipelined mode
•Byte Write (BW) and/or Global Write (GW) operation
•Common data inputs and data outputs
•Clock Control, registered, address, data, and control
•Internal self-timed write cycle
•Automatic power-down for portable applications
•119-bump BGA package
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-11 |
-11.5 |
-100 |
-80 |
-66 |
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Pipeline |
tCycle |
10 ns |
10 ns |
10 ns |
12.5 ns |
15 ns |
3-1-1-1 |
tKQ |
4.0 ns |
4.0 ns |
4.0 ns |
4.5 ns |
5 ns |
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IDD |
225 mA |
225 mA |
225 mA |
200 mA |
185 mA |
Flow |
tKQ |
11 ns |
11.5 ns |
12 ns |
14 ns |
18 ns |
Through |
tCycle |
15 ns |
15 ns |
15 ns |
15 ns |
20 ns |
2-1-1-1 |
IDD |
180 mA |
180 mA |
180 mA |
175 mA |
165 mA |
Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1 and E2), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output Register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising- edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS88218/36B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input on Bump 4L.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
ByteSafe™ Parity Functions
The GS88218/36B features ByteSafe data security functions. See “ByteSafe™ Parity Functions” on page 8 for further information.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart on page 38 for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88218/36B operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
Rev: 1.15 5/2001 |
1/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
GS88236 Pad Out
119-Bump BGA—Top View
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A |
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VDDQ |
A6 |
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A7 |
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ADSP |
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A8 |
A9 |
VDDQ |
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B |
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NC |
E2 |
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A4 |
ADSC |
A15 |
A17 |
NC |
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C |
NC |
A5 |
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A3 |
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VDD |
A14 |
A16 |
NC |
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D |
DQC4 |
DQC9 |
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VSS |
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ZQ |
VSS |
DQB9 |
DQB4 |
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E |
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DQC3 |
DQC8 |
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VSS |
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E1 |
VSS |
DQB8 |
DQB3 |
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F |
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VDDQ |
DQC7 |
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VSS |
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G |
VSS |
DQB7 |
VDDQ |
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G |
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DQC2 |
DQC6 |
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BC |
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ADV |
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BB |
DQB6 |
DQB2 |
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H |
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DQC1 |
DQC5 |
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VSS |
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GW |
VSS |
DQB5 |
DQB1 |
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J |
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VDDQ |
VDD |
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DP |
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VDD |
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QE |
VDD |
VDDQ |
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K |
DQD1 |
DQD5 |
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VSS |
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CK |
VSS |
DQA5 |
DQA1 |
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L |
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DQD2 |
DQD6 |
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BD |
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SCD |
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BA |
DQA6 |
DQA2 |
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M |
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VDDQ |
DQD78 |
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VSS |
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BW |
VSS |
DQA7 |
VDDQ |
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N |
DQD3 |
DQD8 |
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VSS |
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A1 |
VSS |
DQA8 |
DQA3 |
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P |
DQD4 |
DQD9 |
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VSS |
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A0 |
VSS |
DQA9 |
DQA4 |
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R |
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NC |
A2 |
LBO |
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VDD |
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FT |
A13 |
PE |
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T |
NC |
NC |
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A10 |
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A11 |
A12 |
NC |
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ZZ |
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U |
VDDQQ |
TMS |
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TDI |
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TCK |
TDO |
NC |
VDDQ |
Rev: 1.15 5/2001 |
2/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
GS88218 Pad Out
119-Bump BGA—Top View
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3 |
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A |
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VDDQ |
A6 |
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A7 |
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ADSP |
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A8 |
A9 |
VDDQ |
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B |
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NC |
E2 |
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A4 |
ADSC |
A15 |
A17 |
NC |
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C |
NC |
A5 |
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A3 |
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VDD |
A14 |
A16 |
NC |
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D |
DQB1 |
NC |
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VSS |
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ZQ |
VSS |
DQA9 |
NC |
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E |
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NC |
DQB2 |
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VSS |
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E1 |
VSS |
NC |
DQA8 |
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F |
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VDDQ |
NC |
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VSS |
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G |
VSS |
DQA7 |
VDDQ |
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G |
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NC |
DQB3 |
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BB |
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ADV |
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NC |
NC |
DQA6 |
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H |
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DQB4 |
NC |
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VSS |
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GW |
VSS |
DQA5 |
NC |
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J |
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VDDQ |
VDD |
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DP |
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VDD |
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QE |
VDD |
VDDQ |
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K |
NC |
DQB5 |
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VSS |
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CK |
VSS |
NC |
DQA4 |
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L |
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DQB6 |
NC |
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NC |
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SCD |
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BA |
DQA3 |
NC |
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M |
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VDDQ |
DQB7 |
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VSS |
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BW |
VSS |
NC |
VDDQ |
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N |
DQB8 |
NC |
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VSS |
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A1 |
VSS |
DQA2 |
NC |
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P |
NC |
DQB9 |
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VSS |
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A0 |
VSS |
NC |
DQA1 |
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R |
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NC |
A2 |
LBO |
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VDD |
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FT |
A13 |
PE |
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T |
NC |
A10 |
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A11 |
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NC |
A12 |
A18 |
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ZZ |
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U |
VDDQ |
TMS |
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TDI |
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TCK |
TDO |
NC |
VDDQ |
Rev: 1.15 5/2001 |
3/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary |
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GS88218/36B-11/11.5/100/80/66 |
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GS88218/36 BGA Pin Description |
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Pin Location |
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Symbol |
Type |
Description |
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P4, N4 |
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A0, A1 |
I |
Address field LSBs and Address Counter Preset Inputs |
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A2, A3, A5, A6, B3, B5, B6, C2, C3, |
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An |
I |
Address Inputs |
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C5, C6, R2, R6, T3, T5 |
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T4 |
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An |
I |
Address Inputs (x36 Version) |
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T2, T6 |
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NC |
— |
No Connect (x36 Version) |
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T2, T6 |
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An |
I |
Address Inputs (x18 Version) |
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K7, K6, L7, L6, M6, N7, N6, P7, P6 |
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DQA1–DQA9 |
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H7, H6, G7, G6, F6, E7, E6, D7, D6 |
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DQB1–DQB9 |
I/O |
Data Input and Output pins (x36 Version) |
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H1, H2, G1, G2, F2, E1, E2, D1, D2 |
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DQC1–DQC9 |
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K1, K2, L1, L2, M2, N1, N2, P1, P2 |
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DQD1–DQD9 |
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L5, G5, G3, L3 |
BA, BB, BC, BD |
I |
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version) |
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P7, N6, L6, K7, H6, G7, F6, E7, D6 |
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DQA1–DQA9 |
I/O |
Data Input and Output pins (x18 Version) |
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D1, E2, G2, H1, K2, L1, M2, N1, P2 |
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DQB1–DQB9 |
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L5, G3 |
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BA, BB |
I |
Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version) |
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P6, N7, M6, L7, K6, H7, G6, E6, D7, |
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D2, E1, F2, G1, H2, K1, L2, N2, P1, |
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NC |
— |
No Connect (x18 Version) |
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G5, L3, T4 |
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K4 |
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CK |
I |
Clock Input Signal; active high |
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M4 |
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BW |
I |
Byte Write—Writes all enabled bytes; active low |
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H4 |
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GW |
I |
Global Write Enable—Writes all bytes; active low |
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E4 |
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E1 |
I |
Chip Enable; active low |
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B2 |
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E2 |
I |
Chip Enable; active high |
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F4 |
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G |
I |
Output Enable; active low |
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G4 |
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ADV |
I |
Burst address counter advance enable; active low |
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A4, B4 |
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ADSP, ADSC |
I |
Address Strobe (Processor, Cache Controller); active low |
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T7 |
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ZZ |
I |
Sleep Mode control; active high |
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R5 |
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FT |
I |
Flow Through or Pipeline mode; active low |
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R3 |
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LBO |
I |
Linear Burst Order mode; active low |
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L4 |
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SCD |
I |
Single Cycle Deselect/Dual Cycle Deselect Mode Control |
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R7 |
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PE |
I |
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) |
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J3 |
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DP |
I |
Data Parity Mode Input; 1 = Even, 0 = Odd |
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J5 |
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QE |
O |
Parity Error Out; Open Drain Output |
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D4 |
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ZQ |
I |
FLXDrive Output Impedance Control |
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(Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) |
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B1, C1, R1, T1, B7, C7, U6 |
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NC |
— |
No Connect |
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Rev: 1.15 5/2001 |
4/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary |
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GS88218/36B-11/11.5/100/80/66 |
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GS88218/36 BGA Pin Description |
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Pin Location |
Symbol |
Type |
Description |
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U2 |
TMS |
I |
Scan Test Mode Select |
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U3 |
TDI |
I |
Scan Test Data In |
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U5 |
TDO |
O |
Scan Test Data Out |
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U4 |
TCK |
I |
Scan Test Clock |
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J2, C4, J4, R4, J6 |
VDD |
I |
Core power supply |
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D3, E3, F3, H3, K3, M3, N3, P3, D5, |
VSS |
I |
I/O and Core Ground |
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E5, F5, H5, K5, M5, N5, P5 |
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A1, F1, J1, M1, U1, A7, F7, J7, M7, |
VDDQ |
I |
Output driver power supply |
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U7 |
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BPR2000.002.14 |
Rev: 1.15 5/2001 |
5/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
GS88218/36 (PE = 0) Block Diagram
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Register |
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A0–An |
D |
Q |
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A0 |
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A0 |
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D0 |
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Q0 |
A1 |
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A1 |
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D1 |
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Q1 |
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Counter |
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A |
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Load |
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LBO |
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Memory |
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ADV |
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CK |
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Array |
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ADSC |
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ADSP |
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Q |
D |
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GW |
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Register |
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36 |
36 |
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BW |
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D |
Q |
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BA |
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Register |
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D |
Q |
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BB |
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4 |
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4 |
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Register |
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D |
Q |
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BC |
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Register Q D |
Register D Q |
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D Q |
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Register |
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Register |
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D |
Q |
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BD |
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Register |
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36 |
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D |
Q |
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36 |
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36 |
E1 |
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Register |
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D |
Q |
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E2 |
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4 |
32 |
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36 |
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Register |
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Parity |
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Encode |
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D |
Q |
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4 |
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Parity |
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FT |
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Compare |
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G |
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36 |
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ZZ |
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Power Down |
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SCD |
DQx0–DQx9 |
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QE |
DP |
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Control |
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Note: Only x36 version shown for simplicity.
Rev: 1.15 5/2001 |
6/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88218/36 (PE = 1) X16x32 Mode Block Diagram
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Register |
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A0–An |
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D Q |
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A0 |
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A0 |
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D0 |
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Q0 |
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A1 |
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A1 |
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D1 |
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Q1 |
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Counter |
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Load |
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LBO |
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ADV |
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CK |
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ADSC |
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ADSP |
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Register |
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GW |
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BW |
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D |
Q |
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BA |
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BB |
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D |
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BC |
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Note: Only x36 version shown for simplicity. |
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Rev: 1.15 5/2001 |
7/39 |
Preliminary
GS88218/36B-11/11.5/100/80/66
A
Memory
|
Array |
Q |
D |
36 |
36 |
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4 |
Parity
Encode
32 |
4
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Register Q D |
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Register D Q |
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DQx0–DQx8 |
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QE |
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DP |
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
ByteSafe™ Parity Functions
In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16 mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an error in the cycle following parity check.
In x32/x16 mode the device does not drive the 9th data output, even though the internal ByteSafe parity encoding has been activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in applications where parity encoding or checking are not otherwise available. As in any system that checks read parity, reads of un-written memory locations may well produce parity errors. Initialization of the memory should be implemented to avoid this issue.
In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later. (See timing diagram below.) The Data Parity Mode (DP) pin must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
x32 Mode (PE = 1) Read Parity Error Output Timing Diagram
Flow Through Mode
Pipelined Mode
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Address A |
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Address D |
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Address E |
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D Out A |
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tLZ |
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tKQX |
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QE |
Err A |
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Err C |
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DQ |
D Out A |
D Out B |
D Out C |
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tKQ |
tHZ |
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tLZ |
tKQX |
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QE |
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Err A |
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Address F |
D Out E |
D Out D |
Err C
Rev: 1.15 5/2001 |
8/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
x18/x36 Mode (PE = 0) Write Parity Error Output Timing Diagram
Flow Through Mode
Pipelined Mode
CK |
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DQ |
D In A |
D In B |
D In C |
D In D |
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tKQ |
tHZ |
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tLZ |
tKQX |
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QE |
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Err A |
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Err C |
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DQ |
D In A |
D In B |
D In C |
D In D |
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tKQ |
tHZ |
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tLZ |
tKQX |
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QE |
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Err A |
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D In E |
D In E |
Err C
BPR 1999.05.18
Rev: 1.15 5/2001 |
9/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary |
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GS88218/36B-11/11.5/100/80/66 |
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Mode Pin Functions |
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Mode Name |
Pin Name |
State |
Function |
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L |
Linear Burst |
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Burst Order Control |
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LBO |
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H or NC |
Interleaved Burst |
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L |
Flow Through |
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Output Register Control |
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FT |
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H or NC |
Pipeline |
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Power Down Control |
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ZZ |
L or NC |
Active |
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H |
Standby, IDD = ISB |
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Single / Dual Cycle Deselect Control |
SCD |
L |
Dual Cycle Deselect |
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H or NC |
Single Cycle Deselect |
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ByteSafe Data Parity Control |
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DP |
L |
Check for Odd Parity |
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H or NC |
Check for Even Parity |
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L or NC |
Activate 9th I/Os (x18/36 Mode) |
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Parity Enable |
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PE |
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H |
Deactivate 9th I/Os (x16/32 Mode) |
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FLXDrive Output Impedance Control |
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ZQ |
L |
High Drive (Low Impedance) |
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H or NC |
Low Drive (High Impedance) |
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Note:
There are pull-up devices on the LBO, ZQ, SCD, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
10 |
11 |
00 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
00 |
01 |
10 |
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Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
00 |
11 |
10 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
10 |
01 |
00 |
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Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.15 5/2001 |
10/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
Byte Write Truth Table
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Function |
GW |
BW |
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BA |
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BB |
BC |
BD |
Notes |
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Read |
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H |
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H |
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X |
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X |
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X |
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X |
1 |
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Read |
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H |
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L |
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H |
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H |
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H |
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H |
1 |
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Write byte a |
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H |
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L |
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L |
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H |
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H |
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H |
2, 3 |
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Write byte b |
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H |
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L |
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H |
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L |
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H |
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H |
2, 3 |
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Write byte c |
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H |
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L |
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H |
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H |
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L |
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H |
2, 3, 4 |
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Write byte d |
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H |
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L |
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H |
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H |
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H |
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L |
2, 3, 4 |
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Write all bytes |
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H |
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L |
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L |
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L |
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L |
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L |
2, 3, 4 |
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Write all bytes |
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L |
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X |
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X |
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X |
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X |
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X |
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Notes:
1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4.Bytes “C” and “D” are only available on the x36 version.
Rev: 1.15 5/2001 |
11/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36B-11/11.5/100/80/66
Synchronous Truth Table
|
Address |
State |
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Operation |
Diagram |
E2 |
|
ADSP |
|
ADSC |
ADV |
W3 |
DQ4 |
|||||
Used |
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Key5 |
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|||
Deselect Cycle, Power Down |
None |
X |
X |
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X |
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L |
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X |
X |
High-Z |
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Deselect Cycle, Power Down |
None |
X |
F |
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L |
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X |
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X |
X |
High-Z |
|||
Deselect Cycle, Power Down |
None |
X |
F |
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H |
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L |
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X |
X |
High-Z |
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Read Cycle, Begin Burst |
External |
R |
T |
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L |
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X |
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X |
X |
Q |
|||
Read Cycle, Begin Burst |
External |
R |
T |
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H |
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L |
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X |
F |
Q |
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|||
Write Cycle, Begin Burst |
External |
W |
T |
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H |
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L |
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X |
T |
D |
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Read Cycle, Continue Burst |
Next |
CR |
X |
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H |
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H |
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L |
F |
Q |
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|||
Read Cycle, Continue Burst |
Next |
CR |
X |
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X |
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H |
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L |
F |
Q |
|||
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|||
Write Cycle, Continue Burst |
Next |
CW |
X |
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H |
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H |
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L |
T |
D |
|||
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|||
Write Cycle, Continue Burst |
Next |
CW |
X |
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X |
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H |
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L |
T |
D |
|||
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|||
Read Cycle, Suspend Burst |
Current |
|
X |
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H |
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H |
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H |
F |
Q |
|||
Read Cycle, Suspend Burst |
Current |
|
X |
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X |
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H |
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H |
F |
Q |
|||
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|||
Write Cycle, Suspend Burst |
Current |
|
X |
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H |
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H |
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H |
T |
D |
|||
Write Cycle, Suspend Burst |
Current |
|
X |
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X |
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H |
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H |
T |
D |
|||
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Notes:
1.X = Don’t Care, H = High, L = Low
2.E = T (True) if E2 = 1; E = F (False) if E2 = 0
3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).
5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.15 5/2001 |
12/39 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.