Preliminary
GS840Z18/36AT-180/166/150/100
Commercial Temp |
4Mb Pipelined and Flow Through |
3.3 V V |
100-Pin TQFP |
|
180 MHz–100 MHz |
|
|
DD |
Industrial Temp |
Synchronous NBT SRAMs 2.5 V and 3.3 V VDDQ |
|
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|
•256K x 18 and 128K x 36 configurations
•User configurable Pipeline and Flow Through mode
•NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
•Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
•Pin-compatible with 2M, 8M and 16M devices
•3.3 V +10%/–5% core power supply
•2.5 V or 3.3 V I/O supply
•LBO pin for Linear or Interleave Burst mode
•Byte write operation (9-bit Bytes)
•3 chip enable signals for easy depth expansion
•Clock Control, registered address, data, and control
•ZZ Pin for automatic power-down
•JEDEC-standard 100-lead TQFP package
|
|
–180 |
–166 |
–150 |
–100 |
|
Pipeline |
tCycle |
5.5 ns |
6.0 ns |
6.6 ns |
10 ns |
|
tKQ |
3.2 ns |
3.5 ns |
3.8 ns |
4.5 ns |
||
3-1-1-1 |
||||||
IDD |
335 mA |
310 mA |
280 mA |
190 mA |
||
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Flow |
tKQ |
8 ns |
8.5 ns |
10 ns |
12 ns |
|
Through |
tCycle |
9.1 ns |
10 ns |
12 ns |
15 ns |
|
2-1-1-1 |
IDD |
210 mA |
190 mA |
165 mA |
135 mA |
The GS840Z18/36AT is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
The GS840Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.
The GS840Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock |
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Address |
A |
B |
C |
D |
E |
F |
|
Read/Write |
R |
W |
R |
W |
R |
W |
|
Flow Through |
|
QA |
DB |
QC |
DD |
QE |
|
Data I/O |
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|||||
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Pipelined |
|
|
QA |
DB |
QC |
DD |
QE |
Data I/O |
|
|
Rev: 1.02 11/2002 |
1/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS840Z18/36AT-180/166/150/100
NC
NC
NC
VDDQ
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
VDD
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
|
A6 |
A7 |
E1 |
E2 |
NC |
NC |
BB BA E3 |
V |
V |
CK W |
CKE |
G |
ADV NC NC A8 |
A9 |
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DD |
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SS |
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100 |
99 |
98 |
97 |
96 |
95 |
94 |
93 |
|
92 |
91 |
90 |
89 |
88 |
|
87 |
86 |
85 |
84 |
83 |
82 |
81 |
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||||||||||||||||||||||||||||||||||||||
1 |
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80 |
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|||
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2 |
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79 |
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|||
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3 |
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78 |
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|||
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4 |
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77 |
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|||
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5 |
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76 |
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|||
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|||||
6 |
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75 |
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|||
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7 |
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74 |
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|||
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8 |
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73 |
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|||
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9 |
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256K x 18 |
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72 |
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10 |
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71 |
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Top View |
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11 |
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70 |
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12 |
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69 |
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13 |
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68 |
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14 |
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67 |
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15 |
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66 |
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16 |
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65 |
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17 |
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64 |
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18 |
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63 |
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19 |
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62 |
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20 |
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61 |
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|||
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|||||
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21 |
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60 |
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|||
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|||||
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|||||
22 |
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59 |
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|||
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|||||
23 |
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58 |
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|||
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|||||
24 |
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57 |
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|||
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25 |
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56 |
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26 |
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55 |
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|||
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27 |
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54 |
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|||
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28 |
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53 |
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29 |
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52 |
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30 |
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51 |
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|||
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|||||
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
|
39 |
40 |
41 |
42 |
43 |
|
44 |
45 |
46 |
47 |
48 |
49 |
50 |
|
|
||||||||||||||||||||||||||||||||||||||
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|
LBO A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
NC NC |
|
SS |
|
DD |
NC NC A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
|
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||||||||||||||||||||||||||||||||||||||||
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|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
V |
V |
|
|
A17
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.02 11/2002 |
2/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
DQC9
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
VDD
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
|
A6 |
A7 |
E1 |
E2 |
BD BC BB BA E3 |
V |
V |
CK W |
CKE |
G |
ADV NC NC A8 |
A9 |
|
|
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DD |
|
SS |
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|
|
|
|
|
|
|
100 |
99 |
98 |
97 |
96 |
95 |
94 |
93 |
|
92 |
91 |
90 |
89 |
88 |
|
87 |
86 |
85 |
84 |
83 |
82 |
81 |
|
|
||||||||||||||||||||||||||||||||||||||
1 |
|
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|
80 |
|
|
|||
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|||||
2 |
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79 |
|
|
|||
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|||||
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|||||
3 |
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|
78 |
|
|
|||
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|||||
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|||||
4 |
|
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|
77 |
|
|
|||
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|||||
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|||||
5 |
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76 |
|
|
|||
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|||||
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|||||
6 |
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75 |
|
|
|||
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|||||
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|||||
7 |
|
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74 |
|
|
|||
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|||||
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|||||
8 |
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73 |
|
|
|||
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|||||
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|||||
9 |
|
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|
128K x 36 |
|
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72 |
|
|
||||||||||||||||
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|||||||||||||||||||
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|||||||||||||||||||
10 |
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71 |
|
|
|||||||||||||||||
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|||||||||||||||||||
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Top View |
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|||||||||||||||||
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||||||||||||||||||
11 |
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70 |
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||||||||||||||||
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||||||||||||||||||
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||||||||||||||||||
12 |
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69 |
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13 |
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68 |
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14 |
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67 |
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15 |
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66 |
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16 |
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65 |
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17 |
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64 |
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18 |
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63 |
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19 |
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62 |
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20 |
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61 |
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|||
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|||||
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21 |
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60 |
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|||
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|||||
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22 |
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59 |
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|||
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|||||
23 |
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58 |
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|||
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|||||
24 |
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57 |
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|||
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25 |
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56 |
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26 |
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55 |
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|||
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27 |
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54 |
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|||
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28 |
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53 |
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29 |
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52 |
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30 |
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51 |
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31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
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39 |
40 |
41 |
42 |
43 |
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44 |
45 |
46 |
47 |
48 |
49 |
50 |
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LBO A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
NC NC |
|
SS DD |
NC NC A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
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V V |
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|
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
Rev: 1.02 11/2002 |
3/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Symbol |
Type |
|
|
Description |
|||||||||||
|
|
|
|||||||||||||
A0, A1 |
In |
Burst Address Inputs; preload the burst counter |
|||||||||||||
A2–A17 |
In |
|
|
Address Inputs |
|||||||||||
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||||||||||
|
CK |
In |
|
|
Clock Input Signal |
||||||||||
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||||||||
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A |
In |
Byte Write signal for data inputs DQA1-DQA9; active low |
||||||||
|
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B |
|||||||||||||
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B |
In |
Byte Write signal for data inputs DQB1-DQB9; active low |
||||||||
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B |
|||||||||||||
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C |
In |
Byte Write signal for data inputs DQC1-DQC9; active low |
|||||||||
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B |
|||||||||||||
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D |
In |
Byte Write signal for data inputs DQD1-DQD9; active low |
|||||||||
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B |
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In |
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Write Enable; active low |
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W |
|||||||||||||
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1 |
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|
In |
|
Chip Enable; active low |
|||
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E |
|||||||||||||
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E2 |
In |
Chip Enable; active high; for self decoded depth expansion |
|||||||||||
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3 |
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In |
Chip Enable; active low, for self decoded depth expansion |
||||
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E |
|||||||||||||
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In |
|
Output Enable; active low |
||
|
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G |
||||||||||||
|
ADV |
In |
Advance / |
|
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||||||||||
Load—Burst address counter control pin |
|||||||||||||||
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|
In |
Clock Input Buffer Enable; active low |
||
|
CKE |
||||||||||||||
DQA1–DQA9 |
I/O |
Byte A Data Input and Output pins |
|||||||||||||
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|||||||||||||
DQB1–DQB9 |
I/O |
Byte B Data Input and Output pins |
|||||||||||||
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|||||||||||||
DQC1–DQC9 |
I/O |
Byte C Data Input and Output pins |
|||||||||||||
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|||||||||||||
DQD1–DQD9 |
I/O |
Byte D Data Input and Output pins |
|||||||||||||
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||||||||||||
|
ZZ |
In |
Power down control; active high |
||||||||||||
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|||||||||
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In |
Pipeline/Flow Through Mode Control; active low |
|||
|
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FT |
|||||||||||||
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In |
|
Linear Burst Order; active low |
||
|
LBO |
|
|||||||||||||
|
VDD |
In |
|
|
3.3 V power supply |
||||||||||
|
VSS |
In |
|
|
Ground |
||||||||||
VDDQ |
In |
3.3 V output power supply for noise reduction |
|||||||||||||
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NC |
— |
|
|
No Connect |
||||||||||
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Rev: 1.02 11/2002 |
4/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
DQa–DQn
FT |
|
|
K |
Q |
|
Write Data |
Register 1 |
D |
K |
K
SenseAmps |
|
Register 2 |
|
|
|
WriteData |
|
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|
|
Memory Array |
|
|
|
QD SA1 SA1’ SA0Burst SA0’ |
Counter |
|
AddressWrite Write Address |
1Register |
Match |
WriteDrivers |
LogicControl |
FT |
|
K |
andWriteRead, |
CoherencyData |
|||||||
|
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2 Register |
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K |
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K |
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K |
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K
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W |
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BA |
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BB |
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BC |
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BD |
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|||||
A0–A16 |
|
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E1 E2 |
|
E3 |
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G |
||||||||||||
ADV |
|
LBO |
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CK |
|
CKE |
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||
Rev: 1.02 11/2002 |
5/25 |
|
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|
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
|
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Function |
|
W |
|
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BA |
|
BB |
|
BC |
|
BD |
||||
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||||
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||||
Read |
|
H |
|
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X |
|
X |
|
X |
|
X |
||||
|
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|
||||
Write Byte “a” |
|
L |
|
|
L |
|
H |
|
H |
|
H |
||||
|
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|
||||
Write Byte “b” |
|
L |
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|
H |
|
L |
|
H |
|
H |
||||
|
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|
||||
Write Byte “c” |
|
L |
|
|
H |
|
H |
|
L |
|
H |
||||
|
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|
||||
Write Byte “d” |
|
L |
|
|
H |
|
H |
|
H |
|
L |
||||
|
|
|
|
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|
|
|
|
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|
||||
Write all Bytes |
|
L |
|
|
L |
|
L |
|
L |
|
L |
||||
|
|
|
|
|
|
|
|
|
|
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|
||||
Write Abort/NOP |
|
L |
|
|
H |
|
H |
|
H |
|
H |
||||
|
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Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 1.02 11/2002 |
6/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
|
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|
Operation |
Type |
Address |
|
E1 |
E2 |
|
E3 |
ZZ |
ADV |
|
W |
|
|
Bx |
|
G |
|
CKE |
CK |
DQ |
Notes |
|||||
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|||||
Deselect Cycle, Power Down |
D |
None |
|
H |
X |
|
X |
L |
L |
|
X |
|
|
X |
|
X |
|
L |
L-H |
High-Z |
|
|||||
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|||||
Deselect Cycle, Power Down |
D |
None |
|
X |
X |
|
H |
L |
L |
|
X |
|
|
X |
|
X |
|
L |
L-H |
High-Z |
|
|||||
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|||||
Deselect Cycle, Power Down |
D |
None |
|
X |
L |
|
X |
L |
L |
|
X |
|
|
X |
|
X |
|
L |
L-H |
High-Z |
|
|||||
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|||||
Deselect Cycle, Continue |
D |
None |
|
X |
X |
|
X |
L |
H |
|
X |
|
|
X |
|
X |
|
L |
L-H |
High-Z |
1 |
|||||
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|||||
Read Cycle, Begin Burst |
R |
External |
|
L |
H |
|
L |
L |
L |
|
H |
|
|
X |
|
L |
|
L |
L-H |
Q |
|
|||||
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|||||
Read Cycle, Continue Burst |
B |
Next |
|
X |
X |
|
X |
L |
H |
|
X |
|
|
X |
|
L |
|
L |
L-H |
Q |
1,10 |
|||||
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|||||
NOP/Read, Begin Burst |
R |
External |
|
L |
H |
|
L |
L |
L |
|
H |
|
|
X |
|
H |
|
L |
L-H |
High-Z |
2 |
|||||
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|
|||||
Dummy Read, Continue Burst |
B |
Next |
|
X |
X |
|
X |
L |
H |
|
X |
|
|
X |
|
H |
|
L |
L-H |
High-Z |
1,2,10 |
|||||
|
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|
|||||
Write Cycle, Begin Burst |
W |
External |
|
L |
H |
|
L |
L |
L |
|
L |
|
|
L |
|
X |
|
L |
L-H |
D |
3 |
|||||
|
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|
|||||
Write Cycle, Continue Burst |
B |
Next |
|
X |
X |
|
X |
L |
H |
|
X |
|
|
L |
|
X |
|
L |
L-H |
D |
1,3,10 |
|||||
|
|
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|
|
|
|
|
|||||
NOP/Write Abort, Begin Burst |
W |
None |
|
L |
H |
|
L |
L |
L |
|
L |
|
|
H |
|
X |
|
L |
L-H |
High-Z |
2,3 |
|||||
|
|
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|
|||||
Write Abort, Continue Burst |
B |
Next |
|
X |
X |
|
X |
L |
H |
|
X |
|
|
H |
|
X |
|
L |
L-H |
High-Z |
1,2,3,10 |
|||||
|
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|
|
|
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|
|||||
Clock Edge Ignore, Stall |
|
Current |
|
X |
X |
|
X |
L |
X |
|
X |
|
|
X |
|
X |
|
H |
L-H |
- |
4 |
|||||
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|
|
|
|
|
|
|||||
Sleep Mode |
|
None |
|
X |
X |
|
X |
H |
X |
|
X |
|
|
X |
|
X |
|
X |
X |
High-Z |
|
|||||
|
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|
Notes:
1.Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect cycle is executed first
2.Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A write abort occurs when the W pin is sampled low, but no byte write pins are active, so no write operation is performed.
3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles.
4.If CKE high occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE high occurs during a write cycle, the bus will remain in High Z.
5.X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are low
6.All inputs, except G and ZZ, must meet setup and hold times of rising clock edge.
7.Wait states can be inserted by setting CKE high.
8.This device contains circuitry that ensures all outputs are in High Z during power-up.
9.A 2-bit burst counter is incorporated.
10.The address counter is incriminated for all Burst continue cycles.
Rev: 1.02 11/2002 |
7/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Pipelined and Flow Through Read-Write Control State Diagram
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D |
B |
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Deselect |
W |
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R |
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D |
D |
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New Read |
W |
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New Write |
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R |
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R |
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W |
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B |
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B |
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R |
W |
R |
W |
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Burst Read |
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Burst Write |
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B |
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B |
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D |
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D |
Key |
Input Command Code |
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Notes |
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ƒ Transition |
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Current State (n) |
Next State (n+1) |
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n |
n+1 |
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Clock (CK) |
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Command |
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ƒ |
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ƒ |
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Current State |
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Next State |
1.The Hold command (CKE Low) is not
shown because it prevents any state change.
2.W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
n+2 n+3
ƒ ƒ
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.02 11/2002 |
8/25 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com