GE VMIVME-9150 Product Manual

GE Fanuc Automation

VMIVME-9150

Communications Controller

PRODUCT MANUAL 500-009150-000 REV. G

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The information in this document has been carefully checked and is believed to be entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the preparation of this manual, GE Fanuc Embedded Systems assumes no responsibility resulting from omissions or errors in this manual, or from the use of information contained herein.

GE Fanuc Embedded Systems reserves the right to make any changes, without notice, to this or any of GE Fanuc Embedded Systems’ products to improve reliability, performance, function, or design.

GE Fanuc Embedded Systems does not assume any liability arising out of the application or use of any product or circuit described herein; nor does GE Fanuc Embedded Systems convey any license under its patent rights or the rights of others.

For warranty and repair policies, refer to GE Fanuc Embedded Systems’ Standard Conditions of Sale.

AMXbus, BITMODULE, COSMODULE, DMAbus, IOMax, IOWorks Access, IOWorks Foundation, IOWorks Manager, IOWorks Server, MAGICWARE, MEGAMODULE, PLC ACCELERATOR (ACCELERATION), Quick Link, RTnet, Soft Logic

Link, SRTbus, TESTCAL, “The Next Generation PLC”, The PLC Connection, TURBOMODULE, UCLIO, UIOD, UPLC, Visual Soft Logic Control(ler), VMEbus Access, VMEmanager, VMEmonitor, VMEnet, VMEnet II, VMEprobe and VMIC Shutdown are trademarks and The I/O Experts, The I/O Systems Experts, The Soft Logic Experts, and The Total Solutions Provider are service marks of GE Fanuc Embedded Systems.

IOWorks, Visual IOWorks and the VMIC logo are registered trademarks of GE Fanuc Embedded Systems.

Other registered trademarks are the property of their respective owners.

This document shall not be duplicated, nor its contents used for any purpose, unless granted express written permission from GE Fanuc Embedded Systems.

This page is intentionally left blank.

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Document Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Safety Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 1 - System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Multi-IIOC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

I/O Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Data Buffer Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Byte Order Accommodation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Digital Output Flashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Digital Input Software Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Digital Input Change Of State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Generic Scan Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Chapter 2 - Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Host Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Host Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Status and Information Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 3 - IIOC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reflective Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

VMIVME-9150 Communications Controller

IIOC Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

IIOC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

IIOC Real-Time Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 4 - Control Terminal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Menu Tree Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Diagnostics Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Remote Terminal for IIOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Network Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Chapter 5 - Suggestions for System

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Using Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Asynchronous Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

DI Latching and DI Change of State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Command Sequence for an I/O Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Chapter 6 - Status and Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Control Terminal Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Host Computer Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Appendix A - Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

VMIVME-9150 Default Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Configuring a VMIVME-7700 Board for Use as 9150-700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

VMIVME-9150-700 Control Terminal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Chassis Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Reflective Memory Interface to IIOCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Reflective Memory Host Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

List of Figures

Figure 1-1 System Configuration with a Dual Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 1-2 System Configuration with a Single Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 1-3 Little- and Big-Endian Byte Offset Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 2-1 Reflective Memory Host Interface Configuration (Shared Link and Split Link) . . . . . . . 42

Figure 2-2 Status Block Longword Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 2-3 Error Data Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 2-4 Information Block Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 2-5 Buffer Definition Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 2-6 Configuration Data Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 2-7 Flash Rates for Periods One Through Four . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 2-8 Configuration Data for Generic Scan Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 2-9 DI Change-of-State Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 2-10 Point Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 4-1 Power-Up Diagnostics Screen One . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 4-2 Power-Up Diagnostics Screen Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 4-3 Main Menu Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 4-4 Diagnostics Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 4-5 Memory Tests Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 4-6 Local Reflective Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 4-7 Node Reflective Memory Test and Node Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 4-8 Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 4-9 Node Scan Timing Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 4-10 Buffer Transfer Timing Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 4-11 9150 CPU Utilization Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 4-12 Timer Resolution Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 4-13 I/O Exercising . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 4-14 Generate Automatic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

VMIVME-9150 Communications Controller

Figure 4-15 Change Configuration Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 4-16 Run (Asynchronous Scanning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 4-17 Buffer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 4-18 Display Buffer HEX Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 4-19 Display Buffer Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 4-20 Slave Chassis Power Down/Up Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 4-21 System Information Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 4-22 Reflective Memory Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 4-23 Node Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 4-24 Detailed Node Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 4-25 Detailed Node Status Pages 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 4-26 Buffer Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 4-27 Detailed Buffer Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 4-28 I/O Board Map for a Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 4-29 I/O Board Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 4-30 I/O Board Address Table for I/O Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 4-31 Host Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 4-32 Host Error Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 4-33 Remote Terminal for IIOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 4-34 Remote to IIOC Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 4-35 IIOC Main Menu Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 4-36 Reset a Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 4-37 Reset All Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 4-38 Reset 9150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 4-39 Reset 9150 and ALL Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 4-40 Bring a Node Online . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 4-41 Configuration Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 4-42 Display Configuration Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 4-43 Download Configuration to All Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-44 Download Configuration to One Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-45 Purge Configuration on ALL Nodes (Screen One) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-46 Purge Configuration on ALL Nodes (Screen Two) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-47 Purge Configuration on One Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-48 Purge 9150 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 4-49 Network Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 4-50 FDDI Network Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-51 Display Network IP Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

VMIVME-9150 Communications Controller

Figure 4-52 Change Network Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 4-53 Network Port Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 4-54 Display Network Port Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-55 Change Network Port Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 5-1 DO Data Buffer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 5-2 Mixed DO and AO Buffer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 5-3 Sample C Code for Asynchronous I/O and DI Latching . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 5-4 Sample C Code for Asynchronous I/O and DI Change of State . . . . . . . . . . . . . . . . . . 146

Figure 6-1 Error Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure A-1 MVME162PA-252SE Switch and Jumper Field Locations . . . . . . . . . . . . . . . . . . . . . . 157

Figure A-2 CPU-33B/4 Jumper Field Locations and Default Jumper Settings . . . . . . . . . . . . . . . . 158

Figure A-3 MVME162-220, MVME162-222, and MVME162-223 Jumper Field Locations . . . . . . 160

Figure A-4 VMIVME-7700 Jumper and Switch Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure A-5 Front Panel LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure A-6 VMIVME-7700 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure A-7 Chassis Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

VMIVME-9150 Communications Controller

This page is intentionally left blank.

List of Tables

Table 1-1 Digital Input Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-1 VMIVME-9150 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 2-2 Status Longword Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 2-3 IIOC Node Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 2-4 Associated Scan List Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 2-5 Address Modifier Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 4-1 9150 Menu Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 4-2 Change Configuration Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Table 5-1 Buffer Number Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 6-1 VMIVME-9150 Error Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table A-1 Processor Board Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Table A-2 Supported Host interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Table A-3 Default Switch and Jumper Settings for MVME162PA-252SE & MVME162P2-242 .156

Table A-4 EPROM Locations for MVME162PA-252SE and MVME162P-242 . . . . . . . . . . . . . .156

Table A-5 Default Jumper Settings for MVME162-220, MVME162-222, and MVME162-223 . .159

Table A-6 EPROM Locations for MVME162-220, MVME162-222, and MVME162-223 . . . . . .159

Table A-7 Default Jumper Settings for VMIVME-7589-946 . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Table A-8 Board Connectors and Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table A-9 CMOS Clear (User Configurable) - Jumper (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table A-10 Watchdog Timer (Factory Configurable) - Switch (S6) . . . . . . . . . . . . . . . . . . . . . . .165

Table A-11 Universe II Mapping, SYSFAIL Generation (Factory Configurable) - Switch (S8) . . .165

Table A-12 CompactFlash Write Protect/BIOS Boot Mode (Factory Configurable) - Switch (S9) 165

Table A-13 Battery Enable/Disable (User Configurable) - Switch (S10) . . . . . . . . . . . . . . . . . . . .165

Table A-14 VMEbus SYSRESET Enable/Disable (User Configurable) - Switch (S11) . . . . . . . .165

VMIVME-9150 Communications Controller

Table A-15 Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .167

Table A-16 Board Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Table A-17 Reflective Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Table A-18 Default Jumper Settings for 512KB VMIVME-5550 . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table A-19 Default Jumper Settings for 512KB VMIVME-5576 . . . . . . . . . . . . . . . . . . . . . . . . .174

Table A-20 Default Jumper Settings for 512KB VMIVME-5588 . . . . . . . . . . . . . . . . . . . . . . . . . .175

Table A-21 Default Jumper Settings for 512KB VMIVME-5588DMA . . . . . . . . . . . . . . . . . . . . . .176

Table A-22 Default Jumper Settings for VMIVME-5565 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

Table A-23 Default Jumper Settings for 512KB VMIVME-5576 . . . . . . . . . . . . . . . . . . . . . . . . . .178

Table A-24 Default Jumper Settings for 512KB VMIVME-5588 . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table A-25 Default Jumper Settings for 512KB VMIVME-5588DMA . . . . . . . . . . . . . . . . . . . . . .180

Table A-26 Default Jumper Settings for VMIVME-5565 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Overview

Introduction

The VMIVME-9150 is a Communications Controller board designed by GE Fanuc Embedded Systems to work with Intelligent I/O Controllers (IIOCs). The VMIVME-9150 expands IIOC product capabilities by interfacing with multiple controllers through Reflective Memory boards.

Output data from the host is available simultaneously to the IIOCs using Reflective Memory. Likewise, data from many input boards is transferred to the host in a timely manner. The VMIVME-9150 conserves the resources of the host computer by controlling the communication between the IIOCs and I/O boards.

A basic hardware configuration is made up of:

• One or two host computers

• A host interface board for each host computer

• A VMIVME-9150 communications controller board

• Multiple VMIVME-9064 and/or VMIVME-9081 IIOCs

• A Reflective Memory board for each IIOC and the VMIVME-9150

The VMIVME-9150 communicates with the host computer through a host interface board. The host issues commands and transmits and receives data through the host interface to the VMIVME-9150.

The VMIVME-9150 communicates with multiple VMIVME-9064 or VMIVME-9081 Intelligent I/O Controllers through VMIVME-5550, -5565, -5576, -5588, or -5588DMA Reflective Memory boards. The chassis where the VMIVME-9150 processor board and host interface boards reside contains one Reflective Memory board for IIOC communication. The same network may have up to fifteen IIOC controllers, each paired with one Reflective Memory board.

The VMIVME-9150 acts as the “host computer” to each IIOC. The external host computer interfaces only to the VMIVME-9150, and the VMIVME-9150 controls all functions of the IIOCs.

IIOCs combine the intelligence to ease integration and simplify maintenance with the power to significantly reduce the impact of real-time I/O on your host computer

VMIVME-9150 Communications Controller

resources. The IIOCs provide a high-density, high-throughput, low-cost solution to the data acquisition and control problem by offloading the I/O scanning, scaling computation, and engineering unit conversion tasks from host computer computational resources.

Intended Audience

The VMIVME-9150 Product Manual is written for those familiar with the theory and practice of real-time processing. In addition, a familiarity with computers, including some knowledge of computer programming, is assumed. Knowledge of GE Fanuc Embedded Systems IIOC systems is helpful and may be obtained through the study of the IIOC Family Instruction Manual.

GE Fanuc Technical Support

GE Fanuc Embedded Systems provides complete system support, including technical manuals, system configuration manuals, training classes, field support, depot repair and 72-hour board swap-out service. GE Fanuc Embedded Systems has an established worldwide network of sales representatives to provide customer support before and after the sale.

Document Structure

The VMIVME-9150 Product Manual is divided into six chapters. This manual furnishes general information about the architecture and theory pertaining to communications controller systems. In-depth information about the use of a control terminal for controlling the VMIVME-9150 and IIOCs is also included.

Chapter 1 - System Description provides an overview of the VMIVME-9150 system and of the increased capabilities it provides for the IIOC by interfacing to multiple I/O controllers through Reflective Memory.

Chapter 2 - Host Interface describes the role of the VMIVME-9150 as a slave device for the supported host interfaces. Included are the protocols used with the VMIVME-HSDA, VMIVME-5620, VMIVME-5610, network interfaces and Reflective Memory, as well as the set of commands available from the external host computer.

Chapter 3 - IIOC Interface provides a more detailed description of the interface between the VMIVME-9150 Communications Controller and the Intelligent I/O Controller.

Chapter 4 - Control Terminal Operation details the control key usage, menus, and operations using the control terminal of the VMIVME-9150 Communications Controller.

Overview

Chapter 5 - Suggestions for System Operation offers suggestions for the practical use of a VMIVME-9150 system such as initialization, data buffers, asynchronous scanning, DI latching and change of state, and example command sequences for an I/O frame.

Chapter 6 - Status and Error Reporting discusses how to obtain the status and error information displayed on the control terminal and host program by the VMIVME-9150. Included is information on the two major classes of errors, as well as examples of each of the different error types.

Appendix A - Configuration provides illustrations and tables for help in jumpering a spare or repaired board to the VMIVME-9150 default configuration.

VMIVME-9150 Communications Controller

Technical Support

You can contact GE Fanuc Embedded Systems software customer care in any of the following ways:

TELEPHONE: 1-800-GEFANUC (or 1-800-433-2682), or 1-780-401-7700

E-MAIL: support.embeddedsystems@gefanuc.com.

With your correspondence, please provide the following:

•Product version.

• Type of computer hardware: Processor, available disk space, RAM, and network

• Software version numbers.

• Exact wording of any messages on your screen.

• What you were doing when the error occurred.

• What steps you have taken (if any) to resolve the problem.

In addition, when e-mailing, please include the following:

•Your name.

• Your company’s name.

• Your phone and fax numbers.

Overview

board.

VMIVME-9150 Communications Controller

References

VMIVME-7700, Ultra Low Voltage Intel Celeron Processor Product Manual, Document Number 500-007700-000, GE Fanuc Embedded Systems

IIOC Family Instruction Manual, Document Number 500-009000-000, GE Fanuc Embedded Systems

VMIVME-5565, Ultrahigh-Speed Fiber-Optic Reflective Memory Board with Interrupts Product Manual, Document Number 500-005565-000, GE Fanuc Embedded Systems

VMIPCI-5565 Ultra High-Speed Fiber-Optic Reflective Memory with Interrupts Product Manual, Document Number 500-855565-000, GE Fanuc Embedded Systems

VMIPMC-5565 Ultra High-Speed Fiber-Optic Reflective Memory with Interrupts Product Manual, Document Number 500-755565-000, GE Fanuc Embedded Systems

VMIPCI-5565PIORC Ultra High-Speed Fiber-Optic Reflective Memory with Interrupts Product Manual, Document Number 500-9367855565-000, GE Fanuc Embedded Systems

VMIPMC-5565PIORC Ultra High-Speed Fiber-Optic Reflective Memory with Interrupts Product Manual Document Number 500-9367755565-000, GE Fanuc Embedded Systems

VMIACC-5595, 2Gb/s Reflective Memory Hub Assembly, Document Number 522-805595-000, GE Fanuc Embedded Systems

VMIVME-5588, Reflective Memory Board Product Manual, Document Number 500-005588-000, GE Fanuc Embedded Systems

VMIVME-5588DMA, Reflective Memory Board Product Manual, Document Number 500-105588-000, GE Fanuc Embedded Systems

Physical Description and Specifications

Refer to Product Specifications 800-009150-000 available from:

GE Fanuc Embedded Systems 12090 South Memorial Pkwy. Huntsville, AL 35803-3308, USA (256) 880-0444 (800) 322-3616 FAX: (256) 882-0859

www.gefanucembedded.com

Safety Summary

The following general safety precautions must be observed during all phases of the operation, service, and repair of this product. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of this product.

GE Fanuc Embedded Systems assumes no liability for the customer's failure to comply with these requirements.

Ground the System

To minimize shock hazard, the chassis and system cabinet must be connected to an electrical ground. A three-conductor AC power cable should be used. The power cable must either be plugged into an approved three-contact electrical outlet or used with a three-contact to two-contact adapter with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet.

Do Not Operate in an Explosive Atmosphere

Do not operate the system in the presence of flammable gases or fumes. Operation of any electrical system in such an environment constitutes a definite safety hazard.

Overview

Keep Away from Live Circuits

Operating personnel must not remove product covers. Component replacement and internal adjustments must be made by qualified maintenance personnel. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone

Do not attempt internal service or adjustment unless another person, capable of rendering first aid and resuscitation, is present.

Do Not Substitute Parts or Modify System

Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification to the product. Return the product to GE Fanuc Embedded Systems for service and repair to ensure that safety features are maintained.

Dangerous Procedure Warnings

Warnings, such as the example below, precede only potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed.

WA RN IN G: Dangerous voltages, capable of causing death, are present in this system. Use extreme caution when handling, testing, and adjusting.

VMIVME-9150 Communications Controller

Safety Symbols Used in This Manual

STOP: This symbol informs the operator that a practice or procedure should not be

performed. damage to or destruction of part or all of the system.

WA RN IN G: This sign denotes a hazard. It calls attention to a procedure, practice, or condition, which, if not correctly performed or adhered to, could result in injury or death to personnel.

CAUTION: This sign denotes a hazard. It calls attention to an operating procedure, practice, or condition, which, if not correctly performed or adhered to, could result in damage to or destruction of part or all of the system.

NOTE: Calls attention to a procedure, practice, or condition which is essential to highlight.

Actions could result in injury or death to personnel, or could result in

System Description

Contents

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Multi-IIOC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

I/O Scanning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Data Buffer Offsets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Byte Order Accommodation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Digital Output Flashing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Digital Input Software Latching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Digital Input Change Of State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Generic Scan Lists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

CHAPTER

Introduction

The VMIVME-9150 is a Communications Controller designed by GE Fanuc Embedded Systems to work with Intelligent I/O Controllers. The VMIVME-9150 offers increased capabilities for the IIOC products by interfacing to multiple I/O controllers through Reflective Memory.

The IIOCs are connected by Reflective Memory and operate in parallel to perform I/O and data conversion as directed by the VMIVME-9150. The design provides a highly distributed solution for systems with a large number of I/O signals.

A Host Software Support Package developed for use with the IIOC products is supported by the VMIVME-9150. This package is a set of host resident tools and interface software to configure, document, and program the IIOC and IIOC systems. Using these tools to create application programs minimizes errors and facilitates changes.

1 VMIVME-9150 Communications Controller

A basic VMIVME-9150 system hardware configuration as shown in Figure 1-1 on page 23 and Figure 1-2 on page 23 consists of the following:

• One or more host computers

• A host interface board for each host computer

• A VMIVME-9150 communications controller board

• Multiple IIOCs (up to fifteen)

• A Reflective Memory board for each IIOC and the VMIVME-9150

The VMIVME-9150 communicates with the host computer through a host interface board. The host issues commands and transmits and receives data through the host interface to the VMIVME-9150.

For small I/O systems, the host computer can communicate with the VMIVME-9150 using Ethernet. In this case, using a VMIVME-9150 with onboard Ethernet eliminates the need for a separate host interface board.

The VMIVME-9150 acts as the "host computer" to each IIOC. The external host computer interfaces only to the VMIVME-9150, and the VMIVME-9150 controls all functions of the IIOCs.

Figure 1-1 System Configuration with a Dual Host Interface

R F M

Figure 1-2 System Configuration with a Single Host Interface

R F M

1 VMIVME-9150 Communications Controller

Some of the features of the VMIVME-9150 Communications Controller discussed in the following sections include:

• Multiple host computer interfaces

• Synchronous and asynchronous I/O scanning

• Arbitrary offset assignments for data points

• Little- and big-endian byte order accommodation

• Digital output flashing

• Digital input latching

• Digital input change of state

• Support for generic scan lists

Host Interface

Host Interface 1

A single VMIVME-9150 can communicate with two host computers by supporting two host interface boards, one for each host computer. In FDDI systems, one or more hosts can be networked with the VMIVME-9150 system using only one FDDI interface board. Separate multiple networks are supported by using one FDDI board for each host computer.

Each host has the same functional control of the VMIVME-9150, but the possibility of conflicting demands prohibits concurrent dual host control. determined by interrupts.

The VMIVME-9150 supports the following DMA interface boards:

•VMIVME-HSDA

• VMIVME-5620

• VMIVME-5610

The VMIVME-9150 supports the following FDDI interface boards:

• VMIVME-5211S

• VMIVME-5211D

The host control is

The VMIVME-9150 supports the following Reflective Memory host interface boards:

• VMIVME-5565

• VMIVME-5576

• VMIVME-5588

• VMIVME-5588DMA

Smaller I/O systems can use an Ethernet interface such as the following:

• Onboard 10 Mbit or 100 Mbit Ethernet (depending on the model)

• VMIVME-6224 100 Mbit Ethernet

All transfers are initiated by commands from the host computer. The VMIVME-9150 does not perform any data transfers unless commanded by the host computer.

Refer to Table A-1 on page 154 and Table A-2 on page 155 for the VMIVME-9150 processor models and the supported host interfaces for each model.

1 VMIVME-9150 Communications Controller

Multi-IIOC Interface

The external host downloads configuration information to the VMIVME-9150 separately for each of the VMIVME-9064 or VMIVME-9081 IIOCs. The VMIVME-9150 configures the designated IIOC as each configuration data block is downloaded.

On the external host computer, the configuration data may be contained in one file designating the location of points by node, chassis, slot, and channel. The host software that creates the binary configuration data for downloading divides the points into groups for each node, so that the configuration data can be quickly downloaded to the VMIVME-9150 and to each of the IIOC nodes.

I/O Scanning

I/O Scanning 1

Synchronous and asynchronous I/O scanning can be performed by the VMIVME-9150 system. During synchronous I/O scanning, the I/O equipment is scanned only when commanded from the host computer (with the exception of digital input special processing). With synchronous operation, the host has greater control of the timing of I/O scan operations.

During asynchronous scanning, the host does not issue scan commands to the I/O system, but only transfer data commands. To begin asynchronous I/O scanning, the host sends a value for the rate at which the I/O system is to perform I/O scanning operations. The rate may be one which is faster than the rate at which the host transfers the data. The scanning operations are performed asynchronously to the transfer of data. The VMIVME-9150 uses a hardware timer to initiate scanning at the desired rate. At each time interval, the VMIVME-9150 broadcasts an interrupt to the IIOCs controllers with a command to scan.

With the asynchronous mode of operation, output points transmitted in the same data transfer may not change during the same scan, but the points are updated on the next scan. Also, some input data points may have values more recent than other points in the buffer as points might be scanned after the beginning of the data transfer.

1 VMIVME-9150 Communications Controller

Data Buffer Offsets

Up to sixteen data buffers are used for real-time input and output operations. Data buffers in the VMIVME-9150 system allow the mapping of points from multiple nodes and multiple scan lists by explicitly specifying the offset of each point in the buffer at configuration time.

The I/O system is able to assign arbitrary offsets to individual points within data buffers. Data buffer sizes are defined by the host computer. Input and output points cannot be mixed in the same data buffer. A buffer may contain points from multiple scan lists, but all data for one scan list resides in only one buffer.

The configuration data can define points whose buffer offset is not specified. These points, however, will not be processed, since there is no location for the associated data.

During real-time operation, the host can define an alternate buffer offset to substitute for a given point in a specified output scan list. The point is identified by current buffer offset and scan list. Subsequently, the data used for the output data point is obtained from the alternate offset.

Changing an output point’s buffer offset during real-time affects all output signals configured with that point. In other words, if the point is configured as a single bit, then only one output signal is affected. Whereas, if multiple bits are configured with a configuration item, changing the offset affects multiple output signals. This rule applies to conversion types which convert an entire board’s worth of data and those which convert a group of bits.

Byte Order Accommodation

The VMIVME-9064 is based on a 680x0 processor which uses big-endian byte order for representing data items. The big-endian byte order places the most significant byte at the smaller address, and the least significant data bytes at successive higher addresses. In other words, a 16-bit quantity at location 0 has the most significant bits (15-8) at byte location 0, and the least significant bits (7-0) are at byte location 1. Other popular big-endian processor architectures include SPARC, (selectable). Computers such as the VAX, Alpha, and Intel byte order, which places the least significant byte at the smaller address.

For external host computers that use big-endian byte order, the data is transmitted and received as intended. However, when interfacing to a little-endian external host via a 32-bit interface, the following problems may arise:

• Longword (32-bit) data not aligned on a 32-bit boundary is not transmitted properly.

• Word (16-bit) data not aligned on a 16-bit boundary is not transmitted properly.

• Offsets that reference byte and word locations are not the same for big-endian and little-endian, as shown below.

Byte Order Accommodation 1

88000, and MIPS

80x86 use little-endian

Big-Endian IIOC 31

0123

4567

The first two problems can be avoided entirely by aligning 32-bit and 16-bit data items on their proper boundaries in the data buffers on the external host computer.

The third problem is resolved in the I/O system by converting the host-specified offset into one that is usable by the I/O system, thus giving the proper result. The little-endian host may specify offsets native to its own byte order, and the I/O system accounts for the difference. This third problem is illustrated in Figure 1-3 which shows the byte offsets for each byte in two 32-bit longwords. The word offsets are the even numbers.

0031

Figure 1-3 Little- and Big-Endian Byte Offset Comparison

Little-Endian Host

0 4

0123

4567

1 VMIVME-9150 Communications Controller

Restrictions to Little-Endian External Hosts

The following restrictions apply to little-endian external hosts:

• All longword (32-bit) data items must be located on 4 byte-aligned boundaries.

• All word (16-bit) data items must be located on 2 byte-aligned boundaries.

• Byte and word logical conversions may not use multiple bits. Logical conversions are those which convert a group of N bits to a sequence of N bytes, words, or longwords. Specifically, digital conversion types 0 and 1 may not be used since they reference an entire board. If conversion type 4, 5, 10, or 11 is used, the number of bits must be equal to 1. Bit field conversions which convert a group of N bits to a byte, word, or longword may still be used.

NOTE: For little-endian hosts, the host software automatically selects the little-endian mode of operation prior to downloading configuration data.

If two host interfaces are being used, then the little-endian mode affects the interpretation of offsets for both external host computers. The little-endian mode applies only to real-time data buffers for which explicit offset control is available. It does not change the layout of command packets or other data buffers, such as those used for configuration data, error data, and I/O board lists. The host software routines provided account for byte order differences in these other buffers.

+ 153 hidden pages

GE VMIVME-9150 Product Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

List of Figures

List of Tables

Overview

Document Structure

Related Documents

Technical Support

References

Safety Summary

System Description

Host Interface

Multi-IIOC Interface

I/O Scanning

Data Buffer Offsets

Byte Order Accommodation

Restrictions to Little-Endian External Hosts