GATEWAY m460 Schematics
5
VinaFix.com
4
3
2
1
MAX1845 ( +1.5V & 2.5VSUS )
P34
SC1470 ( VCCP1.05V )
P35
D D
SC1470 ( VGA_CORE )
P36
MAX1999 ( 3VPCU & 5VPCU)
P37
MAX1907 ( CPU_CORE )
P38
DDR II
BATTERY CHARGER
BATTERY SELEC T
P39, 40
SODIMM0
SMDDR_VTERM
1.8VSUS
DDR II
DISCHARGE
C C
P41
SATA 0
HDD (PATA OR SATA)
+5V
HDD(PATA &
BAYVCC
SATA)/CD-ROM/USB FDD
SATA 1
B B
TO Port
Replicator
A A
MIC IN
JACK
Line-in
P24
AMCODEC
CONEXANT
20468-31
+5V
+3V
HeadPhone
P23
AMP
MAX9755
P24
INT. SPEAKER
P24
SODIMM1
P22
BUS
SWITCH
AC'97
MODEM DAA
CONEXANT
20493-31
+5V
+3V
3VSUS
RJ11
P30
P24
P10
P22
P22
USB Port 0 ~ 3
5VSUS
P23
WIRE
MA1 SYSTEM BLOCK D I A GRAM
Intel Dothan/Yonah Processor
VCC_CORE
GMCH_VTT
VCCA
Dual Channel DDR
Master
Slave
PATA
SATA
USB 2.0
P21
USB 2.0
Finger
Printer
5VSUS
P26
X'TAL
32.768K
478 uFCPGA
Alviso-GM
82875GM/GME
GMCH_VTT
1.8VSUS
+1.5V
1257 PCBGA
+2.5V
+3V
X'TAL
32.768K
ICH6-M
+3V
3VSUS
+2.5V
+1.5V
1.5VSUS
VCCRTC
GMCH_VTT
EC/KBC
PC97551
3VPCU
+3V
VCCRTC
FSB
533/400MHz
GMCH
DMI interface
609 BGA
LPC
ISA BIOS
TOUCHPAD
Keyboard
P5,6,7,8,9
P18,19,20
P25
PCI-EXPRESS
SIO
PC87383
Parallel Port
Serial Port
3VPCU
P25
+5V
P26
P26
P3,4
P27
TO Port
Replicator
TRACK
POINT
+5V
CPU Thermal
Sensor
+5V
P3
VIDEO RAM
+2.5V
P14,15
ATI M22-P
708 PCBGA
VGA_CORE
VGA1.2V
+1.8V
VDD_MEM
+2.5V
+3V
FOR Alviso-G (LCD/CRT/S-VIDEO)
TYPE III
MINI-PCI
Socket
3VSUS
5VSUS
P26
P11,12,13
PCI Bus interface
X'TAL
INTB/C
REQ1
GNT1
AD20
24.576M
P28
IEEE 1394
PORT B
TO Port
Replicator
X'TAL
14.318M
+3V
VIN
LCD/INV
+5V
+3V
CONN
+5V
+2.5V
S-VIDEO
TI PCI7411
288 PBGA
( PCMCIA+1394
+Cardreader )
+3V
3VSUS+3V
5VSUS
+1.5V
IEEE 1394
PORT A
1394
Conn.
P33
CK-GEN
CK410M
ICS954206
CRT
P16
P17
P17
P2
Port
Replicator
USB 2.0
CRT
S-VIDEO
Parallel Port
Serial Port
RJ11/RJ45
Headphone/Line -In
IEEE 1394
POWER JACK
BROADCOM
BCM5705E/BCM5751
X'TAL
25M
INTA/B/C
REQ0 AD16
GNT0
AD25
P31, 32
LANVCC
LANVCC18
LANVCC10
INTD
REQ2
GNT2
4 in 1 Cardreader
Socket
P32
RJ45
CARDBUS
Slot
P31
PROJECT : MA1
P33
P29, 30
P30
Quanta Computer Inc.
5
4
3
Size Document Number Rev
2
Date: Sheet
Block Diagram
1
of
141Thursday, November 25, 2004
1ACustom
5
VinaFix.com
+3V
D D
+3V
C C
L30
ACB2012L-120
120 ohms@100Mhz
L19
ACB2012L-120
120 ohms@100Mhz
CLKVDD
C619
C622
0.047U
0.047U
R131 2.2
R345 2.2
R150 1 RP19 33X2
CLK_VDDA
CLKVDD1
C611
0.047U
CLK_VDD48
CLK_VDDREF
C620
0.047U
C327
0.047U
C608
0.047U
C617
0.047U
C621
0.047U
C309
4.7U/10V
C368
4.7U/10V
C618
4.7U/10V
C348
0.047U
C340
0.047U
C322
0.01U
FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33
Default
4
Place these termination to close CK410M.
CLK48_7411(31)
CLK48_USB(19)
CG_BSEL2
Iref=5mA,
Ioh=4*Iref
DOT96(5)
DOT96#(5)
C369
27P
C370
27P
CLK_EN#(38) HCLK_MCH (5)
STP_PCI#(19)
STP_CPU#(19,38)
SMbus address D2
R146 15
R143 15
R352 4.7K
R138 475/F
DOT96
DOT96#
21
RP21
1
3
Y1
14.318MHZ
33X2
CG_XIN
CG_XOUT
CLK_EN#
STP_PCI#
STP_CPU#
CGCLK_SMB
CGDAT_SMB
CG_BSEL0
CG_BSEL1
FSC_BSEL2
CLK_VDDREF
CLKVDD
CLKVDD1
CLKVDD
CLK_VDD48
IREF
R_DOT96
2
R_DOT96#
4
50
49
10
55
54
46
47
12
16
53
48
42
21
28
34
11
39
14
15
U12
XTAL_IN
XTAL_OUT
VTT_PWRGD#/PD
PCI_STOP#
CPU_STOP#
SCLK
SDATA
FSA/USB_48
FSB/TEST_MODE
FSC/TEST_SEL
VDD_REF
VDD_CPU
1
VDD_PCI_1
7
VDD_PCI_2
VDD_SRC0
VDD_SRC1
VDD_SRC2
VDD_48
IREF
DOT96
DOT96#
CK-410M
ICS954206
3
CLK_VDDA
CK-410M
GND_48
51
13
GND_REF
GND_PCI_1
2
37
VDDA
GND_PCI_2
62945
38
VSSA
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
PCIF0/ITP_EN
GND_SRC
GND_CPU
250mA ( MAX. )
REF
CPU0
CPU0#
CPU1
CPU1#
SRC6
SRC6#
SRC5
SRC5#
SRC4
SRC4#
SRC3
SRC3#
SRC2
SRC2#
SRC1
SRC1#
SRC0
SRC0#
PCI5
PCI4
PCI3
PCI2
PCIF1
52
44
43
41
40
36
35
33
32
31
30
26
27
24
25
22
23
19
20
17
18
5
4
3
56
9
8
Change the footprint
R157 12.1/F
R159 12.1/F
14M_REF
RHCLK_CPU
RHCLK_CPU#
RHCLK_MCH
RHCLK_MCH#
RSRC_LAN
RSRC_LAN#
RSRC_MCH
RSRC_MCH#
RSRC_SATA
RSRC_SATA#
RSRC_ICH
RSRC_ICH#
RSRC_PEG
RSRC_PEG#
RDREFSSCLK
RDREFSSCLK#
R_PCLK_591
R_PCLK_7411
R_PCLK_ICH
R_PCLK_MINI
R_PCLK_LAN
R_PCLK_SIO
R_PCLK_SIO
R_PCLK_LAN
RP22 33X2
1
3
RP18 33X2
1
3
RP77 33X2
1
3
RP8 33X2
3
1
RP9 33X2
3
1
RP10 33X2
3
1
RP11 33X2
3
1
3
1
R155 33
R158 33
R160 33
R161 33
R149 33
R152 33
R154 10K
R151 10K
2
14M_SIO (27)
14M_ICH (19)
2
4
2
4
2
4
4
2
4
2
4
2
4
2
4
2
HCLK_CPU (3)
HCLK_CPU# (3)
HCLK_MCH# (5)
+LANCLK (29)
-LANCLK (29)
SRC_MCH (6)
SRC_MCH# (6)
SRC_SATA (18)
SRC_SATA# (18)
SRC_ICH (19)
SRC_ICH# (19)
SRC_PEG (11)
SRC_PEG# (11)
DREFSSCLK (5)
DREFSSCLK# (5)
PCLK_591 (25)
PCLK_7411 (31)
PCLK_ICH (18)
PCLK_MINI (28)
PCLK_LAN (29)
PCLK_SIO (27)
Place these termination to close CK410M.
+3V
+3V
HCLK_CPU
HCLK_CPU#
HCLK_MCH
HCLK_MCH#
+LANCLK
-LANCLK
SRC_MCH#
SRC_MCH
SRC_SATA#
SRC_SATA
SRC_ICH#
SRC_ICH
SRC_PEG#
SRC_PEG
DREFSSCLK#
DREFSSCLK
DOT96#
DOT96
1
+3V(3,8,10,11,12,13,16,18,19,20,22,24,25,26,27,28,29,35,36,37,38,41)
VCCP(3,4,5,6,8,9,18,20,35,41)
RP23 49.9/FX2
RP20 49.9/FX2
RP78 49.9/FX2
RP58 49.9/FX2
RP57 49.9/FX2
RP56 49.9/FX2
RP55 49.9/FX2
RP54 49.9/FX2
RP53 49.9/FX2
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 RESERVED
B B
+3V
SELPSB1_CLK(3)
SELPSB0_CLK(3)
R122 0
R135
10K
R349
*1K
VCCP
R351
*1K
CG_BSEL0
CG_BSEL1
CG_BSEL2
R129 1KR128 0
R121 1K
MCH_BSEL1 (5)
MCH_BSEL2 (5)
PDAT_SMB(10,19,29,33)
PCLK_SMB(10,19,29,33)
+3V
Q21
2N7002E
3
Q22
2N7002E
3
2
+3V
2
R184
10K
1
1
These are for backdrive issue
R191
10K
CGDAT_SMB
CGCLK_SMB
( 48 MHz )
CLK48_USB
CLK48_7411
( 33 MHz )
PCLK_SIO
PCLK_LAN
PCLK_MINI
PCLK_ICH
PCLK_7411
PCLK_591
( 14 MHz )
14M_SIO
14M_ICH
C338 *10P
C346 *10P
C615 *10P
C616 *10P
C361 *10P
C607 *10P
C609 *10P
C613 *10P
C354 *10P
C355 *10P
R348
R136
*10K
A A
5
R350
*0
*0
Size Document Number Rev
Custom
4
3
2
Date: Sheet
PROJECT : MA1
Quanta Computer Inc.
CLOCK GENERATOR
1
of
241Thursday, November 25, 2004
1A
A
VinaFix.com
B
C
D
E
HD#[0..63]
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
T96
T90
T1
T99
T100
T97
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
PM_PSI#
SELPSB0_CLK
SELPSB1_CLK
H_GTLREF
HDSTBN0#
HDSTBP0#
HD#[0..63]
HDSTBN1#
HDSTBP1#
Layout note: 0.5" ma x length.
R3
2K/F
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
K24
L24
J26
C16
C14
AF7
AC1
E26
AD26
E1
B2
C3
U46B
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
RSVD
RSVD
RSVD
RSVD
RSVD
GTLREF
Dothan_478P
DATA GRP
2
DATA GRP
0
DATA GRP
3
DATA GRP
1
MISC
RSVD/DPRSTP#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
SLP#
TEST1
TEST2
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
P25
P26
AB2
AB1
G1
B7
C19
E4
A6
C5
F23
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
COMP0
COMP1
COMP2
COMP3
DPRSLP#
DPSLP#
DPWR#
CPUPWRGD
CPUSLP#
H_TEST1
H_TEST2
R511
*1K
VCCP
SELPSB0_CLK(2)
SELPSB1_CLK(2)
HD#[0..63](5)
HDSTBN0#(5)
HDSTBP0#(5)
DINV#0(5)
HDSTBN1#(5)
HDSTBP1#(5)
DINV#1(5)
R2 1K/F
HA#[3..31](5)
4 4
HADSTB0#(5)
HREQ#0(5)
HREQ#1(5)
HREQ#2(5)
HREQ#3(5)
HREQ#4(5)
3 3
HADSTB1#(5)
2 2
HA#[3..31]
HA#[3..31]
A20M#(18)
FERR#(18)
IGNNE#(18)
STPCLK#(18)
INTR(18)
NMI(18)
SMI#(18)
A20M#
FERR#
IGNNE#
STPCLK#
INTR
NMI
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HADSTB0#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HA#17
HA#18
HA#23
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB1#
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
Y3
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
U46A
A3#
A4#
0
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
1
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
Dothan_478P
ADDR GROUP
DEFER#
DRDY#
DBSY#
LOCK#
RESET#
CONTROLXTP/ITP
TRDY#
ADDR GROUP
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TRST#
SIGNALS
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
THERMH CLK
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
ADS#
BNR#
BPRI#
BR0#
IERR#
INIT#
RS0#
RS1#
RS2#
HIT#
HITM#
TCK
TDO
TMS
DBR#
ADS#
N2
BNR#
L1
BPRI#
J3
DEFER#
L4
DRDY#
H2
DBSY#
M2
HBREQ0#
N4
IERR#
A4
CPUINIT#
B5
HLOCK#
J2
CPURST#
B11
RS#0
H1
RS#1
K1
RS#2
L2
HTRDY#
M3
HIT#
K3
HITM#
K4
BPM#0HA#19
C8
BPM#1HA#20
B8
BPM#2HA#21
A9
BPM#3HA#22
C9
PRDY#
A10
PREQ#HA#24
B10
TCK
A13
TDI
C12
TDI
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
TDO
TMS
TRST#
DBR#
CPU_PROCHOT#
THERMDA
THERMDC
THRMTRIP#
HCLK_CPU#
HCLK_CPU
TP1
ADS# (5)
BNR# (5)
BPRI# (5)
DEFER# (5)
DRDY# (5)
DBSY# (5)
HBREQ0# (5)
CPUINIT# (18)
HLOCK# (5)
CPURST# (5)
RS#0 (5)
RS#1 (5)
RS#2 (5)
HTRDY# (5)
HIT# (5)
HITM# (5)
T94
T87
T89
T86
T88
DBR# (19)
THRMTRIP# (5,18)
T93
T92
HCLK_CPU# (2)
HCLK_CPU (2)
VCCP
VCCP
R500
56
R501
56
HD#[0..63]
HDSTBN2#
HDSTBP2#
HD#[0..63]
HDSTBN3#
HDSTBP3#
R518 27.4
R517 54.9
R4 27.4
R5 54.9
DPRSLP# (18)
DPSLP# (18)
DPWR# (5)
CPUSLP# (5,18)
R8
*1K
HDSTBN2# (5)
HDSTBP2# (5)
DINV#2 (5)
HDSTBN3# (5)
HDSTBP3# (5)
DINV#3 (5)
VCCP
R7
200
CPUPWRGD (18)
CPUSLP#
1). Connected between Dothan and
ICH6 for Dothan A Stepping.
2). .Connected between Dothan and
Alviso for Dothan B Stepping.
G1: NC for Dothan and
DPRSTP# for Yona h
+3V
VCCP +3V
TDI 6648VCC
TMS
TDO
CPURST#
TCK
TRST#
PREQ#
THRMTRIP# SYS_SHDN#
1 1
R483 150
R486 39.2
R484 *54.9
R485 54.9
R482 27.4
R481 680
VCCP
R487 56
R499 *56
A
THRMTRIP#
R503 *470
B
R14
*4.7K
Q1
2
*MMBT3904
1 3
SYS_SHDN#
3
R11
2
Q2
*2N7002E
1
+3V(2,8,10,11,12,13,16,18,19,20,22,24,25,26,27,28,29,35,36,37,38,41)
VCCP(2,4,5,6,8,9,18,20,35,41)
6648_ALERT#(25)
SYS_SHDN#(37)
THCLK_SMB(11,25)
THDAT_SMB(11,25)
C
1
1
2
2
THCLK_SMB
THDAT_SMB
6648_ALERT#
Q46
2N7002E
ABCLK
3
ABDATA
3
Q45
2N7002E
ABCLK (25,40)
+3V
ABDATA (25,40)
D
10K
R13
10K
Size Document Number Rev
Custom
Date: Sheet
R16
10K
R12 200
R15
*10K
U45
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
MAX6648MUA
VCC
DXP
DXN
GND
1
2
3
5
ADDRESS: 98H
PROJECT : MA1
Quanta Computer Inc.
Dothan CPU (Host Bus)
C69
0.1U
THERMDA
C777
2200P
THERMDC
1A
of
341Thursday, November 25, 2004
E
A
VinaFix.com
CPU_CORE CPU_CORE
U46C
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
4 4
3 3
2 2
CPU_CORE
C21
0.1U
1 1
CPU_CORE
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
E17
E19
E21
F18
F20
F22
G21
C64
0.1U
D6
D8
E5
E7
E9
F6
F8
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
Dothan_478P
C56
0.1U
VCCA1/RSVD
VCCA2/RSVD
VCCA3/RSVD
VCCSENSE
VSSSENSE
C68
0.1U
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
C14
0.1U
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
TP_VCCSENSE
AE7
TP_VSSSENSE
AF6
CPU_CORE
CPU_CORE
TP_VCCA1
TP_VCCA2
TP_VCCA3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
R520
*54.9
C15
0.1U
CPU_VCCA
C16
0.1U
C783
0.01U
T91
T95
T98
VCCP
CPU_VID0 (38)
CPU_VID1 (38)
CPU_VID2 (38)
CPU_VID3 (38)
CPU_VID4 (38)
CPU_VID5 (38)
R519
*54.9
C17
0.1U
B
C18
0.1U
C784
10U
C19
0.1U
CPU_VCCA
+
C43
C28
0.1U
150U
270U/2.0V(CC7343) 12 mΩ * 4
04/13 Intel recommend
CPU_CORE
C42
C38
10U
10U
CPU_CORE
C29
C30
10U
10U
CPU_CORE
C46
C47
10U
10U
CPU_CORE
C6
C786
10U
10U
C782
0.1U
C37
10U
C52
10U
C48
10U
C27
10U
R513 0
R512 *0
C59
C44
0.1U
0.1U
C36
10U
C39
10U
C50
10U
C787
10U
C
C31
10U
C789
10U
C51
10U
C33
10U
C41
0.1U
+1.5V
+1.8V
VCCPVCCP
C35
0.1U
C57
0.1U
VCCP
C61
0.1U
CPU_CORE
C12
C13
10U
10U
CPU_CORE
C10
C4
10U
10U
CPU_CORE
C24
C9
10U
10U
10U/6.3V/X5R(CC0805)
5 mOhm*35
---> 10U/4V/X5R(CC0603)
CPU_CORE(38,41)
C32
0.1U
C58
0.1U
C3
10U
C5
10U
C785
10U
VCCP(2,3,5,6,8,9,18,20,35,41)
+1.5V(8,12,19,20,32,34,41)
+1.8V(12,13,34,36,41)
C60
0.1U
C40
0.1U
C11
10U
C788
10U
C23
10U
Murata
C62
0.1U
C34
0.1U
C8
10U
C45
10U
C7
10U
C63
0.1U
D
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B12
B16
B19
B22
B25
C10
C13
C15
C18
C21
C24
D11
U46D
A2
A5
A8
B3
B6
B9
C1
C4
C7
D2
D5
D7
D9
Dothan_478P
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
E
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
C20
C22
0.1U
0.1U
A
C25
0.1U
C26
0.1U
C49
0.1U
C53
0.1U
C55
0.1U
C65
0.1U
C66
0.1U
B
C67
0.1U
C
Size Document Number Rev
Custom
D
Date: Sheet
PROJECT : MA1
Quanta Computer Inc.
Dothan CPU (Power)
E
of
441Thursday, November 25, 2004
1A
5
VinaFix.com
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
U37A
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
ALVISO
HOST
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HVREF
HBNR#
HBPRI#
BREQ0#
HCPURST#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HCPUSLP#
HTRDY#
HD#[0..63](3)
D D
C C
B B
HD#[0..63]
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
ADS#
HADSTB0#
HADSTB1#
HVREF
BNR#
BPRI#
HBREQ0#
CPURST#
HCLK_MCH#
HCLK_MCH
DBSY#
DEFER#
DINV#0
DINV#1
DINV#2
DINV#3
DPWR#
DRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HIT#
HITM#
HLOCK#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
HCPUSLP#
HTRDY#
HA#[3..31]
HA#[3..31] (3)
ADS# (3)
HADSTB0# (3)
HADSTB1# (3)
BNR# (3)
BPRI# (3)
HBREQ0# (3)
CPURST# (3)
HCLK_MCH# (2)
HCLK_MCH (2)
DBSY# (3)
DEFER# (3)
DINV#0 (3)
DINV#1 (3)
DINV#2 (3)
DINV#3 (3)
DPWR# (3)
DRDY# (3)
HDSTBN0# (3)
HDSTBN1# (3)
HDSTBN2# (3)
HDSTBN3# (3)
HDSTBP0# (3)
HDSTBP1# (3)
HDSTBP2# (3)
HDSTBP3# (3)
HIT# (3)
HITM# (3)
HLOCK# (3)
HREQ#0 (3)
HREQ#1 (3)
HREQ#2 (3)
HREQ#3 (3)
HREQ#4 (3)
RS#0 (3)
RS#1 (3)
RS#2 (3)
HTRDY# (3)
VCCP
R456
100/F
C745
R455
0.1U
200/F
T4
T79
R454 0
R2027 should be populated to
support Dothan B stepping
3
CPUSLP# (3,18)
T18
T14
T20
T15
T68
T69
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
CLK_SDRAM0
CLK_SDRAM1
CLK_SDRAM2
CLK_SDRAM3
CLK_SDRAM4
CLK_SDRAM5
CLK_SDRAM0#
CLK_SDRAM1#
CLK_SDRAM2#
CLK_SDRAM3#
CLK_SDRAM4#
CLK_SDRAM5#
CKE0
CKE1
CKE2
CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
DMI_TXN0(19)
DMI_TXN1(19)
DMI_TXN2(19)
DMI_TXN3(19)
DMI_TXP0(19)
DMI_TXP1(19)
DMI_TXP2(19)
DMI_TXP3(19)
DMI_RXN0(19)
DMI_RXN1(19)
DMI_RXN2(19)
DMI_RXN3(19)
DMI_RXP0(19)
DMI_RXP1(19)
DMI_RXP2(19)
DMI_RXP3(19)
CLK_SDRAM0(10)
CLK_SDRAM1(10)
CLK_SDRAM3(10)
CLK_SDRAM4(10)
CLK_SDRAM0#(10)
CLK_SDRAM1#(10)
CLK_SDRAM3#(10)
CLK_SDRAM4#(10)
CKE0(10)
CKE1(10)
CKE2(10)
CKE3(10)
SM_CS0#(10)
SM_CS1#(10)
SM_CS2#(10)
SM_CS3#(10)
M_ODT0(10)
M_ODT1(10)
M_ODT2(10)
M_ODT3(10)
SMDDR_VREF
It's point to point, 55ohm trace,
keep as short as possible.
AA31
AB35
AC31
AD35
AA35
AB31
AC35
AA33
AB37
AC33
AD37
AA37
AB33
AC37
AM33
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
Y31
Y33
AL1
2
U37C
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO
1
CFG0
MCH_BSEL1
MCH_BSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
R453 0
R382 100
DOT96#
DOT96
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
C744
0.1U
R468
10K
VCCP
R450
1K
+2.5V
R467
10K
DOT96# (2)
DOT96 (2)
DREFSSCLK# (2)
DREFSSCLK (2)
T71
T75
T70
T73
T72
T74
T81
T83
T76
T77
T84
、、、、
T85
MCH_BSEL1 (2)
MCH_BSEL2 (2)
CFG3 (6)
T10
CFG5 (6)
CFG6 (6)
CFG7 (6)
T7
CFG9 (6)
T8
CFG11 (6)
CFG12 (6)
CFG13 (6)
T78
T5
CFG16 (6)
T6
CFG18 (6)
CFG19 (6)
T3
PM_BMBUSY# (19)
THRMTRIP# (3,18)
IMVP_PWG (19,38)
PLTRST# (11,18,19,27,29)
100MHz ( LVDS)
SMDDR_VREF(10,34)
1.8VSUS(8,9,10,34)
VCCP(2,3,4,6,8,9,18,20,35,41)
+2.5V(6,8,12,16,17,20,35,41)
G16
CFG0
H13
CFG1
G14
CFG2
F16
CFG3
F15
CFG4
G15
CFG5
E16
CFG6
D17
CFG7
J16
CFG8
D15
CFG9
E15
CFG10
D14
CFG11
E14
CFG12
H12
CFG13
C14
CFG14
H15
CFG15
DMIDDR MUXING
CFG/RSVDPMLCKNC
THRMTRIP#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
DREF_CLKN
Display Clock Frequency at 96MHz ( CRT,SDVO and TVOUT)
DREF_SSCLKN
Display Clock Frequency (with SSC) at 96
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
PWROK
RSTIN#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
、、、、
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
DREF_CLKP
、、、、
DREF_SSCLKP
VCCP VCCP VCCP
4
HXSCOMP
HXRCOMP
HYSCOMP
HYRCOMP
R381
R380
40.2/F
40.2/F
Route as short
as possible.
3
M_OCDCOMP0
M_OCDCOMP1
R420 54.9
A A
R408
221/F
HXSWING
R409
C727
100/F
0.1U
5
R399
221/F
R397
100/F
HYSWING
C711
0.1U
R418 24.9/F
VCCP
R401 54.9
R395 24.9/F
1.8VSUS
R383
80.6/F
R384
80.6/F
M_RCOMPN
M_RCOMPP
Size Document Number Rev
Custom
2
Date: Sheet
PROJECT : MA1
Quanta Computer Inc.
Alviso Host(1/5)
1
of
541Thursday, November 25, 2004
1A
5
VinaFix.com
T9
T12
SRC_MCH#(2)
SRC_MCH(2)
R504 *0
DDCCLK(11,17)
TV_COMP
R505 *0
TV_Y/G
R506 *0
TV_C/R
R492 0
R491 0
R490 0
DDCCLK
DDCDATA
CRT_B_COM
CRT_G_COM
CRT_R_COM
VSYNC_COM
HSYNC_COM
EXT VGA NC
+2.5V
TLCO-_1
2
TLCO+_1
4
TUCO-_1
2
TUCO+_1
4
TLO0-_1
2
TLO0+_1
4
TLO1-_1
2
TLO1+_1
4
TLO2-_1
2
TLO2+_1
4
TUO0-_1
2
TUO0+_1
4
TUO1-_1
2
TUO1+_1
4
TUO2-_1
2
TUO2+_1
4
R502 *0
R498 *0
R493 *0
R494 *0
R495 *0
R496 *39
R497 *39
R466 *255/F
R439 *0
R457 *2.2K
R463 *2.2K
R440 *0
R464 *0
R469 *0
R433 *1.5K/F
EXT VGA NC
TV_COMP(11,17,33)
TV_Y/G(11,17,33)
TV_C/R(11,17,33)
ATI
R504
D D
R505
R506
R492
R491
R490
R452
R466
I - 255/F(CS12553F906)
A-NC
C C
B B
INTEL
X
0
X
0
X
0
0
150/F
0
150/F
0
150/F
0
4.99K/F
TXLCLKOUT-(11,16)
TXLCLKOUT+(11,16)
TXUCLKOUT-(11,16)
TXUCLKOUT+(11,16)
TXLOUT0-(11,16)
TXLOUT0+(11,16)
TXLOUT1-(11,16)
TXLOUT1+(11,16)
TXLOUT2-(11,16)
TXLOUT2+(11,16)
TXUOUT0-(11,16)
TXUOUT0+(11,16)
TXUOUT1-(11,16)
TXUOUT1+(11,16)
TXUOUT2-(11,16)
TXUOUT2+(11,16)
150/F(CS11502FB04)
4.99K/F(CS24992FB00)
DDCDATA(11,17)
CRT_B_COM(11,17)
CRT_G_COM(11,17)
CRT_R_COM(11,17)
VSYNC_COM(11,17)
HSYNC_COM(11,17)
BLON(11,16)
DDC_CLK(11,16)
DDC_DATA(11,16)
DISP_ON(11,16)
RP65 *0X2
1
3
RP61 *0X2
1
3
RP68 *0X2
1
3
RP67 *0X2
1
3
RP66 *0X2
1
3
RP64 *0X2
1
3
RP63 *0X2
1
3
RP62 *0X2
1
3
SRC_MCH#
SRC_MCH
TV_Y/G_A
TV_C/R_A
R452 0
DDCCLK_R
DDCDATA_R
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_COM#
VSYNC
HSYNC
REFSET
R458 *100K
R38 *100K
T2
T82
T80
T13
T11
TLCO-_1
TLCO+_1
TUCO-_1
TUCO+_1
TLO0-_1
TLO1-_1
TLO2-_1
TLO0+_1
TLO1+_1
TLO2+_1
TUO0-_1
TUO1-_1
TUO2-_1
TUO0+_1
TUO1+_1
TUO2+_1
D_CLK_1
D_DATA_1
H24
H25
AB29
AC29
A15
C16
A17
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
4
J18
J20
U37F
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
ALVISO
MISC
TV VGA LVDS
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
PCI-EXPRESS GRAPHICS
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
3
EXP_COMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3TV_COMP_A
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
R430 24.9/F
PEG_RXN[0..15]
PEG_RXP[0..15]
VCC3G_PCIE
PEG_RXN[0..15] (11)
PEG_RXP[0..15] (11)
+1.5V
2
DC Blocked Cap.
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
C719 0.1U
C723 0.1U
C713 0.1U
C720 0.1U
C706 0.1U
C717 0.1U
C700 0.1U
C709 0.1U
C694 0.1U
C705 0.1U
C690 0.1U
C698 0.1U
C684 0.1U
C693 0.1U
C676 0.1U
C669 0.1U
INT VGA NC
C721 0.1U
PEG_TXP0
C724 0.1U
PEG_TXP1
C716 0.1U
PEG_TXP2
C722 0.1U
PEG_TXP3
PEG_TXP4
C708 0.1U
C718 0.1U
PEG_TXP5
C703 0.1U
PEG_TXP6
C712 0.1U
PEG_TXP7
C697 0.1U
PEG_TXP8
C707 0.1U
PEG_TXP9
C692 0.1U
PEG_TXP10
C701 0.1U
PEG_TXP11
C687 0.1U
PEG_TXP12
C696 0.1U
PEG_TXP13
C681 0.1U
PEG_TXP14
C672 0.1U
PEG_TXP15
PEG_TXN_C0
PEG_TXN_C1
PEG_TXN_C2
PEG_TXN_C3
PEG_TXN_C4
PEG_TXN_C5
PEG_TXN_C6
PEG_TXN_C7
PEG_TXN_C8
PEG_TXN_C9
PEG_TXN_C10
PEG_TXN_C11
PEG_TXN_C12
PEG_TXN_C13
PEG_TXN_C14
PEG_TXN_C15
PEG_TXP_C0
PEG_TXP_C1
PEG_TXP_C2
PEG_TXP_C3
PEG_TXP_C4
PEG_TXP_C5
PEG_TXP_C6
PEG_TXP_C7
PEG_TXP_C8
PEG_TXP_C9
PEG_TXP_C10
PEG_TXP_C11
PEG_TXP_C12
PEG_TXP_C13
PEG_TXP_C14
PEG_TXP_C15
+2.5V(5,8,12,16,17,20,35,41)
VCC3G_PCIE(8)
VCCP(2,3,4,5,8,9,18,20,35,41)
PEG_TXN_C[0..15]
PEG_TXP_C[0..15]
1
PEG_TXN_C[0..15] (11)
PEG_TXP_C[0..15] (11)
CFG5 CFG9
R434
*2.2K
Low=DMIx2
High=DMIx4
CFG7
A A
CFG7(5)
R52
*2.2K
Low=DT/Transportable CPU
High=Movile CPU
5
CFG9(5)CFG5(5)
Low=PCIE Reverse Lanes
High=PCIE Normal Operation
+2.5V +2.5V
CFG18(5)
Low=CPU core VCC 1.05V
High=CPU core VCC 1.5V
CFG18
R56
*2.2K
R44
*1K
CFG12(5)
CFG13(5) CFG6(5)
CFG11(5)
4
CFG12
CFG13
R424
*2.2K
00 : Reserved
01 : XOR Mode Enabled
10 : All Z Mode Enabled
11 : Normal Operation
CFG11
R65
*2.2K
Low=FSB533
R435
*2.2K
CFG6
R54
2.2K
Low=DDR II
High=DDR
CFG3
CFG3(5)
R61
*2.2K
Low=DDR533
3
CFG16
CFG16(5)
R451
*2.2K
Low=FSB Dynamic ODT Disabled
High=FSB Dynamic ODT Enabled
R43
*1K
CFG19
CFG19(5)
Low=CPU VTT 1.05V
High=CPU VTT 1.2V
CRT_COM#
VSYNC
HSYNC
REFSET
CRT_BLUE
CRT_GREEN
CRT_RED
2
R475 0
R471 *0
R479 0
R480 0
R26 0
R507 0
R508 0
R509 0
R478 *150/F
R477 *150/F
R476 *150/F
Size Document Number Rev
Custom
Date: Sheet
VCCP
VCCP
PROJECT : MA1
Quanta Computer Inc.
VGA DMI(2/5)
R475
R471
R479
R480
R26
R507
R508
R509
R478
R477
R476
641Thursday, November 25, 2004
1
ATI
0
X
0
0
0
0
0
0
X
X
X
of
INTEL
X
0
X
X
X
X
X
X
150/F
150/F
150/F
1A
5
VinaFix.com
D D
A_MD[0..63]
A_MD0
A_MD1
A_MD2
A_MD3
A_MD4
A_MD5
A_MD6
A_MD7
A_MD8
A_MD9
A_MD10
A_MD11
A_MD12
A_MD13
A_MD14
A_MD15
A_MD16
A_MD17
A_MD18
A_MD19
A_MD20
A_MD21
A_MD22
C C
B B
A_MD23
A_MD24
A_MD25
A_MD26
A_MD27
A_MD28
A_MD29
A_MD30
A_MD31
A_MD32
A_MD33
A_MD34
A_MD35
A_MD36
A_MD37
A_MD38
A_MD39
A_MD40
A_MD41
A_MD42
A_MD43
A_MD44
A_MD45
A_MD46
A_MD47
A_MD48
A_MD49
A_MD50
A_MD51
A_MD52
A_MD53
A_MD54
A_MD55
A_MD56
A_MD57
A_MD58
A_MD59
A_MD60
A_MD61
A_MD62
A_MD63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U37B
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
ALVISO
4
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
DDR SYSTEM MEMORY A
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
A_BS0#
AK15
A_BS1#
AK16
A_BS2#
AL21
A_DM0
AJ37
A_DM1
AP35
A_DM2
AL29
A_DM3
AP24
A_DM4
AP9
A_DM5
AP4
A_DM6
AJ2
A_DM7
AD3
A_DQS0
AK36
A_DQS1
AP33
A_DQS2
AN29
A_DQS3
AP23
A_DQS4
AM8
A_DQS5
AM4
A_DQS6
AJ1
A_DQS7
AE5
A_DQS#0
AK35
A_DQS#1
AP34
A_DQS#2
AN30
A_DQS#3
AN23
A_DQS#4
AN8
A_DQS#5
AM5
A_DQS#6
AH1
A_DQS#7
AE4
A_MA0
AL17
A_MA1
AP17
A_MA2
AP18
A_MA3
AM17
A_MA4
AN18
A_MA5
AM18
A_MA6
AL19
A_MA7
AP20
A_MA8
AM19
A_MA9
AL20
A_MA10
AM16
A_MA11
AN20
A_MA12
AM20
A_MA13
AM15
A_SCASA#
AN15
A_SRASA#
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
A_BMWEA#
AP15
A_BS0# (10)
A_BS1# (10)
A_BS2# (10)
A_SCASA# (10)
A_SRASA# (10)
A_BMWEA# (10)
A_DM[0..7] (10)
A_DQS[0..7] (10)
A_DQS#[0..7] (10)
A_MA[0..13] (10)
3
B_MD[0..63](10)A_MD[0..63](10)
B_MD[0..63]
B_MD0
B_MD1
B_MD2
B_MD3
B_MD4
B_MD5
B_MD6
B_MD7
B_MD8
B_MD9
B_MD10
B_MD11
B_MD12
B_MD13
B_MD14
B_MD15
B_MD16
B_MD17
B_MD18
B_MD19
B_MD20
B_MD21
B_MD22
B_MD23
B_MD24
B_MD25
B_MD26
B_MD27
B_MD28
B_MD29
B_MD30
B_MD31
B_MD32
B_MD33
B_MD34
B_MD35
B_MD36
B_MD37
B_MD38
B_MD39
B_MD40
B_MD41
B_MD42
B_MD43
B_MD44
B_MD45
B_MD46
B_MD47
B_MD48
B_MD49
B_MD50
B_MD51
B_MD52
B_MD53
B_MD54
B_MD55
B_MD56
B_MD57
B_MD58
B_MD59
B_MD60
B_MD61
B_MD62
B_MD63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
U37G
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
ALVISO
2
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
DDR SYSTEM MEMORY B
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
B_BS0#
AJ15
B_BS1#
AG17
B_BS2#
AG21
B_DM0
AF32
B_DM1
AK34
B_DM2
AK27
B_DM3
AK24
B_DM4
AJ10
B_DM5
AK5
B_DM6
AE7
B_DM7
AB7
B_DQS0
AF34
B_DQS1
AK32
B_DQS2
AJ28
B_DQS3
AK23
B_DQS4
AM10
B_DQS5
AH6
B_DQS6
AF8
B_DQS7
AB4
B_DQS#0
AF35
B_DQS#1
AK33
B_DQS#2
AK28
B_DQS#3
AJ23
B_DQS#4
AL10
B_DQS#5
AH7
B_DQS#6
AF7
B_DQS#7
AB5
B_MA0
AH17
B_MA1
AK17
B_MA2
AH18
B_MA3
AJ18
B_MA4
AK18
B_MA5
AJ19
B_MA6
AK19
B_MA7
AH19
B_MA8
AJ20
B_MA9
AH20
B_MA10
AJ16
B_MA11
AG18
B_MA12
AG20
B_MA13
AG15
B_SCASA#
AH14
B_SRASA#
AK14
SB_RCVENIN#
AF15
SB_RCVENOUT#
AF14
B_BMWEA#
AH16
B_BS0# (10)
B_BS1# (10)
B_BS2# (10)
B_SCASA# (10)
B_SRASA# (10)
T16T21
T17T19
B_BMWEA# (10)
1
B_DM[0..7] (10)
B_DQS[0..7] (10)
B_DQS#[0..7] (10)
B_MA[0..13] (10)
A A
PROJECT : MA1
Quanta Computer Inc.
ALVISO DDR(3/5)
1
of
741Thursday, November 25, 2004
1A
5
4
3
Size Document Number Rev
Custom
2
Date: Sheet
5
VinaFix.com
VCCP
C752
C746
4.7U/10V
2.2U
D D
C725
0.22U
VCCP_GMCH_CAP4
G1
VTT49
VTT50
C C
VTT51
C704
0.22U
VCCP_GMCH_CAP3
VTT48
G37
VCCP_GMCH_CAP2
VTT47
VSSA_3GBG
F37
C747
C748
0.47U/10V
0.47U
VCCP_GMCH_CAP1
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
U37
R37
N37
L37
J37
Y29
Y28
Y27
VCCP
VCCP
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
AF20
AP19
AF19
AF18
AE37
W37
+2.5V
VCCP
VTT26
VTT27
VTT28
VTT29
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
A28
A27
4
R489 *0
+2.5V
C775 10U
R488 0
VTT25
VCCTX_LVDS0
J10Y9W9U9R9P9N9M9L9J9N8M8N7M7N6M6A6N5M5N4M4N3M3N2M2B2V1N1M1
VTT22
VTT23
VTT24
VCCSM63
VCCSM64
AM1
AE1
R449 *10
C738 0.1U
C739 0.022U
R459 *0
C741 0
C766 *10U
N10
M10
K10
VTT20
VTT21
VCCSM61
VCCSM62
AB10
AB9
AP8
2 1
D31 *RB751V-40
B28
3
ATI
VCC36
K22
VCC35
X
10U
0
X
X
0.1U
0.022U
X
0
X
C128
0.1U
K24
K23
VCC33
VCC34
K25
J25
VCC32
INTEL
0
10U
X
RB751V-40
10
0.1U
0.022U
0
0.1U
10U
K26
H26
VCC30
VCC31
R489
+1.5V
L14
BLM11A121S
C209 0.1U
C245 470U
+
K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
BLM11A121S
C699 0.1U
C168 470U
+
E19
G19
H20
VCC_SYNC
VCCA_CRTDAC1
VVSSA_CRTDAC
L45
F19
VCCA_CRTDAC0
AA2
W18
V18
T18
K18
K17
AC1
AC2
C35
B23
AA1
VCC45
VCC46
VCC47
VCC48
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLB
VCCA_DPLLA
VCCH_MPLL0
VCCH_MPLL1
C775
R488
D31
R449
C738
C739
R459
C741
C766
K21
W20
U20
T20
K20
V19
U19
K19
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
POWER
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
VCC29
VCCSM6
C144
0.1U
H27
VCC28
VCCSM5
AC27
2
VCCP
C117
C110
C127
10U
0.1U
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCCD_LVDS2
VCCA_LVDS
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
B25
A25
A35
B22
B21
A21
AM37
AH37
AP29
AD28
AD27
VCC14
VCCD_LVDS1
10U
L28
B26
C104
10U
T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
E18
H18
G18
D19
H17
VCC3
VCC4
VCC5
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
C18
F18
VCC1
VCC2
VCCA_TVDACA1
VCCA_TVDACB0
E17
D18
U37H
ALVISO
VCC0
VCCA_TVDACA0
F17
1
D32
R472
R473
C735
C736
C754
C758
C765
C753
C757
C764
C691
C759
C763
C689
R470
R472 *10
R473 *0
ATI
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
X
INTEL
RB751V-40
10
0
0.1U
0.022U
0.1U
0.022U
0.1U
0.022U
0.1U
0.022U
0.1U
0.022U
0.1U
0.022U
0
D32
*RB751V-40
21
+1.5V
+3V
C735 0
VCC_DDRDLL
VCC3G_PCIE
C742
0.1U
L39
BLM11A121S
C751
0.1U
VCCA_3GPLL
R374 0.5/F
C660
10U
VCCA_3GPLL
5
+2.5V
C659
0.1U
B B
A A
V1.8_DDR_CAP6
V1.8_DDR_CAP3
V1.8_DDR_CAP4
C662
C673
C686
0.1U
+2.5V
C761
4.7U/10V
+1.5V +1.5V
4
Note: All VCCSM pins
shorted internally.
VCC_DDRDLL
VCC3G_PCIE
0.1U
0.1U
+
C264
100U
C688
10U
C229
0.1U
C680
10U
+
VCC3G_PCIE
C890
10U
C262
330uF
L16
BLM11A121S
L44
BLM11A121S
3
C258
10U
1.8VSUS
C259
10U
Note: All VCCSM pins
shorted internally.
+1.5V
V1.8_DDR_CAP5
C661
0.1U
V1.8_DDR_CAP1
V1.8_DDR_CAP2
C671
C667
0.1U
0.1U
+2.5V +2.5V +1.5V
C740
C762
0.1U
10U
2
R470 *0
+1.5V
C749
C750
0.01U
0.1U
Size Document Number Rev
Custom
Date: Sheet
C776
C737
10U
0.1U
PROJECT : MA1
Quanta Computer Inc.
C736 0
C754 0
C758 0
C765 0
C753 0
C757 0
C764 0
C691 0
C759 0
C763 0
C689 0
Alviso Power(4/5)
841Thursday, November 25, 2004
1
1A
of
5
VinaFix.com
D D
AJ3
AC3
AB3
AA3C3A3
AN2
AL2
AH2
AE2
AD2V2T2P2L2
B27
J26
G26
E26
A26
AN24
VSSALVDS
AL24J2G2D2Y1
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
B36
4
AK7
AG7
AA7V7G7
AJ6
AE6
AC6
AL5W5E5
AN4
AF4Y4U4P4L4H4C4
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
AA6T6P6L6J6B6AP5
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
3
AL14
AJ14
AG14
K14
J14
F14
B14
A14
J12
D12
B12
AN11
AL11
AJ11
AG11
AF11
AA11
Y11
H11
F11
AA10
Y10
L10
D10
AN9
AH9
AE9
AC9
AA9V9T9K9H9A9AL8Y8P8L8E8C8AN7
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
2
C21
AK20
V20
G20
F20
E20
D20
A20
AN19
AG19
W19
T19
J19
H19
C19
AL18
U18
B18
A18
AN17
AJ17
AF17
G17
C17
AL16
K16
H16
D16
A16
K15
C15
AN14
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
1
AF23
H23
AL22
AH22
J22
E22
D22
A22
AN21
AF21
F21
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
U37E
ALVISO
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
AG37
Y37
V37
T37
P37
M37
K37
H37
E37
AN36
AL36
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
W31
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
L29
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
AJ24
AG24
J24
F24
D24
B24
C C
VCCP
W13
V13
U13
T13
R13
P13
N13
M13
L13
W12
V12
U12
T12
R12
P12
N12
M12
VSS_NCTF0
L12
VTT_NCTF0
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
VTT_NCTF7
VTT_NCTF8
VTT_NCTF9
VTT_NCTF10
VTT_NCTF11
VTT_NCTF12
VTT_NCTF13
VTT_NCTF14
VTT_NCTF15
VTT_NCTF16
VTT_NCTF17
U37D
ALVISO
AB26
AA26
Y26
AB25
AA25
Y25
AB24
AA24
Y24
AB23
AA23
Y23
AB22
AA22
Y22
AB21
AA21
Y21
R21
AB20
AA20
AB19
AA19
AB18
AA18
AB17
AA17
Y17
R17
AB16
AA16
Y16
W16
V16
U16
T16
R16
P16
N16
M16
L16
AB15
AA15
Y15
W15
V15
U15
T15
R15
P15
N15
M15
L15
AB14
AA14
Y14
W14
V14
U14
T14
R14
P14
N14
M14
L14
AA13
Y13
AA12
Y12
B B
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36
VSS_NCTF37
VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
VSS_NCTF45
VSS_NCTF46
VSS_NCTF47
VSS_NCTF48
VSS_NCTF49
VSS_NCTF50
VSS_NCTF51
VSS_NCTF52
VSS_NCTF53
VSS_NCTF54
VSS_NCTF55
VSS_NCTF56
VSS_NCTF57
VSS_NCTF58
VSS_NCTF59
VSS_NCTF60
VSS_NCTF61
VSS_NCTF62
VSS_NCTF63
VSS_NCTF64
VSS_NCTF65
VSS_NCTF66
VSS_NCTF67
VSS_NCTF68
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF5
VSS_NCTF6
VSS_NCTF3
VSS_NCTF4
VSS_NCTF1
VSS_NCTF2
NCTF
VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
AD26
AC26
AD25
AC25
AD24
AC24
AD23
AC23
AD22
AC22
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
AD13
AC13
AB13
AD12
AC12
AB12
W26
V26
U26
T26
R26
P26
N26
M26
L26
W25
V25
U25
T25
R25
P25
N25
M25
L25
W24
V24
U24
T24
R24
P24
N24
M24
L24
W23
V23
U23
T23
R23
P23
N23
M23
L23
W22
V22
U22
T22
R22
P22
N22
M22
L22
W21
V21
U21
T21
P21
N21
M21
L21
Y20
R20
P20
N20
M20
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
N18
M18
L18
W17
V17
U17
T17
P17
N17
M17
L17
A A
5
4
3
2
1.8VSUSVCCP
Size Document Number Rev
Custom
Date: Sheet
PROJECT : MA1
Quanta Computer Inc.
VSS/NCTF(5/5)
1
of
941Thursday, November 25, 2004
1A
A
VinaFix.com
A_DM[0..7] (7)
A_MD[0..63] (7)
A_DQS[0..7] (7)
A_DQS#[0..7] (7)
A_MA[0..13] (7)
4 4
CKE0(5) CKE2(5) CKE3 (5)
3 3
A_BS2#(7)
A_BS0#(7)
A_BMWEA#(7)
A_SCASA#(7)
SM_CS1#(5)
2 2
+3V
1 1
1.8VSUS 1.8VSUS 1.8VSUS
SMDDR_VREF
A_MD0
A_MD1
A_DQS#0
A_DQS0
A_MD2
A_MD3
A_MD8
A_MD9
A_DQS#1
A_DQS1
A_MD10 B_MD14
A_MD11
A_MD16
A_MD17
A_DQS#2
A_DQS2
A_MD18
A_MD19
A_MD24
A_MD25
A_DM3
A_MD26
A_MD27
CKE0
A_BS2#
A_MA12
A_MA9
A_MA8
A_MA5
A_MA3
A_MA1
A_MA10
A_BS0#
A_BMWEA#
A_SCASA#
SM_CS1#
M_ODT1
A_MD32
A_MD33
A_DQS#4
A_DQS4
A_MD34
A_MD35
A_MD40
A_MD41
A_DM5
A_MD42 A_MD46
A_MD43
A_MD48
A_MD49
A_DQS#6
A_DQS6
A_MD50
A_MD56
A_MD57
A_DM7
A_MD58
A_MD59
PDAT_SMB
PCLK_SMB
A
JDIM1
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
PC4800 DDR2
CLOCK 0,1 CLOCK 3,4
( Channel A ) ( Channel B )
SMbus address A0 SMbus address A1
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
PC4800 DDR2
SDRAM SO-DIMM
(200P)
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
A_MD4
A_MD5
A_DM0
A_MD6
A_MD7
A_MD12
A_MD13
A_DM1
CLK_SDRAM0
CLK_SDRAM0#
A_MD14
A_MD15
A_MD20
A_MD21
A_DM2
A_MD22
A_MD23
A_MD28
A_MD29
A_DQS#3
A_DQS3
A_MD30
A_MD31
CKE1
A_MA11
A_MA7
A_MA6
A_MA4
A_MA2
A_MA0
A_BS1#
A_SRASA#
SM_CS0#
M_ODT0
A_MA13
A_MD36
A_MD37
A_DM4
A_MD38
A_MD39
A_MD44
A_MD45
A_DQS#5
A_DQS5
A_MD47
A_MD52
A_MD53
CLK_SDRAM1
CLK_SDRAM1#
A_DM6
A_MD54
A_MD55A_MD51
A_MD60
A_MD61
A_DQS#7
A_DQS7
A_MD62
A_MD63
R162
10K
R163
10K
B
CLK_SDRAM0 (5)
CLK_SDRAM0# (5)
CKE1 (5)
A_BS1# (7)
A_SRASA# (7)
SM_CS0# (5)
M_ODT0 (5)
CLK_SDRAM1 (5)
CLK_SDRAM1# (5)
B
C
B_DM[0..7] (7)
B_MD[0..63] (7)
B_DQS[0..7] (7)
B_DQS#[0..7] (7)
B_MA[0..13] (7)
SMDDR_VREF(5,34)
B_BS2#(7)
B_BS0#(7)
B_BMWEA#(7)
B_SCASA#(7)
SM_CS3#(5)
M_ODT3(5)M_ODT1(5)
PDAT_SMB(2,19,29,33)
PCLK_SMB(2,19,29,33)
SMDDR_VREF
B_MD0
B_MD1
B_DQS#0
B_DQS0
B_MD2
B_MD3
B_MD8
B_MD9
B_DQS#1
B_DQS1
B_MD10
B_MD11
B_MD16
B_MD17
B_DQS#2
B_DQS2
B_MD18
B_MD19
B_MD24
B_MD25
B_DM3
B_MD26
B_MD27
CKE2
B_BS2#
B_MA12
B_MA9
B_MA8
B_MA5
B_MA3
B_MA1
B_MA10
B_BS0#
B_BMWEA#
B_SCASA#
SM_CS3#
M_ODT3
B_MD32
B_MD33
B_DQS#4
B_DQS4
B_MD34
B_MD35
B_MD40
B_MD41
B_DM5
B_MD42 B_MD46
B_MD43
B_MD48
B_MD49
B_DQS#6
B_DQS6
B_MD50
B_MD56
B_MD57
B_DM7
B_MD58
B_MD59
PDAT_SMB
PCLK_SMB
+3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
JDIM2
VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
PC4800 DDR2
PC4800 DDR2
CKE 2,3CKE 0,1
High=5.2mmHigh=9.2mm
+3V(2,3,8,11,12,13,16,18,19,20,22,24,25,26,27,28,29,35,36,37,38,41)
1.8VSUS(5,8,9,34)
SMDDR_VTERM(34,41)
SMDDR_VREF(5,34)
C
VSS46
VSS15
VSS5
VSS16
DQ12
DQ13
VSS17
VSS53
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
VDD11
VDD4
VDD12
RAS#
VDD1
ODT0
SDRAM SO-DIMM
VDD6
VSS12
DQ36
DQ37
VSS28
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1#
VSS45
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
DQ4
DQ5
DM0
DQ6
DQ7
DM1
CK0
NC3
DM2
NC2
DM4
CK1
DM6
A15
A14
A11
A7
A6
A4
A2
A0
BA1
S0#
A13
SA0
SA1
1.8VSUS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
(200P)
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
+3V
SMDDR_VTERM
C855
1000P
B_MD4
B_MD5
B_DM0
B_MD6
B_MD7
B_MD12
B_MD13
B_DM1
CLK_SDRAM3
CLK_SDRAM3#
B_MD15
B_MD20
B_MD21
B_DM2
B_MD22
B_MD23
B_MD28
B_MD29
B_DQS#3
B_DQS3
B_MD30
B_MD31
CKE3
B_MA11
B_MA7
B_MA6
B_MA4
B_MA2
B_MA0
B_BS1#
B_SRASA#
SM_CS2#
M_ODT2
B_MA13
B_MD36
B_MD37
B_DM4
B_MD38
B_MD39
B_MD44
B_MD45
B_DQS#5
B_DQS5
B_MD47
B_MD52
B_MD53
CLK_SDRAM4
CLK_SDRAM4#
B_DM6
B_MD54
B_MD55B_MD51
B_MD60
B_MD61
B_DQS#7
B_DQS7
B_MD62
B_MD63
R139
10K
C857
C856
1000P
1000P
R140
10K
C858
1000P
CLK_SDRAM3 (5)
CLK_SDRAM3# (5)
B_BS1# (7)
B_SRASA# (7)
SM_CS2# (5)
CLK_SDRAM4 (5)
CLK_SDRAM4# (5)
SMDDR_VTERM
SMDDR_VTERM
M_ODT2 (5)
C371
0.1U
C333
0.1U
D
1.8VSUS 1.8VSUS
C289
C288
0.1U
1.8VSUS
C376
0.1U
+3V +3V
C625
2.2U
SMDDR_VREF
C347
2.2U
SMDDR_VTERM
C379
C373
0.1U
0.1U
C300
C310
0.1U
0.1U
0.1U
C360
0.1U
C624
0.1U
C353
0.1U
C290
0.1U
C377
0.1U
C614
2.2U
SMDDR_VREF
C298
2.2U
C845
C846
0.1U
0.1U
C315
C312
0.1U
0.1U
C301
C351
0.1U
0.1U
C342
0.1U
C378
0.1U
C610
0.1U
C299
0.1U
C847
0.1U
C364
0.1U
C365
0.1U
1.8VSUS
C848
0.1U
C350
0.1U
C366
0.1U
Place these Caps near So-Dimm1.Place these Caps near So-Dimm1.
C287
C291
2.2U
2.2U
Place these Caps near So-Dimm2.Place these Caps near So-Dimm2.
C381
C357
2.2U
2.2U
SM_CS0#
RP32 56X2
A_BS1#
A_MA8
RP28 56X2
A_MA5
A_MA1
RP27 56X2
A_MA3
A_MA11
RP36 56X2
CKE1
A_BS0#
RP26 56X2
A_MA10
A_MA6
RP35 56X2
A_MA7
A_MA4
RP34 56X2
A_MA2
A_SRASA#
RP33 56X2
A_MA0
A_MA12
RP29 56X2
A_MA9
A_SCASA#
RP25 56X2
A_BMWEA#
B_BS1#
RP14 56X2
B_MA2
B_MA1
RP4 56X2
B_MA3
B_MA5
RP5 56X2
B_MA8
B_MA0
RP15 56X2
B_MA4
B_MA9
RP6 56X2
B_MA12
B_MA7
RP16 56X2
B_MA6
B_BS2#
RP7 56X2
CKE2
B_MA13
RP13 56X2
B_SRASA#
B_SCASA#
RP2 56X2
B_BMWEA#
B_BS0#
RP3 56X2
B_MA10
M_ODT0
RP31 56X2
A_MA13
M_ODT2
RP12 56X2
SM_CS2#
M_ODT3
RP1 56X2
SM_CS3#
M_ODT1
RP24 56X2
SM_CS1#
B_MA11
RP17 56X2
CKE3
A_BS2#
RP30 56X2
CKE0
C850
C849
0.1U
0.1U
C313
C311
0.1U
0.1U
C335
C332
0.1U
0.1U
E
C292
2.2U
C383
2.2U
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
C851
0.1U
C352
0.1U
C362
0.1U
C852
0.1U
C372
0.1U
C363
0.1U
C344
2.2U
C382
2.2U
C343
2.2U
C359
2.2U
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
C853
0.1U
C314
0.1U
C349
0.1U
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C854
0.1U
C367
0.1U
C334
0.1U
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
C859
1000P
C860
1000P
C861
C862
1000P
C863
1000P
1000P
D
C864
1000P
Size Document Number Rev
Custom
Date: Sheet of
PROJECT : MA1
Quanta Computer Inc.
DDR II SODIMM
10 41Thursday, November 25, 2004
E
C341
2.2U
C358
2.2U
1A
5
VinaFix.com
AH30
AG30
AG29
AF29
AE29
AE30
AD30
AD29
AC29
AB29
AB30
AA30
AA29
Y29
W29
W30
V30
V29
U29
T29
T30
R30
R29
P29
N29
N30
M30
M29
K29
K30
AF26
AE26
AC25
AB25
AC27
AB27
AC26
AB26
Y25
W25
Y27
W27
Y26
W26
U25
T25
U27
T27
U26
T26
P25
N25
P27
N27
P26
N26
K25
K27
K26
AF27
AE27
AC23
AB24
AB23
AE25
AD25
AD24
AH21
AK21
AJ22
AK22
AJ24
AK24
AG22
AG23
AJ23
AH24
AH28
AJ29
AH27
AF25
AH25
L29
J30
L25
L27
L26
E8
B6
U36A
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_CALRP
PCIE_CALRN
PCIE_CALI
PCIE_TESTIN
PERSTb
PERSTb_MASK
R2SET
Y_G
C_R_PR
COMP_B_PB
H2SYNC
V2SYNC
DDC3CLK
DDC3DATA
SSIN
SSOUT
XTALIN
XTALOUT
TESTEN
TEST_YCLK
TEST_MCLK
PLLTEST
STEREOSYNC
M24
R47 150/F
R45 100/F
R46 10K/F
R48 10K
R431 *10K
R49 1K
R432 *10K
R73 715/F
R75 10K
R411 *33
R419 *33
R410 1K
R96 0
R107 0
R67 10K
R62 *10K
PEG_TXP_C0
PEG_TXN_C0
PEG_TXP_C1
PEG_TXN_C1
PEG_TXP_C2
PEG_TXN_C2
PEG_TXP_C3
PEG_TXN_C3
PEG_TXP_C4
PEG_TXN_C4
PEG_TXP_C5
PEG_TXN_C5
PEG_TXP_C6
PEG_TXN_C6
PEG_TXP_C7
PEG_TXN_C7
PEG_TXP_C8
PEG_TXN_C8
PEG_TXP_C9
PEG_TXN_C9
PEG_TXP_C10
PEG_TXN_C10
PEG_TXP_C11
PEG_TXN_C11
PEG_TXP_C12
PEG_TXN_C12
PEG_TXP_C13
PEG_TXN_C13
PEG_TXP_C14
PEG_TXN_C14
PEG_TXP_C15
PEG_TXN_C15
V_PEG_RXP0
V_PEG_RXN0
V_PEG_RXP1
V_PEG_RXN1
V_PEG_RXP2
V_PEG_RXN2
V_PEG_RXP3
V_PEG_RXN3
V_PEG_RXP4
V_PEG_RXN4
V_PEG_RXP5
V_PEG_RXN5
V_PEG_RXP6
V_PEG_RXN6
V_PEG_RXP7
V_PEG_RXN7
V_PEG_RXP8
V_PEG_RXN8
V_PEG_RXP9
V_PEG_RXN9
V_PEG_RXP10
V_PEG_RXN10
V_PEG_RXP11
V_PEG_RXN11
V_PEG_RXP12
V_PEG_RXN12
V_PEG_RXP13
V_PEG_RXN13
V_PEG_RXP14
V_PEG_RXN14
V_PEG_RXP15
V_PEG_RXN15
SRC_PEG
SRC_PEG#
VPCIE_CR+
VPCIE_CRVPCIE_CAL
VPCIE_TIN
-VPCIE_RSTM
-VGARST
V_R2SET
V_TV_Y/G
V_TV_C/R
V_TV_COMP
TP5
TP60
VTHM_CLK
VTHM_DAT
TP66
V_PLLTEST
TP15
27M_IN
27M_O
Z_V0101
Z_V0102
Z_V0103
Z_V0104
PEG_TXP_C[0..15](6)
PEG_TXN_C[0..15](6)
PEG_RXP[0..15](6)
D D
C C
B B
A A
PEG_RXN[0..15](6)
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
VGA1.2V
+3V
+3V
C732 18P
Y5
TXC=27MHz
C733 18P
C120 .1U
C124 .1U
C89 .1U
C93 .1U
C137 .1U
C148 .1U
C106 .1U
C109 .1U
C160 .1U
C167 .1U
C114 .1U
C119 .1U
C179 .1U
C187 .1U
C125 .1U
C132 .1U
C195 .1U
C206 .1U
C149 .1U
C161 .1U
C214 .1U
C222 .1U
C169 .1U
C177 .1U
C230 .1U
C235 .1U
C188 .1U
C192 .1U
C240 .1U
C244 .1U
C202 .1U
C211 .1U
SRC_PEG(2)
SRC_PEG#(2)
XT_IN
R414
*1M
XT_OUT
+3V
5
DAC2
SS PCI EXPRESSCLK
4
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO_PWRCNTL
GPIO_MEMSSIN
DVOMODE
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
VREFG
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
LVDS DVO / EXT TMDS / GPIOTHERM TMDSDAC1
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
DDC2CLK
DDC2DATA
HSYNC
VSYNC
DDC1DATA
DDC1CLK
GPIO_AUXWIN
DPLUS
DMINUS
4
BLON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
HPD1
RSET
R
G
B
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20
AE12
AG12
AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12
AE13
AE14
AF12
AK27
AJ27
AJ26
AJ25
AK25
AH26
AG25
AF24
AG24
AF11
AE11
DVOMODE
DVPDATA_16
DVPDATA_17
SDA
R59 0
SCL
R58 0
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DVPCNTL0
DVPCNTL1
DVPCNTL2
DVPCNTL3
VREFG
V_TXLOUT0V_TXLOUT0+
V_TXLOUT1V_TXLOUT1+
V_TXLOUT2V_TXLOUT2+
V_TXLCLKOUTV_TXLCLKOUT+
V_TXUOUT0V_TXUOUT0+
V_TXUOUT1V_TXUOUT1+
V_TXUOUT2V_TXUOUT2+
V_TXUCLKOUTV_TXUCLKOUT+
DISP_ON
BLON
DVI_CLK
DVI_DAT
V_CRT_R_COM
V_CRT_G_COM
V_CRT_B_COM
V_HSYNC_COM
V_VSYNC_COM
V_RST
V_DDCDATA
V_DDCCLK
-VGA_ALERT
VGATHRM+
VGATHRM-
GPIO_0 (13)
GPIO_1 (13)
GPIO_2 (13)
GPIO_3 (13)
GPIO_4 (13)
GPIO_5 (13)
GPIO_6 (13)
TP59
GPIO_8 (13)
GPIO_9 (13)
TP8
GPIO_11 (13)
GPIO_12 (13)
GPIO_13 (13)
TP13
V_PWRCNTL (36)
C714 10P
R84 0
TP70
TP76
TP4
TP79
TP81
TP74
TP78
TP72
TP7
TP62
TP71
TP67
TP18
TP14
TP6
TP21
DVPDATA_21 (13)
DVPDATA_22 (13)
DVPDATA_23 (13)
R429 10K
R428 10K
R427 10K
R426 10K
R92 1K
R91 1K
C154 .1U
DISP_ON (6,16)
BLON (6,16)
R425
*10K
V_PWRCNTL
H=Lower core voltage(1.0V)
L=Higher core voltage(1.2V)
V_MEMSSIN
TP65
TP73
TP80
TP9
TP69
TP77
TP63
TP75
TP82
TP64
TP61
TP68
TP2
TP10
TP3
3
DVPDATA_16 (13)
DVPDATA_17 (13)
DDC_DATA (6,16)
DDC_CLK (6,16)
+3V
+3V
3
SRS= 1 DOWN -2.5%
0 DOWN -1.8%
M DOWN -0.6%
R22 33
+3V
R20 0
R19 0
CLK2_GND CLK2_GND
THDAT_SMB(3,25)
THCLK_SMB(3,25)
VTHM_CLK
VTHM_DAT
+3V
R421 10K
+3V
R436 0
-VGA_ALERT
1726_CKOV_MEMSSIN
R24 *10K
Add R423
R422 0
R423 0
R438 *0
R437 *0
R40 20K
1 3
LVDS
V_TXLOUT0V_TXLOUT0+
V_TXLOUT1V_TXLOUT1+
V_TXLOUT2V_TXLOUT2+
V_TXLCLKOUTV_TXLCLKOUT+
V_TXUOUT0V_TXUOUT0+
V_TXUOUT1V_TXUOUT1+
V_TXUOUT2V_TXUOUT2+
V_TXUCLKOUTV_TXUCLKOUT+
RP75 0X2
1
3
RP74 0X2
1
3
RP73 0X2
1
3
RP72 0X2
1
3
RP76 0X2
1
3
RP71 0X2
1
3
RP70 0X2
1
3
RP69 0X2
1
3
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
CRT
V_CRT_R_COM
V_CRT_G_COM
V_CRT_B_COM
V_HSYNC_COM
V_VSYNC_COM
V_DDCDATA
V_DDCCLK
R441 0
R442 0
R443 0
R31 0
R30 0
R445 0R415 499/F
R444 0
TV_OUT
V_TV_Y/G
V_TV_C/R
V_TV_COMP
R448 0
R446 0
R447 0
2
XT_IN
781-1_SMCLK
781-1_SMDAT
2
Q44
DTC144EUA
TXLOUT0- (6,16)
TXLOUT0+ (6,16)
TXLOUT1- (6,16)
TXLOUT1+ (6,16)
TXLOUT2- (6,16)
TXLOUT2+ (6,16)
TXLCLKOUT- (6,16)
TXLCLKOUT+ (6,16)
TXUOUT0- (6,16)
TXUOUT0+ (6,16)
TXUOUT1- (6,16)
TXUOUT1+ (6,16)
TXUOUT2- (6,16)
TXUOUT2+ (6,16)
TXUCLKOUT- (6,16)
TXUCLKOUT+ (6,16)
CRT_R_COM (6,17)
CRT_G_COM (6,17)
CRT_B_COM (6,17)
HSYNC_COM (6,17)
VSYNC_COM (6,17)
DDCDATA (6,17)
DDCCLK (6,17)
TV_Y/G (6,17,33)
TV_C/R (6,17,33)
TV_COMP (6,17,33)
2
MEMORY CLOCK SPREAD
SPECTRUM
U42
1
XIN
2
VSS
3
SRS
4 5
SSCLK REF
1726_S0
CY25819
MK1726-8
R28
*10K
XOUT
VDD
8
7
6
PD
CLK2_GND
Thermal Sensor
U2
8
SMCLK
7
-GMT871_VGA
6
SMDATA
-ALT
MAX6647
ADDRESS: 9AH
Changed to 150/F
Changed to 150/F
TV_OUT
27MOUT
PLACE CLOSE TO ASIC
PLTRST#(5,18,19,27,29)
Size Document Number Rev
Custom
Date: Sheet
1
XT_OUT
MK1726_VDD
MK_27M
MK_PD
R25
*10K
VCC
DXP
DXN
-OVTGND
R465 33
MK1726_VDD
1
2
3
45
DDC_CLK
DDC_DATA
DDCDATA
DDCCLK
VTHM_CLK
VTHM_DAT
DVPDATA_20
-VGATHRM
CLK2_GND
C743
.1U
781-1_3V
C729 .1U
C726
2200P
R416 4.7K
R417 4.7K
R33 4.7K
R32 4.7K
R42 6.8K/F
R41 6.8K/F
R398 10K
27MOUT
C75
10P
L2 0
C81
22U/16V
R413 100/F
VGATHRM+
VGATHRM-
R412 10K
PLACE CLOSE TO AS I C
VGA27M
+3V
5
2
1
R68 *0
R460 150/F
R461 150/F
R462 150/F
R37 10K
C78 *10P
C79 *10P
C80 *10P
R36 150/F
R34 150/F
R35 150/F
R63 *0
R57 0
R72
71.5/F
U3
7SZ32
4
CRT_R_COM
CRT_G_COM
CRT_B_COM
BLON
CRT_R_COM
CRT_G_COM
CRT_B_COM
TV_Y/G
TV_C/R
TV_COMP
R66 121/F
PROJECT : MA1
Quanta Computer Inc.
VGA HOST(ATI M24)
11 41Thursday, November 25, 2004
1
+3V
+3V
+3V
+3V
27M_IN
27M_O
-VGARST
1A
of
5
VinaFix.com
4
3
2
1
VDD_MEM
C196
C261
1000P
10U
D D
VDD_MEM
C243
C265
.1U
10U
VDD_MEM
C175
C251
.1U
.1U
C95
10U
L4 0
L46 0
VDD_MEM(13,14,15,34,41)
+1.8V
+1.8V
5
L10 0
L9 *0
C94
*10U
VDD_MEM
+1.8V
+1.8V
+1.8V
L47 0
L15 0
C97
10U
C730
10U
+2.5V
C C
B B
A A
LVDR_2.8V
+1.8V
+1.8V
C241
1000P
C239
.1U
C165
.1U
LVDR25
C135
.1U
LVDDR18
C99
.1U
LPVDD
C112
.1U
L40 0
C224 .1U
C247 .1U
L5 0
C96 .1U
C118 .1U
L8 0
L6 0
C242
1000P
C191
.1U
C184
.1U
C100
.1U
C111
.1U
C731
10U
C260
10U
C237
1000P
C252
.1U
C246
.1U
C129
.1U
TXVDDR18
VDDRH
A2VDD25
V_A2VDDQ
V_AVDD
VDD1
PVDD
C728
.1U
MPVDD
C263
.1U
K23
K24
H10
H13
H15
H17
AA1
AA4
AA7
AA8
A15
A21
A28
B30
D26
D23
D20
D17
D14
D11
E27
G10
G13
G15
G19
G22
G27
H22
H19
AD4
L23
AE16
AE17
AF15
AE15
AH19
AH13
AF13
AF14
F18
AF21
AE20
AF23
AH23
AE23
AE22
AK28
T7
R4
R1
N8
N7
M4
L8
N4
J8
J7
J4
J1
T8
V4
V7
V8
A3
A9
B1
D8
D5
F4
G7
N6
A7
U36D
VDDR1_T7
VDDR1_R4
VDDR1_R1
VDDR1_N8
VDDR1_N7
VDDR1_M4
VDDR1_L8
VDDR1_K23
VDDR1_K24
VDDR1_N4
VDDR1_J8
VDDR1_J7
VDDR1_J4
VDDR1_J1
VDDR1_H10
VDDR1_H13
VDDR1_H15
VDDR1_H17
VDDR1_T8
VDDR1_V4
VDDR1_V7
VDDR1_V8
VDDR1_AA1
VDDR1_AA4
VDDR1_AA7
VDDR1_AA8
VDDR1_A3
VDDR1_A9
VDDR1_A15
VDDR1_A21
VDDR1_A28
VDDR1_B1
VDDR1_B30
VDDR1_D26
VDDR1_D23
VDDR1_D20
VDDR1_D17
VDDR1_D14
VDDR1_D11
VDDR1_D8
VDDR1_D5
VDDR1_E27
VDDR1_F4
VDDR1_G7
VDDR1_G10
VDDR1_G13
VDDR1_G15
VDDR1_G19
VDDR1_G22
VDDR1_G27
VDDR1_H22
VDDR1_H19
VDDR1_AD4
VDDR1_L23
LVDDR_25_AE16
LVDDR_25_AE17
LVDDR_18_AF15
LVDDR_18_AE15
LPVDD
TPVDD
TXVDDR_AF13
TXVDDR_AF14
VDDRH0
VDDRH1
A2VDD_AF21
A2VDD_AE20
A2VDDQ
AVDD
VDD1DI
VDD2DI
PVDD
MPVDD
M24
VDD1
PCIE_VDDR_12_AG26
PCIE_VDDR_12_AK29
PCIE_VDDR_12_AJ30
PCIE_VDDR_12_AG28
PCIE_VDDR_12_AG27
PCIE_PVDD_12_N24
PCIE_PVDD_12_N23
PCIE_PVDD_12_P23
PCIE_PVDD_18_U23
PCIE_PVDD_18_T23
PCIE_PVDD_18_V23
PCIE_PVDD_18_W23
I/O POWER
C98
10U
4
VDDC_AC13
VDDC_AD13
VDDC_AD15
VDDC_AC15
VDDC_AC17
VDD15_P8
VDD15_Y8
VDD15_AC11
VDD15_AC20
VDD15_H20
VDD15_H11
VDD15_M23
VDD15_Y23
VDDR3_AD7
VDDR3_AD19
VDDR3_AD21
VDDR3_AC22
VDDR3_AC8
VDDR3_AC21
VDDR3_AC19
VDDR4_AG7
VDDR4_AD9
VDDR4_AC9
VDDR4_AC10
VDDR4_AD10
LVSSR_AF18
LVSSR_AH17
LVSSR_AG15
LVSSR_AG18
TXVSSR_AH14
TXVSSR_AG13
TXVSSR_AG14
A2VSSN_AH20
A2VSSN_AG21
C150
.1U
NC_D9
NC_D13
NC_D19
NC_D25
NC_E4
NC_T4
NC_AB4
AVSSQ
LPVSS
TPVSS
VSSRH0
VSSRH1
A2VSSQ
AVSSN
VSS1DI
VSS2DI
PVSS
MPVSS
C142
.1U
AC13
AD13
AD15
AC15
AC17
P8
Y8
AC11
AC20
H20
H11
M23
Y23
AD7
AD19
AD21
AC22
AC8
AC21
AC19
AG7
AD9
AC9
AC10
AD10
AG26
AK29
AJ30
AG28
AG27
N24
N23
P23
U23
T23
V23
W23
D9
D13
D19
D25
E4
T4
AB4
AD22
AF18
AH17
AG15
AG18
AH18
AH12
AH14
AG13
AG14
F19
M6
AH20
AG21
AF22
AH22
AE24
AE21
AJ28
A6
VGACORE
C232
C182
.1U
C194
.1U
1000P
C176
1000P
C143
.1U
C166
.1U
L13 0
C170
10U
C153
1000P
C152
.1U
C145
.1U
C105 10U
C116 .1U
(PCIE PLL/IO 1.8V)
+1.8V
+1.8V
L7 0
+2.5V
C103
*1U
C199
C139
.1U
1000P
C208
C200
.1U
.1U
3
C164
C228
1000P
1000P
+1.5V
C236
10U
+3V
(IO.POWER)
C174
10U
+3V
(EXT.TMDS)
C173
10U
VGA1.2V
(PCIE 1.2V)
VGA1.2V (11,36)
VGA1.2V
(QUIET PCIE 1.2V)
L17 0
C266
10U
L3 0
C90
10U
C88
10U
U1
3 4
IN OUT
1
SHDN
2
GND
*G913
LVDR_2.8V
C146
C163
1000P
1000P
C233
C216
.1U
.1U
(1.2V~1550mA)
VGA_PCIE18
C101
.1U
C141
.1U
5
SET
R55 *100K/F
R64 *78.7K/F
C183
1000P
C215
.1U
C221
C185
1000P
1000P
C217
C231
1000P
1000P
C151
C147
.1U
.1U
C155
C156
.1U
.1U
C113 .1U
C122 .1U
C108 .1U
VGA_PCIE12
C218 .1U
C219 .1U
C210 .1U
VGA_PCIE18
C181 .1U
C190 .1U
C203 .1U
TP30
TP31
TP28
TP32
TP29
TP23
TP20
+3V LVDR_2.8V
TXVDDR18
C102
.1U
A2VDD25
C126
.1U
G914_SET
C162
1000P
C226
.1U
C225
1000P
VGACORE
C198
.1U
C91
*1U
(VGA CORE=1.2&1.0V)
VGACORE
VGACORE
C212
C189
.1U
1U
C227
C197
.1U
.1U
2
A10
A16
A22
A29
C28
C30
D27
D24
D21
D18
D15
D12
D10
F27
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
AD12
AG5
AG9
AG11
P17
P18
P19
U12
U13
U14
U17
U18
U19
V19
V18
V17
V14
V13
V12
N18
N17
N14
W17
W18
W12
W13
W14
N13
N19
M19
M18
M12
N12
M13
M14
P12
P13
P14
M17
W19
A2
C1
C3
D6
D4
G9
H9
H8
H4
J23
J24
R7
P4
M7
M8
L4
K1
K7
K8
R8
T1
U36E
VSS_A2
VSS_A10
VSS_A16
VSS_A22
VSS_A29
VSS_C1
VSS_C3
VSS_C28
VSS_C30
VSS_D27
VSS_D24
VSS_D21
VSS_D18
VSS_D15
VSS_D12
VSS_D10
VSS_D6
VSS_D4
VSS_F27
VSS_G9
VSS_G12
VSS_G16
VSS_G18
VSS_G21
VSS_G24
VSS_H27
VSS_H23
VSS_H21
VSS_H18
VSS_H16
VSS_H14
VSS_H12
VSS_H9
VSS_H8
VSS_H4
VSS_J23
VSS_J24
VSS_AD12
VSS_AG5
VSS_AG9
VSS_AG11
VSS_R7
VSS_P4
VSS_M7
VSS_M8
VSS_L4
VSS_K1
VSS_K7
VSS_K8
VSS_R8
VSS_T1
VDDC_P17
VDDC_P18
VDDC_P19
VDDC_U12
VDDC_U13
VDDC_U14
VDDC_U17
VDDC_U18
VDDC_U19
VDDC_V19
VDDC_V18
VDDC_V17
VDDC_V14
VDDC_V13
VDDC_V12
VDDC_N18
VDDC_N17
VDDC_N14
VDDC_W17
VDDC_W18
VDDC_W12
VDDC_W13
VDDC_W14
VDDC_N13
VDDC_N19
VDDC_M19
VDDC_M18
VDDC_M12
VDDC_N12
VDDC_M13
VDDC_M14
VDDC_P12
VDDC_P13
VDDC_P14
VDDC_M17
VDDC_W19
M24
PCIE_VSS_K28
PCIE_VSS_L28
PCIE_VSS_M27
PCIE_VSS_M26
PCIE_VSS_M24
CORE GND
PCIE_VSS_M25
PCIE_VSS_M28
PCIE_VSS_P28
PCIE_VSS_N28
PCIE_VSS_R25
PCIE_VSS_R23
PCIE_VSS_R24
PCIE_VSS_R26
PCIE_VSS_R27
PCIE_VSS_R28
PCIE_VSS_T28
PCIE_VSS_T24
PCIE_VSS_U28
PCIE_VSS_V24
PCIE_VSS_V26
PCIE_VSS_V27
PCIE_VSS_V25
PCIE_VSS_V28
PCIE_VSS_Y28
PCIE_VSS_W24
PCIE_VSS_W28
PCIE_VSS_AA26
PCIE_VSS_AA27
PCIE_VSS_A23
PCIE_VSS_AA24
PCIE_VSS_AA25
PCIE_VSS_AA28
PCIE_VSS_AB28
PCIE_VSS_AC28
PCIE_VSS_AD28
PCIE_VSS_AD26
PCIE_VSS_AD27
PCIE_VSS_AE28
PCIE_VSS_AF28
PCIE_VSS_AH29
CENTER ARRAY
VDDC1_W16
VDDC1_M15
VDDC1_R19
VDDC1_T12
VSS_U4
VSS_U8
VSS_W7
VSS_W8
VSS_Y4
VSS_AB8
VSS_AB7
VSS_AB1
VSS_ AC4
VSS_AC12
VSS_AC14
VSS_AD16
VSS_AC16
VSS_AC18
VSS_AD18
VSS_AK2
VSS_AJ1
VSS_M16
VSS_N16
VSS_N15
VSS_P15
VSS_P16
VSS_R18
VSS_R17
VSS_R16
VSS_R15
VSS_R14
VSS_R13
VSS_R12
VSS_T13
VSS_T14
VSS_T15
VSS_W15
VSS_V16
VSS_V15
VSS_U15
VSS_U16
VSS_T19
VSS_T18
VSS_T17
VSS_T16
U4
U8
W7
W8
Y4
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1
K28
L28
M27
M26
M24
M25
M28
P28
N28
R25
R23
R24
R26
R27
R28
T28
T24
U28
V24
V26
V27
V25
V28
Y28
W24
W28
AA26
AA27
AA23
AA24
AA25
AA28
AB28
AC28
AD28
AD26
AD27
AE28
AF28
AH29
M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
W16
M15
R19
T12
VGA_VDDC
L12 0
C186 .1U
C201 .1U
C223 1U
C207 .1U
PROJECT : MA1
Quanta Computer Inc.
Size Document Number Rev
Custom
Date: Sheet
ATI M24(POWER)
12 41Thursday, November 25, 2004
1
VGACORE
1A
of
5
VinaFix.com
4
3
2
1
R109
100
R106
100
MDB[0..63](15)
C256
.1U
R101
100
R103
100
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
VDDR1
1.8V
2.5V
U36C
D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
M24
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
MEMVMODE_0
GND
+VDDC_CT
MEMORY INTERFACE B
ROMCS#
MEMVMODE_0
MEMVMODE_1
MEMTEST
MEMVMODE_1
+VDDC_CT
GND
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB_0
DIMB_1
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
E3
AA3
AF5
C6
C7
C8
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
-DQMB0
-DQMB1
-DQMB2
-DQMB3
-DQMB4
-DQMB5
-DQMB6
-DQMB7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
-RASB
-CASB
-WEB
-CSB0
-CSB1
CKEB
CLKB0
-CLKB0
CLKB1
-CLKB1
DIMB0
DIMB1
MEMVMODE0
MEMVMODE1
MBMTEST
R108
47
R388 10K
R386 10
R387 10
R389 10
R391 10
R105
*4.7K
MDA[0..63](14)
H28
H29
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
B10
E13
E12
E10
F12
F11
U36B
DQA0
DQA1
J28
DQA2
J29
DQA3
J26
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
C9
DQA53
B9
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
M24
MEMORY INTERFACE A
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
MVREFD
MVREFS
DIMA_0
DIMA_1
MAA0
E22
MAA1
B22
MAA2
B23
MAA3
B24
MAA4
C23
MAA5
C22
MAA6
F22
MAA7
F21
MAA8
C21
MAA9
A24
MAA10
C24
MAA11
A25
MAA12
E21
MAA13
B20
C19
-DQMA0
J25
-DQMA1MDA17
F29
-DQMA2
E25
-DQMA3
A27
-DQMA4
F15
-DQMA5
C15
-DQMA6
C11
-DQMA7
E11
QSA0
J27
QSA1
F30
QSA2
F24
QSA3
B27
QSA4
E16
QSA5
B16
QSA6
B11
QSA7
F10
-RASA
A19
-CASA
E18
-WEA
E19
-CSA0
E20
-CSA1
F20
B19
B21
C20
C18
A18
B7
B8
D30
B13
CLKA0
-CLKA0
CLKA1
-CLKA1
DIMA0
DIMA1
CKEA
R377 10K
R375 10
R376 10
R379 10
R378 10
MVREFD
MVREFS
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
D D
C C
B B
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
-RASA (14)
-CASA (14)
-WEA (14)
-CSA0 (14)
-CSA1 (14)
TP52
TP33
MAA[0..13] (14)
-DQMA[0..7] (14)
QSA[0..7] (14)
CKEA (14)
M_CLKA0 (14)
-M_CLKA0 (14)
M_CLKA1 (14)
-M_CLKA1 (14)
VDD_MEM VDD_MEM
C267
.1U
Place close to ASIC
MAB[0..13] (15)
-RASB (15)
-CASB (15)
-WEB (15)
-CSB0 (15)
-CSB1 (15)
TP27
TP19
R100 *4.7K
R104 4.7K
R102
4.7K
-DQMB[0..7] (15)
QSB[0..7] (15)
M_CLKB0 (15)
-M_CLKB0 (15)
M_CLKB1 (15)
-M_CLKB1 (15)
M26 NC
CKEB (15)
+1.8V
STRAPS PIN STRAPS PIN
PCI-Express Current Calibration Bandgap Backup
GPIO_0
0: use reference voltage from Bandgap
1: use reference voltage from resistor divider
PCI-Express PLL Calibration force enable
GPIO_1
0: Disable PLL force calibration
1: Enable PLL force calibration
00: PCI Express 1.0 mode
GPIO_(3,2)
A A
GPIO_4
01: RESERVED
10: PCI Express 1.0 mode
11: RESERVED
Turn off PCI-Express impedance / strength calibration
0: enable
1: disable
GPIO_5
GPIO_6
Bypass PCI-Express PLL
PCI-Express transmitter current compensation
0: Normal
1: Inject extra current for output buffer switching
5
4
GPIO_8
GPIO(9,13:11)
INT P/D
DVPDATA_21~23
MEM TYPE
Strap to set the debug muxes to bting out DEBUG signals
even if registers are inaccessible
ROMIDCFG
0x0x: No ROM, CHG_ID=0
0x1x: No Rom, CHG_ID=1
1000: Parallel ROM, Chip ID'S from ROM
1000: Parallel ROM, Chip ID'S from ROM
DVPDATA_23
0
0
0
0
1
1
1
1
DVPDATA_22
0
0
1
1
0
0
1
1
DVPDATA_21
0
1
0
1
0
1
0
1
3
DVPDATA_21
Samsung 8M x 32 (1.8V) - M24
Samsung 4M x 32 (1.8V) - M24
Hynix 8M x 32 (1.8V) - M24
Samsung 4M x 32 (1.8V) - M22
Hynix 4M x 32 (1.8V) - M24
+3V
R83 10K
R405 *10K
R76 *10K
R407 *10K
R404 *10K
R403 *10K
R406 *10K
R400 *10K
R402 *10K
R396 *10K
R87 *10K
R82 *10K
R81 *10K
R86 *10K
R77 *10K
R70 *10K
R71 *10K
2
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_8
GPIO_9
GPIO_11
GPIO_12
GPIO_13
DVPDATA_16
DVPDATA_17
DVPDATA_21
DVPDATA_22
DVPDATA_23
GPIO_0 (11)
GPIO_1 (11)
GPIO_2 (11)
GPIO_3 (11)
GPIO_4 (11)
GPIO_5 (11)
GPIO_6 (11)
GPIO_8 (11)
GPIO_9 (11)
GPIO_11 (11)
GPIO_12 (11)
GPIO_13 (11)
R78 10K
R89 10K
R79 10K
R69 10K
R60 10K
DVPDATA_16
DVPDATA_17
DVPDATA_21
DVPDATA_22
DVPDATA_23
DVPDATA_16 (11)
DVPDATA_17 (11)
DVPDATA_21 (11)
DVPDATA_22 (11)
DVPDATA_23 (11)
M26 NC
PROJECT : MA1
Quanta Computer Inc.
Size Document Number Rev
Custom
Date: Sheet
ATI M24 MEM/STRAPS PIN
1
13 41Thursday, November 25, 2004
of
1A
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