Fujitsu TF1560GH, C383, S383FA-V151 Schematic

SERVICE MANUAL
TF1560GH C383 S383FA-V151
P/N : 41A50-137
TABLE OF CONTENTS
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PAGE
1. SPECIFICATIONS ....................................................................................................
1-1 GENERAL SPECIFICATIONS ...................................................….............. 3
1-2 LCD MONITOR DESCRIPTION .................................................................. 4
1-3 INTERFACE CONNECTOR .................................................................……. 4
2. PRECAUTION AND NOTICES ................................................................................
2-1 ASSEMBLY PRECAUTION ......................................................................... 5
2-2 OPERATIONG PRECAUTION ..................................................................... 5
2-3 STORAGE PRECAUTION …........................................................................ 5
2-4 HIGH VOLTAGE WARNING ....................................................................... 5
3. OPERATING INSTRUCTIONS ................................................................................
4. ADJUSTMENT ..........................................................................................................
4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS ............................... 7
4-2 ADJUSTMENTS METHOD ...........................................................................
4-3 FRONT PANEL CONTROL KNOBS ............................................................ 8
5. CIRCUIT DESCRIPTION ..........................................................................................
5-1 THE DIFFERENT BETWEEN EACH PANEL ……………………………. 9 5-2 SPECIAL FUNCTION WITH PRESS KEY ……………………………….. 9 5-3 SIMPLE INTRODUCTION ABOUT LM500 CHIPSET …………………... 10
7-8
6. TROUBLE SHOOTING CHART ..............................................................................
7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY......................................
8. PARTS LISTING .........................................................................................………...
9. POWER SYSTEM AND CONSUMPTION CURRENT............................................
9-1 HARDWARE BLOCK DIAGRAM …………………………………………
10. PCB LAYOUT .....................................................................………………………...
11. SCHEMATIC DIAGRAM ….....................................................................................
1. SPECIFICATIONS FOR LCD MONITOR
1-1 General specifications
1. LCD-PANEL :
Active display area 15 inches diagonal
Pixel pitch 0.298 mm x 0.298 mm Pixel format 1024 x 768 RGB vertical stripe arrangement
2. Display Color :
6-bit, 262144 colors
3. External Controls :
Power On/Off, Auto key, Rotary-knob, Contrast, Brightness, Focus, Clock,
H-position, V-position, Language, Recall-7800, Recall-6500, Reset,
Exit-osd, Red, Green, Blue
4. Input Video Signal :
Analog-signal 0.7Vpp
Video signal termination impedance 75 OHM
5. Scanning Frequencies :
Horizontal: 29 KHz - 61 KHz Vertical: 55 Hz – 75 Hz Pixel clock: 80 MHz
6. Factory Preset Timing : 18
User Timings : 19 Input signal tolerance : H tolerance 1 K, V tolerance
7. Power Source :
Switching Mode Power Supply AC 100 – 240 V, 50/60 Hz Universal Type
8. Operating Temperature : 0 - 50 Ambient
Non-operating Temperature : -20 - 60
9. Humidity :
Operating : 20% to 80% RH (non-condensing) Non Operating : 5% to 95%RH (38.7 maximum wet bulb temperature)
10. Weight :
4.6 kg
11. External Connection : 15Pin D-type Connector, AC power-Cord
12. View Angle : x-axis right/left = 60, y-axis up/down = 45
13. Outside dimension : Width x Height x Thickness = 398mm x 401mm x 250mm
14. Plug and Play : VESA DDC1/DDC2B
15. Power saving : VESA DPMS
AC-IN
1-2 LCD MONITOR DESCRIPTION
The LCD MONITOR will contain an main board, an inverter board, a power switch board and a keyboard. The main board will house the flat panel control logic, brightness control logic, DDC and DC-DC conversion to supply the appropriate power to the whole board and LCD panel, and transmitting TTL level signals into LCD Module to drive the LCD display circuit.
The inverter board will drive the two CCFLs (Cold Cathode Fluorescent Tube). The switching power board will provides the power ON/OFF control over the whole monitor and control for DPMS LED indicator. The function keyboard will provides the OSD control signal to the Main Board.
Inverter Flat Panel
CCFT Drive.
ADAPTER
1-3 Interface Connectors
(A) Power Cable (B) Video Signal Connectors and Cable
Monitor Block Diagram
Main Board
Keyboard
HOST Computer
RS232 Connector
Video signal, DDC
2. PRECAUTIONS AND NOTICES
2-1 ASSEMBLY PRECAUTION
(1) Please do not press or scratch LCD panel surface with anything hard. And do not soil LCD panel surface
by touching with bare hands (Polarizer film, surface of LCD panel is easy to be flawed)
In the LCD panel, the gap between two glass plates is kept perfectly even to maintain display
characteristic and reliability. If this panel is subject to hard pressing, the following occurs :
(a) Uniform color (b) Orientation of liquid crystal becomes disorder (2) Please wipe out LCD panel surface with absorbent cotton or soft cloth in case of it being soiled. (3) Please wipe out drops of adhesive like saliva and water in LCD panel surface immediately.
They might damage to cause panel surface variation and color change.
(4) Do not apply any strong mechanical shock to the LCD panel.
2-2 OPERATING PRECAUTIONS
(1) Please be sure to unplug the power cord before remove the back-cover. (be sure the power is turn-off) (2) Please do not change variable resistance settings in MAIN-BOARD, they are adjusted to the most suitable
value. If they are changed, it might happen LUMINANCE does not satisfy the white balance spec.
(3) Please consider that LCD backlight takes longer time to become stable of radiation characteristic in low
temperature than in room temperature.
(4) Please pay attention to displaying the same pattern for very long-time. Image might stick on LCD.
2-3 STORAGE PRECAUTIONS
(1) When you store LCD for a long time, it is recommended to keep the temperature between 0 without
the exposure of sunlight and to keep the humidity less than 90% RH.
(2) Please do not leave the LCD in the environment of high humidity and high temperature such as 60
90%RH.
(3) Please do not leave the LCD in the environment of low temperature; below -15 .
2-4 HIGH VOLTAGE WARNING
The high voltage was only generated by INVERTER module, if carelessly contacted the transformer on this module, can cause a serious shock. (the lamp voltage after stable around 600V, with lamp current around 8mA, and the lamp starting voltage was around 1500V, at Ta=25 )
3. OPERATING INSTRUCTIONS
5
This procedure gives you instructions for installing and using the LM500 LCD monitor display.
1. Position the display on the desired operation and plug the power cord into a convenient AC outlet. Three-
wire power cord must be shielded and is provided as a safety precaution as it connects the chassis and cabinet to the electrical conduct ground. If the AC outlet in your location does not have provisions for the grounded type plug, the installer should attach the proper adapter to ensure a safe ground potential.
2. Connect the 15-pin color display shielded signal cable to your signal system device and lock both screws on the connector to ensure firm grounding. The connector information is as follow:
PIN NO.
DESCRIPTION
1. RED 9. 5V power from VGA-card
2. GREEN 10. GND
3. BLUE 11. SYNC. GND
4. GND 12. SDA
5. GND 13. HORIZ. SYNC
6. GND-R 14. VERT. SYNC
7. GND-G 15. SCL
8. GND-B
3. Apply power to the display by turning the power switch to the "ON" position and allow about thirty seconds for Panel warm-up. The Power-On indicator lights when the display is on.
4. With proper signals feed to the display, a pattern or data should appear on the screen, adjust the brightness and contrast to the most pleasing display, or press auto-key to get the best picture-quality.
5. This monitor has power saving function following the VESA DPMS. Be sure to connect the signal cable to the PC.
6. If your LM500 LCD monitor requires service, it must be returned with the power cord.
1
6
11 15
10
15 - Pin Color Display Signal Cable
PIN NO.
DESCRIPTION
4. ADJUSTMENT
4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS
1. Approximately 30 minutes should be allowed for warm up before proceeding.
2. Adjustments should be undertaken only on following function : contrast, brightness focus, clock, h-position,
v-position, red, green, blue since 6500 color & 7800 color &VR501 have been carefully preset at the factory.
4-2 ADJUSTMENT METHOD
Press MENU key to show OSD window or select function, and Left/Right key to switch the function controls or done the adjustment.
1. White-Balance, Luminance adjustment
Before started adjust white balance ,lets setting the Chroma-7120 MEM. Channel 3 to 7800 color and MEM. channel 4 to 6500 color, how to setting MEM.channel you can reference to chroma 7120 user guide or simple use “ SC” key and “ NEXT” key to modify xyY value and use “ID” key to modify your own description
Following is the step to do white-balance adjust
Press MENU key for 2 seconds at power on (replug power cord) will be in factory mode, and the OSD screen will located at left top of panel.
I. Bias (Low luminance) adjustment :
Press “ AUTO” key , and wait for message “ Pass” appear then set OSD contrast and brightness To maximal, RGB to “50” . then adjust VR501 until Y=210 cd/m2 cd/m2
II. Gain (High light) adjustment : a. adjust 7800 color-temperature
Set OSD contrast = 15, Brightness = -10 Switch the chroma-7120 to RGB-mode(with press “MODE” ) ,and selected the MEM.channel to Channel 03 The lcd-indicator will show x = 296 , y = 311 , Y = 135 cd/m2 Adjust RGB until R=100, G=100, B=100, and then switch the chroma-7120 to xyY mode (With press “MODE” ) Adjust contrast until Y= 150 cd/m2 Press osd-78 to save in 7800 factory mode
b. adjust 6500 color-temperature
Set OSD contrast = 15, Brightness = -10 Switch the chroma-7120 to RGB-mode(with press “MODE” ),and selected the MEM.channel to Channel 04 The lcd-indicator will show x = 313 , y = 329 , Y = 135 cd/m2 Adjust RGB until R=100, G=100, B=100, and then switch the chroma-7120 to xyY mode Adjust contrast until Y= 150 cd/m2 ,Press osd-65 to save in 6500 factory mode
Press POWER-key off-on to quit from factory mode ( in USER-mode, the OSD location was placed at middle of screen)
2. Clock adjustment Set the Chroma at pattern 63 (cross-talk pattern) or WIN98/95 shut-down mode (dot-pattern). Adjust until the vertical-shadow as wide as possible or no visible. This function is adjust the PLL divider of ADC to generate an accurate pixel clock Example : Hsyn = 31.5KHz Pixel freq. = 25.175MHz (from VESA spec)
The Divider number is (N) = (Pixel freq. x 1000)/Hsyn
From this formula, we get the Divider number, if we fill this number in ADC register (divider register), the PLL of ADC will generate a clock which have same period with above Pixel freq.(25.175MHz) the accuracy of this clock will effect the size of screen.(this clock was called PIXEL-CLOCK)
3. Focus adjustment Set the Chroma at pattern 63 (cross talk pattern) or WIN98/95 shut down mode (dot-pattern). Adjust the horizontal interference as less as possible This function is adjust the phase shift of PIXEL-CLOCK to acquire the right pixel data . If the relationship of pixel data and pixel clock not so match, we can see the horizontal interference at screen only at crosstalk pattern and dot pattern we can find this phenomena, other pattern the affect is very light
4. H/V-Position adjustment Set the Chroma at pattern 1 (crosshatch pattern) or WIN98/95 full-white pattern confirm above 2 functions (clock & focus) was done well, if that 2 functions failed, the H/V position will be failed too. Adjust the four edge until all four-edges are visible at the edge of screen.
5. MULTI-LANGUAGE function There have 5 language for selection, press “MENU” to selected and confirm , press “ LEFT” or “ RIGHT” to change the kind of language.
6. Reset function Clear each old status of auto-configuration and re-do auto-configuration ( for all mode) This function also recall 7800 color-temperature , if the monitor status was in “ Factory-mode” this reset function will clear Power-on counter too.
7. OSD-LOCK function Press Left & Right key during switching on the monitor, the access to the OSD is locked, user only has access to “ Contrast, Brightness, Auto-key “. If the operator pressed the Left & Right during switching on the monitor again , the OSD is unlocked.
8. View Power-on counter and reset the Power-on counter( if not necessary , not suggest to entry factory mode) The Power-on counter was used to record how long the backlight of panel already working, the backlight life time was guarantee minimal 25000 hours, the maintainer can check the record only in factory mode. Press MENU key for 2 seconds at power on (replug power cord) will be in factory mode, and the OSD screen will located at left top of panel but take cautions don’t press icon “78” & “65”, if you press 78/65 , your white-balance data will overlap with the new-one, and you must perform the white-balance process again. The result of counter was place at top of OSD, the maximal of record memory was 65000 hours, if exceed 65000 hours the counter will keep in 65000 hours until press “ RESET” at osd-menu in factory mode. The “ RESET” function in factory mode will execute following function :
1. clear the Power-on counter to zero hours
2. clear old auto-configuration status for all mode , so the monitor will automatically re-do auto-config
when change to next mode or power on-off
4-3 MAIN ADJUSTMENTS
Power Key : Press to turn on or off the monitor. Auto Key : Press to perform automatic calculated CLOCK, FOCUS, H/V POSITION, but no affect the color-
temperature Left/Right Key : press to perform select function or adjustment. MENU Key : press to show the OSD menu at the monitor or to confirm your function selection
5. CIRCUIT-DESCRIPTION
5-1 THE DIFFERENT between LG-Panel & Samsung-Panel & CPT-Panel & Hannstar- Panel in
ELECTRICAL Charateristic
LG-Panel 1. Two CCFL (Cold Cathode Fluorescent Tube)
2. Single Pixel, 6 bit color (262144 colors)
3. Panel Vdd = 3.3V (in JP202 select 3.3V)
Samsung-Panel 1. Four CCFL (Cold Cathode Fluorescent Tube)
2. Double Pixel, 6 bit color (262144 colors)
3. Panel Vdd = 5V (in JP201 select 5V)
Chung-Hwa Panel 1. Two CCFL (Cold Cathode Flourescent Tube)
2. Double Pixel, 8 bit color (16.7 Million colors)
3. Panel Vdd = 5V (in JP201 select 5V)
Hannstar Panel 1. Two CCFL (Cold Cathode Flourescent Tube)
2. Double Pixel, 6 bit color (262144 colors)
3. Panel Vdd = 3.3V (in JP202 select 3.3V)
5-2 SPECIAL FUNCTION with PRESS-KEY
press ENTER-key 2 seconds, at POWER-ON: set to FACTORY-mode, when we want to adjust white-balance
with rs232-port or view Power-on-timer. In this mode, OSD­screen will locate in left top of screen.
Press POWER-key off-on : CANCEL above function(quit from factory mode) and set to user-mode.
Press both Left & Right key and switching on-off key : Enable/ Disable OSD-LOCK function
OSD-INDEX EXPLANATION
1. CABLE NOT CONNECTED : Signal-cable not connected.
2. INPUT NOT SUPPORT :
a. INPUT frequency out of range : H > 62kHz, v > 75Hz or H < 28kHz, v < 55Hz b. INPUT frequency out of VESA-spec. (out of tolerance too far)
3. UNSUPPORT mode, try different Video-card Setting :
Input frequency out of tolerance, but still can catch-up by our system (if this message show, that means, this is new-user mode, AUTO-CONFIG will disable)
5-3 SIMPLE-INTRODUCTION about LM500 chipset
1. GMZAN1 (Genesis all-in-one solution for ADC, OSD, scalar and interpolation) :
USE for computer graphics images to convert analog RGB data to digital data for interpolation process, zooming, OSD font & overlay and generate drive-timing for LCD-PANEL,
2. M6759 (ALI- MCU, type 8052 series with 64k Rom-size and 512 byte ram) :
Use for calculate frequency, pixel-dot , detect change mode, rs232-communication, power-consumption control, OSD-index warning…etc.
3. 24LC21 (MicroChip IC) :
EePROM type, 1K ROM-SIZE, for saving DDC-CONTENT.
4. 24C04 (ATMEL IC) :
EePROM type, 4K ROM-SIZE, for saving AUTO-config data, White-balance data, and Power-key status and power on –counter data.
5. LM2569S( NS brand swintching regulator 12V to 5V with 3A load current) :
6. AIC 1084-33CM (AIC brand linear regulator 5V to 3.3V)
MODULE-TPYE COMPONENT :
1. ADAPTER : CONVERSION-module to convert AC 110V-240V to 12VDC, with 3.5 AMP
2. INVERTER : CONVERSION-module to convert DC 12V to High-Voltage around 1600V, with frequency
30K-50Khz, 7mA-9mA
**Use the PC Win 98/95 white pattern, with some icon on it, and Change the Resolution to 640x480 60 Hz / 31
Check INVERTER
-
module
OK, screen is normal
NG
NG
OK
R215= 50M Hz ? U302 pin 20= 20 M Hz ?
Check Power
-
Block
OK
NG, led in dark
KHz
**NOTICE : This system free-running freq. is 48 KHz / 60 Hz, so you better use another frequency to do
trouble shooting(ex:31kHz 60Hz) this trouble shooting is proceed with 640x480 @60Hz 31Khz
I. NO SCREEN APPEAR
OK, led in green-state But still no screen
Replace INVERTER to new-one, and Check the screen is normal ??
Check the FPC cable from CN201,CN202 was tight enough?, check the FPC of panel side too
Measured all power path if have had power?
C309, C310= 5V ?, C312=3.3V ?,U302 MCU pin 44=5V ?
Check crystal & oscillator if keep normal? (for MCU crystal 20MHz, for GMZAN1 oscillator 50MHz)
NG, led in orange
If LED in ORANGE-state, check your signal-cable
OK, still no screen But led is in Green
Re-plug power cord & make sure LED was in green-state? If led is in off-state(dark), press POWER-button to power-on the monitor
OK
6. Trouble-Shooting
NG, still in led ORANGE
GMZAN1-BLOCK
RE-assemble the FPC cable for both side (Cn201,202 & panel-side)
NG
Check Oscillator & crystal relative circuit Or replace
If LED in DARK-state, check the key­Button ,it could be stuck by mechanical
Check Keyboard circuit and check Mechanical key button, why be stuck?
White-balance
OK
NG, no transition
NG OK
C313, R313, D301 !!
OK
NG
Check
GMZAN1
-
BLOCK
Check
PERIPHERAL PANEL BLOCK
OK NG
END
OK
Check MCU reset circuit if normal ? U302 pin 10 = low to high when Power-on??
Check R229 reset for GMZAN1= high to Low twice when power-on ??
Measured PCLK(pin 44 from CN201) PVS,PHS (pin 40,38 from CN201) Is there has any transition? Pclk =31.25MHZ ,PVS=60.09Hz , PHS =50.4KHz ??(for input signal=31K 60 Hz)
OK,there have transition
NG
Check MCU relative reset circuit
Check GMZAN1 relative reset circuit R326,C314,D302,R229
Check input connector CN200 is loose?? Measure R212,R211= 31K & 60 hz?? Measure R200,R201,R202 (RGB input ) had signal??
Tighten CN200 Cable & check Relative Circuit
Screen normal & appear?
PERIPHERAL PANEL BLOCK
NG OK
OK
NG
OK
NG
NG
OK
Note: “Panel vdd “ and “backlight on-off ” can be direct control by :
GMZAN1 or MCU Some panel can direct control by GMZAN1 ,if the relative timing between panel-vdd and backlight on-off is short ( under 80 ms) , otherwise, will be control by MCU If J211 be connected, that means Panel-VDD control was by GMZAN1 ,otherwise by MCU( JP212) If J300 be connected, that means Backlight control was by GMZAN1 ,otherwise by MCU ( JP301)
BUT Hannstar panel & CPT panel still control by J211 & J300
Press on-off key once, make-sure Led is in Green state .check panel-VDD = 3.3V for HANNSTAR And 5V for CPT-panel , measured Panel-p (pin 4,5 from CN201)??
Check CN303 pin 3 = 5 V ? ( that is Backlight controller, On-state= 5V)
Check CN303 pin 4 4.6V ??(that VR is for Backlight luminance control)
FOR HANNSTAR-PANEL , there is the relative timing between input resolution to output timing for panel ( output timing from GMZAN1 chip) as follow :
RESOLUTION( from PC or chroma) PCLK(U200.44) PHS ( U200.74) PVS (U200.73) 640X480 @60 Hz 31.25MHz 50.4 KHz 60.09 Hz 640X480 @70 Hz 35.56MHz 55.93KHz 69.83 Hz 640X480 @72 Hz 36.76MHz 57.64KHz 71.94 Hz 640X480 @75 Hz 37.71MHz 60.12KHz 74.96 Hz 800X600 @60 Hz 28.65MHz 48.45KHz 60.39 Hz 800X600 @70 Hz 32.94MHz 56.05KHz 70.03 Hz 800X600 @72 Hz 34.25MHz 57.61KHz 72.04 Hz 800X600 @75 Hz 35.71MHz 60.10KHz 75.08 Hz 1024x768@60 Hz 28.57MHz 48.36KHz 60.09 Hz 1024x768@70 Hz 32.77MHz 56.05KHz 70.03 Hz 1024x768 @72 Hz 33.97MHz 57.60KHz 71.84 Hz 1024x768@75 Hz 35.41MHz 60.24KHz 74.96 Hz
TURN VR until CN303
Pin 4= 4.7 V??
NG,still no screen
If JP211 was connected, check PPWR relative circuit ( R400,R401,Q250,R223,Q200,R224,R225,C245,Q201 cold-solder or open loop)?? make-sure LED in Green-state, and PPWR (U200.pin 76)= high 3.3V If JP212 was connected, check Backlight_En relative circuit (R223,Q200,R224,R225,Q201,C245), make sure Backlight_En = low 0V ??
If JP300 was connected ,check Pbias relative circuit( R314,R309,R315, Q303,Q304,R311 cold-solder or open loop)?? make-sure LED in Green-state, and Pbias (U200.pin 75)= high 3.3V If JP301 was connected, check Panel-en relative circuit( R315,Q304 R311 cold-solder or open loop ??) make-sure LED in green-state And Panel-en= low 0V ??
If JP300 was connect, replace GMZAN1 Chip, if JP301 was connect , replace MCU
Replace PANEL, maybe the lamp or Driver board was bad
GMZAN1 BLOCK check
OK
State?
OK
NG
OK
OK
NG
Note : set the input signal ( PC or CHROMA) to 640x480 31k 60 hz
Check input connector CN200 is loose?? Measure R212,R211= 31K & 60 hz ? Measure R200,R201,R202 (RGB input ) had signal??
NG
Tighten CN200 cable & check relative circuit
Measure U201 oscillator 50MHz is normal?? (you can measure R215)
NG
Set chroma or PC to power-save mode Check LED in ORANGE state ?
Set chroma or PC to 640x480 @60Hz or Other frequency, check LED in GREEN
Measured PCLK(pin 44 from CN201) PVS,PHS (pin 40,38 from CN201) Is there has any transition? Pclk=31.25MHZ ,PVS=60.09Hz ,PHS=50. 4KHz ??(for input signal=31K 60 Hz)
Re-plug power-cord, and check again Previous function, if still no screen, then Replace GMZAN1 chip
OK, partial of Gmzan1 is good
NG
Replace U201 oscillator 50 MHz
Replace GMZAN1
Check Peripheral-panel block
OK
OK
OK
NG
NG
OK
NG
NG
R300,R301 cold solder
OK
OK, no keep transition
KEYBOARD BLOCK check
Check U302 MCU pin 43,42,41,40,39 at High state(5V)? without press any key
Press power key and check U302 pin 43 = low (0V) ?
Check U302 pin 38 (LED green) will have transition from hi to low or low to hi when we press the power key??
Check U302 pin 20= 20MHz ? and pin 44 (VDD)=5V ? and pin 10 (reset)=0V ? at normal condition
Without press key and change mode, Check U302 pin 16,17(sda,scl)= hi 5V ? or keep transition ?
Replace U302 MCU
NG, MCU no response
NG
Keep transition, that means eeprom no response
Mechanical was stuck, Check !
Replace Tact-switch SW105 at keyboard if still no work replace U302 MCU at main-board and check MCU relative reset circuit, and crystal
If still no Led green indicator, check Q102, R106 & LED at keyboard !! cold solder or bad
If one of this item was NG, check the relative circuit
Check U300 eeprom 24LC04 relative circuit, check U300 pin 7 = low?
Check JP202 is connect ?
Check U300 pin 8 (vdd)= 5V, and check
Replace eeprom
OK
OK
pulse
NG
OK, unstable wave
POWER-BLOCK check **Note : the waving of U304 pin 2 can determined the power situation
1. stable rectangle wave with equal duty, freq around 150K-158KHz
that means all power of this interface board is in normal operation ,all status of 5V & 3.3V is normal working
2. unstable rectangle wave without same duty, that means ABNORMAL operation was happened
check 3.3V or 5V ,short-circuit or bad component
3. rectangle wave with large spike & harmonic pulse on front side of rectangle wave, that means all 3.3v is
no load, Gmzan1 was shut-down, and only MCU still working ,the monitor is in power saving state
Measure input power at U304 LM2596 pin 1= 12V ?
NG
Check ADAPTER and connector if loose?
Check U304 pin 2 is a stable rectangle wave? Around 150k-158kHz stable rectangle wave with equal duty without any spike or harmonic pulse?
The interface board power is good
Check U304 pin 2 is a unstable rectangle wave ?
Check all 3.3V & 5V power, there is short circuit or bad component was happened
NG,with harmonic
The interface board is in power­saving state, press power key to wake up & check your signal input
END
OK OK
NG, interferences still exist
NG
taipei)
NO, all mode
II.ALL SCREEN HAS INTERFERENCES OR NOISE, CAN’T BE FIXED BY AUTO KEY
** NOTE: There is so many kind of interferences, 1). One is cause by some VGA-CARD that not meet VESA spec or
power grounding too bad that influence our circuit
2).other is cause by external interferences, move the monitor far from electronic equipment.( rarely happened)
Use DOT-pattern, or win98/99 shut-down mode pattern, press “AUTO” key, was the interferences disappear ??
Adjust “FOCUS” step by step, until the horizontal interferences disappear
Does your signal-cable have an additional cable for extension ??
Does your noise only exist in one mode only? (ex: only at 1024x768 @ 75 Hz, other is normal)
That was cause by you VGA-CARD setting, your VGA card timing backporch/frontporch exceed vesa timing too far, for some new AGP-VGA-CARD such situation always happened So in your control-panel icon ,select monitor ,setting ,
advance ,screen-adjust,at Size icon, increase step by step slowly, press “”AUTO”
key every step you increase the SIZE . repeat the procedure( increase/decrease SIZE one-step and press AUTO) until the interferences disappear, press “APPLY” to save in your VGA
Yes, has extension
NO additional extension cable
END
Put away the additional cable May be the additional cable grounding is not quite well
Change the Signal-cable to new-one or Try other brand VGA-CARD (make sure just only that brand VGA­CARD has this problem ,contact RD-
each pin
or Pure
array LP201~LP206, both side of
Yes
No
Yes
No
III. DOS MODE has jitter
NOTE :the rule of doing AUTO-CONFIGURATION : must be a full-size screen, if the screen not full , the auto­configuration will fail. So in dos mode ,just set your “CLOCK” in OSD-MENU to zero or use some full screen edit file (ex: PE2, HE) and press “AUTO”
I? . THERE WAS SNOW PHENOMENA or BRIGHT NOISE ON THE SCREEN
When use pattern 32 Gray-scale / or 16 Gray scale, there is a snow phenomena on the screen (like a noise spread inside) that means some output bit to panel was bad, may be cause by FPC loose, or bead-array cold-solder There were some panel (ex :LG),also have this phenomena too, the noise will reduce or increase depend on the contrast/brightness value, this kind of problem was cause by Panel-driver-board it self, we can’t fix it ,the only way to do was find the best-point of brightness/contrast, that the noise is more light
Use following pattern :
1. pure-white 2. Pure Red 3. Pure Green
4. Pure Blue 5. Pure White 6. Character repeat measure GMZAN1 (U200) all output pins must have some transition pulse, but notice
1. For LG panel and HANNSTAR panel , only 6 bit has output, (PD0~ PD17 , PD36 ~ PD41) the
corresponding beads was LP201 ~ LP206
2. For Chung-hwa panel or other’s 8 bit panel, all output are available (PD0-PD47 ), the corresponding beads
was LP201-LP212
Ex : HANNSTAR Panel 6 bits
With 16 gray-scale, adjust contrast /brightness slowly
and observe the noise was increase or reduce or no-
influence at all ?especially at low luminance scale
That was the panel noise, no solution, Just set the brightness to the best point
which noise is more light
Set pattern to full-white, adjust contrast to 50
Check U200 GMZAN1 Pin 71,70,69,68,67,66 ( Red, Pd0 -Pd5) Pin 64,63,62,57,56,55 (Green ,Pd6-Pd11) Pin 54,53,52,51,50,48 (Blue, Pd12- Pd17) There must be have some transition pulse in
All pins has transition
Denotes U200 GMZAN1 work well
Set pattern to Pure-Red or Pure Green Blue repeat above-step until all pins had transition
Some pins no transition
Check bead­bead must have the same transition signal
All 5 pattern already change yet??
Check FPC cable for loose, or FPC bad, if FPC bad, replace it
Replace the correpondens beads array and check the capacitor arrays too
If all pattern already change but still had some pins no transition. That means GMZAN1 (U200) fail, replace U200
V. THE PANEL LUMINANCE WAS DOWN
NG NG
OK OK
±
±
GMZAN1
The gmZAN1device utilizes Genesis’ patented third-generation Advanced Image Magnification technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost effective SVGA/XGA LCD monitor solution. As a pin-compatible replacement for the gmB120, the gmZAN1 incorporates all of the gmB120 features plus many enhanced features; including 10-bit gamma correction, Adaptive Contrast Enhancement (ACE) filtering, Sync On Green (SOG), and an enhanced OSD.
1.1 Features
? Fully integrated 135MHz 8-bit triple-ADC, PLL, and pre-amplifier ? GmZ2 scaling algorithm featuring new Adaptive Contrast Enhancement (ACE) ? On-chip programmable OSD engine ? Integrated PLLs ? 10-bit programmable gamma correction ? Host interface with 1 or 4 data bits ? Pin-compatible with gmB120
Integrated Analog Front End
? Integrated 8-bit triple ADC ? Up to 135MHz sampling rates ? No additional components needed ? All color depths up to 24-bits/pixel are supported
High-Quality Advanced Scaling
? Fully programmable zoom ? Independent horizontal / vertical zoom ? Enhanced and adaptive scaling algorithm for optimal image quality ? Recovery Mode / Native Mode
Input Format
? Analog RGB up to XGA 85Hz ? Support for Sync On Green (SOG) ? Support for composite sync modes
Output Format
? Support for 8 or 6-bit panels (with high quality dithering) ? One or two pixel output format
Built In High-Speed Clock Generator
? Fully programmable timing parameters ? On-chip PLLs generate clocks for the on-chip ADC and pixel clock from a single reference oscillator
Auto-Configuration / Auto-Detection
? Phase and image positioning ? Input format detection
Operation Modes
? Bypass mode with no filtering ? Multiple zoom modes:
? With filtering ? With adaptive (ACE) filtering
Integrated On-Screen Display
? On-chip character RAM and ROM for better customization ? External OSD supported for greater flexibility ? Supports both landscape and portrait fonts ? Many other font capabilities including: blinking, overlay and transparency
1.3 Pin Description
Digital power for ADC encoding logic. Must be bypassed with 0.1uF capacitor to
igital
Digital power for ADC clocking circuit. Must by passed with 0.1uF capacitor to
Digital GND for ADC clocking circuit. Must be directly connected to the digital
Dedicated pin for substrate guard ring that protects the ADC reference system.
Analog ground for ADC analog blocks that are shared by all three channels.
gap reference, master biasing and full scale adjust. Must be directly
Analog power for ADC analog blocks that are shared by all three channels.
adjust. Must be
Analog ground for the blue channel. Must be directly connected to the analog
Analog power for the blue channel. Must be bypassed with 0.1uF capacitor to pin
nel. Must be directly connected to the analog
Analog power for the green channel. Must be bypassed with 0.1uF capacitor to
Analog ground for the red channel. Must be directly connected to the analog
Analog power for the red channel. Must be bypassed with 0.1uF capacitor to pin
Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
Table 1 : Analog-to-Digital Converter
PIN #
77 ADC_VDD2
78 ADC_GND2
79 ADC_VDD1
80 ADC_GND1
81 SUB_GNDA
82 ADC_GNDA
84 ADC_VDDA
83 Reserved 85 ADC_BGNDA
88 ADC_BVDDA
86 BLUE- I 87 BLUE+ I 89 ADC_GGNDA
92 ADC_GVDDA
90 GREEN- I 91 GREEN+ I 93 ADC_RGNDA
96 ADC_RVDDA
94 RED- I 95 RED+ I
Name I/O Description
pin 78 (ADC_GND2) Digital GND for ADC encoding logic. Must be directly connected to the d system ground plane.
pin 80 (ACD_GND1).
system ground plane.
Must be directly connected to the analog system ground plane.
Includes band connected to analog system ground plane.
Includes bandgap reference, master biasing and full scale bypassed with 0.1uF capacitor to pin 82 (ADC_GNDA). For internal testing purpose only. Do not connect.
system ground plane.
85(BGNDA). Negative analog input for the Blue channel.
Positive analog input for the Blue channel. Analog ground for the green chan
system ground plane.
pin 89 (ADC_GGNDA). Negative analog input for the Green channel.
Positive analog input for the Green channel.
system ground plane.
93 (ADC_RGNDA). Negative analog input for the Red channel.
Positive analog input for the Red channel.
Table 2 : Host Interface (HIF) / External On-Screen Display
Displays data from external OSD
When externally pulled down (sampled at reset ) the host
interface is configured for 4 bits wide. In this configuration, MFB9:7 are used as
When externally pulled down (sampled at reset ) the chip
uses an external crystal resonator across pins 141 and 142, instead of an
PIN #
98 HFS I
103 HCLK I
99 HDATA I/O 100 RESETn I 101 IRQ O 115 OSD-HREF O 116 OSD-VREF O 117 OSD-Clk O 118 OSD-Data0 I 119 OSD-Data1 I 120 OSD-Data2 I 121 OSD-Data3 I 122 OSD-FSW I
123 MFB11 I/O 124 MFB10 I/O 102 MFB9 I/O
104 MFB8 I/O
105 MFB7 I/O
106 MFB6 I/O
Name I/O Description
Host Frame Sync. Frames the packet on the serial channel. Clock signal input for the 3-wire serial communication. Data signal for the 3-wire serial communication. Resets the gmZAN1 chip to a known state when low. Interrupt request output. HSYNC output for an external OSD controller chip. VSYNC output for an external OSD controller chip. Clock output for an external OSD controller chip. Data input 0 from an external OSD controller chip. Data input 1 from an external OSD controller chip. Data input 2 from an external OSD controller chip. Data input 3 from an external OSD controller chip.
External OSD window display enable. controller when high.
Multi-Function Bus 11. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 10. One of twelve multi-function signals MFB[11:0].
Multi-Function Bus 9. One of twelve multi-function signals MFB[11:0]. Also used as HDATA3 in a 4-bit host interface configuration. Multi-Function Bus 8. One of twelve multi-function signals MFB[11:0]. Also used as HDATA2 in a 4-bit host interface configuration. Multi-Function Bus 7. One of twelve multi-function signals MFB[11:0]. Also used as HDATA1 in a 4-bit host interface configuration. Multi-Function Bus 6. One of twelve multi-function signals MFB[11:0]. Internally pulled up.
HDATA 3:1.
107 MFB5 I/O
109 MFB4 I/O 110 MFB3 I/O 111 FMB2 I/O 112 MFB1 I/O 113 MFB0 I/O
Multi-Function Bus 5 One of twelve multi-function signals MFB[11:0]. Internally pulled up.
oscillator. Multi-Function Bus 4. One of twelve multi-function signals MFB[11:0].
Multi-Function Bus 3. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 2. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 1. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 0. One of twelve multi-function signals MFB[11:0].
Digital power for Destination DDS (direct digital synthesizer). Must be bypassed
Analog ground for Destination DDS DAC. Must be directly connected to the
Analog power for Destination DDS DAC. Must be bypassed with a 0.1uF
Analog power for the Destination DDS PLL. Must be bypassed with a 0.1uF
ted to the
Dedicated pin for the substrate guard ring that protects the Destination DDS.
at protects the Source DDS. Must be
Analog ground for the Source DDS PLL. Must be directly connected to the
Analog power for the Source DDS DAC. Must be bypassed with a 0.1uF
Analog power for the Source DDS DAC. Must be by passed with a 0.1uF
g power for the Source DDS DAC. Must be directly connected to the
Digital power for the Source DDS. Must be bypassed with a 0.1uF capacitor to
If using an external oscillator, leave this pin floating. If using an external crystal,
d with a 0.1uF
Analog ground for the Reference DDS PLL. Must be directly connected to the
r the substrate guard ring that protects the Reference DDS. Must
PIN #
125 DVDD
127 DAC_DGNDA
128 DAC_DVDDA
129 PLL_DVDDA
130 Reserved
131 PLL_DGNDA
132 SUB_DGNDA
133 SUB_SGNDA
134 PLL_SGNDA
135 Reserved
136 PLL_SVDDA
Name I/O Description
Table 3 : Clock Recovery / Time Base Conversion
with a 0.1uF capacitor to digital ground plane.
analog system ground plane.
capacitor to pin 127 (DAC_DGNDA).
capacitor to pin 131 (PLL_DGNDA). For testing purposes only. Do not connect. Analog ground for the Destination DDS PLL. Must be directly connec
analog system ground plane.
Must be directly connected to the analog system ground plane. Dedicated pin for the substrate guard ring th directly connected to the analog system ground plane.
analog system ground. For testing purposes only. Do not connect.
capacitor to pin 134 (PLL_SGNDA)
137 DAC_SVDDA
138 DAC_SGNDA
139 SVDD
141 TCLK I Reference clock(TCLK) input from the 50 MHz crystal oscillator
142 XTAL O
143 PLL_RVDDA Analog power for the Reference DDS PLL. Must be bypasse
144 PLL_RGNDA
145 Reserved For testing purposes only. Do not connect.
146 SUB_RGNDA Dedicated pin fo
148 VSYNC I CRT Vsync input. TTL Schmitt trigger input.
149 SYN_VDD Digital power for CRT Sync input.
150 HSYNC/CSYNC
capacitor to pin 138 (DAC_SGNDA) Analo analog system ground.
digital ground plane.
connect crystal between TCLK(141) and XTAL(142). See MFB5(pin 107).
capacitor to pin 144(PLL_RGNDA)
analog system ground plane.
be directly connected to the analog system ground plane.
I CRT Hsync or CRT composite sync input. TTL Schmitt trigger input.
Table 4. TFT Panel Interface
PIN # Name I/O
6 PD47 O OB1 - - ­7 PD46 O OB0 - - -
9 PD45 O OG1 - - ­10 PD44 O OG0 - - ­13 PD43 O OR1 - - ­14 PD42 O OR0 - - ­15 PD41 O EB1 - B1 ­16 PD40 O EB0 - B0 ­17 PD39 O EG1 - G1 ­19 PD38 O EG0 - G0 ­20 PD37 O ER1 - R1 ­22 PD36 O ER0 - R0 ­23 PD35 O OB7 OB5 - ­24 PD34 O OB6 OB4 - ­25 PD33 O OB5 OB3 - ­26 PD32 O OB4 OB2 - ­27 PD31 O OB3 OB1 - ­28 PD30 O OB2 OB0 - ­29 PD29 O OG7 OG5 - ­31 PD28 O OG6 OG4 - ­32 PD27 O OG5 OG3 - ­34 PD26 O OG4 OG2 - ­35 PD25 O OG3 OG1 - ­36 PD24 O OG2 OG0 - ­37 PD23 O OR7 OR5 - ­38 PD22 O OR6 OR4 - ­39 PD21 O OR5 OR3 - ­42 PD20 O OR4 OR2 - ­46 PD19 O OR3 OR1 - ­47 PD18 O OR2 OR0 - ­48 PD17 O EB7 EB5 B7 B5 50 PD16 O EB6 EB4 B6 B4 51 PD15 O EB5 EB3 B5 B3 52 PD14 O EB4 EB2 B4 B2 53 PD13 O EB3 EB1 B3 B1 54 PD12 O EB2 EB0 B2 B0 55 PD11 O EG7 EG5 G7 G5 56 PD10 O EG6 EG4 G6 G4 57 PD9 O EG5 EG3 G5 G3 62 PD8 O EG4 EG2 G4 G2
2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk
8bit 6-bit 8-bit 6-bit TFT
Description
Enable automatic PCB assembly test. When this input is pulled high, the
down resistor
PIN # Name I/O
63 PD7 O EG3 EG1 G3 G1 64 PD6 O EG2 EG0 G2 G0 66 PD5 O ER7 EG5 R7 R5 67 PD4 O ER6 ER4 R6 R4 68 PD3 O ER5 ER3 R5 R3 69 PD2 O ER4 ER2 R4 R2 70 PD1 O ER3 ER1 R3 R1 71 PD0 O EG2 ER0 R2 R0 43 PdispE O This output provides a panel display enable signal that is active when flat panel
74 PHS O This output provides the panel line clock signal. 73 PVS O This output provides the frame start signal. 44 PCLKA O This output is used to drive the flat panel shift clock. 45 PCLKB O Same as PCLKA above.
75 Pbias O This output is used to turn on/off the panel bias power or controls backlight. 76 Ppwr O This output is used to control the power to a flat panel.
2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk
8bit 6-bit 8-bit 6-bit TFT
data is valid.
The polarity and the phase of this signal are independently programmable.
Description
Table 5. Test Pins
PIN #
3 PSCAN I
155 SCAN_IN1 I 157 SCAN_IN2 I 159 SCAN_OUT1 O 160 SCAN_OUT2 O 153 Reserved 154 Reserved
Name I/O Description
automatic PCB assembly test mode is entered. An internal pull­drives this input low for normal operation.
Scan input 1 used for automatic PCB assembly tesing. Scan input 2 used for automatic PCB assembly tesing. Scan output 1 used for automatic PCB assembly tesing. Scan output 2 used for automatic PCB assembly tesing.
Table 6. VDD / VSS for Core Circuitry, Host Interface, and Panel/Memory Interface
PIN # Description
65, 40, 33, 12
149, 108, 58, 21, 11
158, 151, 140, 126, 114, 72, 61, 49, 41, 30, 18, 8, 1
PVDD4~PVDD1 for panel / memory interface. Connect to +3.3V. Must be the same voltage as the CVDD’s SRVDD2-1, CVDD4, CVDD2-1 for core circuitry. Connect to +3.3V. Must be the same voltage as the PVDD’s.
Digital grounds for core circuiry and panel / memory interface.
1.4 System-level Block Diagram
ADC_VDD
gmZAN1 Core
CVDD
RVDDA
Video Connector
ADC_GND
L1 L2
R1RR1RR1
R
Red Blue Green
R1RR1 R
RVDDA
Hsync Vsync
C1 C
C2 C
ADC
ADC
To Clock Generator
Clock Generator
TCLK
RGNDA
OSC
SVDDA
SGNDA
DVDDA
Even Data
24
PCLKA
24
Power
Power Switching
Switching Module
Module
DGNDA
PHS PVS PDISPE
Odd Data
TFT Panel
+12V
+5/3.3V
On-Screen Display Controller
MPU with EPROM
MFBs
RESETn
R+,G+,B+
4
OSD-FSW OSD-FSW OSD-CLK
OSD-HREF OSD-VREF
IRQ HES HCLK
HDATA
12
Host Interface
Pbias
Panel Interface
Pbias
CVSS
Figure 2. Typical Stand-alone Configuration
1.5 Operating Modes
The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows: ? The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by
SCLK DDS (direct digital synthesis) and the PLL.
? The Panel Clock is the timing clock for panel data at the single pixel per clock rate. The actual PCLK to the
panel may be one-half of this frequency for double-pixel panel data format. When its frequency is different from that of source clock, the panel clock is generated by Destination Clock (or DCLK) DDS/PLL.
There are six display modes: Native, Slow DCLK, Zoom, Downscaling, Destination Stand Alone, and Source Stand Alone. Each mode is unique in terms of:
? Input video resolution vs. panel resolution ? Source Clock frequency / Panel Clock frequency ratio ? Source Hsync frequency / Panel Hsync frequenc ratio ? Data source (analog RGB, panel background color, on-chip pattern generator
1.5.1 Native
Panel Clock frequency = Source Clock frequency Panel Hsync frequency = Input Hsync frequency Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is the same as the panel resolution and the input data clock frequency is within the panel clock frequency specification of the panel being used.
1.5.2 Slow DCLK
Panel Clock frequency < Source Clock frequency Panel Hsync frequency = Input Hsync frequency Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is the same as the panel resolution, but the input data clock frequency is exceeds the panel clock frequency specification of the panel being used. The panel clock is scaled to the Source Clock, and the internal data buffers are used to spread out the timing of the input data by making use of the large CRT blanking time to extends the panel horizontal display time.
1.5.3 Zoom
Panel Clock frequency > Source Clock frequency Panel Hsync frequency > Input Hsync frequency Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is less than the panel resolution. The input data clock is then locked to the pnael clock, which is at a higher frequency. The input data is zoomed to the panel resolution.
1.5.4 Downscaling
Panel Clock frequency < Source Clock frequency Panel Hsync frequency < Input Hsync frequency Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution. The input clock is operated at a frequency less than that of the input pixel rate(under-sampled horizontally) and the scaling filter is used to drop input lines. In this mode, zoom scaling must be disabled
1.5.5 Destination Stand Alone
Panel Clock = DCLK in open loop (not locked) Panel Hsync frequency = DCLK frequency / (Destination Htotal register value) Panel Vsync frequency = DCLK frequency / (Dest. Htotal register value * Dest. Vtotal register value)
This mode is used when the input is changing or not available. The OSD may still be used as in all other display modes and stable panel timing signals are produced. This mode may be automatically set when the gmZAN1 detects input timing changes that could cause out- of-spec operation of the panel.
1.5.6 Source Stand Alone
Panel Clock = DCLK in open loop (not locked to input Hsync) Panel Hsync frequency = SCLK frequency / (Source Htotal register value) Panel Vsync frequency = SCLK frequency / (Source Htotal register value *Source Vtotal register value)
This mode is used to display the pattern generator data. This mode may be useful for testing an LCD panel on the manufacturing line (color temperature calibration, etc.).
2. FUNCTIONAL DESCRIPTION
Pixel
Reference
Figure 3 below shows the main functional blocks inside the gmZAN1
2.1 Overall Architecture
Figure 3. Block Diagram for gmZAN1
On-Screen Display Control
Analog RGB
Triple ADC
Source Timing Measurement / Generation
Scaling Engine
Gamma Control (CLUT) + Dither
Panel Timing Control
MCU
Host Interface
Clock Recovery
Clock Generator
Clock
2.2 Clock Recovery Circuit
The gmZAN1 has a built-in clock recovery circuit. This circuit consists of a digital clock synthesizer and an analog PLL. The clock recovery circuit generates the clock used to sample analog RGB data (SCLK or source clock). This circuit is locked to the HSUNC of the incoming video signal. The RCLK generated from the TCLK input is used as a reference clock.
The clock recovery circuit adjusts the SCLK period so that the feedback pulse generated every SCLK period multiplied by the Source Horizontal Total value (as programmed into the registers) locks to the rising edge of the Hsync input. Even though the initial SCLK frequency and the final SCLK frequency are as far apart as 60MHz , locking can be achieved in less than 1ms across the operation voltage/temperature range.
Panel
The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital
Output
synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range.
The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input. DCLK frequency divided by N is locked to SCLK frequency divided by M. The value M and N are calculated and programmed in the register by firmware. The value M should be close to the Source Htotal value.
Figure 4. Clock Recovery Circuit
Hsync
Sample
Phase
Delay
DDS Digital
Clock
Synthesis
Course
Adjust
DDS Output
Analog
PLL & VCO
VCO
Clock
Divider
÷ n
Fine
Adjust
PLL
Divider
Prescaler
÷ 2 (or 1)
Source
Horizontal
Total Divider
TCLK
Analog
PLL & VCO
Post Scale
÷ 2 (or 1)
PLL Divider
PLL Divider
SCLK
RCLK
The table below summarizes the characteristics of the clock recovery circuit.
Table 7. Clock Recovery Characteristics
Minimum Typical Maximum
SCLK Frequency 10MHz 135 MHz Sampling Phase Adjustment
0.5 ns/step, 64 steps
Patented digital clock synthesis technology makes the gmZAN1 clock circuits very immune to temperature/voltage drift.
2.2.1 Sampling Phase Adjustment
The ADC sampling phase is adjusted by delaying the Hsync input at the programmable delay cell inside the gmZAN1. The delay value can be adjusted in 64 steps, 0.5 ns/step. The accuracy of the sampling phase is checked by the gmZAN1 and the “score” can be read in a register. This feature will enable accurate auto-adjustment of the ADC sampling phase.
2.2.2 Source Timing Generator
The STG module defines a capture window and sends the input data to the data path block. The figure below shows how the window is defined. For the horizontal direction, it is defined in SCLKs (equivalent to a pixel count). For the vertical direction, it is defined in lines. All the parameters in the figure that begin with “Source” are programmed into the gmZAN1 registers. Note that the vertical total is solely determined by the input. The reference point is as follows:
? The first pixel of a line: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low
to high.
? The first line of a frame: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low
to high.
The gmZAN1 also supports the use of analog composite sync and digital sync signals as described in Section 2.3.2
Figure 5. Capture Window
Reference Point
Source Hstart
Source
Vstart
Source Height
Source Vertical Total (lines)
Source Horizontal Total (pixels)
Source Width
Capture Window
2.3 Analog-to-Digital Converter
2.3.1 Pin Connection
The RGB signals are to be connected to the gmZAN1 chip as described in Table 8 and Table 9.
Table 8. Pin Connection for RGB Input with Hsync/Vsync
GmZAN1 Pin Name (Pin Number) CRT Signal Name
Red+(#95) Red Red- (#94) N/A (Tie to Analog GND for Red on the board) Green+(#91) Green Green- (#90) N/A (Tie to Analog GND for Green on the board) Blue+(#87) Blue Blue- (#86) N/A (Tie to Analog GND for Blue on the board) HSYNC/CS (#150) Horizontal Sync VSYNC (#148) Vertical Sync
Table 9. Pin Connection for RGB Input with Composite Sync
GmZAN1 Pin Name (Pin Number) CRT Signal Name
Red+(#95) Red Red- (#94) N/A (Tie to Analog GND for Red on the board) Green+(#91) Green
When using Sync-On-Green this signal also carries the sync pulse. Green- (#90) N/A (Tie to Analog GND for Green on the board) Blue+(#87) Blue Blue- (#86) N/A (Tie to Analog GND for Blue on the board) HSYNC/CS (#150) Digital composite sync. Not applicable for Sync-On-Green
The gmZAN1 chip has three ADC’s (analog-to-digital converters), one for each color (red, green, and blue). Table 10 summarizes the characteristics of the ADC.
Table 10. ADC Characteristics
MIN TYP MAX NOTE
RGB Track & Hold Amplifiers
Band Width 160MHz Settling Time to 1/2% 8.5ns Full Scale Input = 0.75V, BW=160MHz(*) Full Scale Adjust Range @ R,G,B Inputs 0.45V 0.95V Full Scale Adjust Sensitivity +/-1 LSB Zero Scale Adjust Range For a larger DC offset from an external
Zero Scale Adjust Sensitivity +/-1 LSB
ADC+RGB Track & Hold Amplifiers
Sampling Frequency (fs) 20MHz 110MHz DNL +/- 0.9LSB fs = 80 MHz INL +/- 1.5LSB Channel to Channel Matching +/- 0.5LSB Effective Number of Bits (ENOB) 7 Bits fin = 1MHz, fs=80 MHz Vin= -1db below
Power Dissipation 400mW fs=110 MHz, Vdd=3.3V Shut Down Current 100uA (*) Guaranteed by design (**) Independent of full scale R,G,B input
The gmZAN1 ADC has a built-in clamp circuit. By inserting series capacitors (about 10 nF) the DC offset of an external video source can be removed. The clamp pulse position and width are programmable.
Measured @ ADC Output (**)
video source, the AC coupling feature is used to remove the offset.
Measured @ ADC Output
fs = 80 MHz
full scale=0.75V
2.3.2 Sync. Signal Support
period delta to the previous line / frame exceeds the
The gmZAN1 chip supports digital separate sync (Hsync/Vsync), digital composite sync, and analog composite sync (also known as sync-on-green). All sync types are supported without external sync separation / extraction circuits.
Digital Composite Sync
The types of digital composite sync inputs supported are:
? OR/AND type: No Csync pulses toggling during the vertical sync period ? XOR type: Csync polarity changes during the vertical sync period
The gmZan1 provides enough sync status information for the firmware to detect the digital composite sync type.
Sync-On-Green (Analog Composite Sync)
The voltage level of the sync tip during the vertical sync period can be either –0.3V or 0V
2.3.3 Display Mode Support
A mode calculation utility (MODECALC.EXE) provided by Genesis Microchip may be run before compilation of the firmware to determine which input modes can be supported. Refer to firmware documents for more details.
2.4 Input Timing Measurement
As described in section 2.2.2 above, input data is sent from the analog-to-digital converter to the source timing generator (STG) block. The STG block defines a capture window (Figure5).
The input timing measurement block consists of the source timing measurement (STM) block and interrupt request (IRQ) controller. Input timing parameters are measured by the STM block and stored in registers. Some input conditions will generate an IRQ to an external micro-controller. The IRQ generating conditions are programmable.
2.4.1 Source Timing Measurement
When it receives the active CRT signal (R,G,B and Sync signals) the Source Timing Measurement unit begins measuring the horizontal and vertical timing of the incoming signal using the sync signals and TCLKi as a reference. Horizontal measurement occurs by measuring a minimum and a maximum value for each parameter to account for TCLKi sampling granularity. The measured value is updated every line. Vertical parameters are measured in terms of horizontal lines. The trailing edge of the Hsync input is used to check the polarity of the Vsync input. The table below lists all the parameters that may be read in the source timing measurement (STM) registers of the gmZAN1.
Table 11. Input Timing Parameters Measured by the STM Block
Parameter Unit Updated at:
HSYNC Missing N/A Every 4096 TCLKs and every 80ms (2-bits) VSYNC Missing N/A Every 80ms HSYNC/VSYNC Timing Change N/A When the horizontal period delta or the vertical
HSYNC Polarity Positive/Negative After register read VSYNC Polarity Positive/Negative Every frame Horizontal Period Min/Max TCLKs and SCLKs After register read HSYNC High Period Min/Max TCLKs After register read Vertical Period Lines Every frame VSYNC High Period Lines Every frame Horizontal Display Start SCLKs Every frame Horizontal Display End SCLKs Every frame Vertical Display Start Lines Every frame Vertical Display End Lines Every frame Interlaced Input Detect N/A Every frame CRC Data/Line Data N/A Every frame CSYNC Detect N/A Every 80ms
threshold value (programmable).
The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data above a
Panel
S
S
S
8 10
8 or 6
programmed threshold. The reference point of the STM block is the same as that of the source timing generator (STG) block:
? The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high. ? The first line: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high.
The CRC data and the line data are used to detect a test pattern image sent to the gmZAN1 input port.
2.4.2 IRQ Controller
Some input timing conditions can cause the gmZAN1 chip to generate an IRQ. The IRQ-generating conditions are programmable, as given in the following table.
Table 12. IRQ-Generation Conditions
IRQ Event Remark
Timing Event One of the three events:
? Leading edge of Vsync input, ? Panel line count (the line count is programmable), ? Every 10ms
Only one event may be selected at a time.
Timing Change Any of the following timing changes:
? Sync loss, ? DDS tracking error beyond threshold, ? Horizontal/vertical timing change beyond threshold
Threshold values are programmable.
Reading the IRQ status flags will not affect the STM registers. Note that if a new IRQ event occurs while the IRQ status register is being read, the IRQ signal will become inactive for minimum of one TCLK period and then get re-activated. The polarity of the IRQ signal is programmable.
2.5 Data Path
The data path block of gmZAN1 is shown in Figure 6.
Figure 6. gmZAN1 Data Path
Sampled Data
(or from
pattern
generator
8
Scaling
Filter
Gamma
Table
RGB
Offset
Data
Dither
Background
Color
Internal
OSD
External
OSD
8 or 6
1
0
1
0
1
0
Panel Data
2.5.1 Scaling Filter
The gmZAN1 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc. and provides high quality scaling of real time video and graphics images. This is Genesis’ third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications.
2.5.2 Gamma Table
The gamma table is used to adjust the RGB data for the individual display characteristics of the TFT panel. The overall gamma of the display may be set, as well as separate corrections for each of the three display channels. In addition, the gamma table may be used for contrast, brightness, and white balance (temperature) adjustments. The lookup table has an 8-bit input (256 different RGB entries) and produces a 10-bit output.
2.5.3 RGB Offset
The RGB offsets provide a simple shift (positive or negative) for each of the three color channels. This may be used as a simple brightness adjustment within a limited range. The data is clamped to zero for negative offsets, and clamped to FFh for positive offsets. This adjustment is much faster than recalculating the gamma table, and could be used with the OSD user controller to provide a quick brightness adjust. An offset range of plus 127*4 to minus 127*4 is available.
2.5.4 Panel Data Dither
For TFT panels that have fewer than eight bits for each R,G,B input, the gmZAN1 provides ordered and random dithering patterns to help smoothly shade colors on 6-bit panels.
2.5.5 Panel Background Color
A solid background color may be selected for a border around the active display area. The background color is most often set to black.
2.6 Panel Interface
The gmZAN1 chip interfaces directly with all of today’s commonly used active matrix flat panels with 640x480, 800x600 and 1024x768 resolutions. The resolution and the aspect ratio are NOT limited to specific values.
2.6.1 TFT Panel Interface Timing Specification
The TFT panel interface timing parameters are listed in Table 13 below. Refer to three timing diagrams of Figure 7 and Figure 8 for the timing parameter definition. All aspects of the gmZAN1 interface are programmable. For horizontal parameters, Horizontal Display Enable Start, Horizontal Display Enable End, Horizontal Sync Start and Horizontal Sync End are programmable. Vertical Display Enable Start, Vertical Display Enable End, Vertical Sync Start and Vertical Sync End are also fully programmable. In order to maximize panel data setup and hold time, the panel clock (PCLKA, PCLKB) output skew is programmable. In addition, the current drive strength of the panel interface pins is programmable.
Table 13. gmZAN1 TFT Panel Interface Timing
Signal Name Min Typical Max Unit
PVS
Period t1 0 16.67 2048
-
lines
ms Frequency 60 - Hz Front porch t2 0 2048 lines Back porch t3 0 2048 lines Pulse width t4 0 2048 lines PdispE t5 0 Panel height 2048 lines Disp. Start from VS t6 0 2048 lines PVS set up tp PHS t18 1 2048 PCLK *1 PVS hold from PHS t19 1 2048 PCLK *1
PHS
Period t7 0 2048 [1024 PCLK *1 Front porch t8 0 2048 PCLK *1 Back porch t9 0 2048 PCLK *1 Pulse width t10 0 2048 PCLK *1 PdispE t11 0 Panel width 2048 [1024] PCLK *1 Disp. Start fom HS t12 0 2048 PCLK *1
PCLKA, PCLKB*4
Frequency t13 120 [60] MHz Clock (H) *2 t14 DCLK/2-3 [DCLK-3] DCLK/2-2 [DCLK-2] ns Clock (L) *2 t15 DCLK/2-3 [DCLK-3] DCLK/2-2 [DCLK-2] ns Type - One pxl/clock
-
[two pxl/clock]
Data
Set up *3 t16 DCLK/2-5 [DCLK-5] DCLK/2-2 [DCLK-2] ns Hold *3 t17 DCLK/2-5 [DCLK-5] DCLK/2-2 [DCLK-2] ns width 3 bits 18 bits [36 bits] 24 bits [48 bits] bits/pixel
NOTE: Numbers in [ ] are for two pixels/clock mode. NOTE: The drive current of the panel interface signals is programmable as shown in Table 1. The drive current is to be
programmed through the API upon chip initialization. Output current is programmable from 2 mA to 20mA in increments of 2 mA. Drive strength should be programmed to match the load presented by the cable and input of the panel. Values shown are based on a loading of 20pF and a drive strength of 8 mA.
NOTE *1: The PCLK is the panel shift clock. NOTE *2: The DCLK stands for Destination Clock (DCLK) period. Is equal to:
-PCLK period in one pixel/clock mode,
-twice the PCLK period in two pixels/clock mode. NOTE *3: The setup/hold time spec. for PCLK also applies to PHS and PdispE. The setup time (t16) and the hold time (t17) listed
in this table are for the case in which no clock-to-data skew is added. The PVS/PHS/PdispE/Pdata signals are asserted on the rising edge of the PCLK. The polarity of the PCLK and its skew are programmable. Clock to Data skew can be adjusted in sixteen 800-ps increments. In combination with the PCLK polarity inversion, the clock-to-data phase can be adjusted in total of 31 steps.
NOTE *4: The polarity of the PCLKA and the PCLKB are independently programmable.
The microcontroller must have all the timing parameters of the panel used for the monitor. The parameters are to be stored in a non-volatile memory. As can be seen from this table, the wide range of timing programmability of the gmZAN1 panel interface makes it possible to support various kinds of panels known today:
Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock)
(a) Vertical size in TFT
PVS
PHS
PDE
(b) Vsync width and display position in TFT
PVS
PHS
t18
t4
t19
t1
t5t3
t2
RGBs
(c) Horizontal size in TFT
PHS
PCLK
PDE
RGB data from data paths
t12
(d) Hsync width in TFT
t6
t7
t11
Panel Background Color Displayed
t10
t8
t10
t9
t14
t13
t15
t16
t16
Figure 8. Data latch timing of the TFT Panel Interface
G0
PDE
t14B0t15
t16R0PCLK
t13
t17
t16R1B(n:0)
G(n:0)
R(n:0)
(a) Two pixel per clock mode in TFT
PDE
PCLK
ER
EG
EB
OR
OG
OB
t16
R0,(N:0)
G0,(N:0)
B0,(N:0)
R1,(N:0)
G1,(N:0) G3,(N:0)
B1,(N:0)
(b) One pixel per clock mode in TFT
t14
R2,(N:0)
G2,(N:0)
B2,(N:0)
R3,(N:0)
B3,(N:0)
t13
t15
t16
R4,(N:0)
t17
2.6.2 Power Manager
LCD panels require logic power, panel bias power, and control signals to be sequenced in a specific order, otherwise severe damage may occur and disable the panel permanently. The gmZAN1 has a built in power sequencer (Power Manager) that prevents this kind of damage. The Power Manager controls the power up/down sequences for LCD panels within the four states described below. See the timing diagram Figure 9.
2.6.2.1 State 0 (Power Off)
The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled.
2.6.2.2 State 1 (Power On)
Intermediate step 1. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is forced low (inactive).
2.6.2.3 State 2 (Panel Drive Enabled)
Intermediate step 2. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is active.
2.6.2.4 State 3 (Panel Fully Active)
This is the final step in the power up sequence, with Ppower and Pbias high (active), and the panel interface active. PM is kept in this state until the internal TFT_Enable signal controlled by Panel Control register is disabled. The panel can be disabled through either an API call under program control or automatically by the gmZAN1 to prevent damage to the panel.
Figure 9. Panel Power Sequence
In Figure 9 above, t2=t6 and t3=t5. t1,t2,t3 and t4 are independently programmable from one to eight steps in length. The length of each step is in the range of 511 * X* (TCLKi cycle) or (TCLKi cycle) * 32193 *X, where X is any positive integer value equal to or less than 256. TCLKi is the reference clock to the gmZAN1 chip, and ranges from
14.318 MHz to 50 MHz in frequency. This programmability provides enough flexibility to meet a wide range of power sequencing requirements by various panels.
TFT_EN Bit (register bit)
PPWR Output
Data/Controls Signals
PBias Output
t1
t4
t6
t2
t5
t3
<State3> <State2>
<State1><State2><State0>
<State0><State1>
2.6.3 Panel Interface Drive Strength
As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API calls. See the API reference manual for details.
Table 14. Panel Interface Pad Drive Strength
Value (4 bits) Drive Strength in mA
0 Outputs are in tri-state condition 1 2mA 2 4mA 3 6mA 4 8mA 5 10mA 6 12mA 7 14mA 8 16mA 9 18mA 10,11,12,13,14,15 20mA
2.7 Host Interface
The host microcontroller interface of the gmZAN1 has two modes of operation: gmB120 compatible mode, and a 4­bit serial interface mode. ? GmB120 compatible mode-Four signals consisting of 1 data bit, a frame synchronization signal, a clock signal
and an Interrupt Request signal (IRQ). This mode is entered when a pull-down resistor is not connected to MFB6(pin number 106).
? 4-bit serial interface mode-Same as gmB120 compatible mode with the addition of three data bits so that four
data bits are transferred on each clock edge. This mode is entered when a (10K ohm) pull-down resistor is connected to MFB6(pin number 106).
When the chip is configured for 4-bit host interface, MFB9:7 are used as HDATA3:1 and HDATA is used as HDATA0. For instruction, Read Data, or Write Data, the data order is D3:0, D7:4, D11:8, The burst mode operation then uses three clocks (instead of twelve) for each 12-bit data (or address) transmission.
In both modes, a reset pin sets the chip to a known state when the pin is pulled low. The RESETn pin must be low for at least 100ns after the CVDD has become stable (between +3.15V and +3.45V) in order to reset the chip to a known state.
The gmZAN1 chip has an on-chip pull-down resistor in the HFS input pad. No external pull-up is required. The signal stays low until driven high by the microcontroller.
2.7.1 Serial Communication Protocol
In the serial communication between the microcontroller and the gmZAN1, the microcontroller always acts as an initiator while the gmZAN1 is always the target. The following timing diagram describes the protocol of the serial channel of the gmZAN1 chip.
Figure 10. Timing Diagram of the gmZAN1 Serial Communication
Table 15 summarizes the serial channel specification of the gmZAN1. Refer to Figure 10 for the timing parameter definition.
Table 15. gmZAN1 Serial Channel Specification
Parameter Min. Typ. Max.
Word Size (Instruction and Data) --- 12 bits --­HCLK low to HFS high (t1) 100 ns HFS low to HCLK inactive (t2) 100 ns HDATA Write to Read Turnaround Time (t3) 1 HCLK cycle 1 HCLK cycle HCLK cycle (t4) 100 ns Data in setup time (t5) 25 ns Data in hold time (t6) 25 ns Data out valid (t7) 5 ns 10
In the read operation, the microcontroller (Initiator) issues an instruction lasting 12 HCLKs. After the last bit of the command is transferred to the gmZAN1 on the 12th clock, the microcontroller must stop driving data before the next rising edge of HCLK at which point the gmZAN1 will start driving data. At the 13th rising edge of HCLK, the gmZAN1 will begin driving data.
Figure 11. Serial Host Interface Data Transfer Format
2 bits 10 bits 12 bits
Command Address Data
Command: 01 Write 00 = Read 1x = Reserved
Note that when the chip is configured for a 4-bit host interface, MFB9:7 are used as HDATA 3:1 and HDATA is used as HDATA0. The command and address information are transferred as Address 1:0+Command1:0, Address5:2 and Address9:6. The data information is transferred as Data3:0,Data 7:4, Data 11:8. Thus, in this mode the HDATA pin carries Command0, Address2, Address6, Data0, Data4 and Data8. On the gmZAN1 reference design board, the microcontroller toggles the HCLK and HDATA lines under program control. Genesis Microchip provides API calls to facilitate communication between the microcontroller and the gmZAN1. Refer to the API reference manual for details.
2.7.2 Multi-Function Bus (MFB)
The Multi-Function Bus provides additional 12 pins that are used as general purpose input and output (GPIO) pins. Each pin can be independently configured as input or output. MFB pins 9 through 5 have special functions: ? When a 10K ohm pull-down resistor is connected to MFB6 (MFB6 has an internal pull-up resistor) MFB9:7 are
used as host data bits HDATA3:1.
? When a 10K ohm pull-down resistor is connected to MFB5 (MFB5 has an internal pull-up resistor) a crystal can
be placed between XTAL and TCLK instead of using an external oscillator for the TCLK input.
Note that all pins on the multi-function bus MFB11:0 are internally pulled-up.
2.8 On-Screen Display Control
The gmZAN1 chip has a built-in OSD (On-Screen Display) controller with an integrated font ROM. The chip also supports an external OSD controller for monitor vendors to maintain a familiar user interface. The internal and external OSD windows may be displayed anywhere the panel Display Enable is active, regardless of whether the panel would otherwise display panel background color or active data.
2.8.1 OSD Color Map
Both the internal and external OSD display use a 16 location SRAM block for the color programming. Each color location is a twelve-bit value that defines the upper four bits of each of the 8 bit Red, Blue and Green color components as follows:
? D3:0 Blue; D7:4 of blue component of color ? D7:4 Green; D7:4 of green component of color ? D11:8 Red; D7:4 of red component of color
To extend the 4-bit color value programmed to the full 8 bits the following rule is applied: if any of the upper four color bits are a “1”, then R (G, B) data 3:0=1111b, otherwise R (G, B) data 3:0=0000b
2.8.2 On-Chip OSD Controller
The internal OSD uses a block of SRAM of 1536x12 bits and a ROM of 1024x12 bits. The SRAM is used for both the font data and the character-codes while the ROM is used to store the bit data for 56 commonly used characters. The font data is for 12 pixel x 18 line characters, one bit per pixel. The font data starts at address zero. The character-codes start at any offset (with an address resolution of 16) that is greater than the last location at which font data has been written . It is the programmer’s responsibility to ensure that there is no overlap between fonts and character-codes. This implementation results in a trade-off between the number of unique fonts on-screen at any one time and the total number of characters displayed. For example, one configuration would be 98 font maps (56 fonts in ROM and 42 fonts in SRAM) and 768 characters (e.g. in a 24x32 array).
The on-chip OSD of the gmZAN1 can support a portrait mode (in which the LCD monitor screen is rotated 90 degrees). In this portrait mode, all the fonts must be loaded in the SRAM, because the ROM stores fonts for a landscape mode (typical orientation) only. The font size in the portrait mode is 12 pixels by 12 lines. As is the case in landscape mode, the SRAM is divided into a font storage area and a character code storage area. For example, 64 fonts can be stored in RAM and an OSD window of 768 characters (such as 24x32) can still be displayed.
The first address of SRAM to be read for the first character displayed (upper left corner of window)is also programmable, with an address resolution of 16 (8-bits as the top bits of the 12-bit SRAM address). The character­code is a 12-bit value used as follows:
? D6:0 font-map select, this is the top seven bits of the address for the first line of font bits ? D8:7 Background color, 00=bcolor0, 01=bcolor1, 10=bcolor2, 11=transparent background ? D10:9 Foreground color (0, 1, 2 or 3) ? D11 Blink enable if set to 1, otherwise no blink
Although the OSD color map has room for sixteen colors, only seven are used by the internal OSD: three background colors and four foreground colors.
The blink rate is based on either a 32 or 64 frame cycle and the duty cycle may be selected as 25/75/50/50% or 75/25%. The 2-bit foreground and background attributes directly select the color (there is no indirect “look-up”, i.e. there is no TMASK function). The 2560 addresses of the ROM/SRAM are mapped as 10 segments of 256 contiguous addresses each, to the OSD memory page of 100h-1FFh in the host interface. A 4-bit register value selects the segment to map to the host R/W page.
The character cell height and width are programmable from 5-66 pixels or 2-65 lines. The X/Y offset of the font bit­map upper-left pixel relative to the upper-left pixel of the character cell is also programmable from 0-63 (pixels or lines). The OSD window height and width in characters/rows is programmable from 1-64.
The Start X/Y position for the upper left corner of the OSD window is programmable (in panel pixels and lines) from 0-2047. There is an optional window border (equal width on all four sides of the window) or a window shadow (the window bottom and right side) the border is a solid color that is selected by an SRAM location as RGB444. The border width may be set as 1, 2, 4 or 8 pixels/lines. These parameters are summarized in Figure 12 and Table 16. The Font Data D11:0 for each line is displayed with bit D11 first (leftmost) and D0 last. The reference point for the OSD start is always the upper left corner of the Panel display, which is the start (leading edge) of Panel Display Enable for both Horizontal and Vertical timing.
The OSD Window start position sets the location of the first pixel of the OSD to display, including any border. That is; if the border is enabled, the start of the character display of the OSD is offset from the OSD start position by the width/height of the border.
To improve the appearance and make it easy to find the OSD window on the screen, the user may select optional shadowing (3D effect). The “Shadow” feature operates in the same manner as in the B120; that is, it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window, but offset to the right and down by 8 pixels/lines (the border width setting has no effect). OSD foreground and background colors always cover the OSD window region of the “shadow”, but transparent background pixels in the OSD will show the half intensity panel data. Therefore, it is not recommended to use both the “shadow” feature and transparent background OSD pixels together. The ”shadow” does not change the intensity of any panel background color over which it may be located. The border and shadow are mutually exclusive, only one may be selected at a time.
The OSD window is not affected by the scaling operation. The size will stay the same whether the source input data is scaled or not.
2.9 TCLK Input
The source timing is measured by using the TCLK input as a reference. Also, the reference clock to the on-chip PLLs are derived from the TCLK. It is therefore crucial to have a jitter-free clock reference. Table 19 shows the requirements for the TCLK signal.
Table 19. TCLK Specification
Frequency 20 MHz to 50 MHz Jitter 250 ps maximum Rise Time (10% to 90%) 5 ns Duty Cycle 40-60
There is also an option to use a crystal (instead of an oscillator) for the TCLK input. This option is selected by pulling down MFB5 and connecting the crystal between XTAL and TCLK.
3. ELECTRICAL CHARACTERISTICS
Table 20. Absolute Ratings
Parameter Min. Typ. Max. Note
PVDD 5.6 volts CVDD 5.6 volts Vin Vss-0.5 volt Vcc+0.5V Operating temperature 0 degree C 70 degree C Storage temperature -65 degree C 150 degree C Maximum power consumption ~2W
Table 21. DC Electrical Characteristic
Parameter Min. Typ. Max. Note
PVDD 3.15 volts 3.3 volts 3.47 volts CVDD 3.15 volts 3.3 volts 3.47 volts Vil (COMS inputs) Vil (TTL inputs) Vih (COMS inputs) Vih (TTL inputs) Voh 2.4 volts CVDD Vol 0.2 volts 0.4 volts Input Current -10 uA 10 uA PVDD operating supply current 0 mA 20 mA/pad @ 10pF (2) CVDD operating supply current 0 mA 500 mA (3) NOTE 1:5V-Tolerent TTL Input pads are as follows:
? CRT Interface: HSYNC (pin #150), VSYNC (#148) ? Host Interface: HFS (#98), HCLK (#103), HDATA (#99), RESETN (#100), MFB[11:0]: MFB11 (#123),
MFB10 (#124), MFB9 (#102), MFB8 (#104), MFB7 (#105), MFB6 (#106), MFB5 (#107), MFB4 (#109), MFB3 (#110), MFB2 (#111), MFB1 (#112), MFB0 (#113)
? OSD Interface: OSD_DATA3 (#121), OSD_DATA2 (#120), OSD_DATA1 (#119), OSD_DATA0 (#118),
OSD_FSW (#122)
? Non-5V-Tolerant TTL Input Pad is: TCLK(#141) NOTE 2: When the panel interface is disabled, the supply current is 0 mA. The drive current of each pad can be programmed in the range of 2 mA to 20 mA (@capacitive loading = 10 pF) NOTE 3: When all circuits are powered down and TCLK is stopped, the CVDD supply current becomes 0 mA.
0.3*CVDD
0.8 volts
0.7 * CVDD
2.0 volts
1.1*CVDD
5.0+0.5 volts
(1)
7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY
INVERTER BOARD
INVERTER SHIELD
79AL15-6-S
Q1A1030-12-128X4
EARTH CLIP
TURN BASE
BASE SHIELD
BASE HOLDER
15A5688 X 4
SCREW
Q1A340-16-128X4
SCREW
Q1A1030-10-128 X 4
Q1A1030-10-128 X 4
SCREW
RUBBER FOOT
12A385-1 X 4
REAR COVER
34A675
SHIELD
85A548
MAIN BOARD
MAIN FRAME
15A5683(HANNSTAR)
SCREW
LCD PANEL
750ALCDX41-1
KEY PAD
33A4095
FRONT BEZEL
34A785
KEPC
KEPC560EKMN
POWER LENS 33A3782
SHIELD 85A580
SUPPORT(FRONT)
34E676
BASE
34A787
34A786
85A577
HINGE
37A442
SUPPORT(BACK)
34A677
ADAPTER BOARD
80AL15-2-L1
85A562
SCREW
15A5687
PLASTIC GEAR 11A144-1
Q1A1020-6-120
1
1
1
2
1
1
1
2
1
1
3
2
2
1
1
1
1
2
1
1
1
2
4
1
5
6
1
1
1
7
3
2
1
1
1
1
2
6
2
5
5
8
6
6
LOCATION
11A 144­ 12A 385­ 15A 5674­ 15A 5683­ 15A 5687­ 15A 5688­ 15A 5689­ 19A 550­ 33A 3782­ 33A 4095­ 34A 675­ 34A 676­ 34A 677­ 34A 785­ 34A 786­ 34A 787­ 37A 442­ 40A 152- 27 40A 152- 28 40A 154- 501 - 1
!
!
!
40A 155- 182 40A 581- 26 - 668 41A 68- 622 - 1C 41A 401- 929 44A 3138­ 44A 3145­ 44A 3146­ 44A 3229­ 44A 3229­ 44A 3229­ 44A 3231­ 44A 3231­ 44A 3231­ 45A 113­ 45A 116­ 45A 120­ 70A L15­ 71A 100- 14 85A 548­ 85A 557­ 85A 562­ 85A 580­ 85A 581­ 85A 583­ 85A 583­ 79A L15­ 80A L15­ 89A 404A- 15N - IS 89A 173- L15 - 6 89A 178- 60 - 1 95A 8014­ B1A 1030­ B1A 1030­ M1A 330­ M1A 1030- 10 - 128 M1A 1740- 12 - 128 Q1A 340- 12 - 128 Q1A 340- 16 - 128 Q1A 1020­ Q1A 1030- 10 - 128 Q1A 1030- 12 - 128 750A LCD- X14 - 1
TF1560GH SPECIFICATION
CBPC560GHMN CONVERSION BOARD KEPC560EKMN KEY BOARD
DAMPER GEAR RUBBER FOOT CABLE CLAMP MAIN FRAME SHIELD-BASE HOLDER-BASE GND. CABLE CLAMP EARTH SPRING POWER LED LENS KEY PAD
- AL
- AT
- AT
- AL
- AL
- AL
- SM
- S
- LI
- 4
- 128
- 128
- 128
- 120
BACK COVER SUPPORT FRONT SUPPORT BACK BEZEL TURN BASE BASE LCD HINGE SERIAL No. REV. No. HI/POT LABEL ID LABEL BAR-CODE WARRANTY CORD MANUAL CORNER PAD WOODEN FLAT PALLETS WOODEN FLAT PALLETS EPS (L) EPS (R) CARTON EVA EVA EVA(DOUBLE) PROTECT COVER PROTECT COVER PE-LD BAG DRIVE DISK SIEMENS CORD SHIELD CBPC SHIELD INVERTORY EARTH CLIP SHIELD INVERTORY PANED SHILED SOFT-SHIELD SOFT-SHIELD INVERTER BY SAMPO ADAPTOR BY LINEARITY POWER CORD UL/CSA SIGNAL CABLE FPC CABLE HARNESS SCREW SCREW SCREW SCREW SCREW SCREW SCREW SCREW SCREW SCREW LCD PANEL HSD150MX41
PARTS LIST OF CONVERSION BOARD
8
1
7
4
4
4
4
1
1
LOCATION CBPC1560GHMN SPECIFICATION
CN303 33A 3802- 5H CN302 33A 3802- 9H CN202 33A 3804- 30 CN201 33A 3804- 45 CN200 33A 8013- 14 - H 40A 152- 26 U200 56A 562­U304 56A 563­U305 56A 563­U302 56A 1125- 61 - H U203 56A 1133- 16 U300 56A 1133- 17 Q200 57A 417­Q250 57A 417­Q303 57A 417­Q304 57A 417­Q201 57A 748­D211 57A 754­RP300 61A 125- 103 - 8 JP202 61A 0603- 000 JP211 61A 0603- 000 JP222 61A 0603- 000 JP300 61A 0603- 000 L204 61A 0603- 000 L205 61A 0603- 000 L206 61A 0603- 000 R200 61A 0603- 000 R201 61A 0603- 000 R202 61A 0603- 000 R203 61A 0603- 000 R207 61A 0603- 000 R208 61A 0603- 000 R317 61A 0603- 000 R319 61A 0603- 000 R211 61A 0603- 101 R212 61A 0603- 101 R218 61A 0603- 101 R219 61A 0603- 101 R220 61A 0603- 101 R227 61A 0603- 101 R213 61A 0603- 102 R214 61A 0603- 102 R216 61A 0603- 103 R217 61A 0603- 103 R223 61A 0603- 103 R300 61A 0603- 103 R301 61A 0603- 103 R309 61A 0603- 103 R311 61A 0603- 103 R313 61A 0603- 103 R314 61A 0603- 103 R315 61A 0603- 103 R326 61A 0603- 103 R327 61A 0603- 103 R328 61A 0603- 103 R319 61A 0603- 103 R400 61A 0603- 103 R401 61A 0603- 103 R224 61A 0603- 104 R225 61A 0603- 104
WAFER 5P PLUG RIGHT ANELE WAFER 9P PLUG RIGHT ANELE WAFER FH12-30S-0.5SH WAFER FH12-45S-0.5SH 13P PLUG RIGHT ANGLE LABEL ZAN1 POFP-160 IC TF1560E NS AIC1084-33M M6759 IC IC NPN GENERAL PURPOSE TRAN NPN GENERAL PURPOSE TRAN NPN GENERAL PURPOSE TRAN NPN GENERAL PURPOSE TRAN MOSFET BAT54C-GS08 CHIP ARRAY 10K OHM 1/16W 8P4R CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 0 OHM 1/10W CHIP 100 OHM 1/10W CHIP 100 OHM 1/10W CHIP 100 OHM 1/10W CHIP 100 OHM 1/10W CHIP 100 OHM 1/10W CHIP 100 OHM 1/10W CHIP 1KOHM 1/10W CHIP 1KOHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 10K OHM 1/10W CHIP 100K OHM 1/10W CHIP 100K OHM 1/10W
LOCATION CBPC1560GHMN SPECIFICATION
R209 61A 0603- 202 R210 61A 0603- 202 R226 61A 0603- 302 R229 61A 0603- 511 R204 61A 0603- 750 R205 61A 0603- 750 R206 61A 0603- 750 CP301 65A 600- 102 - 8T CP302 65A 600- 102 - 8T CP201 65A 600- 220 - 8T CP202 65A 600- 220 - 8T CP203 65A 600- 220 - 8T CP204 65A 600- 220 - 8T CP205 65A 600- 220 - 8T CP206 65A 600- 220 - 8T CP207 65A 600- 220 - 8T CP208 65A 600- 220 - 8T CP209 65A 600- 220 - 8T CP210 65A 600- 220 - 8T CP211 65A 600- 220 - 8T CP212 65A 600- 220 - 8T C235 65A 0603- 101 - 32 C236 65A 0603- 101 - 32 C229 65A 0603- 103 - 32 C230 65A 0603- 103 - 32 C231 65A 0603- 103 - 32 C232 65A 0603- 103 - 32 C233 65A 0603- 103 - 32 C234 65A 0603- 103 - 32 C251 65A 0603- 103 - 32 C201 65A 0603- 104 - 12 C202 65A 0603- 104 - 12 C204 65A 0603- 104 - 12 C205 65A 0603- 104 - 12 C207 65A 0603- 104 - 12 C208 65A 0603- 104 - 12 C209 65A 0603- 104 - 12 C210 65A 0603- 104 - 12 C211 65A 0603- 104 - 12 C212 65A 0603- 104 - 12 C213 65A 0603- 104 - 12 C215 65A 0603- 104 - 12 C217 65A 0603- 104 - 12 C218 65A 0603- 104 - 12 C219 65A 0603- 104 - 12 C220 65A 0603- 104 - 12 C221 65A 0603- 104 - 12 C222 65A 0603- 104 - 12 C223 65A 0603- 104 - 12 C225 65A 0603- 104 - 12 C226 65A 0603- 104 - 12 C227 65A 0603- 104 - 12 C228 65A 0603- 104 - 12 C237 65A 0603- 104 - 12 C244 65A 0603- 104 - 12 C245 65A 0603- 104 - 12 C246 65A 0603- 104 - 12 C261 65A 0603- 104 - 12 C300 65A 0603- 104 - 12 C304 65A 0603- 104 - 12 C308 65A 0603- 104 - 12
CHIP 2K OHM 1/10W CHIP 2K OHM 1/10W CHIP 3K OHM 1/10W CHIP 510 OHM 1/10W CHIP 75 OHM 1/10W CHIP 75 OHM 1/10W CHIP 75 OHM 1/10W
CHIP ARRAY 1000PF 8P CHIP ARRAY 1000PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP 100PF 100PF 50V CHIP 100PF 100PF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V
CHIP 0.01UF 50V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V CHIP 0.1UF 10V
1
2
2
1
LOCATION CBPC1560GHMN SPECIFICATION
C311 65A 0603- 104 - 12 C250 65A 0603- 330 - 31 C262 65A 0603- 330 - 31 C303 65A 0603- 330 - 31 C306 65A 0603- 330 - 31 C307 67A 305- 331 - 6 C309 67A 305- 331 - 6 C310 67A 305- 331 - 6 C312 67A 305- 331 - 6 C200 67A 312- 220 - 3 C203 67A 312- 220 - 3 C206 67A 312- 220 - 3 C214 67A 312- 220 - 3 C216 67A 312- 220 - 3 C224 67A 312- 220 - 3 C305 67A 312- 220 - 3 C313 67A 312- 220 - 3 C314 67A 312- 220 - 3 FB301 71A 55- 28 R215 71A 56­LP201 71A 56A- 121 - 8T LP202 71A 56A- 121 - 8T LP203 71A 56A- 121 - 8T LP204 71A 56A- 121 - 8T LP205 71A 56A- 121 - 8T LP206 71A 56A- 121 - 8T LP207 71A 56A- 121 - 8T LP208 71A 56A- 121 - 8T LP209 71A 56A- 121 - 8T LP210 71A 56A- 121 - 8T LP211 71A 56A- 121 - 8T LP212 71A 56A- 121 - 8T L207 71A 56G- 151 - A L200 71A 57G- 601 L201 71A 57G- 601 L202 71A 57G- 601 L203 71A 57G- 601 L300 73A 253- 108 - LI VR501 75A 335- 103
87A 202- 44 90A 372­X300 93A 22- 55 U201 93A 22- 57 D200 93A 39- 139 D201 93A 39- 139 D208 93A 39- 139 D209 93A 39- 139 D210 93A 39- 139 D300 93A 60- 209 D202 93A 64- 32 D203 93A 64- 32 D204 93A 64- 32 D205 93A 64- 32 D206 93A 64- 32 D207 93A 64- 32 D301 93A 64- 32 D302 93A 64- 32 95A 3261­ 715A 763-
-
24
CHIP 0.1UF 10V
33PF 50V NPO 33PF 50V NPO 33PF 50V NPO
33PF 50V NPO 330UF +-20% 35V 330UF +-20% 35V 330UF +-20% 35V 330UF +-20% 35V
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE
SMD EC 22uF 16V 85CC SIZE BEAD TECST BEAD TECSTAR CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD ARRAY 120 OHM CHIP BEAD 150 OHM CHIP BEAD 600 OHM CHIP BEAD 600 OHM CHIP BEAD 600 OHM CHIP BEAD 600 OHM CHOKE COIL 10K OHM +-30% SMT PLCC CONN HEAT SINK CRYSTAL 20MHz HC-49US OSCILATOR 50MHz ZENER DIODE TF1560E FCI ZENER DIODE TF1560E FCI ZENER DIODE TF1560E FCI ZENER DIODE TF1560E FCI ZENER DIODE TF1560E FCI DIODE DIODE FCI DIODE FCI DIODE FCI DIODE FCI DIODE FCI DIODE FCI DIODE FCI DIODE FCI HARNESS COVERSION BOARD
PARTS LIST OF KEY PC BOARD
1
1
1
1
1
1
5
9
1
LOCATION
40A 152- 25 Q101 57A 419- PP - T Q102 57A 419- PP - T R101 61A 602- 103 - 52T R102 61A 602- 103 - 52T R103 61A 602- 103 - 52T R104 61A 602- 103 - 52T R105 61A 602- 103 - 52T R107 61A 602- 103 - 52T R108 61A 602- 221 - 52T C101 65A 450- 104 - 7T SW1 77A 600­SW2 77A 600­SW3 77A 600­SW4 77A 600­SW5 77A 600­T101 77A 700­LED1 81A 10­J101 95A 90- 23 J102 95A 90- 23 95A 8014­ 715A 707-
KEPC560EKMN
- G
- G
- G
- G
- G
- BH
- 5
SPECIFICATION
KEPC560EEKMN-A LABEL TR. 2PC945P TR. 2PC945P 10K OHM +-5% 1/6W 10K OHM +-5% 1/6W 10K OHM +-5% 1/6W 10K OHM +-5% 1/6W 10K OHM +-5% 1/6W 10K OHM +-5% 1/6W 220 OHM +-5% 1/6W
0.1uF +80-20% Y5V 50V WITH GROUND WITH GROUND WITH GROUND WITH GROUND WITH GROUND EC11B20244 ENCODER RORW BICOLOR LED LAMPS TIN COATED TIN COATED HARNESS 265mm 9P KEY BOARD
9. POWER SYSTEM AND CONSUMPTION CURRENT
ADAPTER MODULE Input AC 110V, 60Hz/240V, 50Hz Output DC 12V 3.5A
Main board power system
LM2596S-5, 12V to 5V (3A SPEC)
INVERTER MODULE Input DC 12V Output AC 1500V/30K-50KHz Current 9mA
5V
AIC1084, 5V to 3.3V (5A SPEC)
3.3V
To Hannstar – Panel (consumption current arround 363mA MAX) and GMZAN1
To CPU, Eeprom, 24c21, control-inverter-on.off 860mA when Cable not Connected 841mA when Normal operation
800mA when Cable not Connected 760mA when Normal operation
CN302
(Panel-Select)
R320 R322 R324
10K (NC)
(NC)
0
1 2 3 4
C304
8 7 6 5
R217
10K
D209
R216
5.5V 10K
D208
5.5V
R101 R102 R103 R104 R105
1/4W
10K
R318
10K (NC)
R319
KEY
10K
SW101 SW102
AUTO KEY
KEY PAD
1 2 3 4 5 6 7 8 9
+3.3V
U200
+5V
87 65
RP300
10K
+5V
10K (NC)
R325R323R321
(NC)0(NC)0(NC)
+5V
0
+5V
R329R328
10K10K
1 2 3 4
CP302CP301
10001000
8 7 6 5
R220
100
R219
100
VCC
10K
10K
10K
10K
1/4W
1/4W
1/4W
1/4W
SW104 SW105
SW103
KEY
KEY
LCD
2SC945
C101
KEY
ENTER
LEFT
ON/OFF
RIGHT
0.1
R107 R106
10K 1/4W
4321
R317
0
MFB2
VDDA
D202
1N4148
R200
L204
R206
C229
C247
D203
0
0.15uH
75
10nF
22
1N4148
(NC)
R203
VDDA
VDDA
D206
1N4148
D207
1N4148
Q101
DP101
C232
0
10nF
D204
1N4148
R201
L205
R205
C230
D205
0
0
C248
75
10nF
1N4148
(NC)
R207
C233
0
10nF
R202
L206
R204
C231
0
0
C249
75
10nF
(NC)
+3.3V
R208
C234
0
R210
10nF
2K
R214
R212
R209
R218
1K
C236
D201
100
2K
100
5.6V100
R213
R211
1K
100
C235
D200
100 5.6V
JP101
1
VCC
2
LCD ON/OFF
3
KEY LEFT
4
KEY RIGHT
5
KEY ENTER
6
AUTO KEY
7
LED ORANGE
8
LED GREEN
Q102
9
2SC945
10K 1/4W
DUAL
LED1
R108
220 1/4W
RVDD2
RVDD1
SRVDD2
SRVDD1
HDATA0
99
HDATA
MFB7
105
MFB7
MFB8
104
MFB8
MFB9
102
MFB9
HCLK
103
HCLK
IRQ
101
IRO
HFS
98
HFS
107
MFB5
106
MFB6
R316
NC
124
MFB10
123
MFB11
109
MFB4
110
MFB3
111
MFB2
112
MFB1
113
MFB0
95
RED+
94
RED-
91
GREEN+
GREEN-
90
87
BLUE+
86
BLUE-
150
HSYNC/CS
148
VSYNC
2
Reserved
3
PSCAN
4
Reserved
5
Reserved
59
Reserved
60
Reserved
83
Reserved
97
NC
130
Reserved
135
Reserved
142
XTAL(Reserved)
145
Reserved
147
Reserved
152
Reserved
153
STI_TM1
RVSS3
CVSS2
RVSS2
SRVSS1
RVSS1
CVSS1
1 8 18 30 41 49 61 72 114 126 140 151 158 78 80 81 82 85 89 93 131 132 133 134 127 138 144 146
GND
VDDA
RVDDA
DVDDA
SVDDA
TCLK1
+3.3V
R230
14313713612912896928884149139125108797765584033211211
0
TCLK
(NC)
C206
141
SVDD
DVDD
CVDD4
RVDD3
CVDD2
CVDD1
SYN_VDD
ADC_VDDA
ADC_VDD1
ADC_VDD2
ADC_BVDDA
ADC_BGNDA
ADC_GNDA
SUB_GNDA
ADC_GND1
ADC_GND2
SRVSS2
SYN_VSS
SVSS
DVSS
CVSS4
CVSS3
RVSS4
TCLK
PD47
PLL_RVDDA
DAC_SVDDA
PLL_SVDDA
PLL_DVDDA
DAC_DVDDA
ADC_RVDDA
ADC_GVDDA
PD46
PD45 PD44
PD43 PD42 PD41
PD40
PD39 PD38
PD37 PD36 PD35
PD34
PD33 PD32
PD31 PD30 PD29
PD28
PD27 PD26
PD25 PD24 PD23
PD22
PD21 PD20
PD19 PD18 PD17
PD16
PD15 PD14
PD13 PD12 PD11
PD10
PD9 PD8
PD7 PD6 PD5
PD4
PD3 PD2
PD1 PD0 PVS
PHS
PBIAS
PPWR
PDISPE PCLKA PCLKB
OSD_CLK
OSD_VREF
OSD_HREF
OSD_DATA2
OSD_DATA1 OSD_DATA0
OSD_FSW
OSD_DATA3
RESETn
STI_TM2
SCAN_IN1 Reserved
SCAN_IN2 SCAN_OUT1
SCAN_OUT2
SUB_RGNDA
PLL_RGNDA
DAC_SGNDA
DAC_DGNDA
PLL_SGNDA
SUB_SGNDA
SUB_DGNDA
PLL_DGNDA
ADC_RGNDA
ADC_GGNDA
PLL_GNDAADC_AGND
6
7
9 10
13 14 15
16
17 19
20 22 23
24
25 26
27 28 29
31
32 34
35 36 37
38
39 42
46 47 48
50
51 52
53 54 55
56
57 62
63 64 66
67
68 693
70 71 73
74
75 76
43 44 45
117
116
115
120
119 118
122
121
100
154
155 156
157 159
160
PD47
PD46
PD45 PD44 PD43
PD42 PD41
PD40 PD39
PD38 PD37
PD36 PD35
PD34 PD33
PD32 PD31
PD30 PD29
PD28 PD27
PD26 PD25
PD24 PD23
PD22 PD21
PD20 PD19
PD18 PD17
PD16 PD15
PD14 PD13
PD12 PD11
PD10
PD9
PD8 PD7
PD6 PD5
PD4 PD3
PD2 PD1
PD0 PVS
PHS PBIAS
PPWR
PDISPE
PCLKA
PCLK
L207
C262
120
33
R305 R306
10K
10K
(NC)
(NC)
R326
D302
10K
1N4148
R307
C314
10K
22UF
(NC)
C207 C208 C209 C210 C211 C212 C213
22UF
0.1 0.1 0.1 0.1 0.1 0.1 0.1
C216
22UF
L203
C224
1UH
C225 C226 C227 C228
22UF
0.1 0.1 0.1 0.1
L200
C200
1UH
C202C201
22UF
0.10.1
L201
C203
1UH
C205C204
22UF
0.10.1
L202
U201
C237
1UH 50MHz
0.1
1
8
VCC
SB
4 5
OUT
GND
+5V
R303 R304
R302
270
270
270
(NC)
(NC)
(NC)
2
OSD_CLK
10
VREF
5
HREF
15
R
14
G
13
B
12
FBKG
6
SSB
2
1
+5V
R312
C313
10K
D301
22UF
(NC)
1N4148
Q300
R313
MMBT3904
10K
(NC)
RST
PD13-1 PD12-1 PD41-1 PD40-1
1
2
3
CP202
22
8
7
6
PD7-1 PD6-1 PD39-1 PD38-1
1
2
3
CP204
22
8
7
6
PD1-1 PD0-1 PD37-1 PD36-1
1
2
3
CP206
22
8
7
6
R401
10K
JP201
0
Q250 R223
JP202
MMBT3904 10K
PANLE_EN
PD31-1 PD30-1 PD47-1 PD46-1
CP208
22
PD25-1 PD24-1 PD45-1 PD44-1
1
2
3
CP210
22
8
7
6
PD19-1 PD18-1 PD43-1 PD42-1
1
2
3
CP212
22
8
7
6
R309
R311
10K
10K
Q304
MMBT3904
R315
10K
1 2 3 12345
JP301
0
LP201
120
1
8
PD14
2
7
PD15
3
6
PD16
4
5
PD17
1
2
3
4
8
7
6
5
LP203
120
PD8
1
8
2
7
PD9
3
6
PD10
4
5
PD11
1
2
3
4
8
7
6
5
LP205
120
PD2
1
8
2
7
PD3
3
6
PD4
4
5
PD5
1
2
3
4
8
7
6
5
+12V
R224
100K
R225
100K
Q201
MGSF1N03
C245
Q200
0.1
MMBT3904
R226
C426
3K
0.1
LP207LP208
120120
PD32
11
88
22
77
PD33
33
66
PD34
44
55
PD35
11
22
33
44
88
77
66
55
LP209
120
PD26
1
8
2
7
PD27
3
6
PD28
4
5
PD29
1
2
3
4
8
7
6
5
LP211
120
PD20
1
8
2
7
PD21
3
6
PD22
4
5
PD23
1
2
3
4
8
7
6
5
R522
10K7
VR501
10K
R523
10K7
+12V
CN303
LP202
120
PD13
1
8
2
7
PD12
C223C222C221C220C219C218C217
3
6
PD41
0.10.10.10.10.10.10.1
4
5
PD40
VDDA
DVDDA
SVDDA
RVDDA
C214
C215
22UF
0.1
TCLK
R215
C250
120
0.1
U301
MTV121
(NC)
11
HTOME
4
VDD1
9
VDD2
C301 C302
0.1 (NC)
1
VSS1
16
VSS2
SDA
7
SDA
SCL
8
SCL
NC
3
U303
DS1813 (NC)
VCC
3
GND
RST
R229
510
4
5
LP204
120
PD7
1
8
2
7
PD6
3
6
PD39
4
5
PD38
4
5
LP206
120
PD1
1
8
2
7
PD0
3
6
PD37
4
5
PD36
4
5
PPWR
R400
10K
PD31 PD30 PD47 PD46
LP210
120
PD25
1
8
2
7
PD24
3
6
PD45
0.1
4
5
PD44
(NC)
4
5
LP212
120
PD19
1
8
2
7
PD18
3
6
PD43
4
5
PD42
4
5
+5V
PBIAS
Q303
MMBT3904
R314
10K
BACKLIGH
JP300
CN201
45
PCLK
44 43
PDISPE
42 41
PVS
40 39
PD14-1
PHS
PD15-1
38
PD16-1
37
PD17-1
36 35
CP201
PD17-1
22
34
PD16-1
33
PD15-1
32
PD14-1
31 30
PD13-1
29
PD12-1
28
PD41-1
27
PD8-1
PD40-1
PD9-1
26
PD10-1
25
PD11-1
PD11-1
24
PD10-1
CP203
23
22
PD9-1
22
PD8-1
21 20
PD7-1
19
PD6-1
18
PD39-1
17
PD38-1
16
PD2-1
15
PD3-1
PD5-1
PD4-1
14
PD5-1
PD4-1
13
PD3-1
12
CP205
PD2-1
22
11 10
PD1-1
9
PD0-1
8
PD37-1
7
PD36-1
6 5
+5V
R526
R528
10K
4
10K
JP201
3
0
+3.3V
2
JP202
R529 R527
1
0 0
PANEL_P
PD32-1 PD33-1 PD34-1
CN202
PD35-1
30
PD35-1
29
CP207
PD34-1
22
28
PD33-1
27
PD32-1
26 25
PD31-1
24
PD30-1
23
PD47-1
22
PD46-1
21
PD26-1
20
PD27-1
PD29-1
PD28-1
19
PD29-1
PD28-1
18
PD27-1
17
CP209
PD26-1
22
16 15
PD25-1
14
PD24-1
13
PD45-1
12
PD44-1
11 10
PD23-1
PD20-1
9
PD22-1
PD21-1
8
PD22-1
PD21-1
7
PD23-1
PD20-1
6
CP211
5
22
PD19-1
4
PD18-1
3
PD43-1
2
PD42-1
1
C383FA-1
U302
8XC51/PLCC
HDATA0
2
24
P2.0/A8
T2/P1.0
MFB7
3
25
P2.1/A9
T2EX/P1.1
MFB8
4
26
P2.2/A10
P1.2
MFB9
5
27
P2.3/A11
P1.3
HCLK
6
28
P2.4/A12
P1.4
HFS
7
29
P2.5/A13
P1.5
BACKLIGHT_EN
8
30
P2.6/A14
P1.6
PANLE_EN
9
31
P2.7/A15
P1.7
RST
10
32
PSEN
RST
33
ALE/PROG
RXD
11
RXD/P3.0
WP
TXD
13
36
P0.7/AD7
TXD/P3.1
IRQ
14
37
P0.6/AD6
INT0/P3.2
MFB2
15
38
P0.5/AD5
INT1/P3.3
SDA
16
39
P0.4/AD4
T0/P3.4
SCL
17
40
P0.3/AD3
T1/P3.5
R327
10K
R227
100
C251
D210
1nF
5.6V
CN200
RXD
14
TXD
13 12 11
VGA_VSYNC
10
VGA_HSYNC
9
/VGA_CON
8 7 6 5
GREEN
4 3
RED
2 1
CN301
POWER+12V
FB301
+12V
C308
C307
330UF 0.1
35V
COREPOWER
10/24/2000
RST1
18
41
P0.2/AD2
WR/P3.6
/VGA_CON
19
42
P0.1/AD1
RD/P3.7
43
P0.0/AD0
XTAL2
TCLK1
20
XTAL2
R222
0
(NC)
C303
33
U304
LM2596S-5.0
+5V
TO263
4
FBK
1
VIN
2
Vout
GND
/ON
D300
5 3
B320
44
VCC X300
20MHz
35
EA/VP
21
XTAL1
GNDNCNCNCNC
C305 C306
33
24LC04
R301R300
10K10K
5
SI
6
SCK
L300 C309
33uH
22UF 0.1
22 1 12 23 34
+5V
U300
R330
8
VCC
10K
C300
0.1
JP221
WP
0
7
WP
JP222
1
A0
2
A1
3
A2
4
VSS
2 1
+5V
D211
BAT54
3
U203
24LC21A3
8
VCC
1
5
SDANC
2
6
SCL
NC
C244
0.1
3
7
VCLK
NC
GND
4
+3.3V
U305
AIC1084
312
VoutVin
C312
C310
GND
330UF
C311
330UF
0.1 35V
35V
330UF 35V
CN302
(Panel-Select)
R320 R322 R324
10K
10K
(NC)
(NC)
0
KEY
1 2 3 4
C304
8 7 6 5
R217
10K
D209
R216
5.5V 10K
D208
5.5V
R101 R102 R103 R104 R105
10K
1/4W
KEY PAD
R318
10K (NC)
R319
SW101 SW102
AUTO KEY
1 2 3 4 5 6 7 8 9
+3.3V
U200
+5V
87 65
RP300
10K
+5V
10K (NC)
R325R323R321
(NC)0(NC)0(NC)
+5V
0
+5V
R329R328
10K10K
1 2 3 4
CP302CP301
10001000
8 7 6 5
R220
100
R219
100
VCC
10K
10K
10K
10K
1/4W
1/4W
1/4W
1/4W
SW104 SW105
SW103
KEY
KEY
LCD
2SC945
C101
KEY
ENTER
LEFT
ON/OFF
RIGHT
0.1
R107 R106
10K 1/4W
4321
HDATA0
99
HDATA
MFB7
105
MFB7
MFB8
104
MFB8
MFB9
102
MFB9
HCLK
103
HCLK
IRQ
101
IRO
HFS
98
HFS
107
MFB5
R317
0
106
MFB6 R316
NC
124
MFB10
123
MFB11
109
MFB4
110
MFB3
MFB2
111
MFB2
112
MFB1
113
VDDA
D202
1N4148
L204
D203
0.15uH
1N4148
VDDA
D204
1N4148
L205
D205
1N4148
VDDA
D206
1N4148
L206 D207
1N4148
+3.3V
R209
R218
2K
100
R213
1K
Q102
Q101
2SC945
DUAL
DP101
LED1
R108
220 1/4W
MFB0
95
RED+
R200
R206
C229
C247
0
75
10nF
22
(NC)
94
RED-
R203
C232
0
10nF
91
GREEN+
R201
R205
C230
0
0
C248
75
10nF
(NC)
GREEN-
90
R207
C233
0
10nF
87
BLUE+
R202
R204
C231
0
0
C249
75
10nF
(NC)
86
BLUE-
R208
C234
0
R210
10nF
2K
150
HSYNC/CS
R214
R212
1K
C236
D201
100
5.6V100
148
VSYNC R211
100
C235
D200
100 5.6V
2
Reserved
3
PSCAN
4
Reserved
5
Reserved
59
Reserved
60
Reserved
83
Reserved
97
NC
130
Reserved
135
Reserved
142
XTAL(Reserved)
145
Reserved
147
Reserved
152
Reserved
153
STI_TM1
JP101
1
VCC
2
LCD ON/OFF
3
KEY LEFT
4
KEY RIGHT
5
KEY ENTER
6
AUTO KEY
7
LED ORANGE LED GREEN
10K 1/4W
CVSS1
1 8 18 30 41 49 61 72 114 126 140 151 158 78 80 81 82 85 89 93 131 132 133 134 127 138 144 146
8 9
GND
C383FA-1
U302
8XC51/PLCC
HDATA0
2
24
P2.0/A8
T2/P1.0
MFB7
3
25
P2.1/A9
T2EX/P1.1
MFB8
4
26
P2.2/A10
P1.2
MFB9
5
27
P2.3/A11
P1.3
HCLK
6
28
P2.4/A12
P1.4
HFS
7
29
P2.5/A13
P1.5
BACKLIGHT_EN
8
30
P2.6/A14
P1.6
PANLE_EN
9
31
P2.7/A15
P1.7
RST
10
32
PSEN
RST
33
ALE/PROG
RXD
11
RXD/P3.0
WP
TXD
13
36
P0.7/AD7
TXD/P3.1
IRQ
14
37
P0.6/AD6
INT0/P3.2
MFB2
15
38
P0.5/AD5
INT1/P3.3
SDA
16
39
P0.4/AD4
T0/P3.4
SCL
17
40
P0.3/AD3
T1/P3.5
R327
10K
R227
100
C251
D210
1nF
5.6V
CN200
RXD
14
TXD
13 12 11
VGA_VSYNC
10
VGA_HSYNC
9
/VGA_CON
8 7 6 5
GREEN
4 3
RED
2 1
CN301
POWER+12V
FB301
+12V
C308
C307
330UF 0.1 35V
COREPOWER
10/24/2000
RST1
18
41
P0.2/AD2
WR/P3.6
/VGA_CON
19
42
P0.1/AD1
RD/P3.7
43
P0.0/AD0
XTAL2
TCLK1
20
XTAL2
R222
0
(NC)
C303
33
U304
LM2596S-5.0
+5V
TO263
4
FBK
1
VIN
2
Vout
GND
/ON
D300
5 3
B320
44
VCC X300
20MHz
35
EA/VP
21
XTAL1
GNDNCNCNCNC
C305 C306
33
R301R300
10K10K
5
SI
6
SCK
L300 C309
33uH
22UF 0.1
22 1 12 23 34
+5V
U300
24LC04
R330
8
VCC
10K
C300
0.1
JP221
WP
0
7
WP
JP222
1
A0
2
A1
3
A2
4
VSS
2 1
+5V
D211
BAT54
3
U203
24LC21A3
8
VCC
1
5
SDANC
2
6
SCL
NC
C244
0.1
3
7
VCLK
NC
GND
4
+3.3V
U305
AIC1084
312
VoutVin
C312
C310
GND
330UF
C311
330UF
0.1 35V
35V
330UF
35V
+3.3V
U200
87 65
RP300
10K
4321
HDATA0
99
MFB7
105
MFB8
104
MFB9
102
HCLK
103
IRQ
101
HFS
98
107
R317
0
106
R316
NC
124
123
109
110
MFB2
111
112
113
95
R200
C229
0
10nF
94
R203
C232
0
10nF
91
R201
C230
0
10nF
90
R207
C233
0
10nF
87
R202
C231
0
10nF
86
R208
C234
0
10nF
150
C236
D201
5.6V100
148
C235
D200
100 5.6V
2
3
4
5
59
60
83
97
130
135
142
145
147
152
153
CVDD2
CVDD1
RVDD2
RVDD1
SRVDD2
SRVDD1
HDATA
MFB7
MFB8
MFB9
HCLK
IRO
HFS
MFB5
MFB6
MFB10
MFB11
MFB4
MFB3
MFB2
MFB1
MFB0
RED+
RED-
GREEN+
GREEN-
BLUE+
BLUE-
HSYNC/CS
VSYNC
Reserved
PSCAN
Reserved
Reserved
Reserved
Reserved
Reserved
NC
Reserved
Reserved
XTAL(Reserved)
Reserved
Reserved
Reserved
STI_TM1
CVSS3
RVSS4
RVSS3
CVSS2
RVSS2
SRVSS1
RVSS1
CVSS1
1 8 18 30 41 49 61 72 114 126 140 151 158 78 80 81 82 85 89 93 131 132 133 134 127 138 144 146
GND
VDDA
RVDDA
DVDDA
SVDDA
TCLK1
+3.3V
R230
14313713612912896928884149139125108797765584033211211
0
TCLK
(NC)
C206
141
SVDD
DVDD
CVDD4
RVDD3
SYN_VDD
ADC_VDDA
ADC_VDD1
ADC_VDD2
ADC_BVDDA
ADC_BGNDA
ADC_GNDA
SUB_GNDA
ADC_GND1
ADC_GND2
SRVSS2
SYN_VSS
SVSS
DVSS
CVSS4
TCLK
PD47
PLL_RVDDA
DAC_SVDDA
PLL_SVDDA
PLL_DVDDA
DAC_DVDDA
ADC_RVDDA
ADC_GVDDA
PD46
PD45 PD44
PD43 PD42 PD41
PD40
PD39 PD38
PD37 PD36 PD35
PD34
PD33 PD32
PD31 PD30 PD29
PD28
PD27 PD26
PD25 PD24 PD23
PD22
PD21 PD20
PD19 PD18 PD17
PD16
PD15 PD14
PD13 PD12 PD11
PD10
PD9 PD8
PD7 PD6 PD5
PD4
PD3 PD2
PD1 PD0 PVS
PHS
PBIAS
PPWR
PDISPE PCLKA PCLKB
OSD_CLK
OSD_VREF
OSD_HREF
OSD_DATA2
OSD_DATA1 OSD_DATA0
OSD_FSW
OSD_DATA3
RESETn
STI_TM2
SCAN_IN1 Reserved
SCAN_IN2 SCAN_OUT1
SCAN_OUT2
SUB_RGNDA
PLL_RGNDA
DAC_SGNDA
DAC_DGNDA
PLL_SGNDA
SUB_SGNDA
SUB_DGNDA
PLL_DGNDA
ADC_RGNDA
ADC_GGNDA
PLL_GNDAADC_AGND
6
7
9 10
13 14 15
16
17 19
20 22 23
24
25 26
27 28 29
31
32 34
35 36 37
38
39 42
46 47 48
50
51 52
53 54 55
56
57 62
63 64 66
67
68 693
70 71 73
74
75 76
43 44 45
117
116
115
120
119 118
122
121
100
154
155 156
157 159
160
PD47
PD46
PD45 PD44 PD43
PD42 PD41
PD40 PD39
PD38 PD37
PD36 PD35
PD34 PD33
PD32 PD31
PD30 PD29
PD28 PD27
PD26 PD25
PD24 PD23
PD22 PD21
PD20 PD19
PD18 PD17
PD16 PD15
PD14 PD13
PD12 PD11
PD10
PD9
PD8 PD7
PD6 PD5
PD4 PD3
PD2 PD1
PD0 PVS
PHS PBIAS
PPWR
PDISPE
PCLKA
PCLK
L207
C262
120
33
R305 R306
10K
10K
(NC)
(NC)
R326
D302
10K
1N4148
R307
C314
22UF
(NC)
C207 C208 C209 C210 C211 C212 C213
22UF
0.1 0.1 0.1 0.1 0.1 0.1 0.1
C216
22UF
L203
C224
1UH
C225 C226 C227 C228
22UF
0.1 0.1 0.1 0.1
L200
C200
1UH
C202C201
22UF
0.10.1
L201
C203
1UH
C205C204
22UF
0.10.1
L202
U201
C237
1UH 50MHz
0.1
1
8
VCC
SB
4 5
OUT
GND
+5V
R303 R304
R302
270
270
270
(NC)
(NC)
(NC)
2
OSD_CLK
10
VREF
5
HREF
15
R
14
G
13
B
12
FBKG
6
SSB
+5V
R312
C313
10K
22UF
(NC)
1N4148
Q300
R313
MMBT3904
10K
(NC)
10K
RST
U301
MTV121 (NC)
NC
3
U303
DS1813 (NC)
2
VCC
GND
1
RST
R229
510
D301
CN201
TCLK1
+3.3V
R230
0
TCLK
(NC)
C206
141
TCLK
PD47
PD46
PD45 PD44
PD43 PD42 PD41
PD40
PD39 PD38
PD37 PD36 PD35
PD34
PD33 PD32
PD31 PD30 PD29
PD28
PD27 PD26
PD25 PD24 PD23
PD22
PD21 PD20
PD19 PD18 PD17
PD16
PD15 PD14
PD13 PD12 PD11
PD10
PD9 PD8
PD7 PD6 PD5
PD4
PD3 PD2
PD1 PD0 PVS
PHS
PBIAS
PPWR
PDISPE
PCLKA PCLKB
OSD_CLK
OSD_VREF
OSD_HREF
OSD_FSW
RESETn
STI_TM2
SCAN_IN1 Reserved
SCAN_IN2
6
7
9 10
13 14 15
16
17 19
20 22 23
24
25 26
27 28 29
31
32 34
35 36 37
38
39 42
46 47 48
50
51 52
53 54 55
56
57 62
63 64 66
67
68 693
70 71 73
74
75 76
43 44 45
117
116
115
120
119 118
122
121
100
154
155 156
157 159
160
PD47
PD46
PD45 PD44 PD43
PD42 PD41
PD40 PD39
PD38 PD37
PD36 PD35
PD34 PD33
PD32 PD31
PD30 PD29
PD28 PD27
PD26 PD25
PD24 PD23
PD22 PD21
PD20 PD19
PD18 PD17
PD16 PD15
PD14 PD13
PD12 PD11
PD10
PD9
PD8 PD7
PD6 PD5
PD4 PD3
PD2 PD1
PD0 PVS
PHS PBIAS
PPWR PDISPE
PCLKA
22UF
C216
22UF
L203
1UH
L200
1UH
L201
1UH
L202
1UH 50MHz
PCLK
L207
C262
120
33
R305 R306
10K
10K
(NC)
(NC)
R326
D302
10K
1N4148
R307
C314
10K
22UF
(NC)
C207 C208 C209 C210 C211 C212 C213
0.1 0.1 0.1 0.1 0.1 0.1 0.1
C224
C225 C226 C227 C228
22UF
0.1 0.1 0.1 0.1
C200
C202C201
22UF
0.10.1
C203
C205C204
22UF
0.10.1
U201
C237
0.1
1
8
VCC
SB
4 5
OUT
GND
+5V
R303 R304
U301
R302
270
270
MTV121
270
(NC)
(NC)
(NC)
(NC)
2
OSD_CLK
10
VREF
5
HREF
15
R
14
G
13
B
12
FBKG
6
SSB
NC
3
U303
DS1813
(NC)
2
VCC
GND
1
RST
R229
510
+5V
R312
C313
10K
D301
22UF
(NC)
1N4148
Q300
R313
MMBT3904
10K
(NC)
RST
PD13-1 PD12-1 PD41-1 PD40-1
1
2
3
CP202
22
8
7
6
PD7-1 PD6-1 PD39-1 PD38-1
1
2
3
CP204
22
8
7
6
PD1-1 PD0-1 PD37-1 PD36-1
1
2
3
CP206
22
8
7
6
R401
10K
JP201
0
Q250 R223
JP202
MMBT3904 10K
PANLE_EN
PD31-1 PD30-1 PD47-1 PD46-1
CP208
22
PD25-1 PD24-1 PD45-1 PD44-1
1
2
3
CP210
22
8
7
6
PD19-1 PD18-1 PD43-1 PD42-1
1
2
3
CP212
22
8
7
6
R309
R311
10K
10K
Q304
MMBT3904
R315
10K
1 2 3 12345
JP301
0
LP201
120
1
8
PD14
2
7
PD15
3
6
PD16
4
5
PD17
2
3
4
7
6
5
LP203
120
PD8
1
8
2
7
PD9
3
6
PD10
4
5
PD11
2
3
4
7
6
5
LP205
120
PD2
1
8
2
7
PD3
3
6
PD4
4
5
PD5
2
3
4
7
6
5
+12V
R224
100K
R225
100K
Q201
C245
Q200
0.1
MMBT3904
R226
C426
0.1
LP207LP208
120120
PD32
11
88
22
77
PD33
33
66
PD34
44
55
PD35
22
33
44
77
66
55
LP209
120
PD26
1
8
2
7
PD27
3
6
PD28
4
5
PD29
2
3
4
7
6
5
LP211
120
PD20
1
8
2
7
PD21
3
6
PD22
4
5
PD23
2
3
4
7
6
5
R522
10K7
VR501
10K
R523
10K7
+12V
CN303
LP202
120
PD13
1
8
2
7
PD12
C223C222C221C220C219C218C217
3
6
PD41
0.10.10.10.10.10.10.1
4
5
PD40
VDDA
DVDDA
SVDDA
RVDDA
C214
C215
22UF
0.1
TCLK
R215
C250
120
0.1
11
HTOME
4
VDD1
9
VDD2
C301 C302
0.1 (NC)
1
VSS1
16
VSS2
SDA
7
SDA
SCL
8
SCL
3
4
5
LP204
120
PD7
1
8
2
7
PD6
3
6
PD39
4
5
PD38
4
5
LP206
120
PD1
1
8
2
7
PD0
3
6
PD37
4
5
PD36
4
5
PPWR
R400
10K
PD31 PD30 PD47 PD46
LP210
120
PD25
1
8
2
7
PD24
3
6
PD45
0.1
4
5
PD44
(NC)
4
5
LP212
120
PD19
1
8
2
7
PD18
3
6
PD43
4
5
PD42
4
5
+5V
PBIAS
Q303
MMBT3904
R314
10K
BACKLIGH
JP300
45
PCLK
44 43
PDISPE
42 41
PVS
40 39
PD14-1
PHS
PD15-1
38
PD16-1
37
PD17-1
36
1
35
CP201
PD17-1
22
34
8
PD16-1
33
PD15-1
32
PD14-1
31 30
PD13-1
29
PD12-1
28
PD41-1
27
PD8-1
PD40-1
PD9-1
26
PD10-1
25
PD11-1
PD11-1
24
1
PD10-1
CP203
23
22
PD9-1
22
8
PD8-1
21 20
PD7-1
19
PD6-1
18
PD39-1
17
PD38-1
16
PD2-1
15
PD3-1
PD5-1
PD4-1
14
PD5-1
PD4-1
13
1
PD3-1
12
CP205
PD2-1
22
11
8
10
PD1-1
9
PD0-1
8
PD37-1
7
PD36-1
6 5
+5V
R526
R528
10K
4
10K
JP201
3
0
+3.3V
2
JP202
R529 R527
1
0 0
MGSF1N03
PANEL_P
3K
PD32-1 PD33-1 PD34-1
CN202
PD35-1
30
11
PD35-1
29
CP207
PD34-1
22
28
88
PD33-1
27
PD32-1
26 25
PD31-1
24
PD30-1
23
PD47-1
22
PD46-1
21
PD26-1
20
PD27-1
PD29-1
PD28-1
19
PD29-1
PD28-1
18
1
PD27-1
17
CP209
PD26-1
22
16
8
15
PD25-1
14
PD24-1
13
PD45-1
12
PD44-1
11 10
PD23-1
PD20-1
9
PD22-1
PD21-1
8
PD22-1
PD21-1
7
PD23-1
PD20-1
1
8
6
CP211
5
22
PD19-1
4
PD18-1
3
PD43-1
2
PD42-1
1
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