FUJITSU MBM29SL800TD, MBM29SL800BD DATA SHEET

查询MBM29SL800TD-10供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

8 M (1 M

8/512 K

××××

××××

MBM29SL800TD/BD

DESCRIPTION

■

The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , 48-ball FBGA and 48-ball
SCSP packages. These devices are designed to be programmed in-system with the standard system 3.0 V V
supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be repro­grammed in standard EPROM programmers.

PRODUCT LINE UP

■

DS05-20871-5E

16) BIT

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CC

(Continued)

Part No. MBM29SL800TD/MBM29SL800BD

Ordering Part No. V
Max Address Access Time (ns) 100 120
Max CE
Max OE

■

Access Time (ns) 100 120
Access Time (ns) 35 50

PACKAGES

48-pin Plastic TSOP (I) 48-pin Plastic TSOP (I) 48-pin Plastic FBGA 48-pin Plastic SCSP

Marking Side

(FPT-48P-M19) (FPT-48P-M20) (BGA-48P-M12) (WLP-48P-M03)

CC = +2.0 V ± 0.2 −10 −12

Marking Side

MBM29SL800TD

(Continued)

The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE
write enable (WE

The MBM29SL800TD/BD are pin and command set compatible with JEDEC standard E
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry . Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29SL800TD/BD are programmed by executing the program command sequence. This will inv oke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and ver ified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.

A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29SL800TD/BD are erased when shipped from the
fac to r y.

) , and output enable (OE) controls.

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/MBM29SL800BD

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2

PROMs. Commands

) ,

The devices f eature single 1.8 V po wer supply oper ation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data
by the Toggle Bit feature on DQ
completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E
of quality, reliability, and cost effectiveness. The MBM29SL800TD/BD memor ies electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are prog rammed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.

6, or the RY/BY output pin. Once the end of a program or erase cycle has been

2

PROM experience to produce the highest levels

CC detector automatically

Polling of DQ7,

2

MBM29SL800TD

FEATURES

■

•

Single 1.8 V read, program, and erase

Minimizes system level power requirements

•

Compatible with JEDEC-standard commands

2

Uses same software commands as E

•

Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
48-ball SCSP (Package suffix : PW)

• Minimum 100,000 program/erase cycles

•

High performance

100 ns maximum access time

•

Sector erase architecture

One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase

•

Boot Code Sector Architecture

T = Top sector
B = Bottom sector

•

Embedded Erase

Automatically pre-programs and erases the chip or any sector

•

Embedded Program

Automatically writes and verifies data at specified address

•Data

•

•

•

•

• Sector Protection set function by Extended sector Protect command

• Fast programming Function by Extended Command

•

Polling and Toggle Bit feature for detection of program or erase cycle completion

Ready/Busy output (RY/BY

Hardware method for detection of program or erase cycle completion

Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode

Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

Sector protection

Hardware method disables any combination of sectors from program or erase operations

Temporary sector unprotection

Temporary sector unprotection via the RESET

TM

Algorithms

TM

Algorithms

)

PROMs

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pin

/MBM29SL800BD

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Embedded Erase

TM

and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

3

MBM29SL800TD

PIN ASSIGNMENTS

■

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/MBM29SL800BD

TSOP (I)

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A15
A14
A13
A12
A11
A10

N.C.
N.C.

WE

RESET

N.C.
N.C.

RY/BY

A
A17

A1
A2
A3
A4
A5
A6

A7
A17
A18

RY/BY

N.C.
N.C.

RESET

WE
N.C.
N.C.

A

A9
A10
A11
A12
A13
A14
A15

A9
A8

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

18

16
17
18
19
20
21
22
23
24

(Marking Side)

Normal Bend

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V

SS

CE
A0

(FPT-48P-M19)

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9

8

8
7
6
5
4
3
2
1

(Marking Side)

Reverse Bend

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A0
CE
V

SS

OE
DQ

0

DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A

16

(FPT-48P-M20)

(Continued)

4

(Continued)

MBM29SL800TD

FBGA

(TOP VIEW)

Marking side

A6 B6 C6 D6 E6 F6 G6 H6

A

13 A12 A14 A15 A16 DQ15/A-1 VSS

A5 B5 C5 D5 E5 F5 G5 H5
A

9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

A4 B4 C4 D4 E4 F4 G4 H4

WE RESET N.C. N.C. DQ

A3 B3 C3 D3 E3 F3 G3 H3

RY/BY N.C. A

A2 B2 C2 D2 E2 F2 G2 H2
A

7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

18 N.C. DQ2 DQ10 DQ11 DQ3

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/MBM29SL800BD

BYTE

5 DQ12 VCC DQ4

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A1 B1 C1 D1 E1 F1 G1 H1
A

3 A4 A2 A1 A0 CE OE VSS

(BGA-48P-M12)

SCSP

(TOP VIEW)

Marking side

A6

B6A4C6A2D6A1E6A0F6

A3

A5

A7B5A17C5A6

A4

RY/BYB4N.C.C4A18D4N.C.E4DQ2F4DQ10G4DQ11H4DQ3

A3

WEB3RESETC3N.C.D3N.C.E3DQ5F3DQ12G3VCCH3DQ4

A2

B2A8C2

A9

A10D2A11E2DQ7F2DQ14G2DQ13H2DQ6

D5A5E5

DQ0F5DQ8G5DQ9H5DQ1

CEG6OEH6VSS

A1

A13B1A12C1A14D1A15E1A16F1BYTE

(WLP-48P-M03)

G1

DQ15/A-1

H1

VSS

5

MBM29SL800TD

PIN DESCRIPTION

■

Pin name Function

A

18 to A0, A-1 Address Inputs

DQ

15 to DQ0 Data Inputs/Outputs

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/MBM29SL800BD

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CE
OE

WE Write Enable

RESET

RY/BY

BYTE Selects 8-bit or 16-bit mode

V

SS Device Ground

V

CC Device Power Supply

N.C. No Internal Connection

Chip Enable
Output Enable

Hardware Reset Pin/Temporary Sector Unprotection
Ready/Busy Output

6

BLOCK DIAGRAM

■

MBM29SL800TD

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/MBM29SL800BD

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VCC
VSS

WE

BYTE

RESET

CE
OE

RY/BY

Buffer

State

Control

Command

Register

Low V

CC Detector

RY/BY

Program Voltage

Generator

Timer for

Program/Erase

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

STB

DQ15 to DQ0

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

A

18 to A0

A-1

LOGIC SYMBOL

■

19

A-1

18 to A0

A

CE
OE
WE
RESET
BYTE

Address Latch

16 or 8

DQ15 to DQ0

RY/BY

7

MBM29SL800TD

DEVICE BUS OPERATION

■

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/MBM29SL800BD

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MBM29SL800TD/800BD User Bus Operations Table (BYTE

Operation CE

Auto-Select Manufacturer Code *
Auto-Select Device Code *
Read *

3

1

0

1

OE WE A

1

LLHLLLVID Code H

A

6

A

LLHHLLVID Code H
LLHA0 A1 A6 A9 DOUT H

====

VIH)

9

A

DQ0 to DQ15RESET

Standby H X X X X X X High-Z H
Output Disable L H H X X X X High-Z H
Write (Program/Erase) L H L A
Enable Sector Protection *
Verify Sector Protection *

2, *4

2, *4

LVID LHLVID XH
LLHLHLVID Code H

Temporary Sector Unprotection XXXXXXX X V

0 A1 A6 A9 DIN H

ID

Reset (Hardware) /Standby XXXXXXX High-Z L

MBM29SL800TD/800BD User Bus Operations Table (BYTE

Operation CE

Auto-Select Manufacturer Code *
Auto-Select Device Code *
Read *

3

1

OE WE

1

LLHLLLLVID Code H

DQ15/

A-

0

A

1

1

A

LLHLHLLVID Code H
LLHA-1 A0 A1 A6 A9 DOUT H

====

VIL)

9

DQ0 to

7

DQ

RESET

6

A

A

Standby H X X X XXXXHigh-Z H
Output Disable LHHXXXXXHigh-Z H
Write (Program/Erase) L H L A­Enable Sector Protection *
Verify Sector Protection *

2, *4

2, *4

Temporary Sector Unprotection *

LVID LLHLVID XH
LLHLLHLVID Code H

5

XXXXXXXX X VID

1 A0 A1 A6 A9 DIN H

Reset (Hardware) /Standby X X X X XXXXHigh-Z L

Legend : L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29SL800TD/800BD Standard Command Definitions Table”.
*2: Refer to the section on Sector Protection.
*3: WE
*4: V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

CC = 2.0 V ± 10%

*5: It is also used for the extended sector protection.

8

MBM29SL800TD

MBM29SL800TD/800BD Standard Command Definitions Table

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/MBM29SL800BD

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Command

Sequence

Read/
Reset

Read/
Reset

Autoselect

Program

Chip
Erase

Sector
Erase

Sector Erase Suspend Erase can be suspended during sector erase with Addr. (“H” or “L”) . Data (B0h)
Sector Erase Resume Erase can be resumed after suspend with Addr. (“H” or “L”) . Data (30h)

Word

Byte

Word

Byte AAAh 555h AAAh

Word

Byte AAAh 555h AAAh

Word

Byte AAAh 555h AAAh

Word

Byte AAAh 555h AAAh AAAh 555h AAAh

Word

Byte AAAh 555h AAAh AAAh 555h

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

1 XXXh F0h 

555h

3

555h

3

555h

4

555h

6

555h

6

AAh

AAh

AAh

AAh

AAh

Second Bus

Write Cycle

2AAh

55h

2AAh

55h

2AAh

55h

2AAh

55h

2AAh

55h

Third Bus

Write Cycle

555h

555h

555h

555h

555h

Fourth Bus

Read/Write

Cycle

F0h RA RD 

90h 

A0h PA PD 

555h

80h

555h

80h

AAh

AAh

Fifth Bus

Write Cycle

2AAh

55h

2AAh

55h SA 30h

Sixth Bus

Write Cycle

555h

10h

Notes : • Address bits A

Sector Address (SA)

• Bus operations are defined in “MBM29SL800TD/800BD User Bus Operations Tables (BYTE
BYTE

= VIL)”.

• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the WE

SA = Address of the sector to be erased. The combination of A

uniquely select any sector.

• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE

• The system should generate the following address patterns :

Word Mode : 555h or 2AAh to addresses A
Byte Mode : AAAh or 555h to addresses A-1 and A0 to A10

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in “MBM29SL800TD/800BD Standard Command Definitions

Table” and “MBM29SL800TD/BD Extended Command Definitions Table” are illegal.

11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA) and

= VIH and

pulse.

18, A17, A16, A15, A14, A13, and A12 will

.

0 to A10

9

MBM29SL800TD

MBM29SL800TD/BD Extended Command Definitions Table

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/MBM29SL800BD

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Bus

Command

Sequence

Write

Cycles

Req'd

Set to
Fast Mode

Fast Program*

Reset from Fast

1

Mode*
Extended Sector

Protect*

2

Word

Byte AAAh 555h AAAh

Word

1

Byte XXXh

Word

Byte XXXh XXXh

Word

Byte

3

2

2

4 XXXh 60h SPA 60h SPA 40h SPA SD

SPA : Sector address to be protected. Set sector address (SA) and (A

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus
Read Cycle

Addr Data Addr Data Addr Data Addr Data

555h

XXXh

XXXh

AAh

A0h PA PD 

90h

2AAh

XXXh

55h

F0h*

6, A1, A0) = (0, 1, 0) .

555h

3



20h 

SD : Sector protection verify data. Output 01h at protected sector address and output 00h at unprotected sector

address.
*1 : This command is valid during Fast Mode.
*2 : This command is valid while RESET

= VID.

*3 : The data “00h” is also acceptable.

MBM29SL800TD/800BD Sector Protection Verify Autoselect Codes Table

12

18

Type A

to A

Manufacture’s Code X V

MBM29SL800TD

Device Code

MBM29SL800BD

Sector Protection

Byte
Word X 22EAh
Byte
Word X 226Bh

XV

XV

Sector

Address

6

A

IL VIL VIL VIL 04h
IL VIL VIH

IL VIL VIH

V

IL VIH VIL VIL 01h*

1

A

0

A

1

A-1*

Code (HEX)

VIL EAh

VIL 6Bh

2

*1 : A

−

is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A

1

−

, the lowest address.

1

*2 : Outputs 01h at protected sector address and outputs 00h at unprotected sector address.

Extended Autoselect Code Table

Type Code

Manufacturer’s Code 04h

(B) * EAh A­ (W)
(B) * 6Bh A­ (W)

Device
Code

MBM29SL
800TD

MBM29SL
800BD

Sector Protection 01h

* : At Byte mode, DQ

8 to DQ14 are High-Z and DQ15 is A

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

A-1/0

22EAh

226Bh

A-1/0

000000000000100

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

1

11101010

0010001011101010

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

1

01101011

0010001001101011

000000000000001

−

, the lowest address.

1

(B) : Byte mode
(W) : Word mode
HI-Z : High-Z

10

0

MBM29SL800TD

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■

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• One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes

• Individual-sector, multiple-sector, or bulk-erase capability

• Individual or multiple-sector protection is user definable.

(×8) (×16) (×8) (×16)

/MBM29SL800BD

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16 Kbyte

8 Kbyte

8 Kbyte
32 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte

FFFFFh
FBFFFh
F9FFFh
F7FFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
00000h

7FFFFh
7DFFFh
7CFFFh
7BFFFh
77FFFh
6FFFFh
67FFFh
5FFFFh
57FFFh
4FFFFh
47FFFh
3FFFFh
37FFFh
2FFFFh
27FFFh
1FFFFh
17FFFh
0FFFFh
07FFFh
00000h

64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte

8 Kbyte
8 Kbyte

16 Kbyte

FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
07FFFh
05FFFh
03FFFh
00000h

7FFFFh
77FFFh
6FFFFh
67FFFh
5FFFFh
57FFFh
4FFFFh
47FFFh
3FFFFh
37FFFh
2FFFFh
27FFFh
1FFFFh
17FFFh
0FFFFh
07FFFh
03FFFh
02FFFh
01FFFh
00000h

MBM29SL800TD Sector Architecture MBM29SL800BD Sector Architecture

11

MBM29SL800TD

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Sector Address Table (MBM29SL800TD)

/MBM29SL800BD

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Sector

Address

SA0 0000XXX00000h to 0FFFFh 00000h to 07FFFh
SA1 0001XXX10000h to 1FFFFh 08000h to 0FFFFh
SA2 0010XXX20000h to 2FFFFh 10000h to 17FFFh
SA3 0011XXX30000h to 3FFFFh 18000h to 1FFFFh
SA4 0100XXX40000h to 4FFFFh 20000h to 27FFFh
SA5 0101XXX50000h to 5FFFFh 28000h to 2FFFFh
SA6 0110XXX60000h to 6FFFFh 30000h to 37FFFh
SA7 0111XXX70000h to 7FFFFh 38000h to 3FFFFh
SA8 1000XXX80000h to 8FFFFh 40000h to 47FFFh
SA9 1001XXX90000h to 9FFFFh 48000h to 4FFFFh
SA10 1010XXXA0000h to AFFFFh50000h to 57FFFh
SA11 1011XXXB0000h to BFFFFh58000h to 5FFFFh
SA12 1100XXXC0000h to CFFFFh60000h to 67FFFh
SA13 1101XXXD0000h to DFFFFh68000h to 6FFFFh
SA14 1110XXXE0000h to EFFFFh70000h to 77FFFh
SA15 11110XXF0000h to F7FFFh78000h to 7BFFFh

18

A

17

A

16

A

15

A

14

A

13

A

12

A

Address Range (

××××

8) Address Range (

××××

16)

SA16 1111100F8000h to F9FFFh7C000h to 7CFFFh
SA17 1111101FA000h to FBFFFh7D000h to 7DFFFh
SA18 111111XFC000h to FFFFFh 7E000h to 7FFFFh

12

MBM29SL800TD

Sector Address Table (MBM29SL800BD)

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/MBM29SL800BD

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Sector

Address

SA0 000000X00000h to 03FFFh 00000h to 01FFFh
SA1 000001004000h to 05FFFh 02000h to 02FFFh
SA2 000001106000h to 07FFFh 03000h to 03FFFh
SA3 00001XX08000h to 0FFFFh 04000h to 07FFFh
SA4 0001XXX10000h to 1FFFFh 08000h to 0FFFFh
SA5 0010XXX20000h to 2FFFFh 10000h to 17FFFh
SA6 0011XXX30000h to 3FFFFh 18000h to 1FFFFh
SA7 0100XXX40000h to 4FFFFh 20000h to 27FFFh
SA8 0101XXX50000h to 5FFFFh 28000h to 2FFFFh
SA9 0110XXX60000h to 6FFFFh 30000h to 37FFFh
SA10 0111XXX70000h to 7FFFFh 38000h to 3FFFFh
SA11 1000XXX80000h to 8FFFFh 40000h to 47FFFh
SA12 1001XXX90000h to 9FFFFh 48000h to 4FFFFh
SA13 1010XXXA0000h to AFFFFh50000h to 57FFFh
SA14 1011XXXB0000h to BFFFFh58000h to 5FFFFh
SA15 1100XXXC0000h to CFFFFh60000h to 67FFFh

18

A

17

A

16

A

15

A

14

A

13

A

12

A

Address Range (

××××

8) Address Range (

××××

16)

SA16 1101XXXD0000h to DFFFFh68000h to 6FFFFh
SA17 1110XXXE0000h to EFFFFh70000h to 77FFFh
SA18 1111XXXF0000h to FFFFFh78000h to 7FFFFh

13

MBM29SL800TD

FUNCTIONAL DESCRIPTION

■

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/MBM29SL800BD

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Read Mode

The MBM29SL800TD/BD have two control functions which m ust be satisfied in order to obtain data at the outputs.
CE

is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.
Address access time (t

access time (t

CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE

ACC) is equal to the delay from stable addresses to valid output data. The chip enable

to valid data at the output pins. (Assuming the
addresses have been stab le for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE

pin from “H” to “L”

Standby Mode

There are two ways to implement the standby mode on the MBM29SL800TD/BD devices, one using both the
CE

and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time
(t

CE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is

required even CE

= “H”.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE

= “H” or “L”) . Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken

high, the device requires t

RH of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29SL800TD/800BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.

To activate this mode, MBM29SL800TD/800BD automatically switch themselves to low power mode when
MBM29SL800TD/800BD addresses remain stably during access fine of 150 ns. It is not necessary to control
CE

, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) .

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29SL800TD/800BD read-out the data for changed addresses.

Output Disable

With the OE

input at a logic high level (VIH) , output from the devices are disabled. This will cause the output

pins to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding prog ramming algorithm. This mode is functional over the
entire temperature range of the devices.

To activate this mode, the programming equipment m ust force V
bytes may then be sequenced from the de vices outputs b y toggling address A
DON’T CARES except A

0, A1, A6, and A-1. (See “MBM29SL800TD/800BD Sector Protection Verify Autoselect

ID (10 V to 11 V) on address pin A9. Two identifier

0 from VIL to VIH. All addresses are

Codes Table” in ■DEVICE BUS OPERATION.)
The manufacturer and device codes may also be read via the command register, for instances when the

MBM29SL800TD/BD are erased or programmed in a system without access to high vo ltage on the A
command sequence is illustrated in “MBM29SL800TD/800BD Standard Command Definitions Table” (in ■DE-
VICE BUS OPERATION). (Refer to Autoselect Command section.)

Byte 0 (A

0 = VIL) represents the manufacturer’ s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier

code (MBM29SL800TD = EAh and MBM29SL800BD = 6Bh for ×8 mode; MBM29SL800TD = 22EAh and
MBM29SL800BD = 226Bh for ×16 mode) . These two bytes/words are giv en in “MBM29SL800TD/800BD Sector
Protection V erify Autoselect Codes T able and Extended Autoselect Code Table (in ■DEVICE BUS OPERA TION”).

14

9 pin. The

MBM29SL800TD

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/MBM29SL800BD

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All identifiers for manufactures and device will exhibit odd parity with DQ
read the proper device codes when executing the autoselect, A

1 must be VIL. (See “MBM29SL800TD/800BD

7 defined as the parity bit. In order to

Sector Protection Verify Autoselect Codes Table and Extended Autoselect Code Table in ■DEVICE BUS OP­ERATION”.)

Write

Device erasure and progr amming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com­mand register is written by bringing WE
falling edge of WE

or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Protection

The MBM29SL800TD/BD feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 18) . The sector protection f eature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V
CE

= VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to

ID on address pin A9 and control pin OE,

be protected. “Sector Address Tables (MBM29SL800TD/BD)” in ■FLEXIBLE SECTOR-ERASE ARCHITEC­TURE define the sector address for each of the nineteen (19) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE
rising edge of the same. Sector addresses must be held constant during the WE

pulse and is terminated with the

pulse. See “(13) Sector
Protection Timing Diagram” in ■TIMING DIAGRAM and “(5) Sector Protection Algor ithm” in ■FLOW CHART
for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must f orce V

ID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while
(A

6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the

devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A

0, A1, and A6

are DON’T CARES. Address locations with A1 = VIL are reserved for A utoselect manuf acturer and de vice codes.
A-

1 requires to apply to VIL on byte mode.

Temporary Sector Unprotection

This feature allows tempor ary unprotection of previously protected sectors of the MBM29SL800TD/BD devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET

pin to high voltage
(VID) . During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the V

ID is taken awa y from the RESET pin, all the prev iously protected sectors will be protected

again. See “(14) Temporary Sector Unprotection Timing Diagram” in ■TIMING DIAGRAM and “(6) Temporar y
Sector Unprotection Algorithm” in ■FLOW CHART.

RESET

Hardware Reset

The MBM29SL800TD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (V

IL) for at least 500 ns in order to properly reset the internal state machine.

Any operation in the process of being executed will be ter minated and the inter nal state machine will be reset
to the read mode 20 µs after the RESET
devices require an additional t

RH before it will allow read access. When the RESET pin is low, the devices will

pin is driven low. Fur thermore, once the RESET pin goes high, the

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY

output signal should be ignored during the RESET pulse. See “(9) RESET, RY/BY Timing
Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.

15

MBM29SL800TD

COMMAND DEFINITIONS

■

Device operations are selected by writing specific address and data sequences into the command register.
“MBM29SL800TD/800BD Standard Command Definitions Table” in ■DEVICE BUS OPERATION defines the
valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands
are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are
functionally equivalent, resetting the device to the read mode. Please note that commands are always written
at DQ

0 to DQ7 and DQ8 to DQ15 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ
operation is initiated by writing the Read/Reset command sequence into the command register . Microprocessor
read cycles retrieve array data from the memor y. The devices remain enabled for reads until the command
register contents are altered.

The devices will automatically power-up in the read/reset state . In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character­istics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM pro­grammers typically access the signature codes by raising A
onto the address lines is not generally desired system design practice.

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/MBM29SL800BD

5 = 1) to read/reset mode, the read/reset

9 to a high voltage. How ever, multiple xing high voltage

-10/12

The device contains an A utoselect command operation to supplement tr aditional PR OM programming method­ology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retriev es the man ufacture code of 04h. A read
cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29SL800TD = EAh and
MBM29SL800BD = 6Bh for ×8 mode; MBM29SL800TD = 22EAh and MBM29SL800BD = 226Bh for ×16
mode) . (See “MBM29SL800TD/800BD Sector Protection Verify Autoselect Codes Table and Extended
Autoselect Code Table in ■DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd
parity with DQ
XX02h for ×16 (XX04h for ×8) .
Scanning the sector addresses (A
logical “1” at device output DQ
mode on the protected sector. (See “MBM29SL800TD/800BD User Bus Oper ations T able (BYTE
= VIL)” in ■DEVICE BUS OPERATION.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.

Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE
latched on the rising edge of CE
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the

7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address

18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a

0 for a protected sector. The programming verification should be perform margin

= VIH and BYTE

or WE, whichever happens later and the data is

or WE, whichever happens first. The r ising edge of CE or WE (whichever

7 is equivalent to data written to this

16

MBM29SL800TD

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/MBM29SL800BD

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system at this particular instance of time. Hence, Data
is being programmed.

If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being
written.

Programming is allowed in any sequence and across sector boundar ies. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.

“(1) Embedded Program
typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” wr ite cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase
Algorithm command sequence the devices will automatically program and ver ify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE
when the data on DQ
mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“(2) Embedded Erase

command strings and bus operations.

TM

Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using

7 is “1” (See Write Operation Status section.) at which time the device returns to read the

TM

Algorithm” in ■FLOW CHART illustr ates the Embedded EraseTM Algorithm using typical

Polling m ust be perf ormed at the memory location which

pulse in the command sequence and terminates

Sector Erase

Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then follo wed b y the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE
(Data = 30h) is latched on the rising edge of WE
erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently b y writing the six bus cycle operations on “MBM29SL800TD/800BD
Standard Command Definitions Table” in ■DEVICE BUS OPERATION. This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recom­mended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last
WE

will initiate the ex ecution of the Sector Er ase command (s) . If another falling edge of the WE occurs within
the 50 µs time-out window the timer is reset. (Monitor DQ
open, see section DQ
data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the
Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase b uff er may be done
in any sequence and with any number of sectors (0 to 18) .

Sector erase does not require the user to program the de vices prior to erase. The devices automatically progr am
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y
controls or timings during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE
sector erase command pulse and terminates when the data on DQ
at which time the devices return to the read mode. Data

3, Sector Erase Timer.) Resetting the devices once execution has begun will corrupt the

. After time-out of 50 µs from the rising edge of the last sector

3 to determine if the sector erase timer window is still

7 is “1” (See Write Operation Status section.)

polling must be performed at an address within any of

, while the command

pulse for the last

17

MBM29SL800TD

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/MBM29SL800BD

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the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogr am­ming) ] × Number of Sector Erase

TM

“(2) Embedded Erase

Algorithm” in ■FLOW CHART illustr ates the Embedded EraseTM Algorithm using typical

command strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perf orm data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. Writting the Erase Suspend command during the
Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.

Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximu m
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the
RY/BY

output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address

of the erasing sector for reading DQ

6 and DQ7 to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices def ault to the er ase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successiv ely reading from the er ase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ

2 to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device b y writing the appropriate com­mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro­gramming in this mode is the same as programming in the regular Progr am mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ
suspended Program operation is detected by the RY/BY
(DQ

6) which is the same as the regular Program operation. Note that DQ7 must be read from the Progr am address

while DQ

6 can be read from any address.

output pin, Data polling of DQ7, or by the Toggle Bit I

2 to toggle. The end of the erase-

To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

Extended Command
(1) Fast Mode

MBM29SL800TD/BD has Fast Mode function. This mode dispenses with the initial tw o uncloc k cycles required
in the standard program command sequence by writing F ast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register.
(Refer to “(8) Embedded Programming Algorithm f or Fast Mode” in ■FLOW CHART Extended algorithm.) The
V

CC active current is required even CE = VIH during Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by wr iting program set-up command (A0h) and data write cycles (PA/PD) . (Refer to the
“(8) Embedded Programming Algorithm for Fast Mode” in ■FLOW CHART Extended algorithm.)

(3) Extended Sector Protection

In addition to normal sector protection, the MBM29SL800TD/BD has Extended Sector Protection as extended
function. This function enable to protect sector by forcing V

ID on RESET pin and write a commnad sequence.

18

MBM29SL800TD

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/MBM29SL800BD

-10/12

Unlike conv entional procedure, it is not necessary to force V

ID and control timing for control pins. The only RESET

pin requires VID for sector protection in this mode. The e xtended sector protect requires VID on RESET pin. With
this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then,
the sector addresses pins (A
sector to be protected (recommend to set V

18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the

IL for the other addresses pins) , and write extended sector protect

command (60h) . A sector is typically protected in 250 µs. To verify programming of the protection circuitry, the
sector addresses pins (A
command (40h) . Following the command write, a logical “1” at device output DQ

18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a

0 will produce for protected

sector in the read operation. If the output data is logical “0”, please repeat to write extended sector protect
command (60h) again. To terminate the operation, it is necessary to set RESET

pin to VIH.

Write Operation Status

Hardware Sequence Flags Table

Status DQ

Embedded Program Algorithm DQ

7

7 Toggle 0 0 1

DQ

6

DQ

5

DQ

3

Embedded Erase Algorithm 0 Toggle 0 1 Toggle*

In Progress

Erase
Suspended
Mode

Erase Suspend Read
(Erase Suspended Sector)

Erase Suspend Read
(Non-Erase Suspended Sector)

Erase Suspend Program
(Non-Erase Suspended Sector)

1 1 0 0 Toggle

Data Data Data Data Data

DQ

7 Toggle 0 0 1*

DQ

2

1

2

Embedded Program Algorithm DQ7 Toggle 1 0 1

Exceeded
Time Limits

*1:Successive reads from the erasing or erase-suspend sector causes DQ

Embedded Erase Algorithm 0 Toggle 1 1 N/A
Erase

Suspended
Mode

Erase Suspend Program
(Non-Erase Suspended Sector)

DQ

7 Toggle 1 0 N/A

2 to toggle.

*2:Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.

7

DQ

Data Polling

The MBM29SL800TD/BD devices feature Data

Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data

Polling (DQ7) is shown in “(3) Data Polling Algorithm” in ■FLOW CHART.

7. Upon completion of the Embedded Program

7. During the Embedded

7 output. Upon completion of the

7 output. The flowchart

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data

Polling m ust be perf ormed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29SL800TD/BD data pins (DQ
enable (OE

) is asserted low. This means that the devices are dr iving status information on DQ7 at one instant

7) may change asynchronously while the output

of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ

7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm

19

MBM29SL800TD

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/MBM29SL800BD

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operation and DQ

7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0

to DQ7 will be read on the successive read attempts.
The Data

Polling f eature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out. (See “Hardware Sequence Flags Table”.)
See “(6) Data

Data

Polling timing specifications and diagrams.

6

DQ

Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the

Toggle Bit I

The MBM29SL800TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE
the devices will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the f ourth WE

6 toggling between one and zero . Once the Embedded Progr am or Erase Algorithm

6 will stop toggling and valid data will be read on the next successive attempts. During

pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE

toggling) data from

pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop

toggling without the data having changed. In erase, the de vices will erase all the selected sectors e xcept f or the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.

Either CE
cause the DQ

or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

6 to toggle.

See “(7) AC W a v eforms f or Toggle Bit I during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagrams.

5

DQ

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (inter nal pulse count) . Under
these conditions DQ
cycle was not successfully completed. Data
condition. The CE
The OE

and WE pins will control the output disable functions as described in “MBM29SL800TD/800BD User

Bus Operations Table (BYTE
The DQ

5 failure condition may also appear if a user tries to progr am a non blank location without er asing. In this

5 will produce a “1”. This is a failure condition which indicates that the program or erase

Polling is the only operating function of the devices under this

circuit will partially power down the device under these conditions (to approximately 2 mA) .

= VIH and BYTE = VIL)” (in ■DEVICE BUS OPERATION).

case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
DQ

5 bit will indicate a “1.” Please note that this is not a device f ailure condition since the devices were incorrectly

7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the

used. If this occurs, reset the device with command sequence.

3

DQ

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data

Polling and Toggle Bit are valid after the initial sector erase

command sequence.
If Data

Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun. If DQ

3 is low (“0”) the device will accept additional sector erase commands. To insure

the command has been accepted, the system software should check the status of DQ
each subsequent Sector Erase command. If DQ

3 were high on the second status check, the command ma y not

3 is high (“1”) the internally controlled

3 prior to and following

have been accepted.

20

MBM29SL800TD

See “Hardware Sequence Flags Table”.

2

DQ

Toggle Bit II

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/MBM29SL800BD

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This toggle bit II, along with DQ

6, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ

2 to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successiv e reads from the er ase-suspended sector will cause
DQ

2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ

2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ

7, is summarized

as follows :
For ex ample, DQ

(DQ

2 toggles while DQ6 does not.) See also “Hardware Sequence Flags T able” and “(15) DQ 2 vs. DQ6” in ■TIMING

2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

DIAGRAM.
Furthermore, DQ

mode, DQ

2 toggles if this bit is read from an erasing sector.

Reading Toggle Bits DQ

2 can also be used to determine which sector is being erased. When the device is in the erase

6

2

/DQ

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or er ase oper ation. The system can
read array data on DQ

7 to DQ0 on the following read cycle.

Howev er, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ

5 is high (see the section on DQ5) . If it is, the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the progra m or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system m ust write
the reset command to return to reading array data.

5

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ

5 through successive read cycles, deter-

5 has not

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status
of the operation. (Refer to “Toggle Bit Algorithm” in “■FLOW CHART”.)

Toggle Bit Status

Mode DQ

7

DQ

6

DQ

2

Program DQ7 Toggle 1
Erase 0 Toggle Toggle*
Erase-Suspend Read

(Erase-Suspended Sector)
Erase-Suspend Program DQ

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ

11Toggle

7 Toggle 1*

2 to toggle.

1

2

*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit.

21

MBM29SL800TD

RY/BY

Ready/Busy

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/MBM29SL800BD

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The MBM29SL800TD/BD provide a RY/BY
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any
read/write or erase operation. If the MBM29SL800TD/BD are placed in an Erase Suspend mode, the RY/BY
output will be high.

During programming, the RY/BY
operation, the R Y/BY
busy condition during the RESET
Timing Diagram” and “(9) RESET
The RY/BY

Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY

Byte/Word Configuration

The BYTE
this pin is driven high, the devices operate in the w ord (16-bit) mode . The data is read and prog rammed at DQ
to DQ15. When this pin is driven low, the devices oper ate in byte (8-bit) mode . Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “(10) Timing Diagram for Word Mode Configuration” and “(11) Timing Diagram for Byte Mode Configuration”
and “(12) BYTE

Data Protection

The MBM29SL800TD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system lev el signals that ma y exist during power transitions. During power up the devices automat­ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The devices also incorporate several features to prevent inadver tent wr ite cycles resulting form V
and power-down transitions or system noise.

pin is pulled high in standby mode.

pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29SL800TD/BD devices. When

pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

Timing Diagram for Write Operations” in ■TIMING DIAGRAM for the timing diagram.

pin is driven low after the rising edge of the fourth WE pulse. During an erase

pulse. Refer to “(8) RY/BY Timing Diagram during Program/Erase Operation

, RY/BY Timing Diag ram” in ■TIMING DIAGRAM f or a detailed timing diagram.

open-drain output pin as a way to indicate to the host system that

CC; multiples of devices may

pin in parallel.

8 to DQ14 bits are tri-stated. Howev er, the command b us cycle is alwa ys

0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer

CC power-up

0

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE

Logical Inhibit

Writing is inhibited by holding any one of OE
must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the devices with WE
The internal state machine is automatically reset to the read mode on power-up.

Sector Protection

Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressd to protected sectors.

Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in

■ FUNCTIONAL DESCRIPTION) .

22

= CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

, CE, or WE will not initiate a write cycle.

= VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

MBM29SL800TD

ABSOLUTE MAXIMUM RATINGS

■

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/MBM29SL800BD

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Parameter Symbol

Storage Temperature Tstg −55 +125 °C
Ambient Temperature with Power Applied T
Voltage with Respect to Ground All pins except A

OE

, and RESET *1,*
A9, OE, and RESET *
Power Supply Voltage *

*1:Voltage is defined on the basis of VSS = GND = 0 V.
*2:Minimum DC voltage on input or I/O pins is −0.5 V. During voltage tr ansitions, input or I/O pins ma y undershoot

VSS to −2.0 V for periods of up to 20 ns. Maximum DC v oltage on input or I/O pins is VCC + 0.5 V . During v oltage
transitions, input or I/O pins may overshoot to V

*3:Minimum DC input voltage on A

pins may undershoot VSS to −2.0 V for periods of up to 20 ns. V oltage diff erence between input and supply voltage
(V

IN - VCC) does not exceed +9.0 V. Maximum DC input v oltage on A9, OE and RESET pins is +11.5 V which ma y

overshoot to +12.5 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

2

1,*3

1

9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET

9,

CC + 2.0 V for periods of up to 20 ns.

A −40 +85 °C

VIN, VOUT −0.5 VCC + 0.5 V

VIN −0.5 +11.5 V

VCC −0.5 +3.0 V

Min Max

Rating

Unit

Parameter Symbol

Ambient Temperature T
Power Supply Voltage* VCC +1.8 +2.2 V

*: Voltage is defined on the basis of VSS = GND = 0 V.
Note: Operating ranges define those limits between which the proper device function is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

A −40 +85 °C

Min Max

Value

Unit

23

MBM29SL800TD

MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

■

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/MBM29SL800BD

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0.2 × VCC

−0.5 V

−2.0 V

VCC + 2.0 V

VCC + 0.5 V

0.8 × V

CC

20 ns

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

20 ns

20 ns20 ns

Figure 2 Maximum Overshoot Waveform 1

+12.5 V

+11.5 V

V

CC + 0.5 V

Note : This waveform is applied for A

Figure 3 Maximum Overshoot Waveform 2

20 ns

20 ns20 ns

9, OE and RESET.

24

MBM29SL800TD

DC CHARACTERISTICS

■

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/MBM29SL800BD

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Parameter Symbol Conditions

Input Leakage Current I
Output Leakage Current I
A

9, OE, RESET Inputs Leakage

Current

CC Active Current *

V

V

CC Active Current *

V

CC Current (Standby) ICC3

1

2

LI VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA

LO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA

ILIT

ICC1

ICC2 CE = VIL, OE = VIH 25 mA

VCC Current (Standby, Reset) ICC4

V

CC Current

(Automatic Sleep Mode) *

3

ICC5

Input Low Voltage V

Value

Unit

Min Typ Max

VCC = VCC Max,
A

9, OE, RESET = 11 V

CE = VIL, OE = VIH,

f = 10 MHz

CE

= VIL, OE = VIH,

f = 5 MHz

Byte

Word 20

Byte

Word 10

VCC = VCC Max, CE = VCC ± 0.3 V,
RESET

= VCC ± 0.3 V

VCC = VCC Max,
RESET

= VSS ± 0.3 V

35 µA

20



mA

10



mA

 15µA

 15µA

VCC = VCC Max, CE = VSS ± 0.3 V,
RESET
V

IL −0.5  0.2 × VCC V

= VCC ± 0.3 V,

IN = VCC ± 0.3 V or VSS ± 0.3 V

 15µA

Input High Voltage V
Voltage for Autoselect and Sector

Protection (A9, OE, RESET) *

4, *5

Output Low Voltage V
Output High Voltage V

IH  0.8 × VCC  VCC + 0.3 V

VID  10 10.5 11 V

OL IOL = 0.1 mA, VCC = VCC Min 0.1 V
OH IOH = −100 µAVCC − 0.1 V

*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: I

CC active while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4: This timing is only for Sector Protection operation and Autoselect mode.
*5: Applicable for only V

CC applying.

25

MBM29SL800TD

AC CHARACTERISTICS

■

•

Read Only Operations Characteristics

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Parameter

Read Cycle Time t

/MBM29SL800BD

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Value (Note)

Symbol

Test Setup

JEDEC Standard

AVAV tRC  100  120  ns

Min Max Min Max

Unit-10 -12

Address to Output Delay t
Chip Enable to Output Delay t

AVQV tACC
ELQV tCE OE = VIL  100  120 ns

CE = VIL
OE = VIL

 100  120 ns

Output Enable to Output Delay tGLQV tOE 35  50 ns
Chip Enable to Output High-Z t
Output Enable to Output High-Z t
Output Hold Time From Addresses,

CE or OE, Whichever Occurs First
RESET

CE

Pin Low to Read Mode  tREADY 20  20 µs

to BYTE Switching Low or High 

EHQZ tDF 30  40 ns

GHQZ tDF 30  40 ns

tAXQX tOH  0  0  ns

tELFL

tELFH

5  5ns

Note : Test Conditions :

Output Load : 1 TTL gate and 30 pF (MBM29SL800TD/BD-10)

1 TTL gate and 100 pF (MBM29SL800TD/BD-12)
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or V

CC

Timing measurement reference level

Input : 0.5 × V

CC

Output : 0.5 × VCC

26

Notes : • C

• C

VCC

IN3064

Device

Under

Test

CL

L = 30 pF including jig capacitance (MBM29SL800TD/BD-10)
L = 100 pF including jig capacitance (MBM29SL800TD/BD-12)

or Equivalent

6.2 kΩ

2.7 kΩ

Diodes = IN3064
or Equivalent

Figure 4 Test Conditions

MBM29SL800TD

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/MBM29SL800BD

-10/12

•

Write/Erase/Program Operations

Value

Parameter

Write Cycle Time t
Address Setup Time t

Symbol

JEDEC Standard

AVAV tWC 100 120 ns
AVWL tAS 0  0 ns

Min Typ Max Min Typ Max

Unit-10 -12

Address Hold Time tWLAX tAH 50 60 ns
Data Setup Time tDVWH tDS 50 60 ns
Data Hold Time t

WHDX tDH 0  0 ns

Output Enable Setup Time  tOES 0  0 ns
Output Enable Hold

Time

Read
Toggle and Data

 t

OEH

Polling 10 10 ns

0  0 ns

Read Recover Time Before Write tGHWL tGHWL 0  0 ns
Read Recover Time Before Write tGHEL tGHEL 0 0 ns
CE

Setup Time tELWL tCS 0  0 ns
WE Setup Time tWLEL tWS 0  0 ns
CE Hold Time tWHEH tCH 0  0 ns
WE

Hold Time tEHWH tWH 0  0 ns
Write Pulse Width tWLWH tWP 50 60 ns
CE Pulse Width tELEH tCP 50 60 ns
Write Pulse Width High t

WHWL tWPH 30 30 ns

CE Pulse Width High tEHEL tCPH 30 30 ns
Programming

Operation
Sector Erase Operation *

V

CC Setup Time  tVCS 50 50 µs

Rise Time to VID *
Voltage Transition Time *
Write Pulse Width *
OE Setup Time to WE Active *
CE Setup Time to WE Active *
Recover Time From RY/BY

Byte

t

WHWH1 tWHWH1

Word  14.6 14.6 µs

1

2

2

2

2

2

tWHWH2 tWHWH2  1.5 1.5  s

 tVIDR 500 500 ns
 tVLHT 4  4 µs
 tWPP 100 100 µs
 tOESP 4 4 µs
 tCSP 4  4 µs
 tRB 0  0 ns

 10.6 10.6 µs

RESET Pulse Width  tRP 500 500 ns
RESET Hold Time Before Read  tRH 200 200 ns
BYTE

Switching Low to Output High-Z  tFLQZ 30 40 ns
BYTE Switching High to Output Active  tFHQV 100 120 ns
Program/Erase Valid to RY/BY

Delay  tBUSY 90 90 ns
Delay Time from Embedded Output Enable  tEOE 100 120 ns
Power On/Off Timing  tPS 0  0 ns

*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection operation.

27

MBM29SL800TD

ERASE AND PROGRAMMING PERFORMANCE

■

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/MBM29SL800BD

-10/12

Parameter

Sector Erase Time  1.5 15 s Excludes programming time prior to erasure
Word Programming Time  14.6 360 µs
Byte Programming Time  10.6 300 µs
Chip Programming Time  7.7 200 s Excludes system-level overhead
Program/Erase Cycle 100,000 cycle —

TSOP (I) PIN CAPACITANCE

■

Parameter Symbol Test Setup

Input Capacitance C
Output Capacitance C
Control Pin Capacitance CIN2 VIN = 01013pF

Notes : • Test conditions TA = +25 °C, f = 1.0 MHz

• DQ

15/A-1 pin capacitance is stipulated by output capacitance.

Min Typ Max

Limits

Unit Remarks

Excludes system-level overhead

Value

Unit

Typ Max

IN VIN = 07.59.5pF
OUT VOUT = 0810pF

FBGA PIN CAPACITANCE

■

Parameter Symbol Test Setup

Input Capacitance C
Output Capacitance COUT VOUT = 0810pF
Control Pin Capacitance C

Notes : • Test conditions TA = +25 °C, f = 1.0 MHz

• DQ

15/A-1 pin capacitance is stipulated by output capacitance.

SCSP PIN CAPACITANCE

■

Parameter Symbol Test Setup

Input Capacitance C
Output Capacitance C
Control Pin Capacitance CIN2 VIN = 01013pF

Notes : • Test conditions TA = +25 °C, f = 1.0 MHz

• DQ

15/A-1 pin capacitance is stipulated by output capacitance.

IN VIN = 07.59.5pF

IN2 VIN = 01013pF

IN VIN = 07.59.5pF
OUT VOUT = 0810pF

Value

Unit

Typ Max

Value

Unit

Typ Max

28

MBM29SL800TD

TIMING DIAGRAM

■

•

Key to Switching Waveforms

-10/12

/MBM29SL800BD

WAVEFORM INPUTS OUTPUTS

-10/12

(1) Read Operation Timing Diagram

Address

Must Be
Steady

May
Change
from H to L

May
Change
from L to H

"H" or "L":
Any Change
Permitted

Does Not
Apply

RC

t

Address Stable

Will Be
Steady

Will Change
from H to L

Will Change
from L to H

Changing,
State
Unknown

Center Line is
High­Impedance
"Off" State

CE

OE

WE

Outputs

tACC

tOE tDF

tOEH

tCE

High-Z High-Z

Outputs Valid

tOH

29

MBM29SL800TD

(2) Hardware Reset/Read Operation Timing Diagram

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/MBM29SL800BD

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RC

t

Address

CE

RESET

Outputs

tACC

tRH

tRP tRH tCE

High-Z

Address Stable

tOH

Outputs Valid

30

MBM29SL800TD

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/MBM29SL800BD

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(3) Alternate WE

Address

CE

OE

WE

Data

Controlled Program Operation Timing Diagram

3rd Bus Cycle Data Polling

tGHWL

555h PA

tWC

tCS

tAS tAH

tCH

tWPHtWP

tDH

tDS

A0h PD

tWHWH1

DQ

PA

7

tRC

tCE

tOE

tDF

DOUT DOUT

tOH

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ

7 is the output of the complement of the data written to the device.

• D

OUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

31

MBM29SL800TD

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/MBM29SL800BD

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(4) Alternate CE

Controlled Program Operation Timing Diagram

3rd Bus Cycle Data Polling

tWS

tGHEL

555h PA

tWC

tCP

tDS

A0h

tAS tAH

tWH

tCPH

tDH

tWHWH1

PD

Address

WE

OE

CE

Data

DQ

PA

DOUT

7

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ

7 is the output of the complement of the data written to the device.

• D

OUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

32

MBM29SL800TD

(5) Chip/Sector Erase Operation Timing Diagram

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/MBM29SL800BD

-10/12

Address

CE

OE

WE

Data

V

CC

tCS

tGHWL

tVCS

555h 2AAh 555h 555h 2AAh SA*

tWC

tWP

tDS

tAS

tAH

tCH

tWPH

tDH

AAh 55h 80h AAh 55h

10h for Chip Erase

10h/
30h

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
Note : These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

33

MBM29SL800TD

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/MBM29SL800BD

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(6) Data

Polling during Embedded Algorithm Operation Timing Diagram

CE

OE

WE

DQ

7

DQ6 to DQ0

tCH

tOEH

Data

Data

tBUSY

tOE

tCE

tWHWH1 or 2

DQ7

DQ

6 to DQ0 =

Outputs Flag

*

tEOE

DQ7 =
Valid Data

6 to DQ0

DQ
Valid Data

tDF

High-Z

High-Z

RY/BY

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

34

MBM29SL800TD

t

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/MBM29SL800BD

(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

Address

tAHT tAHTtASO tAS

CE

tCEPH

WE

-10/12

OE

DQ6/DQ2

RY/BY

Data

tDH

tBUSY

tOE

Toggle

Data

tOEPH

Toggle

Data

tCE

Toggle

Data

tOEHtOEH

*

Stop

Toggling

* : DQ6 stops toggling (The device has completed the Embedded operation) .

Outpu

Valid

35

MBM29SL800TD

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/MBM29SL800BD

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(8) RY/BY

(9) RESET

Timing Diagram during Program/Erase Operation Timing Diagram

CE

Rising edge of the last WE signal

WE

Entire programming
or erase operations

RY/BY

tBUSY

, RY/BY Timing Diagram

WE

RESET

RY/BY

tRP

tRB

tREADY

36

MBM29SL800TD

(10) Timing Diagram for Word Mode Configuration

CE

tCE

BYTE

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/MBM29SL800BD

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DQ

14 to DQ0

DQ15/A-1

tELFH

Data Output

(DQ7 to DQ0)

tFHQV

A-1

(11) Timing Diagram for Byte Mode Configuration

CE

BYTE

DQ

14 to DQ0

DQ15/A-1

tELFL

Data Outputs

(DQ14 to DQ0)

DQ

15

tFLQZ

Data Output

(DQ14 to DQ0)

DQ

15

Data Outputs
(DQ

tACC

7 to DQ0)

A-1

(12) BYTE

Timing Diagram for Write Operations

CE or WE

BYTE

tAS

Falling edge of the last write signal

Input
Valid

tAH

37

MBM29SL800TD

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(13) Sector Protection Timing Diagram

A18, A17, A16
A15, A14, A13
A12

A6, A0

A1

ID

V
VIH

A9

SPAX

tVLHT

/MBM29SL800BD

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SPAY

VID
VIH

OE

WE

CE

Data

VCC

tVLHT

tOESP

tCSP

tVCS

SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected

Note : A-1 is VIL on byte mode.

tWPP

tVLHT

tVLHT

01h

tOE

38

MBM29SL800TD

(14) Temporary Sector Unprotection Timing Diagram

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/MBM29SL800BD

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(15) DQ

VCC

VID
VIH

RESET

CE

WE

RY/BY

2

vs. DQ

tVIDR

tVCS

tVLHT

6

Program or Erase Command Sequence

Unprotection period

tVLHT

tVLHT

Enter

Embedded

Erasing

WE

DQ6

DQ2*

DQ2 and DQ6

with OE or CE

Erase

Toggle

Erase

Suspend

Enter Erase

Suspend Program

Erase Suspend

Read

* : DQ2 is read from the erase-suspended sector.

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

39

MBM29SL800TD

(16) Extended Sector Protection Timing Diagram

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/MBM29SL800BD

-10/12

VCC

RESET

Address

6, A0

A

A1

CE

OE

WE

tVIDR

tVCS

tVLHT

tWC tWC

SPAX SPAX SPAY

tWP

TIME-OUT

40

Data

SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)

60h01h40h60h60h

tOE

MBM29SL800TD

(17) Power ON/OFF Timing Diagram

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/MBM29SL800BD

-10/12

RESET

VCC

Address

Data

0 V

VIH

1.8 V

tPS

tRH

tPS

Input Valid

Output Valid

tACC

41

MBM29SL800TD

FLOW CHART

■

(1) Embedded ProgramTM Algorithm

EMBEDDED ALGORITHM

-10/12

/MBM29SL800BD

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded
Program

No

Verify Data

?

Yes

Algorithm
in program

-10/12

Increment Address

Program Command Sequence (Address/Command):

Program Address/Program Data

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

No

Last Address

?

Yes

Programming Completed

555h/AAh

2AAh/55h

555h/A0h

42

MBM29SL800TD

(2) Embedded Erase

EMBEDDED ALGORITHM

TM

Algorithm

Start

Write Erase

Command Sequence

(See Below)

Data Polling

No

Data = FFh

Erasure Completed

?

-10/12

Yes

/MBM29SL800BD

Embedded
Erase
Algorithm
in progress

-10/12

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Sector Address

/30h

Additional sector
erase commands
are optional.

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

43

MBM29SL800TD

-10/12

/MBM29SL800BD

-10/12

(3) Data

Polling Algorithm

(DQ

DQ7 = Data?

No

(DQ7 to DQ0)

DQ7 = Data?

Start

Read Byte

7 to DQ0)

Addr. = VA

No

DQ5 = 1?

Yes

Read Byte

Addr. = VA

*

No

Yes

Yes

VA = Address for programming

= Any of the sector addresses

within the sector being erased
during sector erase or multiple
erases operation.

= Any of the sector addresses

within the sector not being
protected during sector erase or
multiple sector erases
operation.

Fail Pass

* : DQ

7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

44

MBM29SL800TD

(4) Toggle Bit Algorithm

-10/12

Start

/MBM29SL800BD

-10/12

Read DQ

Addr. = VIH or VIL

Read DQ7 to DQ0

Addr. = VIH or VIL

DQ6 =

Toggle?

No

DQ5 = 1?

Read DQ7 to DQ0

Twice

Addr. = VIH or VIL

DQ6 =

Toggle?

Program/Erase

Operation Not

Complete.Write

Reset Command

7 to DQ0

*1

No

Yes

Yes

*1, *2

No

Yes

Program/Erase

Operation
Complete

*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ

5 changes to “1”.

45

MBM29SL800TD

(5) Sector Protection Algorithm

-10/12

/MBM29SL800BD

Start

Setup Sector Addr.

(A

18, A17, A16, A15, A14, A13, A12)

PLSCNT = 1

OE = V

ID, A9 = VID

CE = VIL, RESET = VIH

A6 = A0 = VIL, A1 = VIH

Activate WE Pulse

-10/12

Increment PLSCNT

No

PLSCNT = 25?

Yes Yes

Remove V

Write Reset Command

ID from A9

Device Failed

Time out 100 µs

WE = V

IH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A

()

A6 = A0 = VIL

No

Data = 01h?

Protect Another

Remove V

Write Reset Command

Sector Protection

Completed

Sector?

ID from A9

1 = VIH

No

*

Yes

46

* : A-1 is VIL on byte mode.

MBM29SL800TD

(6) Temporary Sector Unprotection Algorithm

-10/12

Start

/MBM29SL800BD

-10/12

RESET = V

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotection Completed

*1 : All protected sectors are unprotected.
*2 : All previously protected sectors are protected once again.

ID

*1

*2

47

MBM29SL800TD

-10/12

(7) Extended Sector Protection Algorithm

/MBM29SL800BD

Start

RESET = VID

Wait to 4 µs

-10/12

Device is Operating in

Temporary Sector

Unprotection Mode

Increment PLSCNT

No

PLSCNT = 25?

No

No

Extended Sector

Protection Entry?

To Setup Sector Protection

Write XXXh/60h

PLSCNT = 1

To Protect Secter

Write 60h to Secter Address

(A

6 = A0 = VIL, A1 = VIH)

Time out 250 µs

To Verify Sector Protection

Write 40h to Secter Address

(A

6 = A0 = VIL, A1 = VIH)

Read from Sector Address

(Addr. = SPA, A

A1 = VIH, A6 = VIL)

Data = 01h?

Yes

0 = VIL,

Setup Next Sector Address

48

Yes

Remove V

Write Reset Command

ID from RESET

Device Failed

Yes

Protect Other Group?

No

Remove VID from RESET

Write Reset Command

Sector Protection

Completed

Yes

MBM29SL800TD

(8) Embedded Programming Algorithm for Fast Mode

FAST MODE ALGORITHM

555h/AAh

-10/12

Start

/MBM29SL800BD

-10/12

Increment Address

2AAh/55h

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling

Verify Data?

Yes

No

Last Address

?

Yes

Programming Completed

XXXh/90h

XXXh/F0h

Set Fast Mode

In Fast Program

No

Reset Fast Mode

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

49

MBM29SL800TD

ORDERING INFORMATION

■

Part No. Package Access Time (ns) Sector Architecture

-10/12

/MBM29SL800BD

-10/12

MBM29SL800TD-10PFTN
MBM29SL800TD-12PFTN

MBM29SL800TD-10PFTR
MBM29SL800TD-12PFTR

MBM29SL800TD-10PBT
MBM29SL800TD-12PBT

MBM29SL800TD-10PW
MBM29SL800TD-12PW

MBM29SL800BD-10PFTN
MBM29SL800BD-12PFTN

MBM29SL800BD-10PFTR
MBM29SL800BD-12PFTR

MBM29SL800BD-10PBT
MBM29SL800BD-12PBT

MBM29SL800BD-10PW
MBM29SL800BD-12PW

48-pin plastic TSOP (I)

(FPT-48P-M19)

Normal Bend

48-pin plastic TSOP (I)

(FPT-48P-M20)

Reverse Bend

48-pin plastic FBGA

(BGA-48P-M12)

48-pin plastic SCSP

(WLP-48P-M03)

48-pin plastic TSOP (I)

(FPT-48P-M19)

Normal Bend

48-pin plastic TSOP (I)

(FPT-48P-M20)

Reverse Bend

48-pin plastic FBGA

(BGA-48P-M12)

48-pin plastic SCSP

(WLP-48P-M03)

100
120

100
120

100
120

100
120

100
120

100
120

100
120

100
120

Top Sector

Bottom Sector

50

MBM29SL800TD

-10/12

/MBM29SL800BD

-10/12

MBM29SL800

10

DT

−

TN

PACKAGE TYPE
TN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
TR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PBT = 48-Ball Fine Pitch Ball Grid Array
Package (FBGA)
PW = 48-Ball Super Chip Size Package
(SCSP)

SPEED OPTION
See Product Selector Guide

Device Revision
BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

DEVICE NUMBER/DESCRIPTION
MBM29SL800
8 Mega-bit (1 M × 8-Bit or 512 K × 16-Bit) CMOS Flash Memory

1.8 V-only Read, Program, and Erase

51

MBM29SL800TD

PACKAGE DIMENSIONS

■

-10/12

/MBM29SL800BD

-10/12

48-pin plastic TSOP (I)

(FPT-48P-M19)

LEAD No.

1

INDEX

"A"

20.00

±0.20

(.787±.008)

18.40

±0.20

*

(.724±.008)

0.10(.004)

Note 1 : * : Resin Protrusion. (Each Side : 0.15 (.006) Max)
Note 2 : Pins width and pins thickness include plating thickness.

48

Details of "A" part

0.25(.010)

0~8˚

0.60±0.15

(.024

±.006)

2524

12.00

±0.20*

(.472

0.17
.007

0.50(.020)

+0.03

–0.08

+.001

–.003

TYP

±.008)

11.50REF
(.453)

0.22

(.009±.002)

±0.05

0.10(.004)

(Stand off height)

M

1.10

(Mounting

height)

0.10±0.05

(.004±.002)

+0.10

–0.05

+.004

–.002.043

C

2001 FUJITSU LIMITED F48029S-c-4-5

Dimensions in mm (inches)

(Continued)

52

MBM29SL800TD

-10/12

/MBM29SL800BD

-10/12

48-pin plastic TSOP (I)

(FPT-48P-M20)

LEAD No.

1

INDEX

"A"

0.10(.004)

*

18.40
(.724±.008)

20.00
(.787±.008)

±0.20

±0.20

Note 1 : * : Resin Protrusion. (Each Side : 0.15 (.006) Max)
Note 2 : Pins width and pins thickness include plating thickness.

48

Details of "A" part

0.60±0.15

±.006)

(.024

0~8˚

0.25(.010)

2524

0.17
.007

+0.03

–0.08

+.001

–.003

0.50(.020)
TYP

12.00

0.22

±0.05

(.009±.002)

11.50(.453)REF

±0.20(.472±.008)*

0.10(.004)

M

0.10

±0.05

(.004

±.002)

(Stand off height)

+0.10

1.10

–0.05

+.004

.043

–.002

(Mounting height)

C

2001 FUJITSU LIMITED F48030S-c-4-5

Dimensions in mm (inches)

(Continued)

53

MBM29SL800TD

48-ball plastic FBGA

(BGA-48P-M12)

9.00±0.20(.354±.008)

INDEX

C0.25(.010)

-10/12

/MBM29SL800BD

+.006

+0.15

.041 –.004

–0.10

1.05
(Mounting height)

0.38±0.10(.015±.004)
(Stand off)

6.00±0.20

(.236±.008)

4.00(.157)

G

H

(48-ø.018±.004)

-10/12

5.60(.220)

0.80(.031)TYP

FEDCBA

48-ø0.45±0.10

ø0.08(.003)

6
5
4
3
2
1

M

0.10(.004)

C

2001 FUJITSU LIMITED B48012S-c-3-3

Dimensions in mm (inches)

(Continued)

54

(Continued)

48-ball plastic SCSP

(WLP-48P-M03)

7.06±0.10(.278±.004)

MBM29SL800TD

Y

-10/12

0.50(.020)
TYP

/MBM29SL800BD

(3.50=0.50x7)

((.138=.020x7))

-10/12

3.52±0.10

(.139±.004)

INDEX AREA
(LASER MARKING)

Z

C

2001 FUJITSU LIMITED W48003S-c-1-1

0.10(.004)

X

Z

1.00(.039)
Max.

0.25(.010)
Min.

(2.50=0.50x5)

((.098=.020x5))

0.50(.020)
TYP

(Stand off)

(2.25)

((.089))

4-Ø0.13(4-Ø.005)

48-Ø0.35±0.10

(48-Ø.014±.004)

(0.13SQ)

((.005SQ))

0.08(.003)

(0.25(.010)

M

XYZ

(INDEX)

Dimensions in mm (inches)

55

MBM29SL800TD-10/12/MBM29SL800BD-10/12

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0210

FUJITSU LIMITED Printed in Japan

