FUJITSU MBM29SL800TD, MBM29SL800BD DATA SHEET

查询MBM29SL800TD-10供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

8 M (1 M

8/512 K

××××

××××

MBM29SL800TD/BD

DESCRIPTION

■

The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , 48-ball FBGA and 48-ball
SCSP packages. These devices are designed to be programmed in-system with the standard system 3.0 V V
supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be repro­grammed in standard EPROM programmers.

PRODUCT LINE UP

■

DS05-20871-5E

16) BIT

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CC

(Continued)

Part No. MBM29SL800TD/MBM29SL800BD

Ordering Part No. V
Max Address Access Time (ns) 100 120
Max CE
Max OE

■

Access Time (ns) 100 120
Access Time (ns) 35 50

PACKAGES

48-pin Plastic TSOP (I) 48-pin Plastic TSOP (I) 48-pin Plastic FBGA 48-pin Plastic SCSP

Marking Side

(FPT-48P-M19) (FPT-48P-M20) (BGA-48P-M12) (WLP-48P-M03)

CC = +2.0 V ± 0.2 −10 −12

Marking Side

MBM29SL800TD

(Continued)

The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE
write enable (WE

The MBM29SL800TD/BD are pin and command set compatible with JEDEC standard E
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry . Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29SL800TD/BD are programmed by executing the program command sequence. This will inv oke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and ver ified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.

A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29SL800TD/BD are erased when shipped from the
fac to r y.

) , and output enable (OE) controls.

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/MBM29SL800BD

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2

PROMs. Commands

) ,

The devices f eature single 1.8 V po wer supply oper ation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data
by the Toggle Bit feature on DQ
completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E
of quality, reliability, and cost effectiveness. The MBM29SL800TD/BD memor ies electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are prog rammed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.

6, or the RY/BY output pin. Once the end of a program or erase cycle has been

2

PROM experience to produce the highest levels

CC detector automatically

Polling of DQ7,

2

MBM29SL800TD

FEATURES

■

•

Single 1.8 V read, program, and erase

Minimizes system level power requirements

•

Compatible with JEDEC-standard commands

2

Uses same software commands as E

•

Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
48-ball SCSP (Package suffix : PW)

• Minimum 100,000 program/erase cycles

•

High performance

100 ns maximum access time

•

Sector erase architecture

One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase

•

Boot Code Sector Architecture

T = Top sector
B = Bottom sector

•

Embedded Erase

Automatically pre-programs and erases the chip or any sector

•

Embedded Program

Automatically writes and verifies data at specified address

•Data

•

•

•

•

• Sector Protection set function by Extended sector Protect command

• Fast programming Function by Extended Command

•

Polling and Toggle Bit feature for detection of program or erase cycle completion

Ready/Busy output (RY/BY

Hardware method for detection of program or erase cycle completion

Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode

Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

Sector protection

Hardware method disables any combination of sectors from program or erase operations

Temporary sector unprotection

Temporary sector unprotection via the RESET

TM

Algorithms

TM

Algorithms

)

PROMs

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pin

/MBM29SL800BD

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Embedded Erase

TM

and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

3

MBM29SL800TD

PIN ASSIGNMENTS

■

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/MBM29SL800BD

TSOP (I)

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A15
A14
A13
A12
A11
A10

N.C.
N.C.

WE

RESET

N.C.
N.C.

RY/BY

A
A17

A1
A2
A3
A4
A5
A6

A7
A17
A18

RY/BY

N.C.
N.C.

RESET

WE
N.C.
N.C.

A

A9
A10
A11
A12
A13
A14
A15

A9
A8

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

18

16
17
18
19
20
21
22
23
24

(Marking Side)

Normal Bend

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V

SS

CE
A0

(FPT-48P-M19)

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9

8

8
7
6
5
4
3
2
1

(Marking Side)

Reverse Bend

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A0
CE
V

SS

OE
DQ

0

DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A

16

(FPT-48P-M20)

(Continued)

4

(Continued)

MBM29SL800TD

FBGA

(TOP VIEW)

Marking side

A6 B6 C6 D6 E6 F6 G6 H6

A

13 A12 A14 A15 A16 DQ15/A-1 VSS

A5 B5 C5 D5 E5 F5 G5 H5
A

9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

A4 B4 C4 D4 E4 F4 G4 H4

WE RESET N.C. N.C. DQ

A3 B3 C3 D3 E3 F3 G3 H3

RY/BY N.C. A

A2 B2 C2 D2 E2 F2 G2 H2
A

7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

18 N.C. DQ2 DQ10 DQ11 DQ3

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/MBM29SL800BD

BYTE

5 DQ12 VCC DQ4

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A1 B1 C1 D1 E1 F1 G1 H1
A

3 A4 A2 A1 A0 CE OE VSS

(BGA-48P-M12)

SCSP

(TOP VIEW)

Marking side

A6

B6A4C6A2D6A1E6A0F6

A3

A5

A7B5A17C5A6

A4

RY/BYB4N.C.C4A18D4N.C.E4DQ2F4DQ10G4DQ11H4DQ3

A3

WEB3RESETC3N.C.D3N.C.E3DQ5F3DQ12G3VCCH3DQ4

A2

B2A8C2

A9

A10D2A11E2DQ7F2DQ14G2DQ13H2DQ6

D5A5E5

DQ0F5DQ8G5DQ9H5DQ1

CEG6OEH6VSS

A1

A13B1A12C1A14D1A15E1A16F1BYTE

(WLP-48P-M03)

G1

DQ15/A-1

H1

VSS

5

MBM29SL800TD

PIN DESCRIPTION

■

Pin name Function

A

18 to A0, A-1 Address Inputs

DQ

15 to DQ0 Data Inputs/Outputs

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/MBM29SL800BD

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CE
OE

WE Write Enable

RESET

RY/BY

BYTE Selects 8-bit or 16-bit mode

V

SS Device Ground

V

CC Device Power Supply

N.C. No Internal Connection

Chip Enable
Output Enable

Hardware Reset Pin/Temporary Sector Unprotection
Ready/Busy Output

6

BLOCK DIAGRAM

■

MBM29SL800TD

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/MBM29SL800BD

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VCC
VSS

WE

BYTE

RESET

CE
OE

RY/BY

Buffer

State

Control

Command

Register

Low V

CC Detector

RY/BY

Program Voltage

Generator

Timer for

Program/Erase

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

STB

DQ15 to DQ0

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

A

18 to A0

A-1

LOGIC SYMBOL

■

19

A-1

18 to A0

A

CE
OE
WE
RESET
BYTE

Address Latch

16 or 8

DQ15 to DQ0

RY/BY

7

MBM29SL800TD

DEVICE BUS OPERATION

■

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/MBM29SL800BD

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MBM29SL800TD/800BD User Bus Operations Table (BYTE

Operation CE

Auto-Select Manufacturer Code *
Auto-Select Device Code *
Read *

3

1

0

1

OE WE A

1

LLHLLLVID Code H

A

6

A

LLHHLLVID Code H
LLHA0 A1 A6 A9 DOUT H

====

VIH)

9

A

DQ0 to DQ15RESET

Standby H X X X X X X High-Z H
Output Disable L H H X X X X High-Z H
Write (Program/Erase) L H L A
Enable Sector Protection *
Verify Sector Protection *

2, *4

2, *4

LVID LHLVID XH
LLHLHLVID Code H

Temporary Sector Unprotection XXXXXXX X V

0 A1 A6 A9 DIN H

ID

Reset (Hardware) /Standby XXXXXXX High-Z L

MBM29SL800TD/800BD User Bus Operations Table (BYTE

Operation CE

Auto-Select Manufacturer Code *
Auto-Select Device Code *
Read *

3

1

OE WE

1

LLHLLLLVID Code H

DQ15/

A-

0

A

1

1

A

LLHLHLLVID Code H
LLHA-1 A0 A1 A6 A9 DOUT H

====

VIL)

9

DQ0 to

7

DQ

RESET

6

A

A

Standby H X X X XXXXHigh-Z H
Output Disable LHHXXXXXHigh-Z H
Write (Program/Erase) L H L A­Enable Sector Protection *
Verify Sector Protection *

2, *4

2, *4

Temporary Sector Unprotection *

LVID LLHLVID XH
LLHLLHLVID Code H

5

XXXXXXXX X VID

1 A0 A1 A6 A9 DIN H

Reset (Hardware) /Standby X X X X XXXXHigh-Z L

Legend : L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29SL800TD/800BD Standard Command Definitions Table”.
*2: Refer to the section on Sector Protection.
*3: WE
*4: V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

CC = 2.0 V ± 10%

*5: It is also used for the extended sector protection.

8

MBM29SL800TD

MBM29SL800TD/800BD Standard Command Definitions Table

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/MBM29SL800BD

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Command

Sequence

Read/
Reset

Read/
Reset

Autoselect

Program

Chip
Erase

Sector
Erase

Sector Erase Suspend Erase can be suspended during sector erase with Addr. (“H” or “L”) . Data (B0h)
Sector Erase Resume Erase can be resumed after suspend with Addr. (“H” or “L”) . Data (30h)

Word

Byte

Word

Byte AAAh 555h AAAh

Word

Byte AAAh 555h AAAh

Word

Byte AAAh 555h AAAh

Word

Byte AAAh 555h AAAh AAAh 555h AAAh

Word

Byte AAAh 555h AAAh AAAh 555h

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

1 XXXh F0h 

555h

3

555h

3

555h

4

555h

6

555h

6

AAh

AAh

AAh

AAh

AAh

Second Bus

Write Cycle

2AAh

55h

2AAh

55h

2AAh

55h

2AAh

55h

2AAh

55h

Third Bus

Write Cycle

555h

555h

555h

555h

555h

Fourth Bus

Read/Write

Cycle

F0h RA RD 

90h 

A0h PA PD 

555h

80h

555h

80h

AAh

AAh

Fifth Bus

Write Cycle

2AAh

55h

2AAh

55h SA 30h

Sixth Bus

Write Cycle

555h

10h

Notes : • Address bits A

Sector Address (SA)

• Bus operations are defined in “MBM29SL800TD/800BD User Bus Operations Tables (BYTE
BYTE

= VIL)”.

• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the WE

SA = Address of the sector to be erased. The combination of A

uniquely select any sector.

• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE

• The system should generate the following address patterns :

Word Mode : 555h or 2AAh to addresses A
Byte Mode : AAAh or 555h to addresses A-1 and A0 to A10

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in “MBM29SL800TD/800BD Standard Command Definitions

Table” and “MBM29SL800TD/BD Extended Command Definitions Table” are illegal.

11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA) and

= VIH and

pulse.

18, A17, A16, A15, A14, A13, and A12 will

.

0 to A10

9

MBM29SL800TD

MBM29SL800TD/BD Extended Command Definitions Table

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/MBM29SL800BD

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Bus

Command

Sequence

Write

Cycles

Req'd

Set to
Fast Mode

Fast Program*

Reset from Fast

1

Mode*
Extended Sector

Protect*

2

Word

Byte AAAh 555h AAAh

Word

1

Byte XXXh

Word

Byte XXXh XXXh

Word

Byte

3

2

2

4 XXXh 60h SPA 60h SPA 40h SPA SD

SPA : Sector address to be protected. Set sector address (SA) and (A

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus
Read Cycle

Addr Data Addr Data Addr Data Addr Data

555h

XXXh

XXXh

AAh

A0h PA PD 

90h

2AAh

XXXh

55h

F0h*

6, A1, A0) = (0, 1, 0) .

555h

3



20h 

SD : Sector protection verify data. Output 01h at protected sector address and output 00h at unprotected sector

address.
*1 : This command is valid during Fast Mode.
*2 : This command is valid while RESET

= VID.

*3 : The data “00h” is also acceptable.

MBM29SL800TD/800BD Sector Protection Verify Autoselect Codes Table

12

18

Type A

to A

Manufacture’s Code X V

MBM29SL800TD

Device Code

MBM29SL800BD

Sector Protection

Byte
Word X 22EAh
Byte
Word X 226Bh

XV

XV

Sector

Address

6

A

IL VIL VIL VIL 04h
IL VIL VIH

IL VIL VIH

V

IL VIH VIL VIL 01h*

1

A

0

A

1

A-1*

Code (HEX)

VIL EAh

VIL 6Bh

2

*1 : A

−

is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A

1

−

, the lowest address.

1

*2 : Outputs 01h at protected sector address and outputs 00h at unprotected sector address.

Extended Autoselect Code Table

Type Code

Manufacturer’s Code 04h

(B) * EAh A­ (W)
(B) * 6Bh A­ (W)

Device
Code

MBM29SL
800TD

MBM29SL
800BD

Sector Protection 01h

* : At Byte mode, DQ

8 to DQ14 are High-Z and DQ15 is A

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

A-1/0

22EAh

226Bh

A-1/0

000000000000100

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

1

11101010

0010001011101010

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

1

01101011

0010001001101011

000000000000001

−

, the lowest address.

1

(B) : Byte mode
(W) : Word mode
HI-Z : High-Z

10

0

MBM29SL800TD

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■

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• One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes

• Individual-sector, multiple-sector, or bulk-erase capability

• Individual or multiple-sector protection is user definable.

(×8) (×16) (×8) (×16)

/MBM29SL800BD

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16 Kbyte

8 Kbyte

8 Kbyte
32 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte

FFFFFh
FBFFFh
F9FFFh
F7FFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
00000h

7FFFFh
7DFFFh
7CFFFh
7BFFFh
77FFFh
6FFFFh
67FFFh
5FFFFh
57FFFh
4FFFFh
47FFFh
3FFFFh
37FFFh
2FFFFh
27FFFh
1FFFFh
17FFFh
0FFFFh
07FFFh
00000h

64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte

8 Kbyte
8 Kbyte

16 Kbyte

FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
07FFFh
05FFFh
03FFFh
00000h

7FFFFh
77FFFh
6FFFFh
67FFFh
5FFFFh
57FFFh
4FFFFh
47FFFh
3FFFFh
37FFFh
2FFFFh
27FFFh
1FFFFh
17FFFh
0FFFFh
07FFFh
03FFFh
02FFFh
01FFFh
00000h

MBM29SL800TD Sector Architecture MBM29SL800BD Sector Architecture

11

MBM29SL800TD

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Sector Address Table (MBM29SL800TD)

/MBM29SL800BD

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Sector

Address

SA0 0000XXX00000h to 0FFFFh 00000h to 07FFFh
SA1 0001XXX10000h to 1FFFFh 08000h to 0FFFFh
SA2 0010XXX20000h to 2FFFFh 10000h to 17FFFh
SA3 0011XXX30000h to 3FFFFh 18000h to 1FFFFh
SA4 0100XXX40000h to 4FFFFh 20000h to 27FFFh
SA5 0101XXX50000h to 5FFFFh 28000h to 2FFFFh
SA6 0110XXX60000h to 6FFFFh 30000h to 37FFFh
SA7 0111XXX70000h to 7FFFFh 38000h to 3FFFFh
SA8 1000XXX80000h to 8FFFFh 40000h to 47FFFh
SA9 1001XXX90000h to 9FFFFh 48000h to 4FFFFh
SA10 1010XXXA0000h to AFFFFh50000h to 57FFFh
SA11 1011XXXB0000h to BFFFFh58000h to 5FFFFh
SA12 1100XXXC0000h to CFFFFh60000h to 67FFFh
SA13 1101XXXD0000h to DFFFFh68000h to 6FFFFh
SA14 1110XXXE0000h to EFFFFh70000h to 77FFFh
SA15 11110XXF0000h to F7FFFh78000h to 7BFFFh

18

A

17

A

16

A

15

A

14

A

13

A

12

A

Address Range (

××××

8) Address Range (

××××

16)

SA16 1111100F8000h to F9FFFh7C000h to 7CFFFh
SA17 1111101FA000h to FBFFFh7D000h to 7DFFFh
SA18 111111XFC000h to FFFFFh 7E000h to 7FFFFh

12

MBM29SL800TD

Sector Address Table (MBM29SL800BD)

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/MBM29SL800BD

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Sector

Address

SA0 000000X00000h to 03FFFh 00000h to 01FFFh
SA1 000001004000h to 05FFFh 02000h to 02FFFh
SA2 000001106000h to 07FFFh 03000h to 03FFFh
SA3 00001XX08000h to 0FFFFh 04000h to 07FFFh
SA4 0001XXX10000h to 1FFFFh 08000h to 0FFFFh
SA5 0010XXX20000h to 2FFFFh 10000h to 17FFFh
SA6 0011XXX30000h to 3FFFFh 18000h to 1FFFFh
SA7 0100XXX40000h to 4FFFFh 20000h to 27FFFh
SA8 0101XXX50000h to 5FFFFh 28000h to 2FFFFh
SA9 0110XXX60000h to 6FFFFh 30000h to 37FFFh
SA10 0111XXX70000h to 7FFFFh 38000h to 3FFFFh
SA11 1000XXX80000h to 8FFFFh 40000h to 47FFFh
SA12 1001XXX90000h to 9FFFFh 48000h to 4FFFFh
SA13 1010XXXA0000h to AFFFFh50000h to 57FFFh
SA14 1011XXXB0000h to BFFFFh58000h to 5FFFFh
SA15 1100XXXC0000h to CFFFFh60000h to 67FFFh

18

A

17

A

16

A

15

A

14

A

13

A

12

A

Address Range (

××××

8) Address Range (

××××

16)

SA16 1101XXXD0000h to DFFFFh68000h to 6FFFFh
SA17 1110XXXE0000h to EFFFFh70000h to 77FFFh
SA18 1111XXXF0000h to FFFFFh78000h to 7FFFFh

13

MBM29SL800TD

FUNCTIONAL DESCRIPTION

■

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/MBM29SL800BD

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Read Mode

The MBM29SL800TD/BD have two control functions which m ust be satisfied in order to obtain data at the outputs.
CE

is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.
Address access time (t

access time (t

CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE

ACC) is equal to the delay from stable addresses to valid output data. The chip enable

to valid data at the output pins. (Assuming the
addresses have been stab le for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE

pin from “H” to “L”

Standby Mode

There are two ways to implement the standby mode on the MBM29SL800TD/BD devices, one using both the
CE

and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time
(t

CE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is

required even CE

= “H”.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE

= “H” or “L”) . Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken

high, the device requires t

RH of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29SL800TD/800BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.

To activate this mode, MBM29SL800TD/800BD automatically switch themselves to low power mode when
MBM29SL800TD/800BD addresses remain stably during access fine of 150 ns. It is not necessary to control
CE

, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) .

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29SL800TD/800BD read-out the data for changed addresses.

Output Disable

With the OE

input at a logic high level (VIH) , output from the devices are disabled. This will cause the output

pins to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding prog ramming algorithm. This mode is functional over the
entire temperature range of the devices.

To activate this mode, the programming equipment m ust force V
bytes may then be sequenced from the de vices outputs b y toggling address A
DON’T CARES except A

0, A1, A6, and A-1. (See “MBM29SL800TD/800BD Sector Protection Verify Autoselect

ID (10 V to 11 V) on address pin A9. Two identifier

0 from VIL to VIH. All addresses are

Codes Table” in ■DEVICE BUS OPERATION.)
The manufacturer and device codes may also be read via the command register, for instances when the

MBM29SL800TD/BD are erased or programmed in a system without access to high vo ltage on the A
command sequence is illustrated in “MBM29SL800TD/800BD Standard Command Definitions Table” (in ■DE-
VICE BUS OPERATION). (Refer to Autoselect Command section.)

Byte 0 (A

0 = VIL) represents the manufacturer’ s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier

code (MBM29SL800TD = EAh and MBM29SL800BD = 6Bh for ×8 mode; MBM29SL800TD = 22EAh and
MBM29SL800BD = 226Bh for ×16 mode) . These two bytes/words are giv en in “MBM29SL800TD/800BD Sector
Protection V erify Autoselect Codes T able and Extended Autoselect Code Table (in ■DEVICE BUS OPERA TION”).

14

9 pin. The

MBM29SL800TD

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/MBM29SL800BD

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All identifiers for manufactures and device will exhibit odd parity with DQ
read the proper device codes when executing the autoselect, A

1 must be VIL. (See “MBM29SL800TD/800BD

7 defined as the parity bit. In order to

Sector Protection Verify Autoselect Codes Table and Extended Autoselect Code Table in ■DEVICE BUS OP­ERATION”.)

Write

Device erasure and progr amming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com­mand register is written by bringing WE
falling edge of WE

or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Protection

The MBM29SL800TD/BD feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 18) . The sector protection f eature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V
CE

= VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to

ID on address pin A9 and control pin OE,

be protected. “Sector Address Tables (MBM29SL800TD/BD)” in ■FLEXIBLE SECTOR-ERASE ARCHITEC­TURE define the sector address for each of the nineteen (19) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE
rising edge of the same. Sector addresses must be held constant during the WE

pulse and is terminated with the

pulse. See “(13) Sector
Protection Timing Diagram” in ■TIMING DIAGRAM and “(5) Sector Protection Algor ithm” in ■FLOW CHART
for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must f orce V

ID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while
(A

6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the

devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A

0, A1, and A6

are DON’T CARES. Address locations with A1 = VIL are reserved for A utoselect manuf acturer and de vice codes.
A-

1 requires to apply to VIL on byte mode.

Temporary Sector Unprotection

This feature allows tempor ary unprotection of previously protected sectors of the MBM29SL800TD/BD devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET

pin to high voltage
(VID) . During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the V

ID is taken awa y from the RESET pin, all the prev iously protected sectors will be protected

again. See “(14) Temporary Sector Unprotection Timing Diagram” in ■TIMING DIAGRAM and “(6) Temporar y
Sector Unprotection Algorithm” in ■FLOW CHART.

RESET

Hardware Reset

The MBM29SL800TD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (V

IL) for at least 500 ns in order to properly reset the internal state machine.

Any operation in the process of being executed will be ter minated and the inter nal state machine will be reset
to the read mode 20 µs after the RESET
devices require an additional t

RH before it will allow read access. When the RESET pin is low, the devices will

pin is driven low. Fur thermore, once the RESET pin goes high, the

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY

output signal should be ignored during the RESET pulse. See “(9) RESET, RY/BY Timing
Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.

15

MBM29SL800TD

COMMAND DEFINITIONS

■

Device operations are selected by writing specific address and data sequences into the command register.
“MBM29SL800TD/800BD Standard Command Definitions Table” in ■DEVICE BUS OPERATION defines the
valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands
are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are
functionally equivalent, resetting the device to the read mode. Please note that commands are always written
at DQ

0 to DQ7 and DQ8 to DQ15 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ
operation is initiated by writing the Read/Reset command sequence into the command register . Microprocessor
read cycles retrieve array data from the memor y. The devices remain enabled for reads until the command
register contents are altered.

The devices will automatically power-up in the read/reset state . In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character­istics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM pro­grammers typically access the signature codes by raising A
onto the address lines is not generally desired system design practice.

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/MBM29SL800BD

5 = 1) to read/reset mode, the read/reset

9 to a high voltage. How ever, multiple xing high voltage

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The device contains an A utoselect command operation to supplement tr aditional PR OM programming method­ology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retriev es the man ufacture code of 04h. A read
cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29SL800TD = EAh and
MBM29SL800BD = 6Bh for ×8 mode; MBM29SL800TD = 22EAh and MBM29SL800BD = 226Bh for ×16
mode) . (See “MBM29SL800TD/800BD Sector Protection Verify Autoselect Codes Table and Extended
Autoselect Code Table in ■DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd
parity with DQ
XX02h for ×16 (XX04h for ×8) .
Scanning the sector addresses (A
logical “1” at device output DQ
mode on the protected sector. (See “MBM29SL800TD/800BD User Bus Oper ations T able (BYTE
= VIL)” in ■DEVICE BUS OPERATION.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.

Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE
latched on the rising edge of CE
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the

7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address

18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a

0 for a protected sector. The programming verification should be perform margin

= VIH and BYTE

or WE, whichever happens later and the data is

or WE, whichever happens first. The r ising edge of CE or WE (whichever

7 is equivalent to data written to this

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MBM29SL800TD

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/MBM29SL800BD

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system at this particular instance of time. Hence, Data
is being programmed.

If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being
written.

Programming is allowed in any sequence and across sector boundar ies. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.

“(1) Embedded Program
typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” wr ite cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase
Algorithm command sequence the devices will automatically program and ver ify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE
when the data on DQ
mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“(2) Embedded Erase

command strings and bus operations.

TM

Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using

7 is “1” (See Write Operation Status section.) at which time the device returns to read the

TM

Algorithm” in ■FLOW CHART illustr ates the Embedded EraseTM Algorithm using typical

Polling m ust be perf ormed at the memory location which

pulse in the command sequence and terminates

Sector Erase

Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then follo wed b y the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE
(Data = 30h) is latched on the rising edge of WE
erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently b y writing the six bus cycle operations on “MBM29SL800TD/800BD
Standard Command Definitions Table” in ■DEVICE BUS OPERATION. This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recom­mended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last
WE

will initiate the ex ecution of the Sector Er ase command (s) . If another falling edge of the WE occurs within
the 50 µs time-out window the timer is reset. (Monitor DQ
open, see section DQ
data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the
Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase b uff er may be done
in any sequence and with any number of sectors (0 to 18) .

Sector erase does not require the user to program the de vices prior to erase. The devices automatically progr am
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y
controls or timings during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE
sector erase command pulse and terminates when the data on DQ
at which time the devices return to the read mode. Data

3, Sector Erase Timer.) Resetting the devices once execution has begun will corrupt the

. After time-out of 50 µs from the rising edge of the last sector

3 to determine if the sector erase timer window is still

7 is “1” (See Write Operation Status section.)

polling must be performed at an address within any of

, while the command

pulse for the last

17