FUJITSU MBM29PL160TD-75, MBM29PL160TD-90, MBM29PL160BD-90, MBM29PL160BD-75 DATA SHEET

FUJITSU SEMICONDUCTOR

DATA SHEET

PAGE MODE FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

DS05-20872-1E

MBM29PL160TD

FEATURES

■

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

• Compatible with MASK ROM pinouts

48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
44-pin SOP (Package suffix: PF)

• Minimum 100,000 program/erase cycles

• High performance

25 ns maximum page access time (75ns maximum random access time)

• An 8 words page read mode function

• Sector erase architecture

One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode
One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector
B = Bottom sector

TM

• Embedded Erase

Automatically pre-programs and erases the chip or any sector

• Embedded program

Automatically programs and verifies data at specified address

•Data

• Ready/Busy output (RY/BY)

• Automatic sleep mode

•Low V

Polling and Toggle Bit feature for detection of program or erase cycle completion

Hardware method for detection of program or erase cycle completion

When addresses remain stable, automatically switches themselves to low power mode

write inhibit ≤ 2.5 V

CC

Algorithms

TM

Algorithms

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2

PROMs

/MBM29PL160BD

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(Continued)

Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MBM29PL160TD

(Continued)

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Temporary sector unprotection

Temporary sector unprotection with the software command

• 5V tolerant (Data, Address, and Control Signals)

• In accordance with CFI (C

PACKAGE

■

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ommon Flash Memory Interface)

Marking Side

/MBM29PL160BD

48-pin plastic TSOP (I)

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44-pin plastic SOP

(FPT-44P-M16)

Marking Side

(FPT-48P-M20)(FPT-48P-M19)

2

MBM29PL160TD

GENERAL DESCRIPTION

■

The MBM29PL160TD/BD is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (I), and 44-pin SOP pac kages. The
device is designed to be programmed in-system with the standard system 3.0 V V
V V

are not required for write or erase operations. The de vice can also be reprogr ammed in standard EPROM

CC

programmers.
The standard MBM29PL160TD/BD offers access times of 75 ns and 90 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the de vice has separate chip enable (CE
enable (WE

The MBM29PL160TD/BD is pin and command set compatible with JEDEC standard E
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and er ase operations . Reading data out of the de vice is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29PL160TD/BD is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before e xecuting the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.

), and output enable (OE) controls.

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/MBM29PL160BD

supply. 12.0 V VPP and 5.0

CC

2

PROMs. Commands are

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), write

Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29PL160TD/BD is erased when shipped from the
factory .

The device f eatures single 3.0 V power supply oper ation f or both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data
or by the Toggle Bit feature on DQ
the device internally resets to the read mode.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiv eness . The MBM29PL160TD/BD memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are programmed one b yte/word
at a time using the EPROM programming mechanism of hot electron injection.

output pin. Once the end of a program or erase cycle has been comleted,

6

detector automatically

CC

Polling of DQ7

3

MBM29PL160TD

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■

• One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode.

• One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user definable.

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 256 Kbytes or 128 Kwords 000000H to 03FFFFH 00000H to 1FFFFH
SA1 256 Kbytes or 128 Kwords 040000H to 07FFFFH 20000H to 3FFFFH
SA2 256 Kbytes or 128 Kwords 080000H to 0BFFFFH 40000H to 5FFFFH
SA3 256 Kbytes or 128 Kwords 0C0000H to 0FFFFFH 60000H to 7FFFFH
SA4 256 Kbytes or 128 Kwords 100000H to 13FFFFH 80000H to 9FFFFH
SA5 256 Kbytes or 128 Kwords 140000H to 16FFFFH A0000H to BFFFFH
SA6 256 Kbytes or 128 Kwords 180000H to 1BFFFFH C0000H to DFFFFH
SA7 224 Kbytes or 112 Kwords 1C0000H to 1F7FFFH E0000H to FBFFFH
SA8 8 Kbytes or 4 Kwords 1F8000H to 1F9FFFH FC000H to FCFFFH
SA9 8 Kbytes or 4 Kwords 1FA000H to 1FBFFFH FD000H to FDFFFH

SA10 16 Kbytes or 8 Kwords 1FC000H to 1FFFFFH FE000H to FFFFFH

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/MBM29PL160BD

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MBM29PL160TD Top Boot Sector Architecture

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 16 Kbytes or 8 Kwords 000000H to 003FFFH 00000H to 01FFFH
SA1 8 Kbytes or 4 Kwords 004000H to 005FFFH 02000H to 02FFFH
SA2 8 Kbytes or 4 Kwords 006000H to 007FFFH 03000H to 03FFFH
SA3 224 Kbytes or 112 Kwords 008000H to 03FFFFH 04000H to 1FFFFH
SA4 256 Kbytes or 128 Kwords 040000H to 07FFFFH 20000H to 3FFFFH
SA5 256 Kbytes or 128 Kwords 080000H to 0BFFFFH 40000H to 5FFFFH
SA6 256 Kbytes or 128 Kwords 0C0000H to 0FFFFFH 60000H to 7FFFFH
SA7 256 Kbytes or 128 Kwords 100000H to 13FFFFH 80000H to 9FFFFH
SA8 256 Kbytes or 128 Kwords 140000H to 17FFFFH A0000H to BFFFFH
SA9 256 Kbytes or 128 Kwords 180000H to 1BFFFFH C0000H to DFFFFH

SA10 256 Kbytes or 128 Kwords 1C0000H to 1FFFFFH E0000H to FFFFFH

MBM29PL160BD Bottom Boot Sector Architecture

4

MBM29PL160TD

PRODUCT LINE UP

■

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/MBM29PL160BD

Part No. MBM29PL160TD/160BD

Ordering Part No.

V

CC

= 3.0 V

+0.6 V
–0.3 V

-75 -90

Max. Address Access Time (ns) 75 90
Max. Page Address Access Time (ns) 25 35
Max. CE

Access Time (ns) 75 90

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Max. OE

■

Access Time (ns) 25 35

BLOCK DIAGRAM

CC

V

SS

V

WE

BYTE

CE
OE

State

Control

Command

Register

Program Voltage

Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

DQ0 to DQ

Input/Output

Buffers

Data Latch

15

A0 to A

STB

CC

Low V

Detector

19

-1

A

Timer for

Program/Erase

Address

Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

5

MBM29PL160TD

CONNECTION DIAGRAMS

■

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/MBM29PL160BD

-75/-90

SOP

(Marking Side)

144

WE

A

18

243

A

17

342
441

A

7

A

6

540

A

5

639
738

A

4

A

3

837

A

2

936

A

1

10 35
11 34

A

0

CE

12 33

V

SS

13 32

OE

14 31

DQ

0

15 30
16 29

DQ

8

DQ

1

17 28

DQ

9

18 27
19 26

DQ

2

DQ

10

20 25
21 24

DQ

3

22 23

DQ

11

FPT-44P-M16

N.C.
A

19

A

8

A

9

A

10

A

11

A

12

A

13

A

14

A

15

A

16

BYTE
V

SS

DQ15/A
DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

TSOP(I)

BYTE

A
A
A
A
A
A
A

A

WE

N.C.

A
A

CE

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

A

9

9

A

8

10

19

11
12
13

18

14

17

15

A

7

16

A

6

17

A

5

18

A

4

19

A

3

20

A

2

21

A

1

22

A

0

23
24

(Marking Side)

Standard Pinout

N.C.

48

V

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

SS

DQ15/A
DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

V

CC

V

SS

DQ

11

DQ

3

DQ

10

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

OE
V

SS

N.C.

-1

FPT-48P-M19

-1

CE

A
A

N.C.

WE

A

A
A
A
A
A
A
A

BYTE

24

A

0

23

A

1

22

A

2

21

A

3

20

A

4

19

A

5

18

A

6

17

A

7

16

17

15

18

14
13
12

19

11

A

8

10

A

9

9

10

8

11

7

12

6

13

5

14

4

15

3

16

2
1

(Marking Side)

Reverse Pinout

N.C.

25

V

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

SS

OE
DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

V

SS

V

CC

V

CC

DQ

4

DQ

12

DQ

5

DQ

13

DQ

6

DQ

14

DQ

7

DQ15/A
V

SS

N.C.

-1

FPT-48P-M20

6

MBM29PL160TD

LOGIC SYMBOL

■

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/MBM29PL160BD

Table 1 MBM29PL160TD/BD Pin Configuration

Pin Function

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20

-1

A

A0 to A

CE
OE
WE
BYTE

19

DQ0 to DQ

15

16 or 8

-1

, A0 to A

A

DQ0 to DQ

CE

OE

WE

BYTE

N.C.

SS

V

CC

V

19

15

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Selects 8-bit or 16-bit mode
Pin Not Connected Internally
Device Ground

Device Power Supply

7

MBM29PL160TD

DEVICE BUS OPERATIONS

■

Table 2 MBM29PL160TD/BD User Bus Operation (BYTE = VIH)

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/MBM29PL160BD

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Operation CE

OE WE A

A

0

A

1

6

Auto-Select Manufacture Code (1) L L H L L L V
Auto-Select Device Code (1) L L H H L L V
Read (3) L L H A

A

0

A

1

6

A

9

ID

ID

A

9

DQ0 to DQ

Code
Code

15

D

OUT

Standby H X X X X X X HIGH-Z
Output Disable LHHXXXXHIGH-Z
Write (Program/Erase) L H L A
Enable Sector Protection (2), (4) L V

ID

LHLVIDX

Verify Sector Protection (2), (4) L L H L H L V

Table 3 MBM29PL160TD/BD User Bus Operation (BYTE

Operation CE

OE WE

DQ15/

A

-1

Auto-Select Manufacture Code (1) L L H L L L L V
Auto-Select Device Code (1) L L H L H L L V
Read (3) L L H A

-1

A

0

A

1

A

6

9

ID

D

IN

Code

= VIL)

A

A

A

A

0

1

6

A

A

0

A

1

6

9

ID

ID

A

9

DQ0 to DQ

Code
Code

D

OUT

7

Standby H X X X X X X X HIGH-Z
Output Disable L H H X X X X X HIGH-Z
Write (Program/Erase) L H L A
Enable Sector Protection (2), (4) L V

ID

-1

0

1

6

LLHLV

Verify Sector Protection (2), (4) L L H L L H L V

Legend:
Notes:

L = V

1. Manufacturer and device codes may also be accessed via a command register write sequence. See

, H = VIH, X = VIL or VIH. = pulse input. See DC Characteristics for voltage levels.

IL

A

9

ID

ID

D

X

Code

A

A

A

Table 7.

2. Refer to the section on Sector Protection.

3. WE

4. V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

= 3.3 V ±10%

CC

IN

8

MBM29PL160TD

FUNCTIONAL DESCRIPTION

■

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/MBM29PL160BD

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Random Read Mode

The MBM29PL160TD/BD has two control functions which must be satisfied in order to obtain data at the outputs.
CE

is the power control and should be used for a de vice selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.
Address access time (t

access time (t
enable access time is the delay from the falling edge of OE
addresses have been stable for at least t
out a data without changing addresses after powe-up, it is necessary to input hardware reset or to change CE
pin from "H" to "L".

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

CE

) is equal to the delay from stable addresses to valid output data. The chip enable

ACC

to valid data at the output pins. (Assuming the

- tOE time.) See Figure 5.1 for timing specifications. When reading

ACC

Page Read Mode

The MBM29PL160TD/BD is capable of fast P age read mode and is compatible with the P age mode MASK ROM
read operation. This mode provides faster read access speed f or random locations within a page. The P age size
of the MBM29PL160TD/BD device is 8 words, or 16 bytes, within the appropriate Page being selected by the
higheraddress bits A
bytewithin that page. This is an asynchronous oper ation with the microprocessor supplying the specific word or
byte location.

The rondom or initial page access is equal to t
specified by the microprocessor fall within that Page) is equivalent to t
and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast
Page mode accesses are obtained by keeping A
word, or changing A

to A2 (in the word mode) and A-1 to A2 (in the byte mode) determining the specific word/

0

and subsequent Page read access (as long as the locations

ACC

. Here again, CE selects the device

PAC C

to A19 constant and changing A0 to A2 to select the specific

3

to A2 to select the specific byte, within that page. See Figure 5.2 for timing specifications.

-1

Standby Mode

The MBM29PL160TD/BD has a standby mode, a CMOS standby mode (CE input hel at VCC ±0.3 V.), when the
current consumed is less than 50 µA. During Embedded Algorithm operation, V
even CE

= “H”. The device can be read with standard access time (tCE) from standby modes.

Active current (I

CC

) is required

CC2

In the standby mode, the outputs are in the high-impedance state, independent of the OE
is deselected during erasure or programming, the device will dr aw active current until the operation is completed.

input. If the device

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29PL160TD/BD data. This mode can be used effectively with an application requesting low power
consumption such as handy terminals.

To activate this mode, MBM29PL160TD/BD automatically switches itself to low power mode when addresses
remain stable for 150 ns. It is not necessary to control CE
current consumed is typically 50 µA (CMOS Lev e l).

Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.

, WE, and OE in this mode. During such mode, the

Output Disable

If the OE input is at a logic high lev el (VIH), output from the device is disabled. This will cause the output pins to
be in a high-impedance state.

9

MBM29PL160TD

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/MBM29PL160BD

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Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manu facturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command ma y also be used to check the status
of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional ov er the entire temper ature range
of the device.

To activate this mode, the programming equipment must force V
identifier bytes may then be sequenced from the devices outputs by toggling address A
addresses are DON’T CARES except A

, A1, and A6 (A-1). (See Table 2 or Table 3.) (Recomend to set VIL for

0

(11.5 V to 12.5 V) on address pin A9. Two

ID

from VIL to VIH. All

0

the other addresses pins.)
The manufacturer and device codes may also be read via the command register, for instances when the

MBM29PL160TD/BD is erased or programmed in a system without access to high voltage on the A

pin. The

9

command sequence is illustrated in Table 7, Command Definitions.
Word 0 (A

= VIL) represents the manufacture’ s code and w ord 1 (A0 = VIH) represents the device identifier code.

0

For the MBM29PL160TD/BD these two bytes are given in the Table 4.2. All identifiers for manufactures and
device will exhibit odd parity with DQ
executing the Autoselect, A

If BYTE
= V

= VIL (for byte mode), the de vice code is 27H (f or top boot bloc k) or 45H (for bottom boot b lock). If BYTE

(for word mode), the device code is 2227H (for top boot block) or 2245H (for bottom boot block).

IH

must be VIL. (See Tables 2 or 3.)

1

In order to determine which sectors are write protected, A
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ

defined as the parity bit. In order to read the proper device codes when

7

must be at VIH while running through the sector

1

(DQ0 =1).

0

10

MBM29PL160TD

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/MBM29PL160BD

Table 4.1 MBM29PL160TD/BD Sector Protection Verify Autoselect Code

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Type A

to A

12

19

Manufacture’s Code X V

Byte

MBM29PL160TD

XV

A

6

IL

IL

A

1

V

IL

V

IL

A

0

V

IL

V

IH

A-1*

V
V

1

IL

IL

Code

(HEX)

04H
27H

Word X 2227H

Device Code

MBM29PL160BD

Byte

XV

IL

V

IL

V

IH

V

IL

45H

Word X 2245H

Sector Protection

Sector

Addresses

Temporary Sector Unprotection X V

V

IL

IL

V

IH

V

IH

V

IL

V

IH

V

IL

V

IL

01H*

01H*

2

3

*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
*3: Outputs 01H at Temporary Sector Unprotect and outputs 00H at Non Temporary Sector Unprotect.

Table 4.2 Expanded Autoselect Code Table

Type

Code DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

Manufacture’s Code 04H A-1/0000000000000100

0

(B)

MBM29PL160TD

Device
Code

MBM29PL160BD

27H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z10100111

(W) 2227H

(B)

45H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z01000101

(W)

2245H

Sector Protection 01H A
Temporary Sector

Unprotection

01H A

(B): Byte mode
(W): Word mode

0010001010100111

0010001001000101

/0000000000000001

-1

/0000000000000001

-1

11

MBM29PL160TD

Table 5 Sector Address Tables (MBM29PL160TD)

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/MBM29PL160BD

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Sector

Address

A

A

A

A

A

A

A

A

19

18

17

16

15

14

13

(× 8) Address Range (× 16) Address Range

12

SA0 000XXXXX000000H to 03FFFFH 00000H to 1FFFFH
SA1 001XXXXX040000H to 07FFFFH 20000H to 3FFFFH
SA2 010XXXXX080000H to 0BFFFFH 40000H to 5FFFFH
SA3 011XXXXX0C0000H to 0FFFFFH60000H to 7FFFFH
SA4 100XXXXX100000H to 13FFFFH 80000H to 9FFFFH
SA5 101XXXXX140000H to 17FFFFH A0000H to BFFFFH
SA6 110XXXXX180000H to 1BFFFFH C0000H to DFFFFH
SA7 1 1 1 00000 - 11011 1C0000H to 1F7FFFH E0000H to FBFFFH
SA8 111111001F8000H to 1F9FFFHFC000H to FCFFFH
SA9 111111011FA000H to 1FBFFFHFD000H to FDFFFH

SA101111111X1FC000H to 1FFFFFH FE000H to FFFFFH

Table 6 Sector Address Tables (MBM29PL160BD)

Sector

Address

A

A

A

A

A

A

A

A

19

18

17

16

15

14

13

(× 8) Address Range (× 16) Address Range

12

SA0 0000000X000000H to 003FFFH 00000H to 01FFFH
SA1 00000010004000H to 005FFFH 02000H to 02FFFH
SA2 00000011006000H to 007FFFH 03000H to 03FFFH
SA3 0 0 0 00100 - 11111 008000H to 03FFFFH 04000H to 1FFFFH
SA4 001XXXXX040000H to 07FFFFH 20000H to 3FFFFH
SA5 010XXXXX080000H to 0BFFFFH 40000H to 5FFFFH
SA6 011XXXXX0C0000H to 0FFFFFH60000H to 7FFFFH
SA7 100XXXXX100000H to 13FFFFH 80000H to 9FFFFH
SA8 101XXXXX140000H to 17FFFFH A0000H to BFFFFH
SA9 110XXXXX180000H to 1BFFFFH C0000H to DFFFFH

SA10 111XXXXX1C0000H to 1FFFFFHE0000H to FFFFFH

12

MBM29PL160TD

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/MBM29PL160BD

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Write

Device erasure and progr amming are accomplished via the command register . The command register is written
by bringing WE
WE

, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first.

Standard microprocessor write timings are used. See Figures 6 to 8.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or

Sector Protection

The MBM29PL160TD/BD features hardware sector protection. This f eature will disable both progr am and erase
operations in any number of sectors (0 through 10). The sector protection f eature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V
V

, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to

IL

the sector to be protected. T ab les 5 and 6 define the sector address for each of the ele ven (11) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE
rising edge of the same. Sector addresses must be held constant during the WE
for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V
with CE
while (A
device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A
A
codes. A

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. P erforming
a read operation at the address location XX02H, where the higher order addresses pins (A
A
Tables 4.1 and 4.2 for Autoselect codes.

and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)

, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector . Otherwise the

6

are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device

6

requires to VIL in byte mode.

-1

, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See

14

on address pin A9 and control pin OE, CE =

ID

pulse and is terminated with the

pulse. See figures 14 and 20

on address pin A9

ID

, A1, and

0

, A18, A17, A16, A15,

19

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29PL160TD/BD de vices
in order to change data. The Temporary Sector Unprotection mode is activated by command register. During
this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once
the mode is taken away using command register, all the previously protected sectors will be protected again.
(See Figures 20.)

13

MBM29PL160TD

Table 7 MBM29PL160TD/BD Standard Command Definitions

-75/-90

/MBM29PL160BD

-75/-90

Command
Sequence

(Notes 1, 2, 3, 5)

Read/Reset
(Note 6)

Read/Reset
(Note 6)

Word

/Byte

Word

Byte AAAH 555H AAAH

Word

Autoselect

Byte AAAH 555H AAAH

Byte/Word
Program
(Notes 3, 4)

Word

Byte AAAH 555H AAAH

Word

Chip Erase

Byte AAAH 555H AAAH AAAH 555H AAAH

Sector Erase
(Note 3)

Sector Erase
Suspend

Sector Erase
Resume

Temporary
Unprotect
Enable

Temporary
Unprotect
Disable

Word

Byte AAAH 555H AAAH AAAH 555H

Word

/Byte

Word

/Byte

Word

Byte AAAH 555H AAAH

Word

Byte AAAH 555H AAAH

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second

Bus

Write Cycle

Third Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

1XXXHF0H——————————

555H

3

555H

3

555H

4

555H

6

555H

6

AAH

AAH

AAH

AAH

AAH

2AAH

2AAH

2AAH

2AAH

2AAH

55H

55H

55H

55H

55H

555H

555H

555H

555H

555H

F0H RA RD — — — —

90H——————

A0H PA PD — — — —

555H

80H

555H

80H

AAH

AAH

2AAH

2AAH

555H

55H

10H

55H SA 30H

1XXXHB0H——————————

1XXXH30H——————————

555H

4

555H

4

AAH

AAH

2AAH

2AAH

55H

55H

555H

E0H XXXH 01H — — — —

555H

E0H XXXH 00H — — — —

14

Notes:

1. Address bits A

to A19 = X = “H” or “L” for all address commands e xcept or Prog r am Address (PA) and

11

Sector Address (SA).

2. Bus operations are defined in Tables 2 and 3.

3. RA =Address of the memory location to be read.
PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE

SA =Address of the sector to be erased. The combination of A

pulse.

, A18, A17, A16, A15, A14, A13, and A12 will

19

uniquely select any sector.

4. RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the rising edge of WE

.

5. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A
Byte Mode: AAAH or 555H to addresses A-1 to A

to A

0

10
10

6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

MBM29PL160TD

Table 8 MBM29PL160TD/BD Extended Command Definitions

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/MBM29PL160BD

-75/-90

Command

Sequence

Set to Fast
Mode

Fast Program *1

Reset from Fast
Mode *1

Query
Command *2

SPA : Sector Address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector

addresses.

. This command is valid while fast mode.

*1

. Addresses from system set to A

*2

. The data" 00H" is also acceptable.

*3

Word

Byte AAAH 555H AAAH

Word

Byte XXXH

Word

Byte XXXH XXXH

Word

Byte AAH

Bus

Write

Cycles

Req'd

3

2

2

2

First Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data

555H

XXXH

XXXH

55H

to A6. The other addresses are “Don’t care”.

0

AAH

A0H PA PD — — — —

90H

98H — — — — — —

Second Bus

Write Cycle

2AAH

XXXH

F0H *3 — — — —

55H

Third Bus

Write Cycle

555H

Fourth Bus
Read Cycle

20H — —

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in prog ress . Moreo v er both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ

to DQ7 and DQ8 to DQ15 bits are ignored.

0

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register . Microprocessor
read cycles retrieve array data from the memory. The device remains enabled for reads until the command
register contents are altered.

The device will automatically power-up in the Read/Reset state . In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters. (See Figure 5.1 and 5.2.)

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufactures and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register .
Following the last command write, a read cycle from address XX00H retrie v es the manufacture code of 04H. A
read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the de vice code (MBM29PL160TD = 27H and

to a high voltage. However, multiplexing high

9

15

MBM29PL160TD

MBM29PL160BD = 45H for ×8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for ×16 mode).
(See Tables 4.1 and 4.2.)

-75/-90

/MBM29PL160BD

-75/-90

All manufactures and device codes will exhibit odd parity with DQ
The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).
Scanning the sector addresses (A
a logical “1” at device output DQ
mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by e xecuting it after writing the Read/Reset command
sequence.

, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

19

for a protected sector . The programming v erification should be perform margin

0

defined as the parity bit.

7

Word/Byte Programming

The device is programmed on a b yte-by-byte (or word-by-word) basis . Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are f ollowed b y the program set-up command and data write cycles .
Addresses are latched on the falling edge of CE
rising edge of CE
first) begins programming. Upon ex ecuting the Embedded Progr am Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The automatic programming operation is completed when the data on DQ
bit at which time the device return to the read mode and addresses are no longer latched. (See T ab le 9, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data

Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.

or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

Polling must be performed at the memory location which is being programmed.

or WE, whichev er happens later and the data is latched on the

is equivalent to data written to this

7

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so ma y either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded Program

TM

Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase
Algorithm command sequence the device will automatically program and v erify the entire memory for an all zero
data pattern prior to electrical erase . (Preprogram Function.) The system is not required to provide an y controls
or timings during these operations.

The automatic erase begins on the rising edge of the last WE
when the data on DQ
(See Figure 8.)

Figure 17 illustrates the Embedded Erase

is “1” (See Write Operation Status section.) at which time the device returns to read mode.

7

TM

Algorithm using typical command strings and bus operations.

pulse in the command sequence and terminates

Sector Erase

Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then follo wed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE
= 30H) is latched on the rising edge of WE
command, the sector erase operation will begin.

. After a time-out of 50 µs from the rising edge of the last sector erase

, while the command (Data

16