FUJITSU MBM29PDS322TE, MBM29PDS322BE DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

32M (2M × 16) BIT

Page Dual Operation

MBM29PDS322TE/BE

DESCRIPTION

■■■■

The MBM29PDS322TE/BE is 32M-bit, 1.8 V-only Flash memor y organized as 2M words of 16 bits each. The device is offered in 63-ball FBGA package. This device is designed to be programmed in system with standard system 1.8 V V also be reprogrammed in standard EPROM programmers.

CC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The de vice can

DS05-20889-1E

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The device is organized into tw o banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as f ar as certain operations are concerned. This device is the same as Fujitsu’ s standard 1.8 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) oper ation is simultaneously taking place on the other bank.

(Continued)

PRODUCT LINE-UP

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Part No. MBM29PDS322TE/BE

Ordering Part No. V Max. Random Address Access Time (ns) 100 115

Max. Page Address Access Time (ns) 45 45 Max. CE Max. OE

■■■■

Access Time (ns) 100 115 Access Time (ns) 35 45

PACKAGE

CC = 2.0 V

+0.2 V –0.2 V

10 11

63-ball plastic FBGA

(BGA-63P-M01)

MBM29PDS322TE/BE

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(Continued)

The device provides truly high perfor mance non-volatile Flash memory solution. The device offers fast page access times of 45 ns with random access times of 100 ns and 115 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the de vice has separate chip enable (CE enable (WE

The device is pin and command set compatible with JEDEC standard E

), and output enable (OE) controls. The page size is 4 words.

PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and er ase operations. Reading data out of the de vice is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by ex ecuting the erase command sequence. This will inv oke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed bef ore ex ecuting the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

), write

The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device f eatures single 1.8 V po w er supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V inhibits write operations on the loss of power. The end of program or erase is detected by Data by the Toggle Bit feature on DQ

6, or the RY/BY output pin. Once the end of a program or erase cycle has been

CC detector automatically

Polling of DQ7,

completed, the device internally resets to the read mode. The device also has a hardware RESET

pin. When this pin is driven low, execution of any Embedded Progr am Algorithm or Embedded Erase Algorithm is terminated. The inter nal state machine is then reset to the read mode. The RESET

pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels of quality , reliability, and cost eff ectiveness . The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29PDS322TE/BE

FEATURES

■■■■

•

0.23 µm Process Technology

•

Simultaneous Read/Write operations (Dual Bank)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program

•

High performance Page Mode

45 ns maximum page access time (100 ns random access time) 4 words Page Size

•

Single 1.8 V read, program, and erase

Minimized system level power requirements

•

Compatible with JEDEC-standard commands

Use the same software commands as E

•

Compatible with JEDEC-standard world-wide pinouts

63-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

•

Sector erase architecture

Eight 4 Kword and sixty-three 32 Kword sectors in word mode Any combination of sectors can be concurrently erased. Also supports full chip erase.

•

Boot Code Sector Architecture

T = Top sector B = Bottom sector

•

Hidden ROM (Hi-ROM) region

64 Kbyte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)

•

/ACC input pin

At V

IL, allows protection of boot sectors, regardless of sector protection/unprotection status.

At VIH, allows removal of boot sector protection. At V

ACC, increases program performance.

•

Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector.

•

Embedded Program

Algorithms

Automatically writes and verifies data at specified address.

•Data

•

Polling and Toggle Bit feature for detection of program or erase cycle completion

Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

•

Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

•

Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device.

•

Sector group protection

Hardware method disables any combination of sector groups from program or erase operations.

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

•

Temporary sector group unprotection

Temporary sector group unprotection via the RESET

PROMs.

pin.

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MBM29PDS322TE/BE

Table 1: MBM29PDS322TE/BE Device Bank Division

Device

Part Number

Organization

Megabits Sector Sizes Megabits Sector Sizes

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Bank 1 Bank 2

MBM29PDS322TE/BE × 16 4 Mbit

Eight 4 Kword,

seven 32 Kword

28 Mbit Fifty-six 32 Kword

PIN ASSIGNMENT

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MBM29PDS322TE/BE

(TOP VIEW)

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A8 B8

N.C.

A7 B7 C7 D7 E7 F7 G7 H7 J7 K7

N.C.

13 A12 A14 A15 A16 DQ15 VSS N.C.

C6 D6 E6 F6 G6 H6 J6 K6

9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

C5 D5 E5 F5 G5 H5 J5 K5

WE RESET N.C. A19 DQ5 DQ12 VCC DQ4

C4 D4 E4 F4 G4 H4 J4 K4

RY/BY WP/ACC A

C3 D3 E3 F3 G3 H3 J3 K3

7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

C2 D2 E2 F2 G2 H2 J2 K2 L2 M2

4 A2 A1 A0 CE OE VSS

(Marking Side)

N.C.

18 A20 DQ2 DQ10 DQ11 DQ3

N.C.

(BGA-63P-M01)

*: Peripheral balls on each corner are shorted together via the substrate but not connected to the die.

MBM29PDS322TE/BE

PIN DESCRIPTION

■■■■

Table 2: MBM29PDS322TE/BE Pin Configuration

Pin name Function

20 to A0 Address Inputs

15 to DQ0 Data Inputs/Outputs

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CE OE

WE Write Enable

RY/BY

RESET

WP/ACC Hardware Write Protection/Program Acceleration

N.C. No Internal Connection

SS Device Ground

VCC Device Power Supply

Chip Enable Output Enable

Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection

BLOCK DIAGRAM

■■■■

A20 to A0

VCC VSS

Bank 2

address

MBM29PDS322TE/BE

Cell Matrix

(Bank 2)

Y-Gating

X-Decoder

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LOGIC SYMBOL

■■■■

RESET

CE OE

WP/ACC

15 to DQ0

State

Control

Command

Status Control

Bank 1

address

CE OE WE RESET WA/ACC

20 to A0

RY/BY

DQ15 to DQ0

X-Decoder

Cell Matrix

(Bank 1)

Y-Gating

DQ15 to DQ0

RY/BY

MBM29PDS322TE/BE

DEVICE BUS OPERATION

■■■■

Table 3: MBM29PDS322TE/BE User Bus Operations

Operation CE

OE WE A0A1A2A3A6A

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DQ15 to

RESET

WP/

ACC

Auto-Select Manufacturer Code *

Auto-Select Device Code * Extended Auto-Select Device

Code * Read *

LLHLLLLLVID Code H X

LLHHLLLLVID Code H X LLHL/HHHHLVID Code H X

LLHA0 A1 A2 A3 A6 A9 DOUT HX Standby H X XXXXXXX High-Z H X Output Disable LHHXXXXXX High-Z H X Write (Program/Erase) L H L A Enable Sector Group

Protection *

2, *4

Verify Sector Group Protection

2, *4

* Temporary Sector Group

Unprotection *

LVID LHLLLVID XHX

LLHLHLLLVID Code H X

XXXXXXXXX X VID X

0 A1 A2 A3 A6 A9 DIN HX

Reset (Hardware) / Standby XXXXXXXXX High-Z L X Boot Block Sector Write

Protection *

Legend: L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels.

XXXXXXXXX X X L

*1:Manufacturer and device codes may also be accessed via a command register write sequence. See Table 3. *2:Refer to section on Sector Group Protection. *3:WE *4:V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

CC must be between the minimum and maximum of the operation range.

*5:It is also used for the extended sector group protection. *6:Protect “outermost” 2 × 4 Kwords of the boot block sectors.

MBM29PDS322TE/BE

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Table 4: MBM29PDS322TE/BE Command Definitions

Fourth Bus Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Second Bus

Write Cycle

Third Bus

Write Cycle

Read/Reset Word 1 XXXh F0h — — — — — — — — — — Read/Reset Word 3 555h AAh 2AAh 55h 555h F0h RA RD — — — — Auto

select

Word 3 555h AAh 2AAh 55h

(BA)

555h

90h——————

Program Word 4 555h AAh 2AAh 55h 555h A0h PA PD — — — — Chip Erase Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Sector

Erase

Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h

Erase Suspend 1 BA B0h — — — — — — — — — — Erase Resume 1 BA30h—————————— Set to

Fast Mode Fast

Program * Reset from

Fast Mode *

Extended Sector Group Protection *

Query Word 1 Hi-ROM

Entry Hi-ROM

Program *

Word 3 555h AAh 2AAh 55h 555h 20h — — — — — —

Word 2 XXXh A0h PA PD — — — — — — — —

Word 2 BA 90h XXXh

F0h

————————

Word 4 XXXh 60h SPA 60h SPA 40h SPA SD — — — —

(BA)

55h

98h——————————

Word 3 555h AAh 2AAh 55h 555h 88h — — — — — —

Word 4 555h AAh 2AAh 55h 555h A0h

(HRA)

PD————

Hi-ROM Erase *

Hi-ROM

Exit *

Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30h

Word 4 555h AAh 2AAh 55h

*1:This command is valid while Fast Mode. *2:This command is valid while RESET

= VID. *3:This command is valid while Hi-ROM mode. *4:The data “00h” is also acceptable. Note 1.Address bits A

20 to A12 = X = “H” or “L” for all address commands e xcept or Program Address (PA), Sector

Address (SA), and Bank Address (BA).

2.Bus operations are defined in Table 8.

3.RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse.

(HRBA)

555h

90h XXXh 00h — — — —

MBM29PDS322TE/BE

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SA = Address of the sector to be erased. The combination of A A BA = Bank Address (A

12 will uniquely select any sector.

20 to A15)

20, A19, A18, A17, A16, A15, A14, A13, and

4.RD = Data read from location RA during the read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5.SPA = Sector group address to be protected. Set sector group address (SGA) and (A

6, A1, A0) = (0, 1, 0).

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses.

6.HRA = Address of the Hi-ROM area 29PDS322TE (Top Boot Type)Word Mode:1F8000h to 1FFFFFh 29PDS322BE (Bottom Boot Type)Word Mode:000000h to 007FFFh

7.HRBA =Bank Address of the Hi-ROM area 29PDS322TE (Top Boot Type):A 29PDS322BE (Bottom Boot Type):A

= A

= A16 = A

= A

= A16 = A

= 1

= 0

8.The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A

10 to A0

9.Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Table 5.1 MBM29PDS322TE Sector Group Protection Verify Autoselect Codes

Type A

to A

Manufacture’s Code BA Device Code Word BA

Extended Device Code *

Word BA Word BA

MBM29PDS322TE/BE

VIL VIL VIL VIL VIL 04h VIL VIL VIL VIL VIH 227Eh VIL VIH VIH VIH VIL 2206h VIL VIH VIH VIH VIH 2201h

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Code (HEX)

Sector Group Protection

Sector Group

Addresses

IL VIL VIL VIH VIL 01h

*1:Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:When V

ID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous oper ation

unable to be ex ecuted. Consequently , specifying the bank address is not demanded. How ever , the bank address needs to be indicated when Autoselect mode is read out at command mode; because then it becomes OK to activate simultaneous operation.

*3:A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh.

Table 5.2 Expanded Autoselect Code Table

Type Code

Manufacturer’s Code

Device Code (W) Extended

Device Code

(W) (W)

Sector Group Protection

227Eh 2206h 2201h

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

04h0 0 0 0 0 00000000100

0 0 1 0 0 01001111110 0 0 1 0 0 01000000110 0 0 1 0 0 01000000001

01h0 0 0 0 0 00000000001

(W): Word mode

MBM29PDS322TE/BE

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Table 5.3 MBM29PDS322BE Sector Group Protection Verify Autoselect Codes

Type A

to A

Manufacture’s Code BA Device Code Word BA

Extended Device Code *

Sector Group Protection

Word BA Word BA

Sector Group

Addresses

Code (HEX)

VIL VIL VIL VIL VIL 04h VIL VIL VIL VIL VIH 227Eh VIL VIH VIH VIH VIL 2206h VIL VIH VIH VIH VIH 2200h

VIL VIL VIL VIH VIL 01h

*1:Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2:When V

ID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous oper ation

* 3:A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh.

Table 5.4 Expanded Autoselect Code Table

Type Code

Manufacturer’s Code

Device Code (W) Extended

Device Code

(W) (W)

Sector Group Protection

227Eh 2206h 2200h

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

04h0000000000000100

0010001001111110 0010001000000110 0010001000000000

01h0000000000000001

(W): Word mode

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■■■■

Table 6.1 Sector Address Tables (MBM29PDS322TE)

Sector Address

Bank Sector

20A19

Bank Address

A18A17A

SA0 0 0 0 0 0 0 X X X 32 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X 32 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X 32 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X 32 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X 32 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X 32 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X 32 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X 32 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X 32 040000h to 047FFFh

SA9 0 0 1 0 0 1 X X X 32 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X 32 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X 32 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X 32 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X 32 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X 32 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X 32 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X 32 080000h to 087FFFh

Bank 2

SA17 0 1 0 0 0 1 X X X 32 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X 32 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X 32 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X 32 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X 32 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X 32 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X 32 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X 32 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X 32 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X 32 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X 32 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X 32 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X 32 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X 32 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X 32 0F8000h to 0FFFFFh SA32 1 0 0 0 0 0 X X X 32 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X 32 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X 32 110000h to 117FFFh

MBM29PDS322TE/BE

Sector

Size

(Kwords)

(

Address Range

××××

16)

(Continued)

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MBM29PDS322TE/BE

(Continued)

Sector Address

Bank Sector

SA35 1 0 0 0 1 1 X X X 32 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X 32 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X 32 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X 32 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X 32 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X 32 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X 32 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X 32 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X 32 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X 32 160000h to 167FFFh

Bank 2

SA45 1 0 1 1 0 1 X X X 32 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X 32 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X 32 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X 32 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X 32 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X 32 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X 32 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X 32 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X 32 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X 32 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X 32 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X 32 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X 32 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X 32 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X 32 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X 32 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X 32 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X 32 1F0000h to 1F7FFFh

Bank 1

SA63 1 1 1 1 1 1 0 0 0 4 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 4 1F9000h to 1F9FFFh SA65111111010 4 1FA000h to 1FAFFFh SA66111111011 4 1FB000h to 1FBFFFh SA67111111100 4 1FC000h to 1FCFFFh SA68111111101 4 1FD000h to 1FDFFFh SA69111111110 4 1FE000h to 1FEFFFh SA70111111111 4 1FF000h to 1FFFFFh

20A19

Bank Address

A18A17A

10/11

Sector

Size

(Kwords)

××××

(

16)

Address Range

MBM29PDS322TE Top Boot Sector Architecture

Bank Sector

SA70 1 1 1 1 1 1 X X X 32 1F8000h to 1FFFFFh SA69 1 1 1 1 1 0 X X X 32 1F0000h to 1F7FFFh SA68 1 1 1 1 0 1 X X X 32 1E8000h to 1EFFFFh SA67 1 1 1 1 0 0 X X X 32 1E0000h to 1E7FFFh SA66 1 1 1 0 1 1 X X X 32 1D8000h to 1DFFFFh SA65 1 1 1 0 1 0 X X X 32 1D0000h to 1D7FFFh SA64 1 1 1 0 0 1 X X X 32 1C8000h to 1CFFFFh SA63 1 1 1 0 0 0 X X X 32 1C0000h to 1C7FFFh SA62 1 1 0 1 1 1 X X X 32 1B8000h to 1BFFFFh SA61 1 1 0 1 1 0 X X X 32 1B0000h to 1B7FFFh SA60 1 1 0 1 0 1 X X X 32 1A8000h to 1AFFFFh SA59 1 1 0 1 0 0 X X X 32 1A0000h to 1A7FFFh SA58 1 1 0 0 1 1 X X X 32 198000h to 19FFFFh SA57 1 1 0 0 1 0 X X X 32 190000h to 197FFFh SA56 1 1 0 0 0 1 X X X 32 188000h to 18FFFFh SA55 1 1 0 0 0 0 X X X 32 180000h to 187FFFh SA54 1 0 1 1 1 1 X X X 32 178000h to 17FFFFh

Bank 2

SA53 1 0 1 1 1 0 X X X 32 170000h to 177FFFh SA52 1 0 1 1 0 1 X X X 32 168000h to 16FFFFh SA51 1 0 1 1 0 0 X X X 32 160000h to 167FFFh SA50 1 0 1 0 1 1 X X X 32 158000h to 15FFFFh SA49 1 0 1 0 1 0 X X X 32 150000h to 157FFFh SA48 1 0 1 0 0 1 X X X 32 148000h to 14FFFFh SA47 1 0 1 0 0 0 X X X 32 140000h to 147FFFh SA46 1 0 0 1 1 1 X X X 32 138000h to 13FFFFh SA45 1 0 0 1 1 0 X X X 32 130000h to 137FFFh SA44 1 0 0 1 0 1 X X X 32 128000h to 12FFFFh SA43 1 0 0 1 0 0 X X X 32 120000h to 127FFFh SA42 1 0 0 0 1 1 X X X 32 118000h to 11FFFFh SA41 1 0 0 0 1 0 X X X 32 110000h to 117FFFh SA40 1 0 0 0 0 1 X X X 32 108000h to 10FFFFh SA39 1 0 0 0 0 0 X X X 32 100000h to 107FFFh SA38 0 1 1 1 1 1 X X X 32 0F8000h to 0FFFFFh SA37 0 1 1 1 1 0 X X X 32 0F0000h to 0F7FFFh SA36 0 1 1 1 0 1 X X X 32 0E8000h to 0EFFFFh SA35 0 1 1 1 0 0 X X X 32 0E0000h to 0E7FFFh

20A19

MBM29PDS322TE/BE

Table 6.2 Sector Address Tables (MBM29PDS322BE)

Sector Address

Bank Address

A18A17A

Sector

Size

(Kwords)

10/11

××××

(

16)

Address Range

(Continued)

MBM29PDS322TE/BE

(Continued)

Sector Address

Bank Sector

SA34 0 1 1 0 1 1 X X X 32 0D8000h to 0DFFFFh SA33 0 1 1 0 1 0 X X X 32 0D0000h to 0D7FFFh SA32 0 1 1 0 0 1 X X X 32 0C8000h to 0CFFFFh SA31 0 1 1 0 0 0 X X X 32 0C0000h to 0C7FFFh SA30 0 1 0 1 1 1 X X X 32 0B8000h to 0BFFFFh SA29 0 1 0 1 1 0 X X X 32 0B0000h to 0B7FFFh SA28 0 1 0 1 0 1 X X X 32 0A8000h to 0AFFFFh SA27 0 1 0 1 0 0 X X X 32 0A0000h to 0A7FFFh SA26 0 1 0 0 1 1 X X X 32 098000h to 09FFFFh

Bank 2

SA25 0 1 0 0 1 0 X X X 32 090000h to 097FFFh SA24 0 1 0 0 0 1 X X X 32 088000h to 08FFFFh SA23 0 1 0 0 0 0 X X X 32 080000h to 087FFFh SA22 0 0 1 1 1 1 X X X 32 078000h to 07FFFFh SA21 0 0 1 1 1 0 X X X 32 070000h to 077FFFh SA20 0 0 1 1 0 1 X X X 32 068000h to 06FFFFh SA19 0 0 1 1 0 0 X X X 32 060000h to 067FFFh SA18 0 0 1 0 1 1 X X X 32 058000h to 05FFFFh SA17 0 0 1 0 1 0 X X X 32 050000h to 057FFFh SA16 0 0 1 0 0 1 X X X 32 048000h to 04FFFFh SA15 0 0 1 0 0 0 X X X 32 040000h to 047FFFh SA14 0 0 0 1 1 1 X X X 32 038000h to 03FFFFh SA13 0 0 0 1 1 0 X X X 32 030000h to 037FFFh SA12 0 0 0 1 0 1 X X X 32 028000h to 02FFFFh SA11 0 0 0 1 0 0 X X X 32 020000h to 027FFFh SA10 0 0 0 0 1 1 X X X 32 018000h to 01FFFFh

SA9 0 0 0 0 1 0 X X X 32 010000h to 017FFFh

SA8 0 0 0 0 0 1 X X X 32 008000h to 00FFFFh

Bank 1

SA7 0 0 0 0 0 0 1 1 1 4 007000h to 007FFFh

SA6 0 0 0 0 0 0 1 1 0 4 006000h to 006FFFh

SA5 0 0 0 0 0 0 1 0 1 4 005000h to 005FFFh

SA4 0 0 0 0 0 0 1 0 0 4 004000h to 004FFFh

SA3 0 0 0 0 0 0 0 1 1 4 003000h to 003FFFh

SA2 0 0 0 0 0 0 0 1 0 4 002000h to 002FFFh

SA1 0 0 0 0 0 0 0 0 1 4 001000h to 001FFFh

SA0 0 0 0 0 0 0 0 0 0 4 000000h to 000FFFh

20A19

Bank Address

A18A17A

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Sector

Size

(Kwords)

××××

(

16)

Address Range

MBM29PDS322BE Bottom Boot Sector Architecture

MBM29PDS322TE/BE

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Table 7.1 Sector Group Address Table (MBM29PDS322TE) (Top Boot Block)

Sector Group A

Sectors

SGA0 000000XXX SA0

SGA1 0000

XXXSA1 to SA310

11 SGA2 0001XXXXXSA4 to SA7 SGA3 0010XXXXXSA8 to SA11 SGA4 0011XXXXXSA12 to SA15 SGA5 0100XXXXXSA16 to SA19 SGA6 0101XXXXXSA20 to SA23 SGA7 0110XXXXXSA24 to SA27 SGA8 0111XXXXXSA28 to SA31 SGA9 1000XXXXXSA32 to SA35

SGA10 1001XXXXXSA36 to SA39 SGA11 1010XXXXXSA40 to SA43 SGA12 1011XXXXXSA44 to SA47 SGA13 1100XXXXXSA48 to SA51 SGA14 1101XXXXXSA52 to SA55 SGA15 1110XXXXXSA56 to SA59

SGA16 1 1 1 1

X X X SA60 to SA6201

SGA17 111111000 SA63 SGA18 111111001 SA64 SGA19 111111010 SA65 SGA20 111111011 SA66 SGA21 111111100 SA67 SGA22 111111101 SA68 SGA23 111111110 SA69 SGA24 111111111 SA70

MBM29PDS322TE/BE

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Table 7.2 Sector Group Address Table (MBM29PDS322BE) (Bottom Boot Block)

Sector Group A

Sectors

SGA0 000000000 SA0 SGA1 000000001 SA1 SGA2 000000010 SA2 SGA3 000000011 SA3 SGA4 000000100 SA4 SGA5 000000101 SA5 SGA6 000000110 SA6 SGA7 000000111 SA7

01 SGA8 0000

X X X SA8 to SA1010

11 SGA9 0001XXXXXSA11 to SA14

SGA10 0010XXXXXSA15 to SA18 SGA11 0011XXXXXSA19 to SA22 SGA12 0100XXXXXSA23 to SA26 SGA13 0101XXXXXSA27 to SA30 SGA14 0110XXXXXSA31 to SA34 SGA15 0111XXXXXSA35 to SA38 SGA16 1000XXXXXSA39 to SA42 SGA17 1001XXXXXSA43 to SA46 SGA18 1010XXXXXSA47 to SA50 SGA19 1011XXXXXSA51 to SA54 SGA20 1100XXXXXSA55 to SA58 SGA21 1101XXXXXSA59 to SA62 SGA22 1110XXXXXSA63 to SA66

SGA23 1 1 1 1

X X X SA67 to SA6901

SGA24 111111XXX SA70

MBM29PDS322TE/BE

FUNCTIONAL DESCRIPTION

■■■■

Simultaneous Operation

The device has feature, which is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, er ase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A

The device has two banks which contain

Bank 1 (4 KW × eight sectors, 32 KW × seven sectors) and Bank 2 (32 KW × fifty-six sectors).

The simultaneous operation can not execute multi-function mode in the same bank. Table 8 shows the possible combinations for simultaneous operation. (Refer to Figure 12 Back-to-Back Read/Write Timing Diagram.)

Case Bank 1 Status Bank 2 Status

1 Read mode Read mode 2 Read mode Autoselect mode 3 Read mode Program mode 4 Read mode Erase mode * 5 Autoselect mode Read mode 6 Program mode Read mode 7 Erase mode * Read mode

20 to A15) with zero latency.

Table 8 Simultaneous Operation

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*: An erase operation may also be suspended to read from or program to a sector not being erased.

Read Mode

The device has two control functions which must be satisfied in order to obtain data at the outputs. CE power control and should be used for a device selection. OE

is the output control and should be used as the

gate data to the output pins if a device is selected. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access

time (t

CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable

access time (t have been stable for at least t it is necessary to input hardware reset or to change CE

OE) is the delay from the f alling edge of OE to valid data at the output pins. (Assuming the addresses

ACC-tOE time.) When reading out data without changing addresses after power-up,

pin from “H” or “L”.

Page Mode Read

The device is capable of fast Page mode read operation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 4 words, within the appropriate Page being selected by the higher address bits A

20 to A2 and the LSB bits A1 and A0 within that page. This is an asynchronous

operation with the microprocessor supplying the specific word location. The random or initial page access is equal to tACC and subsequent Page read access (as long as the locations

specified by the microprocessor fall within that Page) is equivalent to t and OE Page mode accesses are obtained by keeping A

is the output control and should be used to gate data to the output pins if the device is selected. Fast

20 to A2 constant and changing A1 and A0 to select the specific

PAC C. Here again, CE selects the device

word, within that page. See Figure 5.4 for timing specifications.

is the

MBM29PDS322TE/BE

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Standby Mode

There are two ways to implement the standb y mode on the de vice , one using both the CE other via the RESET

pin only.

and RESET pins; the

When using both pins, a CMOS standby mode is achie v ed with CE

and RESET inputs both held at VCC ± 0.3 V. Under this condition, the current consumed is less than 5 µA Max. During Embedded Algorithm operation, V active current (ICC2) is required ev en CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes.

When using the RESET

pin only, a CMOS standby mode is achiev ed with RESET input held at VSS ± 0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken high, the device requires t

In the standby mode, the outputs are in the high impedance state, independently of the OE

RH as wake up time for outputs to be valid for read access.

input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption.

To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE

, WE, and OE on the mode.

Under the mode, the current consumed is typically 50 µA (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically, and the device reads the data for changed addresses.

Output Disable

With the OE

input at a logic high level (VIH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V identifier bytes may then be sequenced from the device outputs by toggling address A addresses are DON’T CARES except A

6, A3, A2, A1, and A0. (See Table 3.)

ID (10.0 V to 11.0 V) on address pin A9. Two

0 from VIL to VIH. All

The manufacturer and de vice codes may also be read via the command register, for instances when the de vice is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 4. (Refer to Autoselect Command section.)

In the command Autoselect mode, the bank addresses BA; (A

20 to A12) must point to a specific bank during the

third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while array data can be read from the other bank.

A read cycle from address (BA)00h returns the manufacturer’s code (Fujitsu = 04h). And a read cycle from address (BA)01h, (BA)0Eh to (BA)0Fh returns the device code. (See Tables 5.1 to 5.4.)

In case of applying V

ID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, the simultaneous oper ation

can not be executed.

MBM29PDS322TE/BE

Write

Device erasure and progr amming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE falling edge of WE

or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The device f eatures hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memor y. (See Table 7.) The sector group protection feature is enabled using prog ramming equipment at the user’s site. The device is shipped with all sector groups unprotected.

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

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T o activ ate this mode, the programming equipment m ust force V V

ID = 11.5 V), CE = VIL and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). The sector group addresses (A20, A19, A18, A17,

16, A15, A14, A13, and A12) should be set to the sector to be protected. T ab les 6.1 and 6.2 define the sector address

ID on address pin A9 and control pin OE, (suggest

for each of the seventy one (71) individual sectors, and tables 7.1 and 7.2 define the sector group address for each of the twenty five (25) individual group sectors . Programming of the protection circuitry begins on the falling edge of the WE constant during the WE

To verify programming of the protection circuitry, the programming equipment must force V

pulse and is terminated with the rising edge of the same. Sector group addresses must be held

pulse. See Figures 16 and 24 for sector group protection waveforms and algorithm.

ID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A

12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a

protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except f or A

0, A1, A2, A3, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for

Autoselect manufacturer and device codes. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Perf orming a read operation at the address location XX02h, where the higher order addresses (A A

16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected

20, A19, A18, A17,

sector group. See Tables 5.1 to 5.4 for Autoselect codes.

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector g roups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET

pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the V

ID is taken away from the RESET pin, all the previously protected sector groups will be

protected again. Refer to Figures 17 and 25.

Extended Sector Group Protection

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing V sequence. Unlike conv entional procedure, it is not necessary to force V only RESET requires V

pin requires VID for sector group protection in this mode. The extended sector group protection

ID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)

into the command register. Then, the sector group addresses pins (A and (A

6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (recommend to set VIL

ID on RESET pin and write a command

ID and control timing for control pins. The

20, A19, A18, A17, A16, A15, A14, A13 and A12)

for the other addresses pins), and write extended sector group protection command (60h). A sector group is

MBM29PDS322TE/BE

10/11

typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins

20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a

(A command (40h). Following the command write, a logical “1” at device output DQ

0 will produce for protected

sector in the read operation. If the output is logical “0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET

pin to VIH. (Refer to the Figures

18 and 26.)

RESET

Hardware Reset

The device may be reset by driving the RESET be kept low (V

IL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process

of being executed will be terminated and the internal state machine will be reset to the read mode “t the RESET “t

RH” before it will allow read access . When the RESET pin is lo w, the device will be in the standby mode for the

pin is driven low. Fur thermore, once the RESET pin goes high, the device requires an additional

pin to VIL. The RESET pin vs. a pulse requirement and has to

READY” after

duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY should be ignored during the RESET

pulse. See Figure 14 for the timing diagram. Refer to Temporary Sector

output signal

Group Unprotection for additional functionality.

Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using V This function is one of two provided by the WP/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 4K word boot sectors independently of whether those sectors are protected or unprotected using the method described in “Sector Protection/Unprotection”. The two outermost 4K word boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (MBM29PDS322TE: SA69 and SA70, MBM29PDS322BE: SA0 and SA1)

If the system asserts V

IH on the WP/ACC pin, the device reverts to whether the two outermost 4K word boot

sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector protection/unprotection”.

ID.

Accelerated Program Operation

The device offers accelerated program operation which enables the programming in high speed. If the system asserts V

ACC

to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program oper ation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from f ast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode.

Removing V

ACC

from the WP/ACC pin returns the device to normal operation. Do not remove V

ACC pin while programming. See Figure 19.

ACC

from WP/

MBM29PDS322TE/BE

COMMAND DEFINITIONS

■■■■

The device operations are selected b y writing specific address and data sequences into the command register . Some commands require Bank Address (BA) input. When command sequences are inputted to bank being read, the commands have priority over reading. Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreov er, both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memor y. The device remains enabled for reads until the command register contents are altered.

The device will automatically powe r-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

7 to DQ0 and DQ15 to DQ8 bits are ignored.

5 = 1) to Read/Reset mode, the Read/

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Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A

9 to a high voltage. How ever , multiple xing high voltage

onto the address lines is not generally desired system design practice. The device contains an A utoselect command operation to supplement tr aditional PR OM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by firstly writing two unlock cycles. This is followed by a third

write cycle that contains the bank address (BA) and the Autoselect command. Then the manuf acture and device codes can be read from the bank, and actual data of memory cell can be read from the another bank.

Following the command write, a read cycle from address (BA)00h retrie ves the manuf acture code of 04h. A read cycle at address (BA)01h returns 7Eh to indicate that this device uses extended device code. The successive read cycle from (BA)0Eh to (BA)0Fh returns this extended device code f or this device. (See Tables 5.1 to 5.4.)

The sector state (protection or unprotection) will be informed by address (BA)02h. Scanning the sector group addresses (A logical “1” at device output DQ

20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a

0 for a protected sector group . The progr amming verification should be perf ormed

by verify sector group protection on the protected sector. (See Table 3.) The manufacture and device codes can be allowed to read from selected bank. To read the manufacture and

device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read.

If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank which doesn’t contain the software.

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command.

MBM29PDS322TE/BE

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Word Programming

The device is programmed on a w ord-b y-word basis . Prog r amming is a four bus cycle operation. There are two “unlock” write cycles. These are follo wed by the prog ram set-up command and data write cycles. Addresses are latched on the falling edge of CE CE

or WE, whichever happens first. The rising edge of CE or WE (whiche ver happens first) begins programming.

or WE, whichever happens later and the data is latched on the rising edge of

Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ or RY/BY

. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

7 (Data Polling), DQ6 (Toggle Bit),

The automatic programming operation is completed when the data on DQ

7 is equivalent to data written to this

bit at which time the device returns to the read mode and addresses are no longer latched. (See T able 9, Hardw are Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data

Polling m ust be performed at the memory location which is being

programmed. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being

written. Programming is allowed in any sequence and across sector boundar ies. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.

Figure 20 illustrates the Embedded Program

Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” wr ite cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase Algorithm command sequence the device will automatically program and v erify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations.

The system can determine the status of the erase operation by using DQ RY/BY

. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ

7 is “1” (See Write Operation Status section.) at which time the

7 (Data Polling), DQ6 (Toggle Bit), or

device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) Figure 21 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

MBM29PDS322TE/BE

Sector Erase

Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE happens later, while the command (Data = 30h) is latched on the rising edge of CE After time-out of “t

TOW” from the rising edge of the last sector erase command, the sector erase operation will begin.

or WE which happens first.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table4. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “t

TOW” otherwise that command will not be accepted and

erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE

or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer .) Resetting the de vice once e x ecution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70).

or WE whichever

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TOW”

Sector erase does not require the user to program the de vice prior to erase. The device automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y controls or timings during these operations.

The system can determine the status of the erase operation by using DQ RY/BY

The sector erase begins after the “t

TOW” time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ section.) at which time the device returns to the read mode. Data

polling and Toggle Bit must be performed at

7 (Data Polling), DQ6 (Toggle Bit), or

7 is “1” (See Write Operation Status

an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogr amming)] × Number of Sector

Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perf orm. Figure 21 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

MBM29PDS322TE/BE

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Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perf orm data reads from or programs to a sector not being erased. This command is applicable ONLY dur ing the Sector Erase operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximu m of “t

SPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the

RY/BY

output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must

use the address of the erasing sector for reading DQ

6 and DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device def aults to the er ase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successiv ely reading from the er ase-suspended sector while the device is in the erase-suspend-read mode will cause DQ

2 to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Progr am mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-progr am mode will cause DQ Program operation is detected by the RY/BY is the same as the regular Program operation. Note that DQ

output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which

7 must be read from the Program address while DQ6

2 to toggle. The end of the erase-suspended

can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase , the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Extended Command

(1) Fast Mode

The device has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also ex ecuted after e xiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to the Figure 27.) The V CE

= VIH during Fast Mode.

CC active current is required even

(2) Fast Programming

During Fast Mode, the progr amming can be executed with tw o bus cycles operation. The Embedded Program Algorithm is executed by wr iting program set-up command (A0h) and data write cycles (PA/PD). (Refer to the Figure 27.)

MBM29PDS322TE/BE

Hidden ROM (Hi-ROM) Region

The Hi-ROM feature provides a Flash memor y region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.

The Hi-ROM region is 32 Kwords in length and is stored at the same address as the 4 KW ×8 sectors. The MBM29PDS322TE occupies the address of the word mode 1F8000h to 1FFFFFh and the MBM29PDS322BE type occupies the address of the word mode 000000h to 007FFFh. After the system has written the Enter HiROM command sequence, the system ma y read the Hi-R OM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is remov ed from the device. On po wer-up, or f ollowing a hardware reset, the device re verts to sending commands to the boot sectors.

10/11

When reading the Hi-ROM region, either change addresses or change CE should be taken (changing addresses or CE sequence to read actual data of memory cell.

Hidden ROM (Hi-ROM) Entry Command

The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possib le in this area until it is protected. Ho w ever, once it is protected, it is impossible to unprotect, so please use this with caution.

Hidden ROM area is 32 K words and in the same address area as 4 KW sector. The address of top boot is 1F8000h to 1FFFFFh at word mode and the bottom boot is 000000h to 007FFFh at word mode. These areas are normally the boot block area (4 KW ×8 sector). Therefore , write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called Hidden ROM mode when the Hidden ROM area appears.

Sector other than the boot block area could be read during Hidden ROM mode. Read/program/erase of the Hidden ROM area is possible during Hidden ROM mode. Wr ite the Hidden ROM reset command sequence to exit the Hidden ROM mode . The bank address of the Hidden R OM should be set on the third cycle of this reset command sequence.

Hidden ROM (Hi-ROM) Program Command

T o program the data to the Hidden R OM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is the same as the program command in usual e xcept to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ data poling, DQ6 toggle bit and RY/BY pin. It is necessary to pay attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, data of the address will be changed.

pin from “H” to “L”) after the system issues the Exit Hi-ROM command

pin from “H” to “L”. The same procedure

Hidden ROM (Hi-ROM) Erase Command

To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode. This command is same as the sector erase command in the past except to write the command during Hidden ROM mode. Theref ore the detection of completion method is the same as in the past, using the DQ DQ

6 toggle bit and RY/BY pin. It is necessary to pay attention to the sector address to be erased. If the sector

address other than the Hidden ROM area is selected, the data of the sector will be changed.

7 data poling,

MBM29PDS322TE/BE

10/11

Hidden ROM (Hi-ROM) Protect Command

There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command(60h), set the sector address in the Hidden ROM area and (A

, A3, A2,A1, A0) = (0,0,0,1,0), and write the sector group protect command(60h) during the Hidden ROM mode. The same command sequence could be used because, it is the same as the extension sector group protect in the past except that it is in the Hidden ROM mode and it does not apply high voltage to RESET

pin. Please refer to “Function Explanation Extended

Sector Group Protection” for details of extension sector group protect setting. The other is to apply high voltage (V

3, A2, A1, A0) = (0, 0, 0, 1, 0), and apply the write pulse during the Hidden ROM mode. To verify the protect

circuit, apply high voltage (V

Hidden ROM area, and read. When “1” appears on DQ

) to A9 and OE, set the sector address in the Hidden ROM area and (A6,

) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the

0, the protect setting is completed. “0” will appear on DQ0

if it is not protected. Please apply write pulse again. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector group protect previously mentioned. Please refer to “Function Explanation Sector Group Protection” f or details of the sector group protect setting.

Other sector group will be effected if the address other than those f or Hidden ROM area is selected f or the sector group address, so please be careful. Once it is protected, protection can not be cancelled, so please pay the closest attention.

Write Operation Status

Detailed in T able 9 are all the status flags that can determine the status of the bank f or the current mode operation. The read operation from the bank which doesn’t operate Embedded Algorithm returns data of memory cells. These bits offer a method f or determining whether a Embedded Algorithm is completed properly . The inf ormation on DQ

2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then

the DQ

2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively

read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from bank (non-busy bank) which doesn’t execute Embedded Algorithm. For

example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>, [2] <non-busy bank>, [3] <busy bank>, the DQ

6 is toggling in the case of [1] and [3]. In case

of [2], the data of memory cells are outputted. In the erase-suspend read mode with the same read sequence, DQ

6 will not be toggled in the [1] and [3].

In the erase suspend read mode, DQ

2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is

outputted.

MBM29PDS322TE/BE

10/11

Table 9 Hardware Sequence Flags

Status DQ

Embedded Program Algorithm DQ

7 Toggle 0 0 1

DQ5DQ

Embedded Erase Algorithm 0 Toggle 0 1 Toggle *

In Progress

Erase Suspended Mode

Erase Suspend Read (Erase Suspended Sector)

Erase Suspend Read (Non-Erase Suspended Sector)

Erase Suspend Program (Non-Erase Suspended Sector)

1 1 0 0 Toggle

Data Data Data Data Data

Embedded Program Algorithm DQ

Exceeded Time Limits

Embedded Erase Algorithm 0 Toggle 1 1 N/A Erase

Suspended Mode

Erase Suspend Program (Non-Erase Suspended Sector)

*: Successive reads from the erasing or erase-suspend sector will cause DQ

suspend sector address will indicate logic “1” at the DQ

Note 1.DQ

0 and DQ1 are reserve pins for future use.

2.DQ

4 is Fujitsu internal use.

2 bit.

7 Toggle 0 0 1 * 7 Toggle 1 0 1

7 Toggle 1 0 N/A

2 to toggle. Reading from non-erase

MBM29PDS322TE/BE

Data Polling

10/11

The device features Data

Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read device will produce a complement of data last written to DQ read device will produce true data last written to DQ device will produce a “0” at the DQ read device will produce a “1” on DQ

For programming, the Data

Polling is valid after the rising edge of the four th wr ite pulse in the four write pulse

7. Upon completion of the Embedded Program Algorithm, an attempt to

7. During the Embedded Erase Algorithm, an attempt to read

7 output. Upon completion of the Embedded Erase Algorithm an attempt to

7. The flowchart for Data Polling (DQ7) is shown in Figure 23.

sequence. For chip erase and sector erase, the Data

write pulse sequence. Data

Polling m ust be perf ormed at sector address of sectors being erased, not protected

Polling is valid after the rising edge of the sixth write pulse in the six

sectors. Otherwise, the status may be invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data

Once the Embedded Algorithm operation is close to completion, the device data pins (DQ chronously while the output enable (OE on DQ

7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the

system samples the DQ Algorithm operation and DQ on DQ

0 to DQ7 will be read on the successive read attempts.

The Data

Polling f eature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm

Polling on DQ7 is activ e for approximately 400 µs , then the bank returns to read mode.

7) may change asyn-

) is asserted low. This means that device is dr iving status information

7 output, it may read the status or valid data. Ev en if device has completed the Embedded

7 has a valid data, data outputs on DQ0 to DQ6 may be still invalid. The valid data

or sector erase time-out. (See Table 9.) See Figure 10 for the Data

Polling timing specifications and diagrams.

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE device will results in DQ is completed, DQ

6 toggling between one and zero . Once the Embedded Program or Erase Algorithm cycle

6 will stop toggling and valid data will be read on the next successive attempts. During pro-

toggling) data from the

gramming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop toggling with data unchanged. In erase, device will er ase all selected sectors except f or ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having data unchanged.

Either CE DQ

The system can use DQ is actively erased (that is, the Embedded Er ase Algorithm is in progress), DQ Erase Suspend mode, DQ

or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause

6 to toggle.

6 to determine whether a sector is actively erased or is erase-suspended. When a bank

6 toggles. When a bank enters the

6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6

to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed.

MBM29PDS322TE/BE

See Figure 11 for the Toggle Bit I timing specifications and diagrams.

Exceeded Timing Limits

5 will indicate if the program or erase time has exceeded the specified limits (inter nal pulse count). Under

these conditions DQ cycle was not successfully completed. Data The CE WE

circuit will partially power down device under these conditions (to approximately 2 mA). The OE and

pins will control the output disable functions as described in Table 8.

5 will produce a “1”. This is a failure condition which indicates that the program or erase

Polling is the only oper ating function of de vice under this condition.

10/11

The DQ

5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In

this case the device locks out and ne v er complete the Embedded Algorithm operation. Hence, the system ne ver read valid data on DQ

7 bit and DQ6 nev er stop toggling. Once de vice has ex ceeded timing limits, the DQ5 bit will

indicate a “1.” Please note that this is not a device failure condition since device was incorrectly used. If this occurs, reset device with command sequence.

Sector Erase Timer

After completion of the initial sector erase command sequence sector erase time-out will begin. DQ low until the time-out is completed. Data

Polling and Toggle Bit are valid after the initial sector erase command

3 will remain

sequence. If Data

Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ cycle has begun.If DQ

3 is low (“0”), the device will accept additional sector erase commands. To insure the

command has been accepted, the system software should check the status of DQ subsequent Sector Erase command. If DQ

3 were high on the second status check, the command ma y not ha v e

3 is high (“1”) the internally controlled erase

3 prior to and following each

been accepted. See Table 9: Hardware Sequence Flags.

Toggle Bit II

This toggle bit II, along with DQ

6, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ

2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successiv e reads from the erase-suspended sector will cause DQ to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ

2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ

7, is summarized

as follows:

For example, DQ (DQ

2 toggles while DQ6 does not.) See also and.

Further more, DQ mode, DQ

2 toggles if this bit is read from an erasing sector.

2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

2 can also be used to determine which sector is being erased. When device is in the erase

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

MBM29PDS322TE/BE

Reading Toggle Bits DQ

/DQ

10/11

Whenever the system initially begins reading toggle bit status , it m ust read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or er ase oper ation. The system can read array data on DQ

7 to DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ went high. If the toggle bit is no longer toggling, the device has successfully completed the progra m or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ gone high. The system may continue to monitor the toggle bit and DQ

5 through successive read cycles, deter-

5 has not

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to Figure 23.)

Table 10 Toggle Bit Status

Mode DQ

Program DQ7 Toggle 1 Erase 0 Toggle Toggle (Note) Erase-Suspend Read

(Erase-Suspended Sector) Erase-Suspend Program DQ

Note Successive reads from the erasing or erase-suspend sector will cause DQ

erase suspend sector address will indicate logic “1” at the DQ

11Toggle

7 Toggle 1 (Note)

2 to toggle. Reading from non-

2 bit.

RY/BY

Ready/Busy

The device provides a RY/BY

open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or has been completed. If output is low, device is busy with either a program or erase operation. If output is high, device is ready to accept an y read/write or erase oper ation. If the device is placed in an Erase Suspend mode, RY/BY

output will be high.

During programming, RY/BY pin is dr iven low after the rising edge of the fourth write pulse. During an erase operation, RY/BY condition during RESET

pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy

pulse. Refer to Figures 13 and 14 for a detailed timing diagram. RY/BY pin is pulled

high in standby mode. Since this is an open-drain output, RY/BY

pins can be tied together in parallel with a pull-up resistor to VCC.

MBM29PDS322TE/BE

Data Protection

The device is designed to off er protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up de vice automatically resets internal state machine in Read mode. Also, with its control register architecture, alteration of memor y contents only occurs after successful completion of specific multi-bus cycle command sequences.

10/11

The device also incorporates several features to prevent inadver tent wr ite cycles resulting from V and power-down transitions or system noise.

Power On/Off Timing

The RESET pin must be held low during V (Refer to Figure 5.3.)

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE

Logical Inhibit

Writing is inhibited by holding any one of OE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE The internal state machine is automatically reset to the read mode on power-up.

= CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

CC ramp up to insure that device power up correctly.

, CE or WE will not initiate a write cycle.

= VIL, CE = VIH, or WE = VIH. To initiate a wr ite cycle CE and WE

CC power-up

MBM29PDS322TE/BE

ABSOLUTE MAXIMUM RATINGS

■■■■

10/11

Parameter Symbol

Unit

Min. Max.

Storage Temperature Tstg –55 +125 °C

Rating

Ambient Temperature with Power Applied T Voltage with Respect to Ground All pins except A

, and RESET (Note 1)

A –40 +85 °C

VIN, VOUT –0.5 VCC+0.5 V

Power Supply Voltage (Note 1) VCC –0.5 +3.0 V A

9, OE, and RESET (Note 2) VIN –0.5 +11.5 V

/ACC (Note 3) VACC –0.5 +10.5 V

Notes: 1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may

undershoot V +0.5 V. During voltage tr ansitions, input or I/O pins may overshoot to V

2.Minimum DC input voltage on A and RESET and supply voltage (V

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC

CC +2.0 V for periods of up to 20 ns.

9, OE and RESET pins is –0.5 V. During voltage transitions, A9, OE

pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input

IN-VCC) does not exceed +9.0V. Maximum DC input voltage on A9, OE and RESET

pins is +11.5 V which may positive overshoot to +12.5 V for periods of up to 20 ns.

3.Minimum DC input voltage on WP undershoot V

SS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin

/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may

is +10.5 V which may positive overshoot to +12.0 V for periods of up to 20ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING RANGES

■■■■

Value

Parameter Symbol Part No.

Unit

Min. Max.

Ambient Temperature T

A MBM29PDS322TE/BE 10/11 –40 +85 °C

Power Supply Voltage VCC MBM29PDS322TE/BE 10/11 +1.8 +2.2 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MAXIMUM OVERSHOOT / UNDERSHOOT

■■■■

MBM29PDS322TE/BE

10/11

0.2 × VCC

−0.5 V

−2.0 V

VCC + 2.0 V

VCC + 0.5 V

0.8 × V

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

20 ns20 ns

+12.5 V

+11.5 V

CC + 0.5 V

Figure 2 Maximum Overshoot Waveform 1

20 ns

20 ns20 ns

Note: This waveform is applied for A9, OE and RESET

Figure 3 Maximum Overshoot Waveform 2

MBM29PDS322TE/BE

ELECTRICAL CHARACTERISTICS

■■■■

1. DC Characteristics

Parameter Symbol Conditions

10/11

Value

Unit

Min. Max.

Input Leakage Current I Output Leakage Current I A9, OE, RESET Inputs Leakage

Current

CC Active Current *

VCC Active Current * V

CC Current (Standby) ICC3

CC Current (Standby, Reset) ICC4

VCC Current (Automatic Sleep Mode) *

CC Active Current *

(Read-While-Program) V

CC Active Current *

(Read-While-Erase) V

CC Active Current

(Erase-Suspend-Program) VCC Active Current

(Intra-Page Read)

LI VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA

LO VOUT = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA

ILIT

VCC = VCC Max. A

9, OE, RESET = 11.0 V

—35µA

CE = VIL, OE = VIH, f = 8 MHz — 21 mA

ICC1

= VIL, OE = VIH, f = 1 MHz — 3 mA

ICC2 CE = VIL, OE = VIH —30mA

VCC = VCC Max., CE = VCC ± 0.3 V, RESET

= VCC ± 0.3 V

VCC = VCC Max.,WE/ACC = VCC ±

0.3 V, RESET

= VSS ± 0.3 V

—5µA

VCC = VCC Max., CE = VSS ± 0.3 V,

ICC5

RESET V

= VCC ± 0.3 V

IN = VCC ± 0.3 V or VSS ± 0.3 V

—5µA

ICC6 CE = VIL, OE = VIH —55mA

ICC7 CE = VIL, OE = VIH —55mA

ICC8 CE = VIL, OE = VIH —35mA

ICC9 CE = VIL, OE = VIH, f = 20 MHz — 5 mA

/ACC Accelerated Program

Current

IACC

Input Low Level V

IL —–0.50.2× VCC V

VCC = VCC Max. WP

/ACC = VACC Max.

—20mA

Input High Level VIH —0.8× VCC VCC+0.3 V Voltage for WP

Protection/Unprotection and Program Acceleration *

Voltage for Autoselect and Sector Protection (A

/ACC Sector

9, OE, RESET) *

VACC — 8.5 12.5 V

VID — 10.0 11.0 V

Output Low Voltage Level VOL IOL = 100 µA, VCC = VCC Min. — 0.1 V Output High Voltage Level V

OH IOH = –100 µAVCC–0.1 — V

*1:The ICC current listed includes both the DC operating current and the frequency dependent component. *2:I

CC is active while Embedded Algorithm (program or erase) is in progress.

*3:Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4:Applicable for only V

CC applying.

*5:Embedded Algorithm (program or erase) is in progress. (@5 MHz)

2. AC Characteristics

•

Read Only Operations Characteristics

Parameter

Read Cycle Time t

MBM29PDS322TE/BE

Value(Note)

Symbol

Conditions

JEDEC Standard Min.Max.Min.Max.

AVAV tRC —100 115  ns

10/11

Unit10 11

Address to Output Delay t Page Read Cycle Time — t

AVQV tACC

PRC —45 45  ns

Page Address to Output Delay — tPACC Chip Enable to Output Delay t

Output Enable to Output Delay t

ELQV tCE OE = VIL  100  115 ns GLQV tOE —  35  45 ns

CE = VIL OE = VIL

 100  115 ns

 45  45 ns

Chip Enable to Output High-Z tEHQZ tDF —  30  30 ns Output Enable to Output High-Z t Output Hold Time From Addresses,

or OE, Whichever Occurs First

GHQZ tDF —  30  30 ns

tAXQX tOH —0 0  ns

RESET Pin Low to Read Mode — tREADY —  20  20 µs

Note: Test Conditions:

Output Load: C

L = 50 pF

Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 2.0 V Timing measurement reference level Input: 1.0 V Output: 1.0 V

Device

Under

Test

Figure 4 Test Conditions

MBM29PDS322TE/BE

•

Write/Erase/Program Operations

Parameter

JEDEC Standard Min. Typ. Max. Min. Typ. Max.

10/11

Value

Symbol

Unit10 11

Write Cycle Time t Address Setup Time t Address Setup Time to OE

Low During

Toggle Bit Polling

AVAV tWC 100 115  ns

AVWL tAS 0 0  ns

—tASO 15 15  ns

Address Hold Time tWLAX tAH 60 60  ns Address Hold Time from CE

During Toggle Bit Polling Data Setup Time t

or OE High

—tAHT 0 0  ns

DVWH tDS 60 60 ns

Data Hold Time tWHDX tDH 0 0  ns Output Enable

Hold Time

Read Toggle and Data

—t

OEH

Polling 10 10 ns

0  0  ns

CE High During Toggle Bit Polling — tCEPH 20 20  ns OE

High During Toggle Bit Polling — tOEPH 20 20  ns

Read Recover Time Before Write t

GHWL tGHWL 0  0 ns

Read Recover Time Before Write tGHEL tGHEL 0  0 ns CE

Setup Time tELWL tCS 0  0 ns

Setup Time tWLEL tWS 0 0  ns

Hold Time tWHEH tCH 0 0  ns WE Hold Time tEHWH tWH 0 0  ns Write Pulse Width t CE

Pulse Width tELEH tCP 60 60 ns

WLWH tWP 60 60  ns

Write Pulse Width High tWHWL tWPH 60 60  ns CE

Pulse Width High tEHEL tCPH 60 60  ns Programming Operation t Sector Erase Operation * V

CC Setup Time — tVCS 50 50  µs

Rise Time to V

ID *

Rise Time to VACC * Voltage Transition Time * Write Pulse Width * OE

Setup Time to WE Active *

WHWH1 tWHWH1  16 16  µs

tWHWH2 tWHWH2  1  1  s

—tVIDR 500 500  ns —tVACCR 500 500  ns —tVLHT 4 4  µs —tWPP 100 100 µs —tOESP 4 4  µs

(Continued)

Parameter

Setup Time to WE Active *

MBM29PDS322TE/BE

Symbol

JEDEC Standard Min. Typ. Max. Min. Typ. Max.

—tCSP 4——4——µs

Value

10/11

Unit10 11

Recover Time From RY/BY RESET Pulse Width — tRP 500 — — 500 — — ns RESET Program/Erase Valid to RY/BY Delay Time from Embedded Output Enable — tEOE — — 90 — — 115 ns Erase Time-out Time — t Erase Suspend Transition Time — t Power On / Off Time — tPS — — 100 — — 115 ns

*1:This does not include the preprogramming time. *2:This timing is for Sector Group Protection operation. *3:This timing is for Accelerated Program operation.

High Level Period Before Read — tRH 200 — — 200 — — ns

Delay — tBUSY — — 90 — — 90 ns

—tRB 0——0——ns

TOW 50 — 50 — — µs

SPD — — 20 — — 20 µs

MBM29PDS322TE/BE

ERASE AND PROGRAMMING PERFORMANCE

■■■■

10/11

Parameter

Sector Erase Time — 1 10 s

Word Programming Time — 16 360 µs

Chip Programming Time — — 100 s Program/Erase Cycle 100,000 — — cycle —

FBGA PIN CAPACITANCE

Parameter Symbol Condition

Input Capacitance C Output Capacitance COUT VOUT = 0 TBD TBD pF Control Pin Capacitance C WP

/ACC Pin Capacitance CIN3 VIN = 0 TBD TBD pF

Note: Test conditions T

A = 25°C, f = 1.0 MHz

Min. Typ. Max.

IN VIN = 0 TBD TBD pF

IN2 VIN = 0 TBD TBD pF

Limits

Unit Comments

Excludes programming time prior to erasure

Excludes system-level overhead

Value

Unit

Typ. Max.

TIMING DIAGRAM

■■■■

•

Key to Switching Waveforms

MBM29PDS322TE/BE

WAVEFORM INPUTS OUTPUTS

10/11

Address

Must Be Steady

May Change from H to L

May Change from L to H

"H" or "L": Any Change Permitted

Does Not Apply

Addresses Stable

Will Be Steady

Will Be Changing from H to L

Will Be Changing from L to H

Changing, State Unknown

Center Line is HighImpedance "Off" State

Outputs

tACC

tOE tDF

tOEH

tCE

High-Z High-Z

Output Valid

tOH

Figure 5.1 Read Operation Timing Diagram

MBM29PDS322TE/BE

10/11

tRC

Address

RESET

Outputs

Address Stable

tACC

tRH

tRP tRH tCE

High-Z

Outputs Valid

Figure 5.2 Hardware Reset/Read Operation Timing Diagram

tOH

MBM29PDS322TE/BE

10/11

A2 to A20

A0 to A1

Output

Same Page Addresses

Aa Ab Ac

High-Z

tOEH

tACC

tCE

tOE

tPRC

tPACC tPACC

tOH tOH tOH

Da Db Dc

Figure 5.3 Page Read Operation Timing Diagram

tDF

MBM29PDS322TE/BE

3rd Bus Cycle Data Polling

10/11

Address

555h

tWC

PA PA

tAS tAH

tCHtCS

tGHWL

tWP

tWPH

tWHWH1

tDH

tDS

Data

A0h

DOUT DOUT

DQ7

Notes: 1.PA is address of the memory location to be programmed.

2.PD is data to be programmed at word address.

3.DQ

7 is the output of the complement of the data written to the device.

4.D

OUT is the output of the data written to the device.

5.Figure indicates last two bus cycles out of four bus cycle sequence.

tRC

tCE

tOE

tOH

Figure 6 Alternate WE Controlled Program Operation Timing Diagram

MBM29PDS322TE/BE

3rd Bus Cycle Data Polling

10/11

Address

555h

tWC

PA PA

tAH

tAS

tWS

tWH

tGHEL

tCP

tCPH

tWHWH1

tDS

tDH

Data

A0h

Notes: 1.PA is address of the memory location to be programmed.

2.PD is data to be programmed at word address.

3.DQ

7 is the output of the complement of the data written to the device.

4.D

OUT is the output of the data written to the device.

5.Figure indicates last two bus cycles out of four bus cycle sequence.

DQ7

DOUT

Figure 7 Alternate CE Controlled Program Operation Timing Diagram

MBM29PDS322TE/BE

10/11

Address

Data

VCC

555h

tWC tAS

tCS tCH

tGHWL

tVCS

tWP

tDS

AAh

2AAh 555h

tAH

tWPH

tDH

55h 80h AAh 55h

555h

2AAh

SA *

10h/

30h

*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.

Figure 8 Chip/Sector Erase Operation Timing Diagram

MBM29PDS322TE/BE

10/11

tCH

tOE

tOEH

tCE

DQ6 to DQ0

Data

tWHWH1 or 2

Data

tBUSY

DQ7

6 to DQ0 =

Output Flag

RY/BY

*: DQ7 = Valid Data (The device has completed the Embedded operation).

DQ7 = Valid Data

tEOE

6 to DQ0

DQ Valid Data

tDF

High-Z

Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram

MBM29PDS322TE/BE

tOEH

tOES

10/11

Data (DQ7 to DQ0)

tDH

6 = Toggle DQ6 = Toggle

6 =

Stop Toggle

tOE

*: DQ6 stops toggling (The device has completed the Embedded operation).

Figure 10 Toggle Bit I during Embedded Algorithm Operation Timing Diagram

DQ7 = DQ0

Data Valid

MBM29PDS322TE/BE

Read Command CommandRead Read Read

tWCtRCtWCtRCtWCtRC

10/11

Address

BA1

tAS

BA2

(555h)

tAH

BA1

tACC

tCE

BA2 (PA)

BA1

tAHT

BA2 (PA)

tAS

tOE

tCEPH

tGHWL

tWP

tOEH

tDF

Valid

Output

tDH

tDS

Valid Input

(A0h) (PD)

Valid

Output

tDF

Valid Input

Valid

Output

Status

Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1. BA2: Address of Bank 2.

Figure 11 Bank-to-Bank Read/Write Timing Diagram

DQ6

DQ2

Enter

Embedded

Erasing

Erase

Toggle

2 and DQ6

with OE

Erase

Suspend

Erase Suspend

Read

Enter Erase

Suspend Program

Erase Suspend Program

Erase Suspend

Note: DQ2 is read from the erase-suspended sector.

Figure 12 DQ2 vs. DQ

Read

Erase

Resume

Erase

Complete

MBM29PDS322TE/BE

10/11

The rising edge of the last WE signal

RY/BY

Entire programming or erase operations

tBUSY

Figure 13 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

RESET

tRP

tRB

RY/BY

tREADY

Figure 14 RESET, RY/BY Timing Diagram

RESET

MBM29PDS322TE/BE

tPS tPS

10/11

VCC

Address

Data

0 V

VIH

1.8 V

Valid Data In

tRH

tACC

Valid Data Out

Figure 15 Power On / Off Timing Diagram

1.8 V

MBM29PDS322TE/BE

A20, A19, A18 A17, A16, A15 A14, A13, A12

A6, A3, A2, A0

V VIH

SPAX

tVLHT

10/11

SPAY

VID VIH

Data

VCC

tVLHT

tOESP

tCSP

tVCS

SPAX: Sector Group Address for initial sector SPAY: Sector Group Address for next sector

tWPP

tVLHT

01h

tOE

Figure 16 Sector Group Protection Timing Diagram

MBM29PDS322TE/BE

10/11

VCC

VID VIH

RESET

RY/BY

tVIDR

tVCS

tVLHT

Program or Erase Command Sequence

Unprotection period

tVLHT

Figure 17 Temporary Sector Group Unprotection Timing Diagram

MBM29PDS322TE/BE

10/11

VCC

RESET

Address

6, A3,

A A

2, A0

tVIDR

tVCS

tVLHT

tWC tWC

SPAX SPAX SPAY

tWP

TIME-OUT

Data

SPAX: Sector Group Address to be protected SPAY: Next Sector Group Address to be protected TIME-OUT: Time-Out window = 250 µs (Min.)

Figure 18 Extended Sector Group Protection Timing Diagram

60h01h40h60h60h

tOE

MBM29PDS322TE/BE

10/11

VCC

VACC

VIH

WP/ACC

RY/BY

tVACCR

tVCS

tVLHT

Program or Erease Command Sequence

Acceleration period

Figure 19 Accelerated Program Timing Diagram

tVLHT

MBM29PDS322TE/BE

FLOW CHARTS

■■■■

EMBEDDED ALGORITHM

10/11

Start

Write Program

Command Sequence

(See Below)

Data Polling

Verify Data

Embedded Program Algorithm in program

Yes

Increment Address

Program Command Sequence (Address/Command):

Last Address

Yes

Programming Completed

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Figure 20 Embedded ProgramTM Algorithm

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Data = FFh

Erasure Completed

MBM29PDS322TE/BE

Embedded Erase Algorithm in progress

Yes

10/11

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Sector Address

/30h

Additional sector erase commands are optional.

Figure 21 Embedded Erase

Algorithm

MBM29PDS322TE/BE

Start

Read Byte

7 to DQ0)

(DQ

Addr. = VA

DQ7 = Data?

DQ5 = 1?

Yes

Read Byte

(DQ

7 to DQ0)

Addr. = VA

10/11

Yes

VA=Address for programming =Any of the sector address within the sector being erased during sector erase or multiple sector erases operation =Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation.

DQ7 = Data?

Fail Pass

Yes

*: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 22 Data Polling Algorithm

Start

MBM29PDS322TE/BE

10/11

Read DQ

Addr. = VA

Read DQ7 to DQ0

Addr. = VA

Toggle Bit

= Toggle?

DQ5 = 1?

Read DQ7 to DQ0

Twice

Addr. = VA

Toggle Bit = Toggle?

Fail Pass

7 to DQ0

Yes

VA=Bank address being executed Embedded Algorithm.

*1, 2

*1:Read toggle bit twice to determine whether or not it is toggling. *2:Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.

Figure 23 Toggle Bit Algorithm

MBM29PDS322TE/BE

10/11

Setup Sector Group Addr.

20, A19, A18, A17, A16,

()

A15, A14, A13, A12

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Start

Increment PLSCNT

PLSCNT = 25?

Yes Yes

Remove V

Write Reset Command

ID from A9

Device Failed

Time out 100 µs

WE = V

IH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A

()

A6 = A3 = A2 = A0 = VIL

Data = 01h?

Protect Another Sector

Remove V

Write Reset Command

Sector Group Protection

Completed

Group?

ID from A9

1 = VIH

Yes

Figure 24 Sector Group Protection Algorithm

MBM29PDS322TE/BE

Start

10/11

RESET = V

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*1: All protected sector groups are unprotected. *2: All previously protected sector groups are protected once again.

Figure 25 Temporary Sector Group Unprotection Algorithm

MBM29PDS322TE/BE

10/11

Start

RESET = VID

Wait to 4 µs

Device is Operating in

Temporary Sector Group

Unprotection Mode

Increment PLSCNT

PLSCNT = 25?

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group Protection

To Verify Sector Group Protection

Read from Sector Group Address

Write XXXh/60h

PLSCNT = 1

To Protect Secter Group

Write 60h to Secter Address

6 = A3 = A2 = A0 = VIL, A1 = VIH)

Time out 250 µs

Write 40h to Secter Address

6 = A3 = A2 = A0 = VIL, A1 = VIH)

(Addr. = SPA,

6 = A3 = A2 = A0 = VIL, A1 = VIH)

Data = 01h?

Setup Next Sector Address

Yes

Remove V

Write Reset Command

ID from RESET

Device Failed

Figure 26 Extended Sector Group Protection Algorithm

Yes

Protect Other Sector

Group?

Remove VID from RESET

Write Reset Command

Sector Protection

Completed

Yes

FAST MODE ALGORITHM

MBM29PDS322TE/BE

Start

555h/AAh

10/11

Increment Address

2AAh/55h

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling

Verify Data?

Yes

Last Address?

Yes

Programming Completed

XXXh/90h

XXXh/F0h

Set Fast Mode

In Fast Program

Reset Fast Mode

Figure 27 Embedded Program

Algorithm for Fast Mode

MBM29PDS322TE/BE

ORDERING INFORMATION

■■■■

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29PDS322 T E 10 PBT

10/11

PACKAGE TYPE PBT =63-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION

Valid Combinations

MBM29PDS322TE/BE

BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector

DEVICE NUMBER/DESCRIPTION MBM29PDS322 32 Mega-bit (2 M × 16-Bit) CMOS Flash Memory

1.8 V-only Read, Program, and Erase

Valid Combinations list configurations planned to be supported in volume for this device. Consult

10 11

PBT

the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations

PACKAGE DIMENSION

■■■■

63-pin plastic FBGA

(BGA-63P-M01)

MBM29PDS322TE/BE

10/11

11.00±0.10(.433±.004)

7.00±0.10

(.276±.004)

INDEX AREA

0.10(.004)

1999 FUJITSU LIMITED B63001S-1C-1

+0.15 –0.10

1.05

+.006

.041 –.004

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(4.00(.157))

(5.60(.220))

(8.80(.346)) (7.20(.283)) (5.60(.220))

0.80(.031)TYP

63-Ø0.45±0.05

(63-Ø0.18±.002)

ABCDEFGH

INDEX BALL

0.08(.003)

Dimensions in mm (inches).

8 7 6 5 4 3 2 1

MBM29PDS322TE/BE

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608 Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220

http://www.fmap.com.sg/

Korea

FUJITSU MICROELECTRONICS K OREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

10/11

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.

F0101

 FUJITSU LIMITED Printed in Japan

FUJITSU MBM29PDS322TE, MBM29PDS322BE DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual