FUJITSU MBM29LV320TE80, MBM29LV320BE80, MBM29LV320BE90, MBM29LV320BE10, MBM29LV320TE90 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

32 M (4 M

MBM29LV320TE MBM29LV320BE

DESCRIPTION

■

The MBM29L V320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. The device is offered in a 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V V for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard device off ers access times 80 ns, 90 ns and 100 ns, allo wing operation of high-speed microprocessors without wait state. To eliminate bus contention the device has separate chip enable(CE and output enable (OE

PRODUCT LINE UP

■

××××

) controls.

8/2 M

80/90/10 80/90/10

16) BIT

××××

CC supply . 12.0 V VPP and 5.0 V VCC are not required

DS05-20894-1E

), write enable(WE)

(Continued)

Part No.

Power Supply Voltage (V) V Max Address Access Time (ns) 80 90 100 Max CE Max OE Access Time (ns) 30 35 35

■

Access Time (ns) 80 90 100

PACKAGES

48-pin plastic TSOP (I) 48-pin plastic TSOP (I) 63-ball plastic FBGA

Marking Side

(FPT-48P-M19) (FPT-48P-M20) (BGA-63P-M01)

80 90 100

CC = 3.3 V VCC = 3.0 V

MBM29LV320TE/BE

0.3 V

−

0.3 V

−

0.6 V

0.3 V

MBM29LV320TE/BE

80/90/10

(Continued)

The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and er ase operations. Reading data out of the de vice is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by ex ecuting the erase command sequence. This will inv oke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed bef ore ex ecuting the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device f eatures single 3.0 V po w er supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V inhibits write operations on the loss of power. The end of program or erase is detected by Data by the Toggle Bit feature on DQ completed, the device internally resets to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The inter nal state machine is then reset to the read mode. The RESET Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E of quality , reliability, and cost eff ectiveness . The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the

6, or the RY/BY output pin. Once the end of a program or erase cycle has been

PROM experience to produce the highest levels

CC detector automatically

Polling of DQ7,

MBM29LV320TE/BE

FEATURES

■

•

• In accordance with CFI (C

µµµµ

0.23

m Process Technology

Single 3.0 V read, program, and erase

Minimized system level power requirements

Compatible with JEDEC-standard commands

Use the same software commands as E

PROMs

Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 63-ball FBGA (Package suffix : PBT)

Minimum 100,000 program/erase cycles High performance

80 ns maximum access time

Sector erase architecture

Eight 4 K word and sixty-three 32 K word sectors in word mode Eight 8 K byte and sixty-three 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase.

Boot Code Sector Architecture

T = Top sector B = Bottom sector

Hidden ROM (Hi-ROM) region

256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)

/ACC input pin

At V

IL, allows protection of boot sectors, regardless of sector protection/unprotection status

At VIH, allows removal of boot sector protection At VACC, increases program performance

Embedded Erase

* Algorithms

Automatically pre-programs and erases the chip or any sector

Embedded Program

* Algorithms

Automatically writes and verifies data at specified address

Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready/Busy output (RY/BY

)

Hardware method for detection of program or erase cycle completion

Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

Low V

write inhibit

≤≤≤≤

2.5 V

Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

Sector Group Protection Set function by Extended sector group protection command Fast Programming Function by Extended Command Temporary sector group unprotection

Temporary sector group unprotection via the RESET

pin.

ommon Flash Memory Interface)

80/90/10

: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MBM29LV320TE/BE

PIN ASSIGNMENTS

■

80/90/10

TSOP (I)

A15 A14 A13 A12 A11 A10

A8 A19 A20

RESET

N.C.

WP/ACC

RY/BY

A A17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

(Marking Side)

MBM29LV320TE/BE

Normal Bend

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE V

CE A

(FPT-48P-M19)

A1 A2 A3 A4 A5 A6

A7 A17 A18

RY/BY

WP/ACC

N.C.

RESET

A A19

A9 A10 A11 A12 A13 A14 A15

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

(Marking Side)

MBM29LV320TE/BE

Reverse Bend

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

A0 CE

V OE

DQ DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A

(FPT-48P-M20)

(Continued)

MBM29LV320TE/BE

FBGA (TOP VIEW) Marking Side

80/90/10

A8 B8

N.C. N.C.

A7 B7 C7 D7 E7 F7 G7 H7

N.C. N.C.

N.C.

N.C.B1N.C.

13 A12 A14 A15 A16 DQ15/

C6 D6 E6 F6 G6 H6 J6 K6

9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

C5 D5 E5 F5 G5 H5 J5 K5

WE RESET N.C. A

C4 D4 E4 F4 G4 H4 J4 K4

RY/BY WP/

ACC

C3 D3 E3 F3 G3 H3 J3 K3

7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

C2 D2 E2 F2 G2 H2 J2 K2 L2 M2

4 A2 A1 A0 CE OE VSS

19 DQ5 DQ12 VCC DQ4

18 A20 DQ2 DQ10 DQ11 DQ3

BYTE

(BGA-63P-M01)

J7 K7

VSS N.C. N.C.

A-1

N.C.

L7L8M7

N.C. N.C.

N.C.M1N.C.

MBM29LV320TE/BE

PIN DESCRIPTION

■

MBM29LV320 TE/BE Pin Configuration Table

Pin Function

20 to A0, A-1 Address Inputs

15 to DQ0 Data Inputs/Outputs

CE Chip Enable

80/90/10

OE WE

RY/BY Ready/Busy Output

RESET

BYTE

WP/ACC Hardware Write Protection/Program Acceleration

N.C. No Internal Connection

SS Device Ground

VCC Device Power Supply

Output Enable Write Enable

Hardware Reset Pin/Temporary Sector Group Unprotection Selects 8-bit or 16-bit mode

BLOCK DIAGRAM

■

MBM29LV320TE/BE

80/90/10

VCC VSS

BYTE

RESET

WP/ACC

CE OE

RY/BY

Buffer

State

Control

Command

Low V

CC Detector

RY/BY

Program Voltage

Generator

Timer for

Program/Erase

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Address

Latch

Y-Decoder

X-Decoder

STB

DQ15 to DQ0

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

20 to A09

A-1

LOGIC SYMBOL

■

A-1

20 to A0

DQ15 to DQ0

CE OE WE RY/BY RESET BYTE WP/ACC

16 or 8

MBM29LV320TE/BE

DEVICE BUS OPERATION

■

80/90/10

====

VIH)

DQ15 to

RESET

WP/

ACC

MBM29LV320TE/BE User Bus Operations Table (BYTE

Operation CE

Auto-Select Manufacturer Code * Auto-Select Device Code *

Extended Auto-Select Device Code * Read *

OE WE A0A1A6A

LLHLLLVID Code H X LLHHLLVID Code H X

LLHHHLVID Code H X

LLHA0 A1 A6 A9 DOUT HX Standby H X X X X X X High-Z H X Output Disable L H H X X X X High-Z H X Write (Program/Erase) L H L A Enable Sector Group Protection * Verify Sector Group Protection *

2, *4

LVID LHLVID XHX *

LLHLHLVID Code H X * Temporary Sector Group Unprotection *5XXXXXXX X VID X *

0 A1 A6 A9 DIN HX

Reset (Hardware) /Standby XXXXXXX High-Z L X Boot Block Sector Write Protection XXXXXXX X X L

Legend

: L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1:Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29LV320TE/BE Command Definitions Table”. *2:See the section on “7. Sector Group Protection” in ■FUNCTIONAL DESCRIPTION. *3:WE *4:V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

CC = 3.3 V ± 10%

*5:It is also used for the extended sector group protection. *6:Conditional exceptions are to be noticed as follows:For MBM29LV320TE (SA22, 23) , WP

For MBM29LV320BE (SA0, 1) , WP

/ACC = VIH.

MBM29LV320TE/BE User Bus Operations Table (BYTE

Operation CE

Auto-Select Manufacturer Code * Auto-Select Device Code *

Extended Auto-Select Device Code * Read *

MBM29LV320TE/BE

====

VIL)

OE WE

A0A1A6A

-1

LLHLLLLVID Code H X LLHLHLLVID Code H X

LLHLHHLVID Code H X LLHA-1 A0 A1 A6 A9 DOUT HX

DQ7 to

80/90/10

RESET

WP/

ACC

Standby H X X X X X X X High-Z H X Output Disable L H H X X X X X High-Z H X Write (Program/Erase) L H L A Enable Sector Group Protection * Verify Sector Group Protection *

2, *4

LVID LLHLVID XHX * LLHLLHLVID Code H X *

-1 A0 A1 A6 A9 DIN HX

Temporary Sector Group Unprotection *5XXX X XXXX X VID X * Reset (Hardware) /Standby X X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X X L

Legend

: L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1:Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29LV320TE/BE Command Definitions Table”. *2:See the section on “7. Sector Group Protection” in ■FUNCTIONAL DESCRIPTION. *3:WE *4:V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

CC = 3.3 V ± 10%

*5:It is also used for the extended sector group protection. *6:Conditional exceptions are to be noticed as follows:For MBM29LV320TE (SA22, 23) , WP

For MBM29LV320BE (SA0, 1) , WP

/ACC = VIH.

MBM29LV320TE/BE

MBM29LV320TE/BE Command Definitions Table

80/90/10

Command

Sequence

Read/ Reset

Autoselect

Program

Chip Erase

Sector Erase

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Bus

Write

Cycles

Req’d

First Bus

Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Second

Bus

Write Cycle

Third Bus

Write Cycle

1 XXXh F0h 

555h

AAh

2AAh

555h

55h

AAAh 555h AAAh

555h

AAh

2AAh

555h

55h

AAAh 555h AAAh

555h

AAh

2AAh

555h

55h

AAAh 555h AAAh

555h

AAh

2AAh

555h

55h

AAAh 555h AAAh AAAh 555h AAAh

555h

AAh

2AAh

555h

55h

AAAh 555h AAAh AAAh 555h

Fourth Bus Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

F0h RA RD 

90h 

A0h PA PD 

555h

80h

555h

80h

AAh

2AAh

555h

55h

10h

55h SA 30h

Erase Suspend 1 XXXh B0h  Erase Resume 1 XXXh 30h 

Set to Fast Mode

Fast Program

Reset from Fast Mode

Extended Sector Group Protection

Query

Hi-ROM Entry

Hi-ROM Program

Hi-ROM

Exit

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555h

AAh

2AAh

55h

555h

20h 

AAAh 555h AAAh XXXh

A0h PA PD 

XXXh

F0h



XXXh

XXXh XXXh

XXXh

90h

4 XXXh 60h SPA 60h SPA 40h SPA SD 

55h

98h 

AAh

555h

AAh

2AAh

55h

555h

88h 

AAAh 555h AAAh

555h

AAAh 555h AAAh

555h

AAh

2AAh

55h

555h

(HRA)

A0h

PD 

90h XXXh 00h 

AAAh 555h AAAh

(Continued)

*1 : This command is valid during Fast Mode.

MBM29LV320TE/BE

80/90/10

*2 : This command is valid while RESET

= VID. *3 : The valid addresses are A6 to A0. *4 : This command is valid during Hi-ROM mode. *5 : The data "00h" is also acceptable. Notes: • Address bits A

20 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and

Sector Address (SA) .

• Bus operations are defined in “MBM29LV320TE/BE User Bus Operations Tables (BYTE = V

IL)” .

• RA = Address of the memory location to be read PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A

will uniquely select any sector.

• RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

• SPA = Sector group address to be protected. Set sector group address (SGA) and (A SD = Sector group protection verify data. Output 01h at protected sector group addresses and

output 00h at unprotected sector group addresses.

• HRA = Address of the Hi-ROM area

29LV320TE (Top Boot Type) Word Mode : 1FFFE0h to 1FFFFFh 29LV320BE (Bottom Boot Type) Word Mode : 000000h to 000040h

• The system should generate the following address patterns :

Word Mode : 555h or 2AAh to addresses A Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in “MBM29LV320TE/BE Command Definition Table” are

illegal.

= VIH and BYTE

20, A19, A18, A17, A16, A15, A14, A13, and A12

6, A1, A0) = (0, 1, 0) .

Byte Mode : 3FFFC0h to 3FFFFFh Byte Mode : 000000h to 000080h

10 to A0

MBM29LV320TE/BE

MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table

Type A

80/90/10

to A

Code (HEX)

-1

Manufacture’s Code SA V

Byte

Device Code

MBM29LV320TE

Word X 22F6h

Byte

MBM29LV320BE

SA V

IL VIL VIL VIL 04h

VIL F6h

IL VIL VIH

VIL F9h

IL VIL VIH

Word X 22F9h

xtend Device Co

MBM29LV320TE/BE

Sector Group Protection

*1 : A

-1 is for Byte mode.

Byte

SA V

IL VIH VIH

Word X 0019h

Sector Group

Addresses

IL VIH VIL VIL 01h

VIL 19h

*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Expanded Autoselect Code Table

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

Type

Manufacturer’s Code 04h

MBM29LV

Device Code

Extend Device Code

320TE

MBM29LV 320BE

MBM29LV 320TE/BE

Sector Group Protection

Code

A-1/0

(B)

F6h A-1 HZ HZ HZ HZ HZ HZ HZ 1 1 1 1 0 1 1 0

(W) 22F6h

(B)

F9h A-1 HZ HZ HZ HZ HZ HZ HZ 1 1 1 1 1 0 0 1

(W) 22F9h

(B)

19h A-1 HZ HZ HZ HZ HZ HZ HZ 0 0 0 1 1 0 0 1

(W) 0019h

A-1/0

01h

0 0 0 0 00000000100

0001001011110110

0001001011111001

0000000000011001

0 0 0 0 00000000001

(B) : Byte mode (W) : Word mode

HZ: High-Z

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■

Sector Address Table (MBM29LV320TE)

MBM29LV320TE/BE

80/90/10

Sec-

tor

A20A19A18A17A16A15A14A13A12A

SA0 0 0 0 0 0 0 X X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA9 0 0 1 0 0 1 X X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

Sector Address

Sector

(Kbytes/

Kwords)

Size

××××

(

Address Range

××××

(

16)

Address Range

SA16 0 1 0 0 0 0 X X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA17 0 1 0 0 0 1 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

(Continued)

MBM29LV320TE/BE

Sec-

tor

A20A19A18A17A16A15A14A13A12A

SA32 1 0 0 0 0 0 X X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA35 1 0 0 0 1 1 X X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

Sector Address

80/90/10

(Kbytes/

Sector

Size

Kwords)

××××

(

Address Range

××××

(

16)

Address Range

SA43 1 0 1 0 1 1 X X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA45 1 0 1 1 0 1 X X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA63 1 1 1 1 1 1 0 0 0 X 8/4 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 X 8/4 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

(Continued)

MBM29LV320TE/BE

80/90/10

(Continued)

Sec-

tor

A20A19A18A17A16A15A14A13A12A

SA65 1 1 1 1 1 1 0 1 0 X 8/4 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh SA66 1 1 1 1 1 1 0 1 1 X 8/4 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh SA67 1 1 1 1 1 1 1 0 0 X 8/4 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh SA68 1 1 1 1 1 1 1 0 1 X 8/4 3FA000h to 3FBFFFh 1FD000h to 1FDFFFh SA69 1 1 1 1 1 1 1 1 0 X 8/4 3FC000h to 3FDFFFh 1FE000h to 1FEFFFh SA70 1 1 1 1 1 1 1 1 1 X 8/4 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A

Sector Address

20 : A0 if in word mode (BYTE = VIH) .

Sector

(Kbytes/

Kwords)

Size

××××

(

Address Range

××××

(

16)

Address Range

MBM29LV320TE/BE

Sector Address Table (MBM29LV320BE)

80/90/10

Sec-

tor

A20A19A18A17A16A15A14A13A12A

SA70 1 1 1 1 1 1 X X X X 64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh SA69 1 1 1 1 1 0 X X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA68 1 1 1 1 0 1 X X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA67 1 1 1 1 0 0 X X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA66 1 1 1 0 1 1 X X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA65 1 1 1 0 1 0 X X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA64 1 1 1 0 0 1 X X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA63 1 1 1 0 0 0 X X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA62 1 1 0 1 1 1 X X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh SA61 1 1 0 1 1 0 X X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh SA60 1 1 0 1 0 1 X X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA59 1 1 0 1 0 0 X X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA58 1 1 0 0 1 1 X X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA57 1 1 0 0 1 0 X X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA56 1 1 0 0 0 1 X X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA55 1 1 0 0 0 0 X X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh

Sector Address

Sector

(Kbytes/

Kwords)

Size

××××

(

Address Range

××××

(

16)

Address Range

SA54 1 0 1 1 1 1 X X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA53 1 0 1 1 1 0 X X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh SA52 1 0 1 1 0 1 X X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA51 1 0 1 1 0 0 X X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA50 1 0 1 0 1 1 X X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA49 1 0 1 0 1 0 X X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh SA48 1 0 1 0 0 1 X X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA47 1 0 1 0 0 0 X X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA46 1 0 0 1 1 1 X X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA45 1 0 0 1 1 0 X X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA44 1 0 0 1 0 1 X X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA43 1 0 0 1 0 0 X X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA42 1 0 0 0 1 1 X X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA41 1 0 0 0 1 0 X X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA40 1 0 0 0 0 1 X X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA39 1 0 0 0 0 0 X X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh SA38 0 1 1 1 1 1 X X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

(Continued)

MBM29LV320TE/BE

Sec-

tor

A20A19A18A17A16A15A14A13A12A

SA37 0 1 1 1 1 0 X X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA36 0 1 1 1 0 1 X X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA35 0 1 1 1 0 0 X X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA34 0 1 1 0 1 1 X X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA33 0 1 1 0 1 0 X X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA32 0 1 1 0 0 1 X X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA31 0 1 1 0 0 0 X X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA30 0 1 0 1 1 1 X X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA29 0 1 0 1 1 0 X X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA28 0 1 0 1 0 1 X X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA27 0 1 0 1 0 0 X X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

Sector Address

Sector

(Kbytes/

Kwords)

Size

××××

(

Address Range

80/90/10

××××

(

16)

SA26 0 1 0 0 1 1 X X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA25 0 1 0 0 1 0 X X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA24 0 1 0 0 0 1 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA23 0 1 0 0 0 0 X X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA22 0 0 1 1 1 1 X X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA21 0 0 1 1 1 0 X X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA20 0 0 1 1 0 1 X X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA19 0 0 1 1 0 0 X X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA18 0 0 1 0 1 1 X X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA17 0 0 1 0 1 0 X X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA16 0 0 1 0 0 1 X X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA15 0 0 1 0 0 0 X X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA14 0 0 0 1 1 1 X X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA13 0 0 0 1 1 0 X X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA12 0 0 0 1 0 1 X X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA11 0 0 0 1 0 0 X X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA10 0 0 0 0 1 1 X X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA9 0 0 0 0 1 0 X X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA8 0 0 0 0 0 1 X X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA7 0 0 0 0 0 0 1 1 1 X 8/4 00E000h to 00FFFFh 007000h to 007FFFh SA6 0 0 0 0 0 0 1 1 0 X 8/4 00C000h to 00DFFFh 006000h to 006FFFh SA5 0 0 0 0 0 0 1 0 1 X 8/4 00A000h to 00BFFFh 005000h to 005FFFh

(Continued)

MBM29LV320TE/BE

80/90/10

(Continued)

Sec-

tor

A20A19A18A17A16A15A14A13A12A

SA4 0 0 0 0 0 0 1 0 0 X 8/4 008000h to 009FFFh 004000h to 004FFFh SA3 0 0 0 0 0 0 0 1 1 X 8/4 006000h to 007FFFh 003000h to 003FFFh SA2 0 0 0 0 0 0 0 1 0 X 8/4 004000h to 005FFFh 002000h to 002FFFh SA1 0 0 0 0 0 0 0 0 1 X 8/4 002000h to 003FFFh 001000h to 001FFFh SA0 0 0 0 0 0 0 0 0 0 X 8/4 000000h to 001FFFh 000000h to 000FFFh

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A

Sector Address

20 : A0 if in word mode (BYTE = VIH) .

Sector

(Kbytes/

Kwords)

Size

××××

(

Address Range

××××

(

16)

Address Range

MBM29LV320TE/BE

Sector Group Address Table (MBM29LV320TE)

(Top Boot Block)

80/90/10

Sector Group A

Sectors

SGA0 0000XXXXXSA0 to SA3 SGA1 0001XXXXXSA4 to SA7 SGA2 0010XXXXXSA8 to SA11 SGA3 0011XXXXXSA12 to SA15 SGA4 0100XXXXXSA16 to SA19 SGA5 0101XXXXXSA20 to SA23 SGA6 0110XXXXXSA24 to SA27 SGA7 0111XXXXXSA28 to SA31 SGA8 1000XXXXXSA32 to SA35

SGA9 1001XXXXXSA36 to SA39 SGA10 1010XXXXXSA40 to SA43 SGA11 1011XXXXXSA44 to SA47 SGA12 1100XXXXXSA48 to SA51 SGA13 1101XXXXXSA52 to SA55 SGA14 1110XXXXXSA56 to SA59

SGA15 1 1 1 1

X X X SA60 to SA6201

10 SGA16 111111000 SA63 SGA17 111111001 SA64 SGA18 111111010 SA65 SGA19 111111011 SA66 SGA20 111111100 SA67 SGA21 111111101 SA68 SGA22 111111110 SA69 SGA23 111111111 SA70

MBM29LV320TE/BE

Sector Group Address Table (MBM29LV320BE)

80/90/10

(Bottom Boot Block)

Sector Group A

Sectors

SGA0 000000000 SA0 SGA1 000000001 SA1 SGA2 000000010 SA2 SGA3 000000011 SA3 SGA4 000000100 SA4 SGA5 000000101 SA5 SGA6 000000110 SA6 SGA7 000000111 SA7

SGA8 0000

X X X SA8 to SA1010

SGA9 0001XXXXXSA11 to SA14 SGA10 0010XXXXXSA15 to SA18 SGA11 0011XXXXXSA19 to SA22 SGA12 0100XXXXXSA23 to SA26 SGA13 0101XXXXXSA27 to SA30 SGA14 0110XXXXXSA31 to SA34 SGA15 0111XXXXXSA35 to SA38 SGA16 1000XXXXXSA39 to SA42 SGA17 1001XXXXXSA43 to SA46 SGA18 1010XXXXXSA47 to SA50 SGA19 1011XXXXXSA51 to SA54 SGA20 1100XXXXXSA55 to SA58 SGA21 1101XXXXXSA59 to SA62 SGA22 1110XXXXXSA63 to SA66 SGA23 1111XXXXXSA67 to SA70

MBM29LV320TE/BE

80/90/10

Common Flash Memory Interface Code Table

Description A6 to A

Query-unique ASCII string “QRY” 10h

Primary OEM Command Set 02h : AMD/FJ standard type

Address for Primary Extended Table 15h

Alternate OEM Command Set (00h = not applicable) 17h

Address for Alternate OEM Extended Table 19h

CC Min (write/erase)

7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit

CC Max (write/erase)

DQ15 to DQ

0051h 11h 12h

13h 14h

0052h

0059h

0002h

0000h

0040h 16h

0000h

0000h 18h

0000h

1Ah

0000h

1Bh 0027h

1Ch 0036h

DQ7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit V

PP Min voltage 1Dh 0000h

PP Max voltage 1Eh 0000h

Typical timeout per single byte/word write 2 Typical timeout for Min size buffer write 2

Typical timeout per individual block erase 2

Typical timeout for full chip erase 2 Max timeout for byte/word write 2 Max timeout for buffer write 2 Max timeout per individual block erase 2 Max timeout for full chip erase 2

Device Size = 2

byte

times typical

µs

times typical

1Fh 0004h

20h 0000h 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h 26h 0000h 27h 0016h

Flash Device Interface description 28h

29h

Max number of byte in multi-byte write = 2

2Ah 2Bh

0002h

0000h

Number of Erase Block Regions within device 2Ch 0002h Erase Block Region 1 Information 2Dh

2Eh 2Fh

30h

Erase Block Region 2 Information 31h

32h 33h 34h

0007h

0000h

0020h

0000h

003Eh

0000h

0001h

(Continued)

MBM29LV320TE/BE

(Continued)

Description A6 to A

80/90/10

DQ15 to DQ

Query-unique ASCII string “PRI” 40h

41h 42h

0050h

0052h

0049h

Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0031h Address Sensitive Unlock

45h 0000h

00h = Required 01h = Not Required

Erase Suspend

46h 0002h

00h = Not Supported 01h = To Read Only 02h = To Read & Write

Sector Group Protection

47h 0004h

00h = Not Supported X = Number of sectors in per group

Sector Group Temporary Unprotection

48h 0001h

00h = Not Supported 01h = Supported

Sector Group Protection Algorithm 49h 0004h Number of Sector for Bank 2

4Ah 0000h

00h = Not Supported Burst Mode Type

4Bh 0000h

00h = Not Supported Page Mode Type

4Ch 0000h

00h = Not Supported V

ACC (Acceleration) Supply Minimum

00h = Not Supported, DQ

7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit

ACC (Acceleration) Supply Maximum

00h = Not Supported, DQ

7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit

Boot Type 02h = MBM29LV320BE 03h = MBM29LV320TE

4Dh 00B5h

4Eh 00C5h

4Fh 00XXh

MBM29LV320TE/BE

FUNCTIONAL DESCRIPTION

■

1. Read Mode

The device has two control functions which must be satisfied in order to obtain data at the outputs. CE power control and should be used for a device selection. OE data to the output pins if a device is selected.

is the output control and should be used to gate

80/90/10

is the

Address access time (t time (t

CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable

access time is the delay from the falling edge of OE have been stable for at least t it is necessary to input hardware reset or to change CE

ACC) is equal to delay from stable addresses to valid output data. The chip enable access

to valid data at the output pins. (Assuming the addresses

ACC-tOE time.) When reading out data without changing addresses after power-up,

pin from “H” or “L”.

2. Standby Mode

There are two ways to implement the standb y mode on the de vice , one using both the CE other via the RESET

When using both pins, a CMOS standby mode is achie ved with CE

pin only.

and RESET inputs both held at VCC ± 0.3 V.

and RESET pins; the

Under this condition the current consumed is less than 5 µA Max During Embedded Algorithm operation, V active current (ICC2) is required ev en CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes.

When using the RESET

pin only, a CMOS standby mode is achieved with RESET input held at V SS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA Max Once the RESET pin is taken high, the device requires t

RH as wake up time for outputs to be valid for read access.

In the standby mode the outputs are in the high impedance state, independently of the OE input.

3. Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption.

To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE

, WE, and OE on the mode.

Under the mode, the current consumed is typically 1 µA (CMOS Level) .

During simultaneous operation, V

CC active current (ICC2) is required.

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and the device read the data for changed addresses.

4. Output Disable

With the OE

input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins

to be in a high impedance state.

5. Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V identifier bytes may then be sequenced from the device outputs by toggling address A addresses are DON’T CARES except A Tables (BYTE

= VIH and BYTE = VIL)” in ■DEVICE BUS OPERATIONS.)

6, A1, and A0 (A-1) . (See “MBM29LV320TE/BE User Bus Operations

ID (11.5 V to 12.5 V) on address pin A9. Two

0 from VIL to VIH. All

The manufacturer and de vice codes may also be read via the command register, for instances when the de vice is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29LV320TE/BE Command Definitions Table” (■DEVICE BUS OPERATIONS) (See “2. Autoselect Command” in ■COMAND DIFINITIONS) .

MBM29LV320TE/BE

80/90/10

Word 0 (A identifier code. Word 3 (A

0 = VIL) represents the manufacturer’ s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device

1 = A0 = VIH) represents the extended de vice code . These three bytes/words are given

in “MBM29L V320TE/BE Sector Group Protection V erify Autoselect Codes T ab le”and “Expanded Autoselect Code Table“ (■DEVICE BUS OPERATIONS) . In order to read the proper device codes when e xecuting the autoselect, A

1 must be VIL. (See “MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table” and “Ex-

panded Autoselect Code Table“ in ■DEVICE BUS OPERATIONS.)

6. Write

The device erasure and progr amming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE falling edge of WE

or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

whichever happens first. Standard microprocessor write timings are used. See “Read Only Operation Characteristics” in ■AC CHARACTERISTICS for specific timing parameters.

7. Sector Group Pr otection

The device f eatures hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See “Sector Group Address Tables (MBM29L V320TE/BE)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE). The sector g roup protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected.

T o activ ate this mode, the programming equipment must f orce V V

ID = 11.5 V) , CE = VIL and A6 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14,

13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29LV320TE/BE)” in

ID on address pin A9 and control pin OE, (suggest

■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the seventy one (71) individual sectors, and “Sector Group Address Tables (MBM29LV320TE/BE)” in ■FLEXIBLE SECT OR-ERASE ARCHITECTURE define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE rising edge of the same. Sector group addresses must be held constant during the WE

pulse and is terminated with the

pulse. See “14. Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “5. Sector Group Protection Algorithm” in ■FLOW CHART for sector group protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V

ID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A

12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 f or a protected sector.

Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A

0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer

and device codes. A

-1 requires to apply to VIL on byte mode.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Perf orming a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A

16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected

sector group. See “MBM29LV320TE/BE Sector Group Protection V erify A utoselect Codes T ab le” and “Expanded Autoselect Code Table” in ■DEVICE BUS OPERATIONS for Autoselect codes.

8. Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector g roups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET

pin to high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the V

ID is taken away from the RESET pin, all the previously protected sector groups will be

protected again. See “15. Temporary Sector Group Unprotection Timing Diagram” in ■TIMING DIAGRAM and “6. Temporary Sector Group Unprotection Algorithm” in ■FLOW CHART.

MBM29LV320TE/BE

80/90/10

9. Extended Sector Group Protection

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing V

ID on RESET pin and write a command

sequence. Unlike conv entional procedure, it is not necessary to force VID and control timing f or control pins. The only RESET requires V into the command register. Then, the sector group addresses pins (A

pin requires VID for sector group protection in this mode. The extended sector group protection

ID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)

20, A19, A18, A17, A16, A15, A14, A13 and A12)

and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins) , and write extended sector group protection command (60h) . A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following the command write, a logical “1” at device output DQ

0 will produce for protected sector in the read operation. If

the output is logical “0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET

pin to VIH. (See “16. Extended Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “7. Extended Sector Group Protection Algorithm” in ■FLOW CHART.)

10. RESET

Hardware Reset

The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (V of being executed will be terminated and the internal state machine will be reset to the read mode “t the RESET “t

RH” before it will allow read access . When the RESET pin is lo w, the device will be in the standby mode for the

IL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process

READY” after

pin is driven low. Fur thermore, once the RESET pin goes high, the device requires an additional

duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY should be ignored during the RESET

pulse. See “10. RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM

output signal

for the timing diagram. See “8. Temporary Sector Group Unprotection” for additional functionality.

11. Boot Block Sector Protection

20, A19,

The Write Protection function provides a hardware method of protecting certain boot sectors without using V This function is one of two provided by the WP

/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 8 K byte boot sectors independently of whether those sectors are protected or unprotected using the method described in “Sector Protection/Unprotection”. The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (MBM29LV320TE : SA69 and SA70, MBM29LV320BE : SA0 and SA1)

If the system asserts V

IH on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot

sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector protection/unprotection”.

12. Accelerated Program Operation

The device offers accelerated program operation which enables the programming in high speed. If the system asserts V

ACC

to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program oper ation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessar y. When the device enters the acceleration mode, the de vice automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode.

Removing V

ACC

from the WP/ACC pin returns the device to normal operation. Do not remove V

ACC

from WP/

ACC pin while programming. See “17. Accelerated Program Timing Diagram” in ■TIMING DIAGRAM.

ID.

MBM29LV320TE/BE

COMMAND DEFINITIONS

■

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The device operations are selected b y writing specific address and data sequences into the command register . Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. “MBM29LV320TE/BE Command Definitions Table” in ■DEVICE BUS OPERATIONS defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ

7 to DQ0 and DQ15 to DQ8 bits are ignored.

1. Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ

5 = 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memor y. The device remain enabled for reads until the command register contents are altered.

The device will automatically powe r-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. See “■AC CHARACTERISTICS” for the specific timing parameters.

2. Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A

9 to a high voltage. How ever , multiple xing high voltage

onto the address lines is not generally desired system design practice. The device contains an A utoselect command operation to supplement tr aditional PR OM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address (XX) 00h retrieves the manufacture code of 04h. A

read cycle from address (XX) 01h for ×16 ( (XX) 02h f or ×8) returns the device code. A read cycle from address (XX) 03h for ×16 ( (XX) 06h f or ×8) returns the extended de vice code . (See “MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table” and “Expanded Autoselect Code Table” in ■DEVICE BUS OPERATIONS.)

The sector state (protection or unprotection) will be informed by address (XX) 02h for ×16 ( (XX) 04h for ×8) . Scanning the sector group addresses (A will produce a logical “1” at device output DQ

20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0)

0 for a protected sector group . The programming v erification should

be performed by verify sector group protection on the protected sector. (See “MBM29LV320TE/BE User Bus Operations Tables (BYTE

= VIH and BYTE = VIL)” in ■DEVICE BUS OPERATIONS.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command.

3. Byte/Word Programming

The device is programmed on a b yte-by-byte (or word-by-w ord) basis. Programming is a four b us cycle operation. There are two “unlock” write cycles. These are f ollow ed by the prog ram set-up command and data write cycles. Addresses are latched on the falling edge of CE rising edge of CE

or WE, whichever happens first. The rising edge of CE or WE (whiche ver happens first) begins

or WE, whichever happens later and the data is latched on the

programming. Upon ex ecuting the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ or RY/BY

. The Data Polling and Toggle Bit m ust be performed at the memory location which is being programmed.

7 (Data Polling) , DQ6 (Toggle Bit) ,

MBM29LV320TE/BE

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The automatic programming operation is completed when the data on DQ

7 is equivalent to data written to this

bit at which time the device return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags Table”.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data

Polling m ust be perf ormed at the memory location which

is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the pro-

gramming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundar ies. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.

“1. Embedded Program

Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using

typical command strings and bus operations.

4. Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” wr ite cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase Algorithm command sequence the device will automatically program and v erify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations.

The system can determine the status of the erase operation by using DQ RY/BY

. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ

7 is “1” (See “12. Write Operation Status”.) at which time the

7 (Data Polling) , DQ6 (Toggle Bit) , or

device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “2. Embedded Erase

Algorithm” in ■FLOW CHART illustrates the Embedded Er aseTM Algorithm using typical

command strings and bus operations.

5. Sector Erase

Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then follo wed b y the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE happens later, while the command (Data = 30h) is latched on the rising edge of CE After time-out of “t

TOW” from the rising edge of the last sector erase command, the sector erase operation will begin.

or WE which happens first.

or WE whichever

Multiple sectors may be erased concurrently by wr iting the six bus cycle operations on “MBM29LV320TE/BE Command Definitions Table” in ■DEVICE BUS OPERATIONS. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “t

TOW” otherwise that command will not be accepted and erasure will not star t. It is

recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t last CE falling edge of CE (Monitor DQ

or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another

or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset.

3 to determine if the sector erase timer window is still open, see “16. DQ3”, Sector Erase Timer.)

TOW” from the rising edge of

Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restar t the erase on those sectors and allow them to complete. (See “12. Write Operation Status” for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70) .

Sector erase does not require the user to program the de vice prior to erase. The device automatically program all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing

MBM29LV320TE/BE

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a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y controls or timings during these operations.

The system can determine the status of the erase operation by using DQ RY/BY

The sector erase begins after the “t

TOW” time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ Status”.) at which time the device return to the read mode. Data

polling and Toggle Bit must be performed at

7 (Data Polling) , DQ6 (Toggle Bit) , or

7 is “1” (See “12. Write Operation

an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogr amming) ] × Number of Sector

Erase “2. Embedded Erase

Algorithm” in ■FLOW CHART illustrates the Embedded Er aseTM Algorithm using typical

command strings and bus operations.

6. Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perf orm data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximu m of “t

SPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the

RY/BY

output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must

use the address of the erasing sector for reading DQ

6 and DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device def aults to the er ase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successiv ely reading from the er ase-suspended sector while the device is in the erase-suspend-read mode will cause DQ

2 to toggle. (See “17. DQ2”.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Progr am mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-progr am mode will cause DQ Program operation is detected by the RY/BY is the same as the regular Program operation. Note that DQ

output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which

7 must be read from the Program address while DQ6

2 to toggle. The end of the erase-suspended

can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

7. Extended Command

(1) Fast Mode

The device has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing F ast Mode command into the command register . In this mode, the required bus cycle for prog ramming is tw o cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (See “8. Embedded Program

Algorithm for F ast Mode” in ■FLOW CHAR T .) The VCC active current is required ev en CE = VIH during

Fast Mode.

MBM29LV320TE/BE

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (See “8. Embedded Program

(3) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific ve ndor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. See “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE for details.

The operation is initiated by writing the query command (98h) into the command register. F ollowing the command write, a read cycle from specific address retrives device inf ormation. Please note that output data of upper byte (DQ

15 to DQ8) is “0” in word mode (16 bit) read. See “Common Flash Memory Interface Code T able” in ■FLEXIBLE

SECTOR-ERASE ARCHITECTURE. To terminate operation, it is necessar y to wr ite the read/reset command sequence into the register. (See “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTORERASE ARCHITECTURE.)

8. Hidden ROM (Hi-ROM ) Region

The Hi-ROM feature provides a Flash memor y region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.

Algorithm for Fast Mode” in ■FLOW CHART.)

80/90/10

The Hi-ROM region is 256 bytes in length and is stored at the same address of the “outermost” 8 K byte boot sector. The MBM29LV320TE occupies the address of the byte mode 3FFFC0h to 3FFFFFh (word mode 1FFFE0h to 1FFFFFh) and the MBM29LV320BE type occupies the address of the byte mode 000000h to 000080h (word mode 000000h to 000040h) . After the system has written the Enter Hi-ROM command sequence, the system may read the Hi-ROM region by using the addresses normally occupied by the boot sector. That is, the device sends all commands that would normally be sent to the boot sector to the Hi-ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sector.

9. Hidden ROM (Hi-ROM ) Entry Command

The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possib le in this area until it is protected. Ho w ever, once it is protected, it is impossible to unprotect, so please use this with caution.

Hidden ROM area is 256 byte and in the same address area of “outermost” 8 K byte boot bloc k. Theref ore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called as Hidden ROM mode when the Hidden ROM area appears.

Sector other than the boot block area could be read during Hidden ROM mode. Read/program of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the Hidden ROM mode.

10. Hidden ROM (Hi-ROM) Program Command

T o program the data to the Hidden R OM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is the same as the program command in usual e xcept to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ data poling, DQ6 toggle bit and RY/BY pin. Need to pa y attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, data of the address will be changed.

Please note that the sector erase command is prohibited during Hidden ROM mode. If the sector erase command is appeared in this mode, data of the address will be erased.

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11. Hidden ROM (Hi-ROM) Protect Command

There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command (60h) , set the sector address in the Hidden ROM area and (A

, A1, A0) = (0,1,0) , and write the sector group protect command (60h) during the Hidden ROM mode. The same command sequence could be used because it is the same as the extension sector group protect in the past except that it is in the Hidden ROM mode and it does not apply high voltage to RESET

pin. Please see “9. Extended Sector Group Protection” in ■FUNCTIONAL

DESCRIPTION for details of extention sector group protect setting. The other is to apply high voltage (V

, A0) = (0,1,0) , and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply

high voltage (V

) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the Hidden ROM area, and

read. When “1” appears on DQ

) to A9 and OE, set the sector address in the Hidden ROM area and (A6,

0, the protect setting is completed. “0” will appear on DQ0 if it is not protected.

Please apply write pulse agian. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector group protect in the past. Please see “7. Sector Group Protection” in ■FUNCTIONAL DESCRIPTION for details of the sector group protect setting.

Other sector group will be effected if the address other than those f or Hidden ROM area is selected f or the sector group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest attention.

12. Write Operation Status

Details in “Hardware Sequence Flags Table” are all the status flags that can be used to check the status of the device for current mode operation. Dur ing sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ consecutively read, then the DQ

2 is address sensitive. This means that if an address from an erasing sector is

2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing

sector is consecutively read. This allows users to determine which sectors are in erase. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is,

one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits.

Hardware Sequence Flags Table

Status DQ

Embedded Program Algorithm DQ

7 Toggle 0 0 1

Embedded Erase Algorithm 0 Toggle 0 1 Toggle *

Erase Suspend Read

In Progress

Erase Suspended Mode

(Erase Suspended Sector) Erase Suspend Read

(Non-Erase Suspended Sector) Erase Suspend Program

(Non-Erase Suspended Sector)

Embedded Program Algorithm DQ

Exceeded Time Limits

Embedded Erase Algorithm 0 Toggle 1 1 N/A Erase

Suspended Mode

Erase Suspend Program (Non-Erase Suspended Sector)

*: Successive reads from the erasing or erase-suspend sector will cause DQ

suspend sector address will indicate logic “1” at the DQ

2 bit.

1100Toggle

Data Data Data Data Data

7 Toggle 0 0 1 * 7 Toggle 1 0 1

7 Toggle 1 0 N/A

2 to toggle. Reading from non-erase

MBM29LV320TE/BE

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13. DQ

Data Polling

The device features Data

Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce a complement of data last written to DQ read device will produce true data last written to DQ device will produce a “0” at the DQ read device will produce a “1” on DQ

7. Upon completion of the Embedded Program Algorithm, an attempt to

7. During the Embedded Erase Algorithm, an attempt to read

7 output. Upon completion of the Embedded Erase Algorithm an attempt to

7. The flowchart for Data Polling (DQ7) is sho wn in “3. Data Polling Algorithm”

( ■FLOW CHART). For programming, the Data

Polling is valid after the rising edge of the four th wr ite pulse in the four write pulse

sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data

Polling m ust be performed at sector address within any of the sectors being erased,

not a protected sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ

asynchronously while the output enable (OE information on DQ on when the system samples the DQ

7 at one instant of time and then that byte’s valid data at the next instant of time. Depending

7 output, it may read the status or valid data. Ev en if the device has completed

the Embedded Algorithm operation and DQ The valid data on DQ

The Data

Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-

0 to DQ7 will be read on the successive read attempts.

) is asserted low. This means that the device is dr iving status

7 has a valid data, the data outputs on DQ0 to DQ6 may be still in valid.

7) may change

rithm, Erase Suspend mode or sector erase time-out. (See “Hardware Sequence Flags” Table.) See “6. Data Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the

Data

Polling timing specifications and diagrams.

14. DQ

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE from the device will results in DQ Algorithm cycle is completed, DQ

6 toggling between one and zero. Once the Embedded Program or Erase

6 will stop toggling and valid data will be read on the next successiv e attempts.

or OE toggling) data

During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector er ase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out.

In program operation, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop toggling with data unchanged. In erase operation, the device will er ase all selected sectors e xcept f or ones that are protected. If all selected sectors are protected, chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having data unchanged.

Either CE

or OE toggling will cause DQ6 to toggle.

See “7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams.

15. DQ

Exceeded Timing Limits

5 will indicate if the program or erase time has exceeded the specified limits (inter nal pulse count) . Under

these conditions DQ cycle was not successfully completed. Data The CE

circuit will partially power down device under these conditions (to approx imately 2 mA) . The OE and

5 will produce a “1”. This is a failure condition which indicates that the program or erase

Polling is the only oper ating function of de vice under this condition.

MBM29LV320TE/BE

pins will control the output disable functions as described in “MBM29LV320TE/BE User Bus Operations

WE Tables (BYTE

= VIH and BYTE = VIL)” (■DEVICE BUS OPERATIONS).

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The DQ

5 failure condition may also appear if a user tries to progr am a non blank location without er asing. In this

case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ

7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device f ailure condition since device was incorrectly used. If this occurs, reset device with command sequence.

16. DQ

Sector Erase Timer

After completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data

Polling and Toggle Bit are valid after the initial sector erase

command sequence. If Data

Polling or Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used

to determine if the sector erase timer window is still open. If DQ

3 is high (“1”) the internally controlled erase cycle

has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data

Polling or Toggle Bit I. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ

3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status

check, the command may not have been accepted. See “Hardware Sequence Flags Table”.

17. DQ

Toggle Bit II

This toggle bit II, along with DQ

6, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ

2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successiv e reads from the erase-suspended sector will cause DQ to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ

2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ

7, is summarized

as follows : For example, DQ

(DQ

2 toggles while DQ6 does not.) See also “T oggle Bit Status Table” and “8. DQ2 vs DQ6” in ■TIMING DIAGRAM.

Furthermore, DQ mode, DQ

2 toggles if this bit is read from an erasing sector.

18. Reading Toggle Bits DQ

2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

2 can also be used to determine which sector is being erased. When the device is in the erase

/DQ

Whenever the system initially begins reading toggle bit status , it m ust read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, this indicates that the device has completed the program or er ase operation. The system can read array data on DQ

7 to DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ

5 is high (see “15. DQ5”) . If it is the system should then determine

5 went high.

If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

MBM29LV320TE/BE

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The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ gone high. The system may continue to monitor the toggle bit and DQ

5 through successive read cycles, deter-

5 has not

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (See “4. Toggle Bit Algorithm” in ■FLOW CHART.)

Toggle Bit Status Table

Mode DQ

Program DQ7 Toggle 1 Erase 0 Toggle Toggle* Erase-Suspend Read

(Erase-Suspended Sector) Erase-Suspend Program DQ

* : Successive reads from the erasing or erase-suspend sector will cause DQ

suspend sector address will indicate logic “1” at the DQ

11Toggle

7 Toggle 1*

2 to toggle. Reading from non-erase

2 bit.

19. RY/BY

Ready/Busy

The device provides a RY/BY

open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If output is low , the device is b usy with either a program or erase operation. If output is high, the device is ready to accept any read/write or erase operation. When the RY/BY

pin is low, the device will not accept any additional program or erase commands. If the device is placed

in an Erase Suspend mode, RY/BY

output will be high.

During programming, RY/BY operation, RY/BY

pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy condition during RESET RESET

, RY/BY Timing Diagr am” in ■TIMING DIA GRAM for a detailed timing diag ram. R Y/BY pin is pulled high

pin is driven low after the rising edge of the fourth write pulse. During an erase

pulse. See “9. RY/BY Timing Diagram during Program/Erase operations” and “10.

in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

20. Byte/Word Configuration

BYTE

pin selects byte (8-bit) mode or word (16-bit) mode fo r device. When this pin is driven high, the device operates in word (16-bit) mode. Data is read and programmed at DQ device operates in byte (8-bit) mode. Under this mode, DQ

15/A-1 pin becomes the lowest address bit, and DQ14

15 to DQ0. When this pin is driven low, the

to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ Diagram”, “12. Byte Mode Configuration Timing Diagram” and “13. BYTE

15 to DQ8 and the DQ7 to DQ0 bits are ignored. See “11. Word Mode Configuration Timing

Timing Diagram for Write Operations”

in ■TIMING DIAGRAM the detail .

21. Data Protection

The device is designed to off er protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up de vice automatically resets internal state machine in Read mode. Also, with its control register architecture, alteration of memor y contents only occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadver tent wr ite cycles resulting from V

CC power-up

and power-down transitions or system noise.

MBM29LV320TE/BE

22. Low V

Write Inhibit

80/90/10

To avoid initiation of a write cycle during V than V

LKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

CC power-up and power-do wn, a write cycle is loc ked out for VCC less

disabled. Under this condition the device will reset to the read mode . Subsequent writes will be ignored until the V

CC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when V

CC is above VLKO (Min) .

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.

23. Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (Typ) on OE

, CE, or WE will not initiate a write cycle.

24. Logical Inhibit

Writing is inhibited by holding any one of OE

= VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

25. Power-Up Write Inhibit

Power-up of the device with WE

= CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

■■■■ ABSOLUTE MAXIMUM RATINGS

MBM29LV320TE/BE

80/90/10

Parameter Symbol

Unit

Min Max

Storage Temperature Tstg −55 +125 °C

Rating

Ambient Temperature with Power Applied T V oltage with Respect to Ground All pins e xcept A

, and RESET * Power Supply Voltage * A

9, OE, and RESET *

/ACC *

1, *4

*1 : Voltage is defined on the basis of V

1, *2

1, *3

SS = GND = 0 V.

A −40 +85 °C

VIN, VOUT −0.5 VCC + 0.5 V

VCC −0.5 +4.0 V

VIN −0.5 +13.0 V

VACC −0.5 +13.0 V

*2 : Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may

undershoot V V

CC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to

SS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is

20 ns.

* 3: Minimum DC input voltage on A

pins may undershoot V and supply voltage (V

SS to −2.0 V for periods of up to 20 ns. Voltage difference between input

IN − VCC) does not exceed +9.0 V.Maximum DC input voltage on A9, OE and RESET pins

9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET

is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.

* 4: Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may

undershoot V +13.0 V which may overshoot to +12.0 V for periods of up to 20 ns when V

SS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is

CC is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■■■■ RECOMMENDED OPERATING RANGES

Parameter Symbol Part No.

Ambient Temperature T

A MBM29LV320TE/BE 80/90/10 −40 +85 °C

MBM29LV320TE/BE 80/90 +3.0 +3.6

Power Supply Voltage V

MBM29LV320TE/BE 10 +2.7 +3.6

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

Value

Unit

Min Max

MBM29LV320TE/BE

MAXIMUM OVERSHOOT/UNDERSHOOT

■

80/90/10

+0.6 V

−0.5 V

−2.0 V

CC + 2.0 V

V VCC + 0.5 V

+2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

20 ns20 ns

+14.0 V

+13.0 V

CC + 0.5 V

Maximum Overshoot Waveform 1

Note : This waveform is applied for A

Maximum Overshoot Waveform 2

20 ns

20 ns20 ns

9, OE, and RESET.

■■■■ DC CHARACTERISTICS

Parameter Symbol Conditions Min Max Unit

Input Leakage Current I

MBM29LV320TE/BE

LI VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA

80/90/10

Output Leakage Current I A

9, OE, RESET Inputs Leakage

Current

CC Active Current *

CC Current (Standby) ICC3

CC Current (Standby, Reset) ICC4

VCC Current (Automatic Sleep Mode) *

/ACC Accelerated Program

Current

ICC1

ICC2 CE = VIL, OE = VIH  40 mA

ICC5

IACC

Input Low Level V Input High Level V Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration

LO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA

ILIT

VCC = VCC Max, A

9, OE, RESET = 12.5 V

CE = VIL, OE = VIH,

f = 5 MHz

= VIL, OE = VIH,

f = 1 MHz

Byte

Word 18

Byte

Word 7

VCC = VCC Max, CE = VCC ± 0.3 V, RESET

= VCC ± 0.3 V

VCC = VCC Max,WE/ACC = VCC ±

0.3 V, RESET

= VSS ± 0.3 V

 35 µA



 5 µA

VCC = VCC Max, CE = VSS ± 0.3 V, RESET V

VCC = VCC Max, WP

IL − 0.5 + 0.6 V IH  2.0 VCC + 0.3 V

ACC  11.5 12.5 V

= VCC ± 0.3 V

IN = VCC ± 0.3 V or VSS ± 0.3 V

/ACC = VACC Max

 5 µA

 20 mA

Voltage for Autoselect and Sector Group Protection (A

9, OE, RESET) *

Output Low Voltage Level V

VID  11.5 12.5 V

OL IOL = 4.0 mA, VCC = VCC Min  0.45 V

VOH1 IOH = −2.0 mA, VCC = VCC Min 2.4  V

Output High Voltage Level

OH2 IOH = −100 µAVCC − 0.4  V

Low V

CC Lock-Out Voltage VLKO  2.3 2.5 V

* 1: The ICC current listed includes both the DC operating current and the frequency dependent component. * 2: I

CC active while Embedded Algorithm (program or erase) is in progress.

* 3: Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. * 4: Applicable for only V

CC applying.

MBM29LV320TE/BE

AC CHARACTERISTICS

■

•

Read Only Operations Characteristics

Parameter

Read Cycle Time t

JEDEC Standard

AVAV tRC  80  90 100  ns

80/90/10

Symbol

Condi-

tion

Value

90* 10*

Min Max Min Max Min Max

Unit

Address to Output Delay t Chip Enable to Output Delay t

Output Enable to Output Delay t Chip Enable to Output High-Z t

AVQV tACC ELQV tCE OE = VIL  80  90  100 ns

GLQV tOE 30  35  35 ns EHQZ tDF 25  30  30 ns

CE = VIL OE = VIL

 80  90  100 ns

Output Enable to Output High-Z tGHQZ tDF 25  30  30 ns Output Hold Time From Addresses,

or OE, Whichever Occurs First

RESET CE

Pin Low to Read Mode  tREADY 20  20  20 µs

to BYTE Switching Low or High 

AXQX tOH  0  0  0  ns

ELFL

tELFH

5  5  5ns

* : Test Conditions :

Output Load : 1 TTL gate and 30 pF (MBM29LV320TE80, MBM29LV320BE80) 100 pF (MBM29LV320TE90/10, MBM29LV320BE90/10) Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V

3.3 V

Device

Under

Test

IN3064 or Equivalent

6.2 kΩ

2.7 kΩ

Notes : CL = 30 pF including jig capacitance (MBM29LV320TE80, MBM29LV320BE80)

L = 100 pF including jig capacitance (MBM29LV320TE90/10, MBM29LV320BE90/10)

Test Conditions

Diodes = IN3064 or Equivalent

MBM29LV320TE/BE

80/90/10

•

Write/Erase/Program Operations

Symbol Value

Parameter

JEDEC Standard

Min

(Note)

Typ

Max Min

(Note)

Typ

Max Min

(Note)

Typ

Unit

Max

Write Cycle Time tAVAV tWC 80 90 100 ns Address Setup Time t

AVWL tAS 0  0  0  ns

Address Hold Time tWLAX tAH 45 45 45 ns Data Setup Time t Data Hold Time t Output En-

Read able Hold Time

Toggle and Data

Polling 10 10 10 ns

Read Recover Time Before Write t Read Recover Time Before Write

(OE

High to CE Low)

DVWH tDS 30 35 35 ns WHDX tDH 0  0  0  ns

0  0  0 ns

 tOEH

GHWL tGHWL 0  0  0 ns

tGHEL tGHEL 0  0  0 ns

CE Setup Time tELWL tCS 0  0  0 ns WE

Setup Time tWLEL tWS 0  0  0 ns

Hold Time tWHEH tCH 0  0  0  ns WE Hold Time tEHWH tWH 0  0  0  ns Write Pulse Width t CE

Pulse Width tELEH tCP 35 35 35 ns Write Pulse Width High t

WLWH tWP 35 35 35 ns

WHWL tWPH 25 30 30 ns

CE Pulse Width High tEHEL tCPH 25 30 30 ns

Programming Operation

Byte

WHWH1 tWHWH1

 8 8  8 µs

Word  16 16 16 µs Sector Erase Operation * V

CC Setup Time  tVCS 50 50 50 µs

Rise Time to V

ID *

Rise Time to VACC * Voltage Transition Time * Write Pulse Width * OE Setup Time to WE Active * CE

Setup Time to WE Active * Recover Time From RY/BY RESET

Pulse Width  tRP 500 500 500 ns

tWHWH2 tWHWH2  1 1  1  s

 tVIDR 500 500 500 ns

 tVACCR 500 500 500 ns  tVLHT 4  4  4  µs  tWPP 100 100 100  µs  tOESP 4  4  4 µs  tCSP 4  4  4  µs  tRB 0  0  0  ns

RESET High Level Period Before Read  tRH 200 200 200 ns

(Continued)

MBM29LV320TE/BE

80/90/10

(Continued)

Symbol Value

Parameter

JEDEC Standard

Min

(Note)

Typ

Max Min

(Note)

Typ

Max Min

(Note)

Typ

Max

BYTE Switching Low to Output High-Z  tFLQZ 30 30 30 ns BYTE

Switching High to Output Active  tFHQV 80 90 100 ns

Program/Erase Valid to RY/BY Delay  tBUSY 90 90 90 ns

Unit

Delay Time from Embedded Output Enable

 t

Erase Time-out Time  t Erase Suspend Transition Time  t

EOE 80 90 100 ns

TOW 50 50 50  µs

SPD 20 20 20 µs

*1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is limited for Accelerated Program operation only.

ERASE AND PROGRAMMING PERFORMANCE

■

MBM29LV320TE/BE

80/90/10

Parameter

Sector Erase Time  110s Word Programming Time  16 360 µs

Byte Programming Time  8 300 µs Chip Programming Time 100 s Program/Erase Cycle 100,000 cycle 

TSOP (I) PIN CAPACITANCE

■

Parameter Symbol Condition

Input Capacitance C Output Capacitance C Control Pin Capacitance CIN2 VIN = 0 8.0 10.0 pF WP

/ACC Pin Capacitance CIN3 VIN = 0 15.0 20.0 pF

Note : Test conditions TA = + 25 °C, f = 1.0 MHz

Min Typ Max

IN VIN = 06.07.5pF OUT VOUT = 0 8.5 12.0 pF

Limits

Unit Comments

Excludes programming time prior to erasure

Excludes system-level overhead

Value

Unit

Typ Max

FBGA PIN CAPACITANCE

■

Parameter Symbol Condition

Input Capacitance C Output Capacitance C Control Pin Capacitance CIN2 VIN = 0 8.0 10.0 pF WP

/ACC Pin Capacitance CIN3 VIN = 0 15.0 20.0 pF

Note : Test conditions TA = + 25 °C, f = 1.0 MHz

IN VIN = 06.07.5pF OUT VOUT = 0 8.5 12.0 pF

Value

Unit

Typ Max

MBM29LV320TE/BE

TIMING DIAGRAM

■

•

Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

80/90/10

1. Read Operation Timing Diagram

Address

Must Be Steady

May Change from H to L

May Change from L to H

"H" or "L" Any Change Permitted

Does Not Apply

Address Stable

Will Be Steady

Will Change from H to L

Will Change from L to H

Changing State Unknown

Center Line is HighImpedance "Off" State

Outputs

tACC

tOE tDF

tOEH

tCE

High-Z High-Z

Output Valid

tOH

Hardware Reset/Read Operation Timing Diagram

MBM29LV320TE/BE

80/90/10

Address

tACC

tRH

tRP tRH tCE

Address Stable

RESET

Outputs

Alternate WE Controlled Program Operation Timing Diagram

Address

High-Z

3rd Bus Cycle Data Polling

555h PA

tWC

tAS tAH

tOH

Output Valid

tRC

tCS

tCH

tGHWL

tWPHtWP

tWHWH1

tDH

tDS

Data

A0h PD

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ

7 is the output of the complement of the data written to the device.

• D

OUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

tCE

tOE

tOH

DOUT DOUT

MBM29LV320TE/BE

Alternate CE Controlled Program Operation Timing Diagram

80/90/10

3rd Bus Cycle Data Polling

Address

tGHEL

Data

555h PA

tWC

tWS

tCP

tDS

A0h

tAS tAH

tWH

tCPH

tDH

tWHWH1

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ

7 is the output of the complement of the data written to the device.

• D

OUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

DOUT

Chip/Sector Erase Operation Timing Diagram

MBM29LV320TE/BE

80/90/10

Address

Data

tCS

tGHWL

tVCS

555h 2AAh 555h 555h 2AAh SA*

tWC

tWP

tDS

tAS

tAH

tCH

tWPH

tDH

AAh 55h 80h AAh 55h

10h for Chip Erase

30h

* : SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase. Note : These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

MBM29LV320TE/BE

Data Polling during Embedded Algorithm Operation Timing Diagram

80/90/10

tCH

tOE

tOEH

tCE

DQ6 to DQ0

Data

tWHWH1 or 2

Data

tBUSY

DQ7

6 to DQ0 =

Output Flag

tEOE

RY/BY

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

DQ7 =

Valid Data

6 to DQ0

DQ Valid Data

tDF

High-Z

Toggle Bit I during Embedded Algorithm Operation Timing Diagram

tOEH

tDH

Data (DQ0 to DQ7)

6 = Toggle

DQ6 = Toggle

* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)

DQ6 =

Stop Toggling

tOE

DQ0 to DQ7

Data Valid

MBM29LV320TE/BE

80/90/10

Enter

Erasing

Erase

Suspend

Erase Suspend

Read

Enter Erase

Suspend Program

8. DQ2 vs. DQ

Embedded

DQ6

DQ2 *

Toggle

DQ2 and DQ6

with OE or CE

* : DQ2 is read from the erase-suspended sector.

RY/BY Timing Diagram during Program/Erase Operations

Erase Suspend Program

Erase Suspend

Read

Erase

Resume

Erase

Complete

RY/BY

10. RESET, RY/BY Timing Diagram

RESET

tRP

Rising edge of the last write pulse

Entire programming or erase operations

BUSY

tRB

RY/BY

tREADY

MBM29LV320TE/BE

11.

Word Mode Configuration Timing Diagram

BYTE

80/90/10

tCE

14 to DQ0

tELFH

DQ15/A-1

Data Output

(DQ7 to DQ0)

tFHQV

A-1

12. Byte Mode Configuration Timing Diagram

BYTE

14 to DQ0

DQ15/A-1

tELFL

Data Output

(DQ14 to DQ0)

DQ15

tFLQZ

Data Output

(DQ14 to DQ0)

Data Output

(DQ7 to DQ0)

tACC

A-1

13. BYTE

Timing Diagram for Write Operations

CE or WE

BYTE

tSET

(tAS)

Falling edge of last write signal

Input Valid

HOLD (tAH)

14.

Sector Group Protection Timing Diagram

A20, A19, A18 A17, A16, A15 A14, A13, A12

A6, A0

V 3 V

3 V

SPAX

tVLHT

MBM29LV320TE/BE

tVLHT

80/90/10

SPAY

tOESP

Data

tVCS

VCC

tCSP

SPAX : Sector Group Address to be protected. SPAY : Next Sector Group Address to be protected.

Note : A

-1 is VIL on byte mode.

tWPP

01h

tOE

MBM29LV320TE/BE

15.

Temporary Sector Group Unprotection Timing Diagram

80/90/10

VCC

VID 3 V

RESET

RY/BY

tVCS

tVIDR

tVLHT

Program or Erase Command Sequence

Unprotection period

tVLHT

16.

Extended Sector Group Protection Timing Diagram

MBM29LV320TE/BE

80/90/10

VCC

RESET

Address

6, A0

tVIDR

tVCS

tVLHT

tWC tWC

SPAX SPAX SPAY

tWP

TIME-OUT

Data

SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min)

60h01h40h60h60h

tOE

MBM29LV320TE/BE

17.

Accelerated Program Timing Diagram

VACC

3 V

WP/ACC

tVACCR

tVCS

80/90/10

tVLHT

RY/BY

tVLHT

Program Command Sequence

Acceleration period

tVLHT

FLOW CHART

■

Embedded ProgramTM Algorithm

EMBEDDED ALGORITHM

MBM29LV320TE/BE

Start

Write Program

Command Sequence

(See Below)

Data Polling

Verify Data

80/90/10

Embedded Program Algorithm in progress

Yes

Increment Address

Program Command Sequence (Address/Command):

Programming Completed

Program Address/Program Data

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Last Address

Yes

555h/AAh

2AAh/55h

555h/A0h

MBM29LV320TE/BE

Embedded EraseTM Algorithm

EMBEDDED ALGORITHM

80/90/10

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Data = FFh

Yes

Erasure Completed

Embedded Erase Algorithm in progress

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Sector Address

/30h

Additional sector erase commands are optional.

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Data Polling Algorithm

MBM29LV320TE/BE

80/90/10

Start

Read Byte

7 to DQ0)

(DQ

Addr. = VA

DQ7 = Data?

DQ5 = 1?

Read Byte

(DQ

7 to DQ0)

Addr. = VA

DQ7 = Data?

Fail Pass

Yes

VA = Address for programming

= Any of the sector addresses

within the sector being erased during sector erase or multiple erases operation

= Any of the sector addresses

within the sector not being protected during sector erase or multiple sector erases operation

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

MBM29LV320TE/BE

Toggle Bit Algorithm

80/90/10

Start

Read DQ

Addr. = "H" or "L"

Read DQ7 to DQ0

Addr. = "H" or "L"

Read DQ7 to DQ0

Addr. = "H" or "L"

Program/Erase

Complete, Write

Reset Command

7 to DQ0

DQ6

= Toggle?

DQ5 = 1?

Twice

DQ6

= Toggle?

Operation Not

Yes

*1, *2

Program/Erase

Operation

Complete

*1 : Read toggle bit twice to determine whether or not it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ

5 changes to “1”.

Sector Group Protection Algorithm

MBM29LV320TE/BE

Start

Setup Sector Group Addr.

20, A19, A18, A17,A16,

()

A15, A14, A13, A12

PLSCNT = 1

OE = VID, A9 = VID,

CE = VIL, RESET = VIH

A6 = A0 = VIL, A1 = VIH

Activate WE Pulse

80/90/10

Increment PLSCNT

PLSCNT = 25?

Yes Yes

Remove V

Write Reset Command

ID from A9

Device Failed

Time out 100 µs

WE = V

IH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A

()

A6 = A0 = VIL

Data = 01h?

Protect Another Sector

Remove V

Write Reset Command

Sector Group Protection

Completed

Group ?

ID from A9

1 = VIH

Yes

* : A-1 is V IL on byte mode.

MBM29LV320TE/BE

Temporary Sector Group Unprotection Algorithm

80/90/10

Start

RESET = V

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again.

7. Extended Sector Group Protection Algorithm

RESET = VID

Wait to 4 µs

MBM29LV320TE/BE

Start

80/90/10

Device is Operating in

Temporary Sector Group

Unprotection Mode

Increment PLSCNT

PLSCNT = 25?

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group Protection

To Verify Sector Group Protection

Write XXXh/60h

PLSCNT = 1

To Protect Sector Group

Write 60h to Sector Address

6 = A0 = VIL, A1 = VIH)

Time out 250 µs

Write 40h to Sector Address

6 = A0 = VIL, A1 = VIH)

Read from Sector Group

Address

0 = VIL, A1 = VIH, A6 = VIL)

Data = 01h?

Setup Next Sector Address

Yes

Remove V

Write Reset Command

ID from RESET

Device Failed

Yes

Protection Other Sector

Remove VID from RESET

Sector Group Protection

Group ?

Write Reset Command

Completed

Yes

MBM29LV320TE/BE

Embedded ProgramTM Algorithm for Fast Mode

FAST MODE ALGORITHM

80/90/10

Start

555h/AAh

Increment Address

2AAh/55h

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling

Verify Data?

Yes

Last Address

Yes

Programming Completed

XXXXh/90h

XXXXh/F0h

Set Fast Mode

In Fast Program

Reset Fast Mode

Notes : •The sequence is applied for × 16 mode.

•The addresses differ from × 8 mode.

MBM29LV320TE/BE

ORDERING INFORMATION

■

Standard Products

Fujitsu standard products are availab le in several packages. The order number is formed by a combination of :

MBM29LV320 T E 80 TN

PACKAGE TYPE TN = 48-Pin Thin Small Outline Package

TR = 48-Pin Thin Small Outline Package PBT = 63-Ball Fine pitch Ball Grid Array

SPEED OPTION See Product Selector Guide

DEVICE REVISION

(TSOP) Standard Pinout (TSOP) Reverse Pinout Package (FBGA)

80/90/10

Valid Combinations Valid Combinations

MBM29LV320TE/BE

BOOT CODE SECTOR ARCHITECTURE T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION MBM29LV320

32Mega-bit (4 M × 8-Bit or 2 M × 16-Bit) CMOS Flash Memory

3.0 V-only Read, Program, and Erase

80 90 10

TN TR

PBT

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.

MBM29LV320TE/BE

PACKAGE DIMENSION

■

80/90/10

48-pin plastic TSOP (I)

(FPT-48P-M19)

LEAD No.

INDEX

"A"

2001 FUJITSU LIMITED F48029S-c-4-5

±0.20

20.00 (.787±.008)

18.40

±0.20

(.724±.008)

0.10(.004)

* Resin Protrusion. (Each Side: 0.15 (.006) Max)

Details of "A" part

0.25(.010)

0~8˚

0.60±0.15

(.024

±.006)

2524

±0.20*

12.00

(.472

0.17 .007

0.50(.020)

+0.03

–

0.08

+.001

–

.003

TYP

±.008)

11.50REF (.453)

0.22

(.009±.002)

±0.05

(Stand off height)

0.10(.004)

1.10

(Mounting

0.10±0.05

(.004±.002)

height)

+0.10

–

+.004

–

0.05 .002.043

Dimensions in mm (inches)

48-pin plastic TSOP (I)

(FPT-48P-M20)

LEAD No.

INDEX

24 25

2000 FUJITSU LIMITED F48030S-3c-4

19.00±0.20 (.748±.008)

0.10(.004)

18.40±0.20

(.724±.008)

20.00±0.20 (.787±.008)

* Resin Protrusion. (Each Side: 0.15 (.006) Max)

Details of "A" part

"A"

0.15(.006) 0.25(.010)

0.50±0.10

(.020±.004)

0.15±0.05

(.006±.002)

0.50(.020) TYP

(.008±.004)

11.50(.453)REF

12.00±0.20(.472±.008)

0.20±0.10

0.15(.006) MAX

0.35(.014) MAX

0.10(.004)

0.10±0.05

(.004±.002)

(STAND OFF)

+0.10 –0.05

1.10

+.004

.043 –.002

(Mounting height)

Mounting height

Dimensions in mm (inches)

(Continued)

63-pin plastic FBGA

(BGA-63P-M01)

MBM29LV320TE/BE

80/90/10

11.00±0.10(.433±.004)

7.00±0.10

(.276±.004)

INDEX AREA

0.10(.004)

2001 FUJITSU LIMITED B63001S-c-2-2

+0.15 –0.10

1.05

+.006

.041 –.004

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(4.00(.157))

(5.60(.220))

(8.80(.346)) (7.20(.283)) (5.60(.220))

0.80(.031)TYP

63-ø0.45±0.05

(63-ø0.18±.002)

DEF

0.08(.003)

INDEX BALL

Dimensions in mm (inches)

8 7 6 5 4 3 2 1

MBM29LV320TE/BE

80/90/10

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608 Fax: +1-408-922-9179

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS K OREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F0202

 FUJITSU LIMITED Printed in Japan

FUJITSU MBM29LV320TE80, MBM29LV320BE80, MBM29LV320BE90, MBM29LV320BE10, MBM29LV320TE90 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual