FUJITSU MBM29LV160TE, MBM29LV160BE DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

MBM29LV160TE/BE

FEATURES

■

• 0.23 µm Process Technology

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT)

• Minimum 1,000,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector B = Bottom sector

• Embedded Erase

Automatically pre-programs and erases the chip or any sector

PRODUCT LINE UP

■

Algorithms

PROMs

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DS05-20883-1E

(Continued)

Part No. MBM29LV160TE/160BE

= 3.3 V

Ordering Part No.

= 3.0 V

Max. Address Access Time (ns) 70 90 120 Max. CE Max. OE

Access Time (ns) 70 90 120 Access Time (ns) 30 35 50

+0.3 V –0.3 V

+0.6 V –0.3 V

70 — —

—9012

Marking Side

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MBM29LV160TE/BE

(Continued)

• Embedded ProgramTM Algorithms

Automatically programs and verifies data at specified address

•Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

•Low V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection Set function by Extended sector Protection command

• Fast Programming Function by Extended command

• Temporary sector unprotection

Temporary sector unprotection via the RESET

• In accordance with CFI (C

write inhibit ≤ 2.5 V

)

ommon Flash Memory Interface)

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PACKAGES

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48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

48-pin plastic CSOP

48-pin plastic TSOP (I)

(FPT-48P-M20)

48-pin plastic FBGA

(LCC-48P-M03)

(BGA-48P-M11)

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MBM29LV160TE/BE

GENERAL DESCRIPTION

■

The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA packages. The de vice is designed to be programmed in-system with the standard system 3.0 V V V V

and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in

standard EPROM programmers. The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of high-

speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE

), write enable (WE), and output enable (OE) controls.

The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and er ase operations . Reading data out of the de vice is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before e xecuting the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.

PROMs. Commands are

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supply . 12.0

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors . The MBM29L V160TE/BE is erased when shipped from the factory . The device f eatures single 3.0 V power supply oper ation f or both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V inhibits write operations on the loss of power. The end of program or erase is detected by Data by the Toggle Bit feature on DQ comleted, the device internally resets to the read mode.

The MBM29LV160TE/BE also has a hardware RESET Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are programmed one b yte/word at a time using the EPROM programming mechanism of hot electron injection.

, or the RY/BY output pin. Once the end of a prog ram or er ase cycle has been

pin. When this pin is driven low, execution of any

pin may be tied to the system reset circuitry. Therefore, if a system reset

detector automatically

Polling of DQ7,

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MBM29LV160TE/BE

PIN ASSIGNMENTS

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A A

9 10 11 12 13 14 15

N.C.

RESET

N.C. N.C.

RY/BY

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TSOP(I)

(Marking Side)

Standard Pinout

(FPT-48P-M19)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

BYTE V

DQ15/A DQ

V CE A

-1

A A

RY/BY

N.C. N.C.

RESET

N.C.

A A A A A A

16 15 14 13 12 11 10

(Marking Side)

Reverse Pinout

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 45 46 47 48

V OE DQ DQ DQ DQ DQ DQ DQ DQ V

DQ DQ DQ DQ DQ DQ DQ DQ V

BYTE

0 8 1 9 2 10 3 11

4 12 5 13 6 14 7 15/A-1

(FPT-48P-M20)

(Continued)

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(Continued)

A17 A18

RY/BY

N.C. N.C.

RESET

N.C.

A10 A11 A12 A13 A14 A15

A A2 A3 A4 A5 A6 A7

A8 A9

MBM29LV160TE/BE

CSOP

(TOP VIEW)

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

(Marking side)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16

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A1 A B1 A C1 A D1 A E1 A

A2 A B2 A C2 A D2 A

E2 DQ F1 CE F2 DQ G1 OE G2 DQ H1 V

H2 DQ

(LCC-48P-M03)

FBGA

(TOP VIEW)

Marking side

(BGA-48P-M11)

A3 RY/BY A4 WE A5 A B3 N.C. B4 RESET B5 A C3 A

D3 N.C. D4 A

E3 DQ F3 DQ G3 DQ H3 DQ

C4 N.C. C5 A

E4 DQ F4 DQ G4 V

H4 DQ

D5 A E5 DQ F5 DQ G5 DQ H5 DQ

A6 A B6 A C6 A D6 A E6 A

F6 BYTE G6 DQ15/A H6 V

-1

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MBM29LV160TE/BE

BLOCK DIAGRAM

■

BYTE

RESET

CE OE

RY/BY Buffer

State

Control

Command

RY/BY

Program Voltage

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Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

DQ0 to DQ

Input/Output

Buffers

Data Latch

A0 to A

STB

Low V

Detector

-1

Timer for

Program/Erase

Address

Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

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LOGIC SYMBOL

■

A-1

A0 to A19

CE OE WE RESET BYTE

DQ0 to DQ15

RY/BY

16 or 8

MBM29LV160TE/BE

Table 1 MBM29LV160TE/BE Pin Configuration

Pin Function

, A0 to A

-1

to DQ

RY/BY

RESET

BYTE

N.C. Pin Not Connected Internally

Address Inputs

Data Inputs/Outputs

Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/

Temporary Sector Unprotection Selects 8-bit or 16-bit mode

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Device Ground Device Power Supply

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MBM29LV160TE/BE

DEVICE BUS OPERATIONS

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Table 2 MBM29LV160TE/BE User Bus Operation (BYTE

Operation CE

Auto-Select Manufacture Code (1) L L H L L L V Auto-Select Device Code (1) L L H H L L V Read (3) L L H A

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OE WE A

= VIH)

DQ0 to DQ

Code H Code H

RESET

OUT

H Standby HXXXXXXHIGH-Z H Output Disable LHHXXXXHIGH-Z H Write (Program/Erase) L H L A Enable Sector Protection (2), (4) L V

LHLVIDXH

Verify Sector Protection (2), (4) L L H L H L V Temporary Sector Unprotection (5) X X X X X X X X V

Code H

Reset (Hardware)/Standby XXXXXXXHIGH-Z L

Table 3 MBM29LV160TE/BE User Bus Operation (BYTE

Operation CE

OE WE

A0A1A6A9DQ0 to DQ

-1

Auto-Select Manufacture Code (1) L L H L L L L V Auto-Select Device Code (1) L L H L H L L V Read (3) L L H A

A0A1A6A

-1

= VIL)

RESET

Code H Code H

OUT

H Standby H X X X X X X X HIGH-Z H Output Disable L H H X X X X X HIGH-Z H Write (Program/Erase) L H L A Enable Sector Protection (2), (4) L V

Verify Sector Protection (2), (4) L L H L L H L V

A0A1A6A

-1

LLHLVIDXH

Temporary Sector Unprotection (5) X X X X X X X X X V

Code H

Reset (Hardware)/Standby X X X X X X X X HIGH-Z L

Legend:

L = V

, H = VIH, X = VIL or VIH. = Pulse input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 7.

2. Refer to the section on Sector Protection.

3. WE

4. V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

= 3.3 V ±10%

5. It is also used for the extended sector protection.

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MBM29LV160TE/BE

FLEXIBLE SECTOR-ERASE ARCHITECTURE

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• One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.

• One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user definable.

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 64 Kbytes or 32 Kwords 00000H to 0FFFFH 00000H to 07FFFH SA1 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH SA2 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH SA3 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH SA4 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH SA5 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH SA6 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH SA7 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH SA8 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH

SA9 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH SA10 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH SA11 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH SA12 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH SA13 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH SA14 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH SA15 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH SA16 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH SA17 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH SA18 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH SA19 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH SA20 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH SA21 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH SA22 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH SA23 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH SA24 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH SA25 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH SA26 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH SA27 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH SA28 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH SA29 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH SA30 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH SA31 32 Kbytes or 16 Kwords 1F0000H to 1F7FFFH F8000H to FBFFFH SA32 8 Kbytes or 4 Kwords 1F8000H to 1F9FFFH FC000H to FCFFFH SA33 8 Kbytes or 4 Kwords 1FA000H to 1FBFFFH FD000H to FDFFFH SA34 16 Kbytes or 8 Kwords 1FC000H to 1FFFFFH FE000H to FFFFFH

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MBM29LV160TE Top Boot Sector Architecture

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MBM29LV160TE/BE

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 16 Kbytes or 8 Kwords 00000H to 03FFFH 00000H to 01FFFH

SA1 8 Kbytes or 4 Kwords 04000H to 05FFFH 02000H to 02FFFH

SA2 8 Kbytes or 4 Kwords 06000H to 07FFFH 03000H to 03FFFH

SA3 32 Kbytes or 16 Kwords 08000H to 0FFFFH 04000H to 07FFFH

SA4 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH

SA5 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH

SA6 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH

SA7 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH

SA8 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH

SA9 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH SA10 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH SA11 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH SA12 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH SA13 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH SA14 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH SA15 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH SA16 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH SA17 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH SA18 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH SA19 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH SA20 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH SA21 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH SA22 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH SA23 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH SA24 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH SA25 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH SA26 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH SA27 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH SA28 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH SA29 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH SA30 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH SA31 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH SA32 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH SA33 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH SA34 64 Kbytes or 32 Kwords 1F0000H to 1FFFFFH F8000H to FFFFFH

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MBM29LV160BE Bottom Boot Sector Architecture

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FUNCTIONAL DESCRIPTION

■

MBM29LV160TE/BE

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•Read Mode

The MBM29L V160TE/BE has two control functions which m ust be satisfied in order to obtain data at the outputs. CE

is the power control and should be used for a de vice selection. OE is the output control and should be used

to gate data to the output pins if a device is selected. Address access time (t

access time (t

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE addresses have been stable for at least t after power-up, it is necessary to input hardware reset or to change CE

) is equal to the delay from stable addresses to valid output data. The chip enable

ACC

to valid data at the output pins. (Assuming the

- tOE time.) When reading out a data without changing addresses

ACC

pin from “H” or “L”.

• Standby Mode

There are two ways to implement the standb y mode on the MBM29LV160TE/BE devices. One is by using both the CE

When using both pins, a CMOS standby mode is achie v ed with CE Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, V Active current (I either of these standby modes.

and RESET pins; the other via the RESET pin only.

) is required even CE = “H”. The device can be read with standard access time (tCE) from

CC2

and RESET inputs both held at VCC ±0.3 V.

When using the RESET (CE

= “H” or “L”). Under this condition the current consumed is less than 5 µA max. Once the RESET pin is

taken high, the device requires t In the standby mode, the outputs are in the high-impedance state, independent of the OE

pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V

of wake up time before outputs are valid for read access.

input.

• Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV160TE/BE data. This mode can be used effectively with an application requesting low power consumption such as handy terminals.

To activate this mode, MBM29LV160TE/BE automatically switches itself to low power mode when addresses remain stable for 150 ns. It is not necessary to control CE

, WE, and OE in this mode. During such mode, the

current consumed is typically 1 µA (CMOS Level). Standard address access timings provide new data when addresses are changed. While in sleep mode, output

data is latched and always available to the system.

• Output Disable

If the OE input is at a logic high lev el (VIH), output from the device is disabled. This will cause the output pins to be in a high-impedance state.

• Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manu facturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command ma y also be used to check the status of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional ov er the entire temper ature range of the device.

To activate this mode, the programming equipment must force V

(11.5 V to 12.5 V) on address pin A9. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A addresses are DON’T CARES except A

, A1, and A6 (A-1). (See Table 2 or Table 3.)

from VIL to VIH. All

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MBM29LV160TE/BE

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The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV160TE/BE is erased or programmed in a system without access to high voltage on the A command sequence is illustrated in Table 7, Command Definitions.

Byte 0 (A

= VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code.

For the MBM29LV160TE/BE these two bytes are given in the Table 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ ex ecuting the Autoselect, A V

), DQ9 and DQ13 are equal to ‘1’ and DQ8, DQ10 to DQ12, DQ14, and DQ15 are equal to ‘0’.

If BYTE = V

= VIL (for byte mode), the de vice code is C4H (f or top boot block) or 49H (f or bottom boot bloc k). If BYTE

(for word mode), the device code is 22C4H (for top boot block) or 2249H (for bottom boot block).

must be VIL. (See Tables 2 or 3.) For device indentification in word mode (BYTE =

In order to determine which sectors are write protected, A addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ

defined as the parity bit. In order to read the proper device codes when

must be at VIH while running through the sector

(DQ0 =1).

Table 4.1 MBM29LV160TE/BE Sector Protection Verify Autoselect Code

Type A

to A

Manufacture’s Code X V

A-1*

pin. The

Code

(HEX)

04H

MBM29LV160TE

Byte

C4H

Word X 22C4H

Device Code

MBM29LV160BE

Byte

49H

Word X 2249H

Sector Protection

is for Byte mode.

*1: A

-1

Sector

Addresses

01H*

*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

Table 4.2 Expanded Autoselect Code Table

Type

Code DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

Manufacture’s Code 04H A-1/0000000000000100

(B) C4H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z11000100

MBM29LV160TE

Device Code

MBM29LV160BE

Sector Protection 01H A

(W)

22C4H0010001011000100 (B) 49H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z01001001 (W)

2249H 0 010001001001001

/0000000000000001

-1

(B): Byte mode (W): Word mode

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MBM29LV160TE/BE

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Table 5 Sector Address Tables (MBM29LV160TE)

Sector

Address

(× 8) Address Range (× 16) Address Range

SA0 00000XXX00000H to 0FFFFH 00000H to 07FFFH SA1 00001XXX10000H to 1FFFFH 08000H to 0FFFFH SA2 00010XXX20000H to 2FFFFH 10000H to 17FFFH SA3 00011XXX30000H to 3FFFFH 18000H to 1FFFFH SA4 00100XXX40000H to 4FFFFH 20000H to 27FFFH SA5 00101XXX50000H to 5FFFFH 28000H to 2FFFFH SA6 00110XXX60000H to 6FFFFH 30000H to 37FFFH SA7 00111XXX70000H to 7FFFFH 38000H to 3FFFFH SA8 01000XXX80000H to 8FFFFH 40000H to 47FFFH

SA9 01001XXX90000H to 9FFFFH 48000H to 4FFFFH SA1001010XXXA0000H to AFFFFH 50000H to 57FFFH SA1101011XXXB0000H to BFFFFH 58000H to 5FFFFH SA1201100XXXC0000H to CFFFFH 60000H to 67FFFH SA1301101XXXD0000H to DFFFFH 68000H to 6FFFFH SA1401110XXXE0000H to EFFFFH 70000H to 77FFFH SA1501111XXXF0000H to FFFFFH 78000H to 7FFFFH SA1610000XXX100000H to 10FFFFH 80000H to 87FFFH SA1710001XXX110000H to 11FFFFH 88000H to 8FFFFH SA1810010XXX120000H to 12FFFFH 90000H to 97FFFH SA1910011XXX130000H to 13FFFFH 98000H to 9FFFFH SA2010100XXX140000H to 14FFFFH A0000H to A7FFFH SA2110101XXX150000H to 15FFFFH A8000H to AFFFFH SA2210110XXX160000H to 16FFFFH B0000H to B7FFFH SA2310111XXX170000H to 17FFFFH B8000H to BFFFFH SA2411000XXX180000H to 18FFFFH C0000H to C7FFFH SA2511001XXX190000H to 19FFFFH C8000H to CFFFFH SA2611010XXX1A0000H to 1AFFFFH D0000H to D7FFFH SA2711011XXX1B0000H to 1BFFFFH D8000H to DFFFFH SA2811100XXX1C0000H to 1CFFFFH E0000H to E7FFFH SA2911101XXX1D0000H to 1DFFFFH E8000H to EFFFFH SA3011110XXX1E0000H to 1EFFFFH F0000H to F7FFFH SA31111110XX1F0000H to 1F7FFFHF8000H to FBFFFH SA32111111001F8000H to 1F9FFFHFC000H to FCFFFH SA33111111011FA000H to 1FBFFFHFD000H to FDFFFH SA341111111X1FC000H to 1FFFFFH FE000H to FEFFFH

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MBM29LV160TE/BE

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Table 6 Sector Address Tables (MBM29LV160BE)

Sector

Address

(× 8) Address Range (× 16) Address Range

SA0 0000000X00000H to 03FFFH 00000H to 01FFFH

SA1 0000001004000H to 05FFFH 02000H to 02FFFH

SA2 0000001106000H to 07FFFH 03000H to 03FFFH

SA3 0000010X08000H to 0FFFFH 04000H to 07FFFH

SA4 00001XXX10000H to 1FFFFH 08000H to 0FFFFH

SA5 00010XXX20000H to 2FFFFH 10000H to 17FFFH

SA6 00011XXX30000H to 3FFFFH 18000H to 1FFFFH

SA7 00100XXX40000H to 4FFFFH 20000H to 27FFFH

SA8 00101XXX50000H to 5FFFFH 28000H to 2FFFFH

SA9 00110XXX60000H to 6FFFFH 30000H to 37FFFH SA1000111XXX70000H to 7FFFFH 38000H to 3FFFFH SA1101000XXX80000H to 8FFFFH 40000H to 47FFFH SA1201001XXX90000H to 9FFFFH 48000H to 4FFFFH SA1301010XXXA0000H to AFFFFH 50000H to 57FFFH SA1401011XXXB0000H to BFFFFH 58000H to 5FFFFH SA1501100XXXC0000H to CFFFFH 60000H to 67FFFH SA1601101XXXD0000H to DFFFFH 68000H to 6FFFFH SA1701110XXXE0000H to EFFFFH 70000H to 77FFFH SA1801111XXXF0000H to FFFFFH 78000H to 7FFFFH SA1910000XXX100000H to 1FFFFFH 80000H to 87FFFH SA2010001XXX110000H to 11FFFFH 88000H to 8FFFFH SA2110010XXX120000H to 12FFFFH 90000H to 97FFFH SA2210011XXX130000H to 13FFFFH 98000H to 9FFFFH SA2310100XXX140000H to 14FFFFH A0000H to A7FFFH SA2410101XXX150000H to 15FFFFH A8000H to 8FFFFH SA2510110XXX160000H to 16FFFFH B0000H to B7FFFH SA2610111XXX170000H to 17FFFFH B8000H to BFFFFH SA2711000XXX180000H to 18FFFFH C0000H to C7FFFH SA2811001XXX190000H to 19FFFFH C8000H to CFFFFH SA2911010XXX1A0000H to 1AFFFFH D0000H to D7FFFH SA3011011XXX1B0000H to 1BFFFFH D8000H to DFFFFH SA3111100XXX1C0000H to 1CFFFFH E0000H to E7FFFH SA3211101XXX1D0000H to 1DFFFFH E8000H to EFFFFH SA3311110XXX1E0000H to 1EFFFFH F0000H to F7FFFH SA3411111XXX1F0000H to 1FFFFFH F8000H to FFFFFH

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MBM29LV160TE/BE

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•Write

Device erasure and progr amming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE the falling edge of WE

or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on

whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

• Sector Protection

The MBM29LV160TE/BE features hardware sector protection. This f eature will disable both prog ram and erase operations in any number of sectors (0 through 34). The sector protection f eature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V V

, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to

the sector to be protected. Tables 5 and 6 define the sector address for each of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE with the rising edge of the same. Sector addresses must be held constant during the WE and 24 for sector protection waveforms and algorithm.

on address pin A9 and control pin OE, CE =

pulse and is terminated

pulse. See Figures 17

To verify programming of the protection circuitry, the programming equipment must force V with CE while (A

and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)

, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector . Otherwise the

device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A A

are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device

codes. A

requires to VIL in byte mode.

-1

on address pin A9

, A1, and

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. P erforming a read operation at the address location XX02H, where the higher order addresses pins (A A

, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See

, A18, A17, A16, A15,

Tables 4.1 and 4.2 for Autoselect codes.

• Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29LV160TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET (V

). During this mode, formerly protected sectors can be programmed or erased by selecting the sector

addresses. Once the V

is taken awa y from the RESET pin, all the previously protected sectors will be protected

again. (See Figures 18 and 25.)

pin to high voltage

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MBM29LV160TE/BE

Table 7 MBM29LV160TE/BE Standard Command Definitions

Command Sequence

Read/Reset

Autoselect

Program

Chip Erase

Bus

Write

Cycles

Req’d

Word

1 XXXH F0H — — — — — — — — — —

Byte

Word

Byte AAAH 555H AAAH

Word

Byte AAAH 555H AAAH

Word

Byte AAAH 555H AAAH

Word

Byte AAAH 555H AAAH AAAH 555H AAAH

First Bus

Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

555H

AAH

555H

AAH

555H

AAH

555H

AAH

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Second

Bus

Write Cycle

2AAH

55H

2AAH

55H

2AAH

55H

2AAH

55H

Third Bus

Write Cycle

555H

F0H RA RD — — — —

555H

90H——————

555H

A0H PA PD — — — —

555H

80H

Fourth Bus Read/Write

Cycle

555H

AAH

Fifth Bus

Write Cycle

2AAH

55H

Sixth Bus

Write Cycle

555H

10H

Sector Erase

Erase Suspend 1 XXXH B0H — — — — — — — — — — Erase Resume 1 XXXH 30H — — — — — — — — — —

Set to Fast Mode

Fast Program *1

Reset from Fast Mode *1

Extended Sector Protection *2

Query *3

Word

Byte AAAH 555H AAAH AAAH 555H

Word

Byte AAAH 555H AAAH

Word

Byte XXXH

Word

Byte XXXH XXXH

Word

Byte

Word

Byte AAH

555H

XXXH

4 XXXH 60H SPA 60H SPA 40H SPA SD — — — —

55H

2AAH

AAH

2AAH

AAH

A0HPAPD————————

XXXH *4

90H

98H——————————

55H

F0H

555H

————————

555H

80H

20H——————

AAH

2AAH

55H SA 30H

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Notes: 1. Address bits A

Sector Address (SA).

2. Bus operations are defined in Tables 2 and 3.

3. RA =Address of the memory location to be read. PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE

SA =Address of the sector to be erased. The combination of A

uniquely select any sector.

4. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. Data is latched on the rising edge of WE

5. SPA=Sector address to be protected. Set sector address (SA) and (A SD =Sector protection verify data. Output 01H at protected sector addressed and output 00H at

unprotected sector addresses.

6. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A Byte Mode: AAAH or 555H to addresses A-1 to A

7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

MBM29LV160TE/BE

to A19 = X = “H” or “L” for all address commands e xcept or Prog r am Address (PA) and

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pulse.

, A18, A17, A16, A15, A14, A13, and A12 will

, A1, A0) = (0, 1, 0).

to A

10 10

*1:This command is valid while Fast Mode. *2: This command is valid while RESET *3: The valid addresses are A

to A0. The other addresses are “Don’t care”.

= VID.

*4: The data “00H” is also acceptable.

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MBM29LV160TE/BE

COMMAND DEFINITIONS

■

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in prog ress . Moreo v er both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ

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to DQ7 and DQ8 to DQ15 bits are ignored.

• Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register . Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered.

The device will automatically power-up in the Read/Reset state . In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. (See Figure 5.1.)

• Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufactures and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the last command write, a read cycle from address XX00H retrie v es the manufacture code of 04H. A read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the de vice code (MBM29LV160TE = C4H and MBM29LV160BE = 49H for ×8 mode; MBM29LV160TE = 22C4H and MBM29LV160BE = 2249H for ×16 mode). (See Tables 4.1 and 4.2.)

All manufactures and device codes will exhibit odd parity with DQ The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8). Scanning the sector addresses (A a logical “1” at device output DQ mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and, also to write the Autoselect command during the operation, by e xecuting it after writing the Read/Reset command sequence.

, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

for a protected sector . The programming v erification should be perform margin

to a high voltage. However, multiplexing high

defined as the parity bit.

• Byte/Word Programming

The device is programmed on a b yte-by-byte (or word-by-word) basis . Programming is a four bus cycle operation. There are two “unlock” write cycles. These are f ollowed b y the program set-up command and data write cycles . Addresses are latched on the falling edge of CE rising edge of CE first) begins programming. Upon ex ecuting the Embedded Progr am Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

or WE, whichev er happens later and the data is latched on the

The automatic programming operation is completed when the data on DQ bit at which time the device return to the read mode and addresses are no longer latched. (See T ab le 8, Hardware

is equivalent to data written to this

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MBM29LV160TE/BE

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Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time. Hence, Data

Polling must be performed at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so ma y either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.

Figure 20 illustrates the Embedded Program

Algorithm using typical command strings and bus operations.

•Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase Algorithm command sequence the device will automatically program and v erify the entire memory for an all zero data pattern prior to electrical erase . (Preprogram Function.) The system is not required to provide an y controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE when the data on DQ

is “1” (See Write Operation Status section.) at which time the device returns to read mode.

pulse in the command sequence and terminates

(See Figure 8.) Figure 21 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

• Sector Erase

Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE = 30H) is latched on the rising edge of WE

. After a time-out of “t

” from the rising edge of the last sector erase

TOW

command, the sector erase operation will begin. Multiple sectors may be erased concurrently b y writing six-bus cycle operations on Table 7. This sequence is

followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “t

” otherwise that command will not be accepted and

TOW

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t from the rising edge of the last WE edge of the WE

occurs within the “t

erase timer window is still open. (See section DQ

will initiate the ex ecution of the Sector Erase command(s). If another falling

” time-out window the timer is reset. Monitor DQ3 to determine if the sector

TOW

, Sector Erase Timer .) Any command other than Sector Erase

or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section f or Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34).

, while the command (Data

TOW

”

Sector erase does not require the user to program the de vice prior to erase. The device automatically prog rams all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y controls or timings during these operations.

The automatic sector erase begins after the “t sector erase command pulse and terminates when the data on DQ at which time the device returns to the read mode. Data

” time out from the rising edge of the WE pulse for the last

TOW

is “1” (See Write Operation Status section)

polling must be performed at an address within any of

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MBM29LV160TE/BE

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the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogr amming) + Sector Erase Time] × Number of Sector Erase.

Figure 21 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

• Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perf orm data reads from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Er ase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maxim um of “t

” to suspend the erase operation. When the devices have entered the erase-suspended mode, the

SPD

RY/BY

output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ writes of the Erase Suspend command are ignored.

and DQ7 to determine if the erase operation has been suspended. Further

When the erase operation has been suspended, the device def aults to the erase-suspend-read mode . Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successiv ely reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ

to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Progr am mode e xcept that the data must be programmed to sectors that are not erase-suspended. Successively reading from the er ase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ suspended Program operation is detected by the RY/BY which is the same as the regular Program operation. Note that DQ while DQ

can be read from any address.

output pin, Data polling of DQ7, or the Toggle Bit (DQ6)

to toggle. The end of the erase-

must be read from the Program address

To resume the operation of Sector Erase , the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

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MBM29LV160TE/BE

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• Extended Command

(1) Fast Mode

MBM29L V160TE/BE has F ast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register . In this mode, the required bus cycle f or progr amming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also ex ecuted after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 26 Extended algorithm.) The V Mode.

(2) Fast Programming

During Fast Mode, the prog ramming can be executed with two b us cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to the Figure 26 Extended algorithm.)

(3) Extended Sector Protection

In addition to normal sector protection, the MBM29L V160TE/BE has Extended Sector Protection as extended function. This function enable to protect sector by f orcing V Unlike conventional procedure, it is not necessary to force V RESET

pin requires VID for sector protection in this mode. The e xtended sector protect requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command register. Then, the sector addresses pins (A

, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0)

should be set to the sector to be protected (recommend to set V extended sector protect command (60H). A sector is typically protected in 250 µs. To verify programming of the protection circuitry, the sector addresses pins (A (0, 1, 0) should be set and write a command (40H). Following the command write, a logical “1” at device output DQ

will produce for protected sector in the read operation. If the output data is logical “0”, please

repeat to write extended sector protect command (60H) again. To terminate the operation, it is necessary to set RESET

pin to VIH.

active current is required even CE = VIH during Fast

on RESET pin and write a commnad sequence.

and control timing for control pins. The only

for the other addresses pins), and write

, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) =

(4) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98H) into the command register. Following the command write, a read cycle from specific address retrives device inf ormation. Please note that output data of upper byte (DQ

to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate

operation, it is necessary to write the read/reset command sequence into the register.

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MBM29LV160TE/BE

• Write Operation Status

Table 8 Hardware Sequence Flags

Status DQ

Embedded Program Algorithm DQ Embedded/Erase Algorithm 0 Toggle 0 1 Toggle

In Progress

Exceeded Time Limits

Erase Suspend Mode

Embedded Program Algorithm DQ Embedded/Erase Algorithm 0 Toggle 1 1 N/A Erase Suspend Program

(Non-Erase Suspended Sector)

Erase Suspend Read (Erase Suspended Sector)

Erase Suspend Read (Non-Erase Suspended Sector)

Erase Suspend Program (Non-Erase Suspended Sector)

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Toggle 0 0 1

1 1 0 0 Toggle

Data Data Data Data Data

Toggle

(Note 1)

Toggle 1 0 1

Toggle 1 0 N/A

(Note 2)

Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ2 to

toggle.

3. DQ

4. DQ

•DQ

and DQ1 are reserve pins for future use.

is Fujitsu internal use only.

Data Polling

The MBM29LV160TE/BE device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce the complement of the data last written to DQ Algorithm, an attempt to read the device will produce the true data last written to DQ Erase Algorithm, an attempt to read the device will produce a “0” at the DQ Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ for Data

For chip erase and sector erase , Data pulse sequence. Data

Polling (DQ7) is shown in Figure 22.

Polling is v alid after the rising edge of the sixth WE pulse in the six-write

Polling m ust be performed at a sector address within any of the sectors being erased and not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29L V160TE/BE data pins (DQ enable (OE

) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’ s v alid data at the next instant of time . Depending on when the system samples the DQ output, it may read the status or valid data. Ev en if the de vice has completed the Embedded Program Algorithm operation and DQ to DQ

will be read on successive read attempts.

has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0

. Upon completion of the Embedded Program

. During the Embedded

output. Upon completion of the

output. The flowchart

) may change asynchronously while the output

The Data

Polling f eature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out. See Figure 9 for the Data

Polling timing specifications and diagram.

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•DQ

MBM29LV160TE/BE

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Toggle Bit I

The MBM29LV160TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE the device will result in DQ cycle is completed, DQ programming, the T oggle Bit I is v alid after the rising edge of the fourth WE

toggling between one and zero . Once the Embedded Program or Erase Algorithm

will stop toggling and valid data can be read on the next successive attempts. During

pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 200 µs and then drop back into read mode, having changed none of the data.

Either CE cause the DQ

or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

to toggle.

See Figure 10 and Figure 23 for the Toggle Bit I timing specifications and diagram.

toggling) data from

pulse in the six-

•DQ

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ cycle was not successfully completed. Data condition. The CE

will produce a “1”. This is a failure condition which indicates that the program or erase

Polling is the only operating function of the device under this

circuit will partially power down the device under these conditions. The OE and WE pins will

control the output disable functions as described in Tables 2 and 3. The DQ

failure condition ma y also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ

and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device f ailure condition since the device was incorrectly used. If this occurs, reset the device with command sequence.

•DQ

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data command sequence.

If Data

Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ

prior to and following each subsequent sector erase command. If DQ3 is high on the

second status check, the command may not have been accepted.

Polling and Toggle Bit I are valid after the initial sector erase

is high (“1”) the internally controlled

Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept

See Table 8: Hardware Sequence Flags.

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MBM29LV160TE/BE

•DQ

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Toggle Bit II

This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ device is in the erase-suspended-read mode, successiv e reads from the erase-suspended sector will cause DQ to toggle. When the device is in the erase-suspended-prog r am mode , successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at DQ

is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. For example, DQ

(DQ

toggles while DQ6 does not.) See also Table 9 and Figure 11.

Furthermore, DQ mode, DQ

toggles if this bit is read from an erasing sector.

and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

can also be used to determine which sector is being erased. When the device is in the erase

Table 9 Toggle Bit Status

Mode DQ

Program DQ

Erase 0 Toggle Toggle

to toggle during the Embedded Erase Algorithm. If the

Toggle 1

Erase Suspend Read (Erase Suspended Sector)

11Toggle

(Note 1) Erase-Suspend Program DQ

Notes: 1. Performing successive read operations from any address will cause DQ

Toggle (Note 1) 1 (Note 2)

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ2 to

toggle.

•RY/BY

Ready/Busy Pin

The MBM29LV160TE/BE provides a R Y/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low , the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY commands with the exception of the Erase Suspend command. If the MBM29LV160TE/BE is placed in an Erase Suspend mode, the RY/BY

output will be high, by means of connecting with a pull-up resister to VCC.

During programming, the R Y/BY operation, the R Y/BY

pin is driven low after the rising edge of the sixth WE pulse. The R Y/BY pin will indicate a busy condition during the RESET is pulled high in standby mode.

pin is low, the devices will not accept any additional program or erase

pin is driven low after the rising edge of the fourth WE pulse. During an erase

pulse. See Figures 12 and 13 for a detailed timing diagram. The RY/BY pin

Since this is an open-drain output, RY/BY

pins can be tied together in parallel with a pull-up resistor to VCC.

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MBM29LV160TE/BE

-70/90/12

• RESET

Hardware Reset Pin

The MBM29LV160TE/BE device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (V

) for at least “tRP” in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “t device requires an additional “t

” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

READY

” before it allows read access. When the RESET pin is low, the device will be

in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY

output signal should be ignored during the RESET pulse. Refer to Figure 13 f or the timing

diagram. Refer to Temporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will

need to be erased again before they can be programmed.

• Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160TE/BE device. When this pin is driven high, the device operates in the w ord (16-bit) mode. The data is read and prog rammed at DQ to DQ becomes the lowest address bit and DQ an 8-bit operation and hence commands are written at DQ Figures 14, 15 and 16 for the timing diagram.

. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin

to DQ14 bits are tri-stated. Howev er , the command b us cycle is alwa ys

to DQ7 and DQ8 to DQ15 bits are ignored. Refer to

• Data Protection

The MBM29LV160TE/BE is designed to offer protection against accidental erasure or programming caused b y spurious system level signals that ma y e xist during power transitions . During power up the de vice automatically resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadvertent write cycles resulting form V

power-up

and power-down transitions or system noise.

•Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-do wn, a write cycle is locked out for VCC less than V

(min.). If VCC < V

LKO

, the command register is disabled and all internal program/erase circuits are

LKO

disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the V to prevent unintentional writes when V

level is g reater than V

. It is the users responsibility to ensure that the control pins are logically correct

LKO

is above V

LKO

(min.).

If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming.

• Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.

• Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE

is a logical one.

• Power-up Write Inhibit

Po wer-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up.

To Top / Lineup / Index

MBM29LV160TE/BE

Table 10 Common Flash Memory Interface Code

Description A

Query-unique ASCII string “QRY”

Primary OEM Command Set 2h: AMD/FJ standard type

Address for Primary Extended Table

Alternate OEM Command Set (00h = not applicable)

Address for Alternate OEM Extended Table

Min. (write/erase)

D7-4: volt, D3-0: 100 mvolt V

Max. (write/erase)

D7-4: volt, D3-0: 100 mvolt V

Min. voltage 1Dh 0000h

Max. voltage 1Eh 0000h

Typical timeout per single byte/word write 2

µS

Typical timeout for Min. size buffer write 2

µS

T ypical timeout per individual block erase 2

Typical timeout for full chip erase 2

Max. timeout for byte/word

write 2

times typical

Max. timeout for buffer write

times typical

Max. timeout per individual block erase 2

times typical

Max. timeout for full chip erase 2

Device Size = 2

times typical

byte

Flash Device Interface description

Max. number of byte in multi-byte write = 2

Number of Erase Block Regions within device

to A

10h 11h 12h

13h 14h

15h 16h

17h 18h

19h 1Ah

1Bh 0027h

1Ch 0036h

1Fh 0004h

20h 0000h

21h 000Ah

22h 0000h

23h 0005h

24h 0000h

25h 0004h

26h 0000h

27h 0015h 28h

29h 2Ah

2Bh 2Ch 0004h

-70/90/12

DQ0 to DQ

0051h 0052h 0059h

0002h 0000h

0040h 0000h

0000h 0000h

0002h 0000h

0000h 0000h

Description A0 to A

Erase Block Region 1 Information

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

Query-unique ASCII string “PRI”

2Dh 2Eh 2Fh

30h 31h

32h 33h 34h

35h 36h 37h 38h

39h 3Ah 3Bh 3Ch

40h

41h

42h

DQ0 to DQ

0000h 0000h 0040h 0000h

0001h 0000h 0020h 0000h

0000h 0000h 0080h 0000h

001Eh 0000h 0000h 0001h

0050h 0052h

0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0031h Address Sensitive Unlock

45h 0000h 0 = Required 1 = Not Required

Erase Suspend

46h 0002h 0 = Not Supported 1 = To Read Only 2 = To Read & Write

Sector Protect

47h 0001h 0 = Not Supported X = Number of sectors in per group

Sector Temporary Unprotect

48h 0001h 00 = Not Supported 01 = Supported

Sector Protection Algorithm 49h 04h Number of Sector for Bank 2

4Ah 00h

00h = Not Supported Burst Mode Ty pe

4Bh 00h

00h = Not Supported Page Mode Type

4Ch 00h

00h = Not Supported

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ABSOLUTE MAXIMUM RATINGS

■

MBM29LV160TE/BE

-70/90/12

Rating

Parameter Symbol Conditions

Unit

Min. Max.

Storage Temperature Tstg Ambient Temperature with

Power Applied

 

–55 +125 °C –40 +85 °C

Voltage with Respect to Ground All pins except A OE

, RESET (Note 1)

Power Supply Voltage (Note 1)

, OE, and RESET

(Note 2)

, V

OUT



–0.5 V

–0.5 +5.5 V

–0.5 +13.0 V

+0.5 V

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative

overshoot V +0.5 V. During voltage tr ansitions,outputs may positiv e overshoot to V

2. Minimum DC input voltage on A and RESET pins may negative overshoot V voltage on A up to 20 ns. Voltage difference between input voltage and supply voltage (V

to –2.0 V for periods of up to 20 ns. Maximum DC v oltage on output and l/O pins are VCC

+2.0 V for periods of up to 20 ns.

, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE,

to –2.0 V for periods of up to 20 ns. Maximum DC input

, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of

– VCC) do not exceed 9 V.

RECOMMENDED OPERATING CONDITIONS

■

Value

Parameter Symbol Conditions

Unit

Min. Typ. Max.

Ambient Temperature T

Power Supply Voltage V

MBM29LV160TE/BE-70 –20

MBM29LV160TE/BE-90/12 –40 MBM29LV160TE/BE-70 +3.0

MBM29LV160TE/BE-90/12 +2.7

   

+70 °C

+85 °C +3.6 V +3.6 V

Operating ranges define those limits between which the functionality of the device is quaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

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MBM29LV160TE/BE

MAXIMUM OVERSHOOT

■

+0.6 V –0.5 V –2.0 V

Figure 1 Maximum Negative Overshoot Waveform

-70/90/12

20 ns

VCC +2.0 V

+0.5 V

+2.0 V

+14.0 V

+13.0 V

VCC +0.5 V

Note:

Figure 2 Maximum Positive Overshoot Waveform 1

This waveform is applied for A

20 ns

, OE, and RESET.

20 ns

Figure 3 Maximum Positive Overshoot Waveform 2

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ELECTRICAL CHARACTERISTICS

■

1. DC Characteristics

Parameter

Symbol

LIT

CC1

CC2

CC3

Parameter Description Test Conditions Min. Max. Unit

Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA Output Leakage Current V A9, OE, RESET Inputs Leakage

Current

VCC Active Current (Note 1)

VCC Active Current (Note 2) CE = VIL, OE = V VCC Current (Standby)

MBM29LV160TE/BE

= VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA

OUT

VCC = VCC Max., A

, OE, RESET = 12.5 V

= VIL, OE = V

f = 10 MHz

= VIL, OE = V

f = 5 MHz

= VCC Max., CE = V

RESET

= V

0.3 V

Byte Word 35 Byte Word 17

0.3 V,

—35µA

—

—35mA —5µA

-70/90/12

= VCC Max.,

CC4

CC5

VCC Current (Standby, RESET)

VCC Current (Automatic Sleep Mode) (Note 3)

Input Low Level — –0.5 0.6 V Input High Level — 2.0 V

RESET = V V

= VCC Max., CE = V

RESET

= V

0.3 V or V

0.3 V

0.3 V,

0.3 V

0.3 V,

—5µA

+ 0.3 V

Voltage for Autoselect,Sector

OH1

Protection, and Temporary Sector Unprotection (A

, OE, RESET) (Note 4)

Output Low Voltage Level IOL = 4.0 mA, VCC = VCC Min. — 0.45 V

= –2.0 mA, VCC = VCC Min. 2.4 — V

—11.512.5V

Output High Voltage Level

OH2

LKO

Low VCC Lock-Out Voltage — 2.3 2.5 V

IOH = –100 µA V

– 0.4 — V

Notes: 1. The lCC current listed includes both the DC operating current and the frequency dependent component.

2. l

active while Embedded Erase or Embedded Progr a m is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. (V

– VCC) do not exceed 9 V.

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MBM29LV160TE/BE

2. AC Characteristics

• Read Only Operations Characteristics

Parameter

Symbols

JEDEC Standard

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

ACC

Read Cycle Time — Min. 70 90 120 ns

Address to Output Delay

Chip Enable to Output Delay OE = VILMax. 70 90 120 ns Output Enable to Output Delay — Max. 30 35 50 ns Chip Enable to Output HIGH-Z — Max. 25 30 30 ns Output Enable to Output HIGH-Z — Max. 25 30 30 ns Output Hold Time From Address,

CE or OE, Whichever Occurs First

Description Test Setup

-70/90/12

(Note)90(Note)12(Note)

= V

OE = V

Max. 70 90 120 ns

—Min.0 0 0 ns

Unit

—t

—

READY

ELFL

ELFH

Note : Test Conditions:

Output Load:1 TTL gate and 30 pF (MBM29LV160TD/BD-70)

1 TTL gate and 100 pF (MBM29LV160TD/BD-90/12) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level

Input: 1.5 V Output:1.5 V

RESET Pin Low to Read Mode — Max. 20 20 20

CE or BYTE Switching Low or High — Max. 5 5 5 ns

3.3 V

Device

Under

Test

IN3064 or Equivalent

6.2 k

Ω

2.7 k

Ω

Diodes = IN3064 or Equivalent

Figure 4 Test Conditions

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• Write (Erase/Program) Operations

Parameter Symbols

JEDEC Standard

AVAV

AVWL

WLAX

DVWH

WHDX

—t

GHWL

t t t t

OES

OEH

GHWL

Write Cycle Time Min. 70 90 120 ns Address Setup Time Min. 0 0 0 ns Address Hold Time Min. 45 45 50 ns Data Setup Time Min. 35 45 50 ns Data Hold Time Min. 0 0 0 ns Output Enable Setup Time Min. 0 0 0 ns

Output Enable Hold Time

Read Recover Time Before Write Min. 0 0 0 ns

Description

MBM29LV160TE/BE

(Note1)90(Note2)12(Note2)

-70/90/12

Unit

Read Min. 0 0 0 ns Toggle and Data

Polling Min. 10 10 10 ns

GHEL

ELWL

WLEL

WHEH

EHWH

WLWH

ELEH

WHWL

EHEL

WHWH1

WHWH2

—t —t —t

GHEL

WPH

CPH

WHWH1

WHWH2

VCS

VIDR

VLHT

Read Recover Time Before Write (OE High to CE Low)

Min. 0 0 0 ns

CE Setup Time Min. 0 0 0 ns WE Setup Time Min. 0 0 0 ns CE Hold Time Min. 0 0 0 ns WE Hold Time Min. 0 0 0 ns Write Pulse Width Min. 35 45 50 ns CE Pulse Width Min. 35 45 50 ns Write Pulse Width High Min. 25 25 30 ns CE Pulse Width High Min. 25 25 30 ns

Programming Operation

Byte

Typ.

888

µs

Word 16 16 16 Sector Erase Operation (Note 1) Typ. 1 1 1 sec VCC Setup Time Min. 50 50 50 µs Rise Time to VID (Note 2) Min. 500 500 500 ns Voltage Transition Time (Note 2) Min. 4 4 4 µs

—t —t —t —t

WPP

OESP

CSP

Write Pulse Width (Note 2) Min. 100 100 100 µs OE Setup Time to WE Active (Note 2) Min. 4 4 4 µs CE Setup Time to WE Active (Note 2) Min. 4 4 4 µs Recover Time From RY/BY Min. 0 0 0 ns

(Continued)

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MBM29LV160TE/BE

-70/90/12

(Continued)

Parameter Symbols

Description

JEDEC Standard

—t —t —t —t —t —t —t —t

BUSY

EOE

FLQZ

FHQV

TOW

SPD

RESET Pulse Width Min. 500 500 500 ns RESET High Level Period Before Read Min. 200 200 200 ns Program/Erase Valid to RY/BY Delay Max.909090ns Delay Time from Embedded Output Enable Max. 70 90 120 ns BYTE Switching Low to Output HIGH-Z Max. 30 35 50 ns BYTE Switching High to Output Active Min. 30 35 50 ns Erase Time-out Time Min. 50 50 50 µs Erase Suspend Transition Time Max. 20 20 20 µs

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Protection operation.

(Note1)90(Note2)12(Note2)

Unit

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MBM29LV160TE/BE

ERASE AND PROGRAMMING PERFORMANCE

■

Parameter

Sector Erase Time — 1 10 sec

Byte Programming Time — 8 300 Word Programming Time — 16 360

Chip Programming Time — 16.8 50 sec

Erase/Program Cycle 1,000,000 — — cycles —

PIN CAPACITANCE

■

Parameter Symbol Test Setup Typ. Max. Unit

Min. Typ. Max.

Limits

Unit Comments

Excludes programming time prior to erasure

µs

Excludes system-level overhead

-70/90/12

Input Capacitance C Output Capacitance C Control Pin Capacitance C

Note: Test conditions TA = 25°C, f = 1.0 MHz

OUT

IN2

VIN = 0 6 7.5 pF V

= 0 8 10 pF

OUT

VIN = 0 7.5 9 pF

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MBM29LV160TE/BE

TIMING DIAGRAM

■

• Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

-70/90/12

Must Be Steady

May Change from H to L

May Change from L to H

“H” or “L”: Any Change Permitted

Will Be Steady

Will Be Change from H to L

Will Be Change from L to H

Changing, State Unknown

Addresses

OEH

Does Not Apply

Addresses Stable

ACC

Center Line is HighImpedance “Off” State

Outputs

HIGH-Z

Output Valid

Figure 5.1 Read Operation Timing Diagram

HIGH-Z

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Addresses

RESET

tACC

tRH

tRP tRH tCE

MBM29LV160TE/BE

t RC

Addresses Stable

tOH

-70/90/12

Outputs

High-Z

Output Valid

Figure 5.2 Hardware Reset/Read Operation Timing Diagram

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MBM29LV160TE/BE

Addresses

555H PA PA

GHWL

WPH

-70/90/12

Data Polling3rd Bus Cycle

WHWH1

OUT

Data

A0H

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ

4. D

is the output of the complement of the data written to the device.

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 6 Alternate WE

Controlled Program Operation Timing Diagram

OUT

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Addresses

GHEL

555H

MBM29LV160TE/BE

Data Polling3rd Bus Cycle

PA PA

CPH

WHWH1

-70/90/12

Data

A0H

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ

4. D

is the output of the complement of the data written to the device.

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 7 Alternate CE

Controlled Program Operation Timing Diagram

OUT

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MBM29LV160TE/BE

Addresses

GHWL

555H

-70/90/12

2AAH

AStAH

WPH

555H

2AAH

SA*

Data

AAH

VCS

55H 80H

AAH

30H for Sector Erase

55H

10H

* :1. SA is the sector address for Sector Erase. Addresses = 555H (W ord), AAAH (Byte) f or Chip

Erase.

2. These wavefor ms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 8 Chip/Sector Erase Operation Timing Diagram

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DQ7

Data

tCH

tOEH

tOE

tCE

tWHWH1 or 2

MBM29LV160TE/BE

tDF

DQ7

DQ7 =

Valid Data

High-Z

-70/90/12

tEOEtBUSY

DQ0 to DQ6

Valid Data

DQ0 to DQ6

RY/BY

Data

0 to DQ6 = Output Flag

* :DQ7 = Valid Data (The device has completed the Embedded operation).

Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram

High-Z

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MBM29LV160TE/BE

OEH

OES

* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)

Data (DQ0 to DQ7)

-70/90/12

= Toggle

DQ6 = Toggle

Stop Toggling

to DQ

Data Valid

Figure 10 Taggle Bit I during Embedded Algorithm Operation Timing Diagram

Enter

Embedded

Erasing

Erase

Toggle

and DQ6

with OE

Erase

Suspend

Suspend Program

Erase Suspend

Read

Note: DQ2 is read from the erase-suspended sector.

Enter Erase

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase Erase

Complete

Figure 11 DQ2 vs. DQ

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RY/BY

MBM29LV160TE/BE

The rising edge of the last WE signal

Entire programming or erase operations

BUSY

-70/90/12

Figure 12 RY/BY

RESET

RY/BY

Timing Diagram during Program/Erase Operation Timing Diagram

READY

Figure 13 RESET, RY/BY Timing Diagram

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MBM29LV160TE/BE

BYTE

DQ0 to DQ

DQ15/A

ELFH

-1

Figure 14 Timing Diagram for Word Mode Configuration

-70/90/12

Data Output

to DQ7)

(DQ

FHQV

-1

Data Output

(DQ0 to DQ14)

BYTE

DQ0 to DQ

DQ15/A

-1

ELFL

Data Output

to DQ14)

(DQ

FLQZ

ACC

Data Output

to DQ7)

(DQ

-1

Figure 15 Timing Diagram for Byte Mode Configuration

The falling edge of the last write signal

CE or WE

BYTE

SET

(tAS)

Input Valid

tHOLD

(tAH)

Figure 16 BYTE Timing Diagram for Write Operations

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19, A18, A17

A16, A15, A14

A13, A12

VID

3 V

tVLHT

SAX

MBM29LV160TE/BE

-70/90/12

SAY

VID 3 V

Data

tVLHT

tOESP

tCSP

tVCS

SAX : Sector Address for initial sector SAY : Sector Address for next sector Note: A

is VIL on byte mode.

-1

Figure 17 Sector Protection Timing Diagram

t VLHTtVLHT

tWPP

01H

tOE

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MBM29LV160TE/BE

VID

3 V

RESET

tVIDR

tVCS

tVLHT

-70/90/12

Program or Erase Command Sequence

tVLHT

3 V

tVLHT

RY/BY

Unprotection period

Figure 18 Temporary Sector Unprotection Timing Diagram

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VCC

RESET

Add SPAXSPAX

tVIDR

tVCS

tVLHT

tWC tWC

MBM29LV160TE/BE

-70/90/12

SPAY

Data

tWP

60H

SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 250 µs (min)

Figure 19 Extended Sector Protection Timing Diagram

TIME-OUT

40H

tOE

01H

60H

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MBM29LV160TE/BE

FLOW CHART

■

EMBEDDED ALGORITHM

-70/90/12

Write Program Command

Start

Sequence

(See Below)

Data

Polling Device

Verify Byte

Yes

Increment Address

Program Command Sequence* (Address/Command):

* :The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Last Address

Yes

Programming Completed

555H/AAH

2AAH/55H

555H/A0H

Program Address/Program Data

Figure 20 Embedded ProgramTM Algorithm

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EMBEDDED ALGORITHM

Start

Write Erase Command

Sequence

(See Below)

Data

Polling or Toggle Bit

from Device

Data = FFH

Erasure Completed

MBM29LV160TE/BE

Yes

-70/90/12

Chip Erase Command Sequence*

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

Individual Sector/Multiple Sector*

Erase Command Sequence

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

Additional sector erase commands are optional.

* :The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Figure 21 Embedded EraseTM Algorithm

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MBM29LV160TE/BE

-70/90/12

Start

Read Byte

(DQ

to DQ7)

Addr. = VA

DQ7 = Data?

DQ5 = 1?

Read Byte

(DQ

to DQ7)

Addr. = VA

Yes

VA =Address for programming

=Any of the sector addresses

within the sector being erased during sector erase or multiple erases operation.

=Any of the sector addresses

within the sector not being protected during sector erase or multiple sector erases operation.

DQ7 = Data?

Fail

Yes

Pass

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 22 Data Polling Algorithm

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Read

(DQ

Addr. = “H” or “L”

DQ6 = Toggle

DQ5 = 1?

Read Byte

(DQ

Addr. = “H” or “L”

MBM29LV160TE/BE

Start

to DQ7)

Yes

to DQ7)

-70/90/12

DQ6 = Toggle

? *

Fail

Yes

Pass

* : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as

changing to “1”.

Figure 23 Toggle Bit Algorithm

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MBM29LV160TE/BE

-70/90/12

Start

Setup Sector Addr.

(

, A17, A

19, A18

A15, A14, A13, A

PLSCNT = 1

= VID, A9 = V

16,

)

A6 = CE = VIL, RESET = V

A0 = VIL, A1 = V

Activate WE Pulse

Increment PLSCNT

Yes

Remove VID from A

Write Reset Command

Device Failed

Time out 100 µs

WE = VIH, CE = OE = V

(A9 should remain VID)

Read from Sector

( A

= VIH, A0 = VIL,

Addr. = SA, A

= VIL)*

Data = 01H?PLSCNT = 25?

Yes

Protect Another Sector?

Remove

VID from A

Write Reset Command

Sector Protection

Completed

* :A-1 is VIL on byte mode.

Figure 24 Sector Protection Algorithm

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MBM29LV160TE/BE

Start

RESET = V

(Note 1)

Perform Erase or

Program Operations

RESET = V

-70/90/12

Temporary Sector

Unprotection Completed

(Note 2)

Notes: 1. All protected sectors are unprotected.

2. All previously protected sectors are protected once again.

Figure 25 Temporary Sector Unprotection Algorithm

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MBM29LV160TE/BE

FAST MODE ALGORITHM

-70/90/12

Start

555H/AAH

2AAH/55H

555H/20H

XXXXH/A0H

Set Fast Mode *

Program Address/Program Data

Increment Address

* :The sequence is applied for ×16 mode. * :The addresses differ from ×8 mode.

Data Polling Device

Verify Byte?

Yes

Last Address

Yes

Programming Completed

XXXXH/90H

XXXXH/F0H

In Fast Program

Reset Fast Mode

Figure 26 Embedded Programming Algorithm for Fast Mode

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Device is Operating in

Temporary Sector Unprotect

Mode

MBM29LV160TE/BE

Start

RESET = V

Wait to 4 µs

Extended Sector

Protect Entry?

To Setup Sector Protect

Write XXXH/60H

PLSCNT = 1

To Sector Protect

Write 60H to Sector Address

(A0 = VIL, A1 = VIH, A6 = VIL)

Yes

-70/90/12

Increment PLSCNT

PLSCNT = 25?

Yes

Remove VID from RESET

Write Reset Command

Device Failed

Time out 250 µs

To Verify Sector Protect

Write 40H to Sector Address

= VIL, A1 = VIH, A6 = VIL)

Read from Sector Address

= VIL, A1 = VIH, A6 = VIL)

Data = 01H?

Protect Other Sector

Remove VID from RESET

Write Reset Command

Sector Protection

Completed

Setup Next Sector Address

Yes

Figure 27 Extended Sector Protection Algorithm

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MBM29LV160TE/BE

ORDERING INFORMATION

■

-70/90/12

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29LV160 T E 70 TN

PACKAGE TYPE TN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

TR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PCV = 48-Pin C- leaded Small Outline

Package (CSOP)

PBT = 48-Pin Fine Pitch Ball Grid Array

Package (FBGA)

SPEED OPTION See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector

DEVICE NUMBER/DESCRIPTION MBM29LV160 16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory

3.0 V-only Read, Write, and Erase

Valid Combinations

MBM29LV160TE/BE

70 90 12

TN TR

PCV

PBT

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.

To Top / Lineup / Index

PACKAGE DIMENSIONS

■

48-pin plastic TSOP (I)

(FPT-48P-M19)

LEAD No.

INDEX

20.00±0.20

(.787±.008)

18.40±0.20

(.724±.008)

MBM29LV160TE/BE

*: Resin protruction. (Each side: 0.15(.006) Max)

"A"

Details of "A" part

0.15(.006) 0.25(.010)

*12.00±0.20

(.472±.008)

11.50REF (.460)

0.15(.006) MAX

0.35(.014) MAX

-70/90/12

+0.10

−0.05

1.10

+.004

.043

−.002

0.05(0.02)MIN STAND OFF

0.10(.004)

0.15±0.05

(.006±.002)

0.50±0.10

0.50(.0197) TYP

0.20±0.10

(.008±.004)

Dimensions in mm (inches)

0.10(.004)

19.00±0.20

(.748±.008)

(.020±.004)

(Continued)

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MBM29LV160TE/BE

48-pin plastic TSOP (I)

(FPT-48P-M20)

LEAD No.

INDEX

19.00±0.20 (.748±.008)

0.10(.004)

-70/90/12

"A"

0.50±0.10

(.020±.004)

0.15±0.10

(.006±.002)

*: Resin protrusion. (Each side: 0.15(.006) Max)

Details of "A" part

0.15(.006) 0.25(.010)

0.50(.0197) TYP

0.15(.006)

0.20±0.10

(.008±.004)

MAX

0.35(.014) MAX

0.10(.004)

0.05(0.02)MIN STAND OFF

18.40±0.20

(.724±.008)

20.00±0.20

(.787±.008)

1996 FUJITSU LIMITED F48030S-2C-2

11.50(.460)REF

*12.00±0.20(.472±.008)

Dimensions in mm (inches)

+0.10

−0.05

1.10

+.004

−.002

.043

(Continued)

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48-pin plastic CSOP

(LCC-48P-M03)

INDEX

LEAD No.

1 24

10.00±0.10(.394±.004)

10.00±0.20 (.394±.008)

9.50±0.10

(.374±.004)

MBM29LV160TE/BE

"A"

INDEX

0.05 .002 –.0

(Stand off)

0.95±0.05(.037±.002) (Mounting height)

+0.05 –0

+.002

0.22±0.035 (.009±.001)

Details of "A" part

0°~10°

-70/90/12

0.40(.016) TYP

1998 FUJITSU LIMITED C48056S-1C-1

9.20(.362)REF

0.08(.003)

0.65(.026)

1.15(.045)

Dimensions in mm (inches)

(Continued)

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MBM29LV160TE/BE

(Continued)

48-pin plastic FBGA

(BGA-48P-M11)

8.00±0.20(.315±.008)

INDEX

C0.25(.010)

-70/90/12

6.00±0.20

(.236±.008)

Note: The actual shape of corners may differ from the dimension.

+.006

+0.15

.041 –.004

–0.10

1.05 (Mounting height)

0.38±0.10(.015±.004) (Stand off)

4.00(.157)

HGFEDCBA

5.60(.221)

0.80(.031)TYP

48-Ø0.45±0.10 (48-.018±.004)

Ø0.08(.003)

6 5 4 3 2 1

0.10(.004)

1998 FUJITSU LIMITED B480011S-1C-1

Dimensions in mm (inches)

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MBM29LV160TE/BE

-70/90/12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608 Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220

http://www.fmap.com.sg/

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F9909

FUJITSU LIMITED Printed in Japan



FUJITSU MBM29LV160TE, MBM29LV160BE DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

PRODUCT LINE UP

PACKAGES

GENERAL DESCRIPTION

PIN ASSIGNMENTS

BLOCK DIAGRAM

LOGIC SYMBOL

DEVICE BUS OPERATIONS

FLEXIBLE SECTOR-ERASE ARCHITECTURE

FUNCTIONAL DESCRIPTION

COMMAND DEFINITIONS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

MAXIMUM OVERSHOOT

ELECTRICAL CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE

PIN CAPACITANCE

TIMING DIAGRAM

FLOW CHART

ORDERING INFORMATION

PACKAGE DIMENSIONS