FUJITSU MBM29LV160TE, MBM29LV160BE DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

-

MBM29LV160TE/BE

FEATURES

■

• 0.23 µm Process Technology

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)

• Minimum 1,000,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector
B = Bottom sector

TM

• Embedded Erase

Automatically pre-programs and erases the chip or any sector

PRODUCT LINE UP

■

Algorithms

2

PROMs

70/90/12

DS05-20883-1E

(Continued)

Part No. MBM29LV160TE/160BE

V

= 3.3 V

CC

Ordering Part No.

V

= 3.0 V

CC

Max. Address Access Time (ns) 70 90 120
Max. CE
Max. OE

Access Time (ns) 70 90 120
Access Time (ns) 30 35 50

+0.3 V
–0.3 V

+0.6 V
–0.3 V

70 — —

—9012

Marking Side

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MBM29LV160TE/BE

(Continued)

• Embedded ProgramTM Algorithms

Automatically programs and verifies data at specified address

•Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

•Low V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection Set function by Extended sector Protection command

• Fast Programming Function by Extended command

• Temporary sector unprotection

Temporary sector unprotection via the RESET

• In accordance with CFI (C

write inhibit ≤ 2.5 V

CC

)

ommon Flash Memory Interface)

-70/90/12

pin

PACKAGES

■

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

48-pin plastic CSOP

48-pin plastic TSOP (I)

(FPT-48P-M20)

48-pin plastic FBGA

(LCC-48P-M03)

2

(BGA-48P-M11)

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MBM29LV160TE/BE

GENERAL DESCRIPTION

■

The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA
packages. The de vice is designed to be programmed in-system with the standard system 3.0 V V
V V

and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in

PP

standard EPROM programmers.
The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of high-

speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable
(CE

), write enable (WE), and output enable (OE) controls.

The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and er ase operations . Reading data out of the de vice is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before e xecuting the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.

2

PROMs. Commands are

-70/90/12

supply . 12.0

CC

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors . The MBM29L V160TE/BE is erased when shipped from the factory .
The device f eatures single 3.0 V power supply oper ation f or both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data
by the Toggle Bit feature on DQ
comleted, the device internally resets to the read mode.

The MBM29LV160TE/BE also has a hardware RESET
Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then
reset to the read mode. The RESET
occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically
reset to the read mode and will have erroneous data stored in the address locations being programmed or
erased. These locations need re-writing after the Reset. Resetting the device enables the system’s
microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are programmed one b yte/word
at a time using the EPROM programming mechanism of hot electron injection.

, or the RY/BY output pin. Once the end of a prog ram or er ase cycle has been

6

pin. When this pin is driven low, execution of any

pin may be tied to the system reset circuitry. Therefore, if a system reset

detector automatically

CC

Polling of DQ7,

3

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MBM29LV160TE/BE

PIN ASSIGNMENTS

■

1

15

A
A

14

2

A

13

3

A

12

4

A

11

5

A

10

6

A

9

7

A

8

8

A

19

WE

A
A

9
10
11
12
13
14
15

18

16

17

17

A

7

18

A

6

19

A

5

20

A

4

21

A

3

22

A

2

23

A

1

24

N.C.

RESET

N.C.
N.C.

RY/BY

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TSOP(I)

(Marking Side)

Standard Pinout

(FPT-48P-M19)

A

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

16

BYTE
V

SS

DQ15/A
DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

DQ

11

DQ

3

DQ

10

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

OE

SS

V
CE
A

0

-1

A
A

RY/BY

N.C.
N.C.

RESET

WE

N.C.

A

A
A
A
A
A
A

24

A

1

A

2

23

A

3

22

A

4

21

A

5

20

A

6

19

A

7

18

17

17

18

16
15
14
13
12
11
10

19

9

A

8

8

A

9

7

10

6

11

5

12

4

13

3

14

2

15

1

(Marking Side)

Reverse Pinout

A

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
45
45
46
47
48

0

CE

SS

V
OE
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

CC

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

SS

BYTE

16

A

0
8
1
9
2
10
3
11

4
12
5
13
6
14
7
15/A-1

(FPT-48P-M20)

(Continued)

4

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(Continued)

A17
A18

RY/BY

N.C.
N.C.

RESET

WE

N.C.

A

A10
A11
A12
A13
A14
A15

A
A2
A3
A4
A5
A6
A7

A8
A9

MBM29LV160TE/BE

CSOP

(TOP VIEW)

1

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

19

17
18
19
20
21
22
23
24

(Marking side)

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16

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A1 A
B1 A
C1 A
D1 A
E1 A

3

4

2

1

0

A2 A
B2 A
C2 A
D2 A

7

17

6

5

E2 DQ
F1 CE F2 DQ
G1 OE G2 DQ
H1 V

SS

H2 DQ

(LCC-48P-M03)

FBGA

(TOP VIEW)

Marking side

A6

A5

A4

A3

A2

A1

B6

B5

B4

B3

B2

B1

C6

C5

C4

C3

C2

C1

D6

D5

D4

D3

D2

D1

E6

E5

E4

E3

E2

E1

F6

F5

F4

F3

F2

F1

G6

G5

G4

G3

G2

G1

H6

H5

H4

H3

H2

H1

(BGA-48P-M11)

A3 RY/BY A4 WE A5 A
B3 N.C. B4 RESET B5 A
C3 A

18

D3 N.C. D4 A

0

8

9

1

E3 DQ
F3 DQ
G3 DQ
H3 DQ

2

10

11

3

C4 N.C. C5 A

19

E4 DQ
F4 DQ
G4 V

CC

H4 DQ

5

12

4

D5 A
E5 DQ
F5 DQ
G5 DQ
H5 DQ

9

8

10

11

7

14

13

6

A6 A
B6 A
C6 A
D6 A
E6 A

13

12

14

15

16

F6 BYTE
G6 DQ15/A
H6 V

SS

-1

5

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MBM29LV160TE/BE

BLOCK DIAGRAM

■

V

CC

V

SS

WE

BYTE

RESET

CE
OE

RY/BY
Buffer

State

Control

Command

Register

RY/BY

Program Voltage

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Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

DQ0 to DQ

Input/Output

Buffers

Data Latch

15

A0 to A

STB

Low V

Detector

CC

19

A

-1

Timer for

Program/Erase

Address

Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

6

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LOGIC SYMBOL

■

A-1

20

A0 to A19

CE
OE
WE
RESET
BYTE

DQ0 to DQ15

RY/BY

16 or 8

MBM29LV160TE/BE

Table 1 MBM29LV160TE/BE Pin Configuration

Pin Function

A

, A0 to A

-1

to DQ

DQ

0

CE

OE

WE

RY/BY

RESET

BYTE

N.C. Pin Not Connected Internally

Address Inputs

19

Data Inputs/Outputs

15

Chip Enable
Output Enable
Write Enable
Ready/Busy Output
Hardware Reset Pin/

Temporary Sector Unprotection
Selects 8-bit or 16-bit mode

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V

SS

V

CC

Device Ground
Device Power Supply

7

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MBM29LV160TE/BE

DEVICE BUS OPERATIONS

■

Table 2 MBM29LV160TE/BE User Bus Operation (BYTE

Operation CE

Auto-Select Manufacture Code (1) L L H L L L V
Auto-Select Device Code (1) L L H H L L V
Read (3) L L H A

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OE WE A

= VIH)

A

0

A

0

A

1

1

6

A

6

A

9

ID

ID

A

9

DQ0 to DQ

Code H
Code H

15

RESET

D

OUT

H
Standby HXXXXXXHIGH-Z H
Output Disable LHHXXXXHIGH-Z H
Write (Program/Erase) L H L A
Enable Sector Protection (2), (4) L V

ID

LHLVIDXH

A

0

Verify Sector Protection (2), (4) L L H L H L V
Temporary Sector Unprotection (5) X X X X X X X X V

A

1

A

6

9

ID

D

IN

Code H

H

ID

Reset (Hardware)/Standby XXXXXXXHIGH-Z L

Table 3 MBM29LV160TE/BE User Bus Operation (BYTE

DQ

Operation CE

OE WE

15

A0A1A6A9DQ0 to DQ

/A

-1

Auto-Select Manufacture Code (1) L L H L L L L V
Auto-Select Device Code (1) L L H L H L L V
Read (3) L L H A

A0A1A6A

-1

= VIL)

ID

ID

9

RESET

7

Code H
Code H

D

OUT

H
Standby H X X X X X X X HIGH-Z H
Output Disable L H H X X X X X HIGH-Z H
Write (Program/Erase) L H L A
Enable Sector Protection (2), (4) L V

ID

Verify Sector Protection (2), (4) L L H L L H L V

A0A1A6A

-1

9

LLHLVIDXH

ID

Temporary Sector Unprotection (5) X X X X X X X X X V

D

IN

Code H

H

ID

Reset (Hardware)/Standby X X X X X X X X HIGH-Z L

Legend:

L = V

, H = VIH, X = VIL or VIH. = Pulse input. See DC Characteristics for voltage levels.

IL

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 7.

2. Refer to the section on Sector Protection.

3. WE

4. V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

= 3.3 V ±10%

CC

5. It is also used for the extended sector protection.

8

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MBM29LV160TE/BE

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■

• One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.

• One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user definable.

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 64 Kbytes or 32 Kwords 00000H to 0FFFFH 00000H to 07FFFH
SA1 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH
SA2 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH
SA3 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH
SA4 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH
SA5 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH
SA6 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH
SA7 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH
SA8 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH

SA9 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH
SA10 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH
SA11 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH
SA12 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH
SA13 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH
SA14 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH
SA15 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH
SA16 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH
SA17 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH
SA18 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH
SA19 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH
SA20 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH
SA21 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH
SA22 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH
SA23 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH
SA24 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH
SA25 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH
SA26 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH
SA27 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH
SA28 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH
SA29 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH
SA30 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH
SA31 32 Kbytes or 16 Kwords 1F0000H to 1F7FFFH F8000H to FBFFFH
SA32 8 Kbytes or 4 Kwords 1F8000H to 1F9FFFH FC000H to FCFFFH
SA33 8 Kbytes or 4 Kwords 1FA000H to 1FBFFFH FD000H to FDFFFH
SA34 16 Kbytes or 8 Kwords 1FC000H to 1FFFFFH FE000H to FFFFFH

-70/90/12

MBM29LV160TE Top Boot Sector Architecture

9

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MBM29LV160TE/BE

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 16 Kbytes or 8 Kwords 00000H to 03FFFH 00000H to 01FFFH

SA1 8 Kbytes or 4 Kwords 04000H to 05FFFH 02000H to 02FFFH

SA2 8 Kbytes or 4 Kwords 06000H to 07FFFH 03000H to 03FFFH

SA3 32 Kbytes or 16 Kwords 08000H to 0FFFFH 04000H to 07FFFH

SA4 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH

SA5 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH

SA6 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH

SA7 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH

SA8 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH

SA9 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH
SA10 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH
SA11 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH
SA12 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH
SA13 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH
SA14 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH
SA15 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH
SA16 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH
SA17 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH
SA18 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH
SA19 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH
SA20 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH
SA21 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH
SA22 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH
SA23 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH
SA24 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH
SA25 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH
SA26 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH
SA27 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH
SA28 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH
SA29 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH
SA30 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH
SA31 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH
SA32 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH
SA33 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH
SA34 64 Kbytes or 32 Kwords 1F0000H to 1FFFFFH F8000H to FFFFFH

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10

MBM29LV160BE Bottom Boot Sector Architecture

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FUNCTIONAL DESCRIPTION

■

MBM29LV160TE/BE

-70/90/12

•Read Mode

The MBM29L V160TE/BE has two control functions which m ust be satisfied in order to obtain data at the outputs.
CE

is the power control and should be used for a de vice selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.
Address access time (t

access time (t

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

CE

enable access time is the delay from the falling edge of OE
addresses have been stable for at least t
after power-up, it is necessary to input hardware reset or to change CE

) is equal to the delay from stable addresses to valid output data. The chip enable

ACC

to valid data at the output pins. (Assuming the

- tOE time.) When reading out a data without changing addresses

ACC

pin from “H” or “L”.

• Standby Mode

There are two ways to implement the standb y mode on the MBM29LV160TE/BE devices. One is by using both
the CE

When using both pins, a CMOS standby mode is achie v ed with CE
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, V
Active current (I
either of these standby modes.

and RESET pins; the other via the RESET pin only.

) is required even CE = “H”. The device can be read with standard access time (tCE) from

CC2

and RESET inputs both held at VCC ±0.3 V.

CC

When using the RESET
(CE

= “H” or “L”). Under this condition the current consumed is less than 5 µA max. Once the RESET pin is

taken high, the device requires t
In the standby mode, the outputs are in the high-impedance state, independent of the OE

pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V

of wake up time before outputs are valid for read access.

RH

input.

• Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV160TE/BE data. This mode can be used effectively with an application requesting low power
consumption such as handy terminals.

To activate this mode, MBM29LV160TE/BE automatically switches itself to low power mode when addresses
remain stable for 150 ns. It is not necessary to control CE

, WE, and OE in this mode. During such mode, the

current consumed is typically 1 µA (CMOS Level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output

data is latched and always available to the system.

• Output Disable

If the OE input is at a logic high lev el (VIH), output from the device is disabled. This will cause the output pins to
be in a high-impedance state.

• Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manu facturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command ma y also be used to check the status
of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional ov er the entire temper ature range
of the device.

To activate this mode, the programming equipment must force V

(11.5 V to 12.5 V) on address pin A9. Two

ID

identifier bytes may then be sequenced from the devices outputs by toggling address A
addresses are DON’T CARES except A

, A1, and A6 (A-1). (See Table 2 or Table 3.)

0

from VIL to VIH. All

0

11

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MBM29LV160TE/BE

-70/90/12

The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV160TE/BE is erased or programmed in a system without access to high voltage on the A
command sequence is illustrated in Table 7, Command Definitions.

Byte 0 (A

= VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code.

0

For the MBM29LV160TE/BE these two bytes are given in the Table 4.2. All identifiers for manufactures and
device will exhibit odd parity with DQ
ex ecuting the Autoselect, A
V

), DQ9 and DQ13 are equal to ‘1’ and DQ8, DQ10 to DQ12, DQ14, and DQ15 are equal to ‘0’.

IH

If BYTE
= V

= VIL (for byte mode), the de vice code is C4H (f or top boot block) or 49H (f or bottom boot bloc k). If BYTE

(for word mode), the device code is 22C4H (for top boot block) or 2249H (for bottom boot block).

IH

must be VIL. (See Tables 2 or 3.) For device indentification in word mode (BYTE =

1

In order to determine which sectors are write protected, A
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ

defined as the parity bit. In order to read the proper device codes when

7

must be at VIH while running through the sector

1

(DQ0 =1).

0

Table 4.1 MBM29LV160TE/BE Sector Protection Verify Autoselect Code

Type A

to A

12

18

Manufacture’s Code X V

A

6

IL

A

1

V

IL

A

0

V

IL

A-1*

V

1

IL

pin. The

9

Code

(HEX)

04H

MBM29LV160TE

Byte

XV

IL

V

IL

V

IH

V

IL

C4H

Word X 22C4H

Device Code

MBM29LV160BE

Byte

XV

IL

V

IL

V

IH

V

IL

49H

Word X 2249H

Sector Protection

is for Byte mode.

*1: A

-1

Sector

Addresses

V

IL

V

IH

V

IL

V

IL

01H*

2

*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

Table 4.2 Expanded Autoselect Code Table

Type

Code DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

0

Manufacture’s Code 04H A-1/0000000000000100

(B) C4H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z11000100

MBM29LV160TE

Device
Code

MBM29LV160BE

Sector Protection 01H A

(W)

22C4H0010001011000100
(B) 49H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z01001001
(W)

2249H 0 010001001001001

/0000000000000001

-1

(B): Byte mode
(W): Word mode

12

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MBM29LV160TE/BE

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Table 5 Sector Address Tables (MBM29LV160TE)

Sector

Address

A

A

A

A

A

A

A

A

19

18

17

16

15

14

13

(× 8) Address Range (× 16) Address Range

12

SA0 00000XXX00000H to 0FFFFH 00000H to 07FFFH
SA1 00001XXX10000H to 1FFFFH 08000H to 0FFFFH
SA2 00010XXX20000H to 2FFFFH 10000H to 17FFFH
SA3 00011XXX30000H to 3FFFFH 18000H to 1FFFFH
SA4 00100XXX40000H to 4FFFFH 20000H to 27FFFH
SA5 00101XXX50000H to 5FFFFH 28000H to 2FFFFH
SA6 00110XXX60000H to 6FFFFH 30000H to 37FFFH
SA7 00111XXX70000H to 7FFFFH 38000H to 3FFFFH
SA8 01000XXX80000H to 8FFFFH 40000H to 47FFFH

SA9 01001XXX90000H to 9FFFFH 48000H to 4FFFFH
SA1001010XXXA0000H to AFFFFH 50000H to 57FFFH
SA1101011XXXB0000H to BFFFFH 58000H to 5FFFFH
SA1201100XXXC0000H to CFFFFH 60000H to 67FFFH
SA1301101XXXD0000H to DFFFFH 68000H to 6FFFFH
SA1401110XXXE0000H to EFFFFH 70000H to 77FFFH
SA1501111XXXF0000H to FFFFFH 78000H to 7FFFFH
SA1610000XXX100000H to 10FFFFH 80000H to 87FFFH
SA1710001XXX110000H to 11FFFFH 88000H to 8FFFFH
SA1810010XXX120000H to 12FFFFH 90000H to 97FFFH
SA1910011XXX130000H to 13FFFFH 98000H to 9FFFFH
SA2010100XXX140000H to 14FFFFH A0000H to A7FFFH
SA2110101XXX150000H to 15FFFFH A8000H to AFFFFH
SA2210110XXX160000H to 16FFFFH B0000H to B7FFFH
SA2310111XXX170000H to 17FFFFH B8000H to BFFFFH
SA2411000XXX180000H to 18FFFFH C0000H to C7FFFH
SA2511001XXX190000H to 19FFFFH C8000H to CFFFFH
SA2611010XXX1A0000H to 1AFFFFH D0000H to D7FFFH
SA2711011XXX1B0000H to 1BFFFFH D8000H to DFFFFH
SA2811100XXX1C0000H to 1CFFFFH E0000H to E7FFFH
SA2911101XXX1D0000H to 1DFFFFH E8000H to EFFFFH
SA3011110XXX1E0000H to 1EFFFFH F0000H to F7FFFH
SA31111110XX1F0000H to 1F7FFFHF8000H to FBFFFH
SA32111111001F8000H to 1F9FFFHFC000H to FCFFFH
SA33111111011FA000H to 1FBFFFHFD000H to FDFFFH
SA341111111X1FC000H to 1FFFFFH FE000H to FEFFFH

13

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MBM29LV160TE/BE

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Table 6 Sector Address Tables (MBM29LV160BE)

Sector

Address

A

A

A

A

A

A

A

A

19

18

17

16

15

14

13

(× 8) Address Range (× 16) Address Range

12

SA0 0000000X00000H to 03FFFH 00000H to 01FFFH

SA1 0000001004000H to 05FFFH 02000H to 02FFFH

SA2 0000001106000H to 07FFFH 03000H to 03FFFH

SA3 0000010X08000H to 0FFFFH 04000H to 07FFFH

SA4 00001XXX10000H to 1FFFFH 08000H to 0FFFFH

SA5 00010XXX20000H to 2FFFFH 10000H to 17FFFH

SA6 00011XXX30000H to 3FFFFH 18000H to 1FFFFH

SA7 00100XXX40000H to 4FFFFH 20000H to 27FFFH

SA8 00101XXX50000H to 5FFFFH 28000H to 2FFFFH

SA9 00110XXX60000H to 6FFFFH 30000H to 37FFFH
SA1000111XXX70000H to 7FFFFH 38000H to 3FFFFH
SA1101000XXX80000H to 8FFFFH 40000H to 47FFFH
SA1201001XXX90000H to 9FFFFH 48000H to 4FFFFH
SA1301010XXXA0000H to AFFFFH 50000H to 57FFFH
SA1401011XXXB0000H to BFFFFH 58000H to 5FFFFH
SA1501100XXXC0000H to CFFFFH 60000H to 67FFFH
SA1601101XXXD0000H to DFFFFH 68000H to 6FFFFH
SA1701110XXXE0000H to EFFFFH 70000H to 77FFFH
SA1801111XXXF0000H to FFFFFH 78000H to 7FFFFH
SA1910000XXX100000H to 1FFFFFH 80000H to 87FFFH
SA2010001XXX110000H to 11FFFFH 88000H to 8FFFFH
SA2110010XXX120000H to 12FFFFH 90000H to 97FFFH
SA2210011XXX130000H to 13FFFFH 98000H to 9FFFFH
SA2310100XXX140000H to 14FFFFH A0000H to A7FFFH
SA2410101XXX150000H to 15FFFFH A8000H to 8FFFFH
SA2510110XXX160000H to 16FFFFH B0000H to B7FFFH
SA2610111XXX170000H to 17FFFFH B8000H to BFFFFH
SA2711000XXX180000H to 18FFFFH C0000H to C7FFFH
SA2811001XXX190000H to 19FFFFH C8000H to CFFFFH
SA2911010XXX1A0000H to 1AFFFFH D0000H to D7FFFH
SA3011011XXX1B0000H to 1BFFFFH D8000H to DFFFFH
SA3111100XXX1C0000H to 1CFFFFH E0000H to E7FFFH
SA3211101XXX1D0000H to 1DFFFFH E8000H to EFFFFH
SA3311110XXX1E0000H to 1EFFFFH F0000H to F7FFFH
SA3411111XXX1F0000H to 1FFFFFH F8000H to FFFFFH

14

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MBM29LV160TE/BE

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•Write

Device erasure and progr amming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE
the falling edge of WE

or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on

whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

• Sector Protection

The MBM29LV160TE/BE features hardware sector protection. This f eature will disable both prog ram and erase
operations in any number of sectors (0 through 34). The sector protection f eature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V
V

, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to

IL

the sector to be protected. Tables 5 and 6 define the sector address for each of the thirty five (35) individual
sectors. Programming of the protection circuitry begins on the falling edge of the WE
with the rising edge of the same. Sector addresses must be held constant during the WE
and 24 for sector protection waveforms and algorithm.

on address pin A9 and control pin OE, CE =

ID

pulse and is terminated

pulse. See Figures 17

To verify programming of the protection circuitry, the programming equipment must force V
with CE
while (A

and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)

, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector . Otherwise the

6

device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A
A

are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device

6

codes. A

requires to VIL in byte mode.

-1

on address pin A9

ID

, A1, and

0

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. P erforming
a read operation at the address location XX02H, where the higher order addresses pins (A
A

, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See

14

, A18, A17, A16, A15,

19

Tables 4.1 and 4.2 for Autoselect codes.

• Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29LV160TE/BE devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET
(V

). During this mode, formerly protected sectors can be programmed or erased by selecting the sector

ID

addresses. Once the V

is taken awa y from the RESET pin, all the previously protected sectors will be protected

ID

again. (See Figures 18 and 25.)

pin to high voltage

15

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MBM29LV160TE/BE

Table 7 MBM29LV160TE/BE Standard Command Definitions

Command
Sequence

Read/Reset

Read/Reset

Autoselect

Program

Chip Erase

Bus

Write

Cycles

Req’d

Word

1 XXXH F0H — — — — — — — — — —

Byte

Word

3

Byte AAAH 555H AAAH

Word

3

Byte AAAH 555H AAAH

Word

4

Byte AAAH 555H AAAH

Word

6

Byte AAAH 555H AAAH AAAH 555H AAAH

First Bus

Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

555H

AAH

555H

AAH

555H

AAH

555H

AAH

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Second

Bus

Write Cycle

2AAH

55H

2AAH

55H

2AAH

55H

2AAH

55H

Third Bus

Write Cycle

555H

F0H RA RD — — — —

555H

90H——————

555H

A0H PA PD — — — —

555H

80H

Fourth Bus
Read/Write

Cycle

555H

AAH

Fifth Bus

Write Cycle

2AAH

55H

Sixth Bus

Write Cycle

555H

10H

Sector
Erase

Erase Suspend 1 XXXH B0H — — — — — — — — — —
Erase Resume 1 XXXH 30H — — — — — — — — — —

Set to
Fast Mode

Fast
Program *1

Reset from
Fast Mode
*1

Extended
Sector
Protection
*2

Query *3

Word

Byte AAAH 555H AAAH AAAH 555H

Word

Byte AAAH 555H AAAH

Word

Byte XXXH

Word

Byte XXXH XXXH

Word

Byte

Word

Byte AAH

555H

6

555H

3

XXXH

2

XXXH

2

4 XXXH 60H SPA 60H SPA 40H SPA SD — — — —

55H

1

2AAH

AAH

2AAH

AAH

A0HPAPD————————

XXXH *4

90H

98H——————————

55H

55H

F0H

555H

555H

————————

555H

80H

20H——————

AAH

2AAH

55H SA 30H

16

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Notes: 1. Address bits A

Sector Address (SA).

2. Bus operations are defined in Tables 2 and 3.

3. RA =Address of the memory location to be read.
PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE

SA =Address of the sector to be erased. The combination of A

uniquely select any sector.

4. RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the rising edge of WE

5. SPA=Sector address to be protected. Set sector address (SA) and (A
SD =Sector protection verify data. Output 01H at protected sector addressed and output 00H at

unprotected sector addresses.

6. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A
Byte Mode: AAAH or 555H to addresses A-1 to A

7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

MBM29LV160TE/BE

to A19 = X = “H” or “L” for all address commands e xcept or Prog r am Address (PA) and

11

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pulse.

, A18, A17, A16, A15, A14, A13, and A12 will

19

.

, A1, A0) = (0, 1, 0).

6

to A

0

10
10

*1:This command is valid while Fast Mode.
*2: This command is valid while RESET
*3: The valid addresses are A

to A0. The other addresses are “Don’t care”.

6

= VID.

*4: The data “00H” is also acceptable.

17

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MBM29LV160TE/BE

COMMAND DEFINITIONS

■

Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in prog ress . Moreo v er both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ

-70/90/12

to DQ7 and DQ8 to DQ15 bits are ignored.

0

• Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register . Microprocessor
read cycles retrieve array data from the memory. The device remains enabled for reads until the command
register contents are altered.

The device will automatically power-up in the Read/Reset state . In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters. (See Figure 5.1.)

• Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufactures and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the last command write, a read cycle from address XX00H retrie v es the manufacture code of 04H. A
read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the de vice code (MBM29LV160TE = C4H and
MBM29LV160BE = 49H for ×8 mode; MBM29LV160TE = 22C4H and MBM29LV160BE = 2249H for ×16 mode).
(See Tables 4.1 and 4.2.)

All manufactures and device codes will exhibit odd parity with DQ
The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).
Scanning the sector addresses (A
a logical “1” at device output DQ
mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by e xecuting it after writing the Read/Reset command
sequence.

, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

19

for a protected sector . The programming v erification should be perform margin

0

to a high voltage. However, multiplexing high

9

defined as the parity bit.

7

• Byte/Word Programming

The device is programmed on a b yte-by-byte (or word-by-word) basis . Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are f ollowed b y the program set-up command and data write cycles .
Addresses are latched on the falling edge of CE
rising edge of CE
first) begins programming. Upon ex ecuting the Embedded Progr am Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

or WE, whichev er happens later and the data is latched on the

The automatic programming operation is completed when the data on DQ
bit at which time the device return to the read mode and addresses are no longer latched. (See T ab le 8, Hardware

18

is equivalent to data written to this

7