FUJITSU MBM29DL32XTD, MBM29DL32XBD Service Manual

查询MBM29DL321BD-80供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

32M (4M × 8/2M × 16) BIT

MBM29DL32XTD/BD

FEATURES

■

• 0.33 µm Process Technology

• Simultaneous Read/Write operations (dual bank)

Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

PRODUCT LINE UP

■

DS05-20873-4E

Dual Operation

-80/90/12

(Continued)

Part No. MBM29DL32XTD/MBM29DL32XBD

V

= 3.3 V

Ordering Part No.

Max. Address Access Time (ns) 80 90 120
Max. CE
Max. OE

PACKAGES

■

Em\edded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

Access Time (ns) 80 90 120
Access Time (ns) 30 35 50

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

CC

V

CC

= 3.0 V

+0.3 V
–0.3 V

+0.6 V
–0.3 V

80 — —
—9012

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M20)

57-ball plastic FBGA

(BGA-57P-M01)

MBM29DL32XTD/BD

-80/90/12

(Continued)

• Compatible with JEDEC-standard commands

Uses same software commands as E

2

PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
57-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

80 ns maximum access time

• Sector erase architecture

Eight 4K word and sixty-three 32K word sectors in word mode
Eight 8K byte and sixty-three 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector
B = Bottom sector

• Hidden ROM (Hi-ROM) region

64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)

/ACC input pin

•WP

At V

, allows protection of boot sectors, regardless of sector protection/unprotection status

IL

At V

, allows removal of boot sector protection

IH

At V

, increases program performance

ACC

TM

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

TM

Algorithms

Automatically writes and verifies data at specified address

•Data

• Ready/Busy output (RY/BY

Polling and Toggle Bit feature for detection of program or erase cycle completion

)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

•Low V

write inhibit ≤ 2.5 V

CC

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET

• In accordance with CFI (C

ommon Flash Memory Interface)

pin.

2

GENERAL DESCRIPTION

■

MBM29DL32XTD/BD

-80/90/12

The MBM29DL32XTD/BD are a 32M-bit, 3.0 V - only Flash memory organized as 4M bytes of 8 bits each or 2M
words of 16 bits each. The MBM29DL32XTD/BD are offered in a 48-pin TSOP(I) and FBGA Package. These
devices are designed to be programmed in-system with the standard system 3.0 V V

5.0 V V

are not required for write or erase operations. The devices can also be reprogrammed in standard

CC

supply. 12.0 V VPP and

CC

EPROM programmers.
MBM29DL32XTD/BD are organized into two banks, Bank 1 and Bank 2, which can be considered to be two

separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is
simultaneously taking place on the other bank.

In the MBM29DL32XTD/BD , a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.

The standard MBM29DL32XTD/BD offer access times 80 ns, 90 ns and 120 ns , allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE
write enable (WE), and output enable (OE) controls.

The MBM29DL32XTD/BD are pin and command set compatible with JEDEC standard E

2

PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry . Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

),

The MBM29DL32XTD/BD are programmed by e x ecuting the program command sequence . This will inv ok e the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before e xecuting the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29DL32XTD/BD are erased when shipped from the
factory .

The devices f eature single 3.0 V pow er supply operation f or both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a prog ram or er ase cycle has been

6

detector automatically

CC

7

completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E

2

PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL32XTD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are progr ammed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.

,

3

MBM29DL32XTD/BD

Table 1 MBM29DL32XTD/BD Device Bank Divisions

-80/90/12

Device

Part Number

MBM29DL321TD/BD

MBM29DL322TD/BD 4 Mbit

MBM29DL323TD/BD 8 Mbit

MBM29DL324TD/BD 16 Mbit

Organization

8/× 16

×

Megabits Sector sizes Megabits Sector sizes

0.5 Mbit Eight 8K byte/4K word 31.5 Mbit

Bank 1 Bank 2

Eight 8K byte/4K word,

seven 64K byte/32K word

Eight 8K byte/4K word,

fifteen 64K byte/32K word

Eight 8K byte/4K word,

thirty-one 64K byte/

32K word

28 Mbit

24 Mbit

16 Mbit

Sixty-three

64K byte/32K word

Fifty-six

64K byte/32K word

Forty-eight

64K byte/32K word

Thirty-two

64K byte/32K word

4

PIN ASSIGNMENTS

■

MBM29DL32XTD/BD

TSOP(I)

-80/90/12

A15
A14
A13
A12
A11
A10

A9

A8
A19
A20

WE

RESET

N.C.

WP/ACC

RY/BY

A
A17

A7

A6

A5

A4

A3

A2

A1

A1

A2

A3

A4

A5

A6

A7

A17
A18

RY/BY

WP/ACC

N.C.

RESET

WE

A
A19

A8

A9

A10
A11
A12
A13
A14
A15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

18

16
17
18
19
20
21
22
23
24

24
23
22
21
20
19
18
17
16
15
14
13
12
11

20

10
9
8
7
6
5
4
3
2
1

(Marking Side)

Standard Pinout

FPT-48P-M19

(Marking Side)

Reverse Pinout

FPT-48P-M20

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A16
BYTE
VSS
DQ 15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V

SS

CE
A

0

A0
CE
V

SS

OE
DQ

0

DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16

5

MBM29DL32XTD/BD

-80/90/12

(Continued)

FBGA

(TOP VIEW)
Marking side

A3A1 A2 A4 A6A5
B1 B2 B3 B4 B5 B6
C1 C2 C3 C4 C5 C6
D1 D2 D3 D4 D5 D6
E1 E2 E3 E4 E5 E6
F1 F2 F3 F4 F5 F6
G1 G2 G3 G4 G5 G6
H1 H2 H3 H4 H5 H6

(BGA-57P-M01)

A1 A
B1 A
C1 A
D1 A
E1 A

3

4

2

1

0

F1 CE F2 DQ
G1 OE G2 DQ
H1 V

SS

A2 A
B2 A
C2 A
D2 A

7

17

6

5

E2 DQ

H2 DQ

A3 RY/BY A4 WE A5 A
B3 WP/ACC B4 RESET B5 A
C3 A
D3 A

0

8

9

1

E3 DQ
F3 DQ
G3 DQ
H3 DQ

18

20

2

10

11

3

C4 N.C. C5 A
D4 A

19

E4 DQ
F4 DQ
G4 V

CC

H4 DQ

5

12

4

D5 A
E5 DQ
F5 DQ
G5 DQ
H5 DQ

9

8

10

11

7

14

13

6

A6 A
B6 A
C6 A
D6 A
E6 A

13

12

14

15

16

F6 BYTE
G6 DQ15/A
H6 V

SS

Regarding additional No Internal Connection balls, please contact a Fujitsu representative for more
information.

-1

6

BLOCK DIAGRAM

■

V CC
V SS

MBM29DL32XTD/BD

-80/90/12

A

0 to A20

(A-1)

RESET

WE

CE

OE

BYTE

WP/ACC

DQ 0 to DQ 15

State

Control

&

Command

Register

Bank 2 Address

RY/BY

Status

Bank 1 Address

Control

Cell Matrix

(Bank 2)

X-Decoder

X-Decoder

Cell Matrix

(Bank 1)

Y-Gating & Data Latch

Y-Gating &

Data Latch

DQ 0 to DQ 15

7

MBM29DL32XTD/BD

LOGIC SYMBOL

■

-80/90/12

Table 2 MBM29DL32XTD/BD Pin Configuration

Pin Function

21

A-1

A0 to A20

CE
OE
WE
RESET
BYTE
WP/ACC

DQ 0 to DQ 15

RY/BY

16 or 8

A

, A0 to A

-1

DQ

0

RY/BY

RESET

BYTE

WP

to DQ

CE

OE

WE

/ACC

Address Inputs

20

Data Inputs/Outputs

15

Chip Enable
Output Enable
Write Enable
Ready/Busy Output
Hardware Reset Pin/Temporary Sector

Group Unprotection
Selects 8-bit or 16-bit mode
Hardware Write Protection/Program

Acceleration

N.C. No Internal Connection

V

SS

V

CC

Device Ground
Device Power Supply

8

DEVICE BUS OPERATION

■

Table 3 MBM29DL32XTD/BD User Bus Operations (BYTE

MBM29DL32XTD/BD

= VIH)

-80/90/12

Operation CE

Auto-Select Manufacturer Code (1) L L H L L L V
Auto-Select Device Code (1) L L H H L L V
Read (3) L L H A

OE WE A0A1A6A9DQ0 to DQ15RESET WP/ACC

Code H X

ID

Code H X

ID

A1A6A

0

D

9

OUT

HX
Standby HXXXXXX HIGH-Z H X
Output Disable L H H X X X X HIGH-Z H X
Write (Program/Erase) L H L A
Enable Sector Group Protection (2), (4) L V

ID

Verify Sector Group Protection (2), (4) L L H L H L V

A1A6A

0

9

LHLVIDXHX

ID

Temporary Sector Group Unprotection (5) XXXXXXX X V

D

IN

HX

Code H X

ID

X
Reset (Hardware)/Standby XXXXXXX HIGH-Z L X
Boot Block Sector Write Protection XXXXXXX X X L

Table 4 MBM29DL32XTD/BD User Bus Operations (BYTE

Operation CE

OE WE

DQ15/

A

-1

A0A1A6A9DQ0 to DQ7RESET WP/ACC

Auto-Select Manufacturer Code (1) L L H L L L L V
Auto-Select Device code (1) L L H L H L L V

= VIL)

Code H X

ID

Code H X

ID

Read (3) L L H A

A0A1A6A

-1

D

9

OUT

HX
Standby HXXX XXXX HIGH-Z H X
Output Disable L H H X X X X X HIGH-Z H X
Write (Program/Erase) L H L A
Enable Sector Group Protection

(2), (4)
Verify Sector Group Protection

(2), (4)
Temporary Sector Group

Unprotection (5)

LV

ID

LLHLLHLV

XXX X XXXX X V

A0A1A6A

-1

9

D

IN

HX

LLHLVIDXHX

Code H X

ID

ID

X

Reset (Hardware)/Standby X X X X X X X X HIGH-Z L X
Boot Block Sector Write Protection X X X X X X X X X X L

Legend:

L = V

, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels.

IL

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 12.

2. Refer to the section on Sector Group Protection.

3. WE

can be VIL if OE is VIL, OE at VIH initiates the write operations.

4. V

= 3.3 V ± 10%

CC

5. It is also used for the extended sector group protection.

9

MBM29DL32XTD/BD

ABSOLUTE MAXIMUM RATINGS(See WARNING)

■

-80/90/12

Parameter Symbol Conditions

Unit

Min. Max.

Rating

Storage Temperature Tstg
Ambient Temperature with

Power Applied

T

A




–55 +125 °C
–40 +85 °C

Voltage with Respect to
Ground All pins except A
OE

, RESET (Note 1)

Power Supply Voltage
(Note 1)

A

, OE, and RESET

9

(Note 2)
WP

/ACC (Note 3) V

,

9

, V

V

IN

OUT

V

CC

V

IN

IN








–0.5 V

–0.5 +4.0 V

–0.5 +13.0 V
–0.5 +10.5 V

+0.5 V

CC

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative

overshoot V
+0.5 V. During voltage transitions, outputs ma y positive ov ershoot to V

2. Minimum DC input voltage on A
and RESET pins may negative overshoot V
voltage on A
up to 20 ns. when V

3. Minimum DC input voltage on WP
negative ov ershoot V

to –2.0 V for periods of up to 20 ns. Maximum DC v oltage on output and I/O pins are VCC

SS

+2.0 V for periods of up to 20 ns.

CC

, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE

9

to –2.0 V for periods of up to 20 ns. Maximum DC input

SS

, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of

9

is applied.

CC

/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may

to –2.0 V for periods of up to 20 ns. Maximum DC input v oltage on WP/ACC pin

SS

iis +10.5V which may positive overshoot to +10.5V for periods of up to 20ns when Vcc is applied.

RECOMMENDED OPERATING CONDITIONS

■

Value

Parameter Symbol Conditions

Min. Max.

Ambient Temperature T

Power Supply Voltage V

MBM29DL32XTD/BD-80

A

MBM29DL32XTD/BD-90/12
MBM29DL32XTD/BD-80

CC

MBM29DL32XTD/BD-90/12

–20 +70 °C

–40 +85 °C
+3.0 +3.6 V
+2.7 +3.6 V

Operating ranges define those limits between which the functionality of the devices are guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

10

Unit

MAXIMUM OVERSHOOT

■

MBM29DL32XTD/BD

-80/90/12

+0.6 V
–0.5 V

–2.0 V

CC +2.0 V

V

V CC +0.5 V

+2.0 V

20 ns

20 ns

20 ns

Figure 1 Maximum Negative Overshoot Waveform

20 ns

20 ns20 ns

+14.0 V

+13.0 V

V

CC +0.5 V

Figure 2 Maximum Positive Overshoot Waveform 1

20 ns

20 ns20 ns

*: This waveform is applied for A9, OE, and RESET.

Figure 3 Maximum Positive Overshoot Waveform 2

11

MBM29DL32XTD/BD

ELECTRICAL CHARACTERISTICS

■

1. DC Characteristics

Parameter Symbol Conditions

-80/90/12

Value

Unit

Min. Max.

Input Leakage Current I
Output Leakage Current I
A

, OE, RESET Inputs Leakage

9

Current

V

Active Current (Note 1) I

CC

V

Active Current (Note 2) I

CC

Current (Standby) I

V

CC

V

Current (Standby, Reset) I

CC

V

Current

CC

(Automatic Sleep Mode) (Note 3)

VCC Active Current (Note 5)
(Read-While-Program)

V

Active Current (Note 5)

CC

(Read-While-Erase)
V

Active Current

CC

(Erase-Suspend-Program)

I

I

I

I

I

LI

LO

LIT

CC1

CC2

CC3

CC4

CC5

CC6

CC7

CC8

VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0
V

= VSS to VCC, VCC = VCC Max. –1.0 +1.0

OUT

VCC = VCC Max.
A

, OE, RESET = 12.5 V

9

CE = VIL, OE = VIH,

f = 5 MHz

CE

= VIL, OE = VIH,

f = 1 MHz

CE = VIL, OE = V

IH

Byte

Word 18

Byte

Word 7

VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = V

± 0.3 V

CC

VCC = VCC Max.,WE/ACC = VCC ±

0.3 V, RESET

= V

± 0.3 V

SS

—35µA

16

—

7

—

—35mA
—5µA

—5µA

VCC = VCC Max., CE = VSS ± 0.3 V,
RESET
V

= V

± 0.3 V

CC

= VCC ± 0.3 V or VSS ± 0.3 V

IN

—5µA

Byte — 51

CE = VIL, OE = V

IH

Word — 53

Byte — 51

CE = VIL, OE = V

IH

Word — 53

CE = VIL, OE = V

IH

—35mA

µ
µ

mA

mA

mA

mA

A
A

ACC Accelerated Program
Current

Input Low Level V
Input High Level V

I

ACC

IL

IH

VCC = VCC Max.
WP/ACC = V

ACC

Max.

—20mA

—–0.50.6V
—2.0V

+0.3 V

CC

Voltage for WP/ACC Sector
Protection/Unprotection and

V

ACC

—8.59.5V

Program Acceleration
V oltage f or Autoselect and Sector

Protection (A

, OE, RESET)

9

V

ID

— 11.5 12.5 V

(Note 4)

(Continued)

Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component.

2. I

active while Embedded Algorithm (program or erase) is in progress.

CC

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only V

applying.

CC

5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)

12

(Continued)

Parameter Symbol Conditions

Output Low Voltage Level V

MBM29DL32XTD/BD

-80/90/12

Value

Unit

Min. Max.

OL

IOL = 4.0 mA, VCC = VCC Min. — 0.45 V

V

OH1

IOH = –2.0 mA, VCC = VCC Min. 2.4 — V

Output High Voltage Level

Low V

Lock-Out Voltage V

CC

V

OH2

LKO

IOH = –100 µAV

–0.4 — V

CC

—2.32.5V

Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component.

2. I

active while Embedded Algorithm (program or erase) is in progress.

CC

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only V

applying.

CC

5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)

13

MBM29DL32XTD/BD

2. AC Characteristics

• Read Only Operations Characteristics

Parameter

symbols

JEDEC Standard

Description Test setup

-80/90/12

80

(Note)90(Note)12(Note)

Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

—t

—

t

RC

t

ACC

t

CE

t

OE

t

DF

t

DF

t

OH

READY

t

ELFL

t

ELFH

Note: Test Conditions:

Output Load:1 TTL gate and 30 pF (MBM29DL32XTD/BD 80)

1 TTL gate and 100 pF (MBM29DL32XTD/BD 90/12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level

Input: 1.5 V
Output:1.5 V

Read Cycle Time — Min. 80 90 120 ns

Address to Output Delay

CE
OE = V

IL

Max. 80 90 120 ns

IL

= V

Chip Enable to Output Delay OE = VILMax. 80 90 120 ns
Output Enable to Output Delay — Max. 30 35 50 ns
Chip Enable to Output High-Z — Max. 25 30 30 ns
Output Enable to Output High-Z — Max. 25 30 30 ns
Output Hold Time from Addresses,

CE or OE, Whichever Occurs First
RESET Pin Low to Read Mode — Max. 20 20 20

—Min.000ns

µ

CE or BYTE Switching Low or High — Max. 5 5 5 ns

s

14

Device

Under

Test

IN3064
or Equivalent

6.2 kΩ

CL

Figure 4 Test Conditions

3.3 V

2.7 kΩ

Diodes = IN3064
or Equivalent

• Write/Erase/Program Operations

MBM29DL32XTD/BD

-80/90/12

Parameter symbols

JEDEC Standard

t

AVAV

t

AVWL

—t

t

WLAX

—t

t

DVWH

t

WHDX

—t

—t
—t

t

GHWL

t

GHEL

t

WC

t

ASO

t

AHT

t
t

OEH

CEPH

OEPH

t

GHWL

t

GHEL

AS

AH

DS

DH

Description 80 90 12 Unit

Write Cycle Time Min. 80 90 120 ns
Address Setup Time Min. 0 0 0 ns
Address Setup Time to OE Low During

Toggle Bit Polling

Min. 12 15 15 ns

Address Hold Time Min. 45 45 50 ns
Address Hold Time from CE or OE High

During Toggle Bit Polling

Min. 0 0 0 ns

Data Setup Time Min. 30 35 50 ns
Data Hold Time Min. 0 0 0 ns

Output Enable
Hold Time

Read Min. 0 0 0 ns
Toggle and Data

Polling Min. 10 10 10 ns
CE High During Toggle Bit Polling Min. 20 20 20 ns
OE High During Toggle Bit Polling Min. 20 20 20 ns
Read Recover Time Before Write Min. 0 0 0 ns
Read Recover Time Before Write Min. 0 0 0 ns

t

ELWL

t

WLEL

t

WHEH

t

EHWH

t

WLWH

t

ELEH

t

WHWL

t

EHEL

t

WHWH1

t

WHWH2

—t
—t
—t
—t
—t
—t

t

CS

t

WS

t

CH

t

WH

t

WP

t

CP

t

WPH

t

CPH

t

WHWH1

t

WHWH2

VCS

VIDR

VACCR

VLHT

WPP

OESP

CE Setup Time Min. 0 0 0 ns
WE Setup Time Min. 0 0 0 ns
CE Hold Time Min. 0 0 0 ns
WE Hold Time Min. 0 0 0 ns
Write Pulse Width Min. 35 35 50 ns
CE Pulse Width Min. 35 35 50 ns
Write Pulse Width High Min. 25 30 30 ns
CE Pulse Width High Min. 25 30 30 ns
Byte Programming Operation Typ. 8 8 8 µs
Sector Erase Operation (Note 1) Typ. 1 1 1 sec
VCC Setup Time Min. 50 50 50 µs
Rise Time to VID (Note 2) Min. 500 500 500 ns
Rise Time to VID (Note 2) Min. 500 500 500 ns
Voltage Transition Time (Note 2) Min. 4 4 4 µs
Write Pulse Width (Note 2) Min. 100 100 100 µs
OE Setup Time to WE Active (Note 2) Min. 4 4 4 µs

(Continued)

15

MBM29DL32XTD/BD

(Continued)

-80/90/12

Parameter symbols

Description 80 90 12 Unit

JEDEC Standard

—t
—t
—t
—t
—t
—t
—t
—t
—t
—t

CSP

RB

RP

RH

FLQZ

FHQV

BUSY

EOE

TOW

SPD

CE Setup Time to WE Active (Note 2) Min. 4 4 4 µs
Recover Time from RY/BY Min. 0 0 0 ns
RESET Pulse Width Min. 500 500 500 ns
RESET High Level Period before Read Min. 200 200 200 ns
BYTE Switching Low to Output High-Z Max. 30 30 40 ns
BYTE Switching High to Output Active Max. 80 90 120 ns
Program/Erase Valid to RY/BY Delay Max. 90 90 90 ns
Delay Time from Embedded Output Enable Max. 80 90 120 ns
Erase Time-Out Time Min. 50 50 50 µs
Erase Suspend Transition Time Max. 20 20 20 µs

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Group Protection operation.

16

ERASE AND PROGRAMMING PERFORMANCE

■

MBM29DL32XTD/BD

-80/90/12

Parameter

Sector Erase Time — 1 10 sec

Word Programming Time — 16 360
Byte Programming Time — 8 300

Chip Programming Time — — 100 sec

Program/Erase Cycle 100,000 — — cycles —

PIN CAPACITANCE

■

Parameter

symbol

C

IN

C

OUT

C

IN2

Parameter description Test setup Typ. Max. Unit

Input Capacitance VIN = 0 6 7.5 pF
Output Capacitance V
Control Pin Capacitance VIN = 0 8 11 pF

Min. Typ. Max.

Limits

= 0 8.5 12 pF

OUT

Unit Comments

Excludes programming time
prior to erasure

s

µ
µ

Excludes system-level
overhead

s

Excludes system-level
overhead

C

IN3

Note: Test conditions TA = 25°C, f = 1.0 MHzs

WP/ACC Pin Capacitance VIN = 0 21.5 22.5 pF

17

MBM29DL32XTD/BD

TIMING DIAGRAM

■

• Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

-80/90/12

Addresses

Must Be
Steady

May
Change
from H to L

May
Change
from L to H

“H” or “L”
Any Change
Permitted

Does Not
Apply

t RC

Addresses Stable

Will Be
Steady

Will Be
Changing
from H to L

Will Be
Changing
from L to H

Changing
State
Unknown

Center Line is
High­Impedance
“Off” State

18

CE

OE

WE

Outputs

t ACC

t OE

t OEH

t CE

High-Z

Output Valid

Figure 5.1 AC Waveforms for Read Operations

t DF

t OH

High-Z

Addresses

t ACC

MBM29DL32XTD/BD

t RC

Addresses Stable

-80/90/12

CE

RESET

Outputs

t RH

t RP t RH t CE

t OH

High-Z

Output Valid

Figure 5.2 AC Waveforms for Hardware Reset/Read Operations

19

MBM29DL32XTD/BD

-80/90/12

Data Polling

PA

Addresses

3rd Bus Cycle

555H

t WC

t AS

PA

t AH

CE

t CS

t CH

OE

t GHWL

t WPH

t WHWH1

t WP

WE

t DS

t DH

Data

A0H

PD

DQ 7

D OUT

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ

4. D

is the output of the complement of the data written to the device.

7

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

t RC

t CE

t OE

t OH

D OUT

20

Figure 6 AC Waveforms for Alternate WE Controlled Program Operations

MBM29DL32XTD/BD

Data Polling3rd Bus Cycle

-80/90/12

Addresses

555H

t WC

PA PA

t AS

t AH

WE

t WS

t WH

OE

t CPH

t GHEL

t CP

t WHWH1

CE

t DS

t DH

Data

A0H

PD

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ

4. D

is the output of the complement of the data written to the device.

7

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

DQ 7

OUT

D

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations

21

MBM29DL32XTD/BD

-80/90/12

Addresses

CE

OE

WE

Data

V CC

555H

t WC

t CS

t GHWL

t VCS

t WP

t DS

2AAH 555H

t AS t AH

t CH

t WPH

t DH

555H

2AAH SA *

55H55H 80H AAHAAH

10H/

30H

*: SA is the sector address for Sector Erase. Addresses = 555H (W ord), AAAH (Byte) for Chip Erase .

Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 8 AC Waveforms for Chip/Sector Erase Operations

22

CE

MBM29DL32XTD/BD

-80/90/12

t CH

t OE

t DF

OE

t OEH

WE

t CE

*

t EOEt BUSY

DQ7 =

Valid Data

DQ0 to DQ6
Valid Data

DQ7

DQ0 to DQ6

Data

t WHWH1 or 2

Data

DQ7

0 to DQ6 = Output Flag

DQ

RY/BY

* :DQ7 = Valid Data (The device has completed the Embedded operation).

Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations

High-Z

High-Z

23

MBM29DL32XTD/BD

Address

CE

-80/90/12

tAHT tAHTtASO tAS

tCEPH

WE

OE

DQ 6/DQ2

RY/BY

tDH

Data

tBUSY

tOEPH

tOE tCE

Toggle

Data

Toggle

Data

Toggle

Data

tOEHtOEH

*

Stop

Toggling

* :DQ6 stops toggling (The device has completed the Embedded operation).

Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

Output

Valid

24

MBM29DL32XTD/BD

Read Command CommandRead Read Read

tRC tRC tRC tRCtWC tWC

-80/90/12

Address BA1 BA1 BA1

tAS

BA2

(555H)

tAH

tACC

tCE

BA2
(PA)

tAHT

tAS

BA2

(PA)

CE

tOE

tCEPH

OE

tGHWL

tWP

tOEH

tDF

WE

tDH

tDS tDF

DQ

Valid

Output

Valid

Intput

Valid

Output

Valid

Intput

Valid

Output

Status

(A0H) (PD)

Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1.
BA2: Address of Bank 2.

Figure 11 Bank-to-bank Read/Write Timing Diagram

WE

DQ6

DQ2

Enter

Embedded

Erasing

Erase

Suspend

Erase

Toggle

DQ

2 and DQ6

with OE or CE

Erase Suspend

Read

Enter Erase

Suspend Program

Erase
Suspend
Program

Note: DQ2 is read from the erase-suspended sector.

Figure 12 DQ2 vs. DQ

6

Erase Suspend

Read

Erase

Resume

Erase Erase

Complete

25

MBM29DL32XTD/BD

CE

WE

RY/BY

Figure 13 RY/BY Timing Diagram during Program/Erase Operations

-80/90/12

The rising edge of the last write pulse

Entire programming
or erase operations

t BUSY

WE

RESET

RY/BY

tRP

t RB

tREADY

Figure 14 RESET, RY/BY Timing Diagram

26