FUJITSU MB90420G, MB90425G (A) DATA SHEET

查询MB90420G供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13711-1E

16-Bit Original Microcontroller

CMOS

F2MC-16LX MB90420G/5G (A) Series

MB90423G/423GA/F423G/F423GA/V420G MB90427G/427GA/428G/428GA/F428G/F428GA

DESCRIPTIONS

■■■■

The FUJITSU MB90420G/5G (A) Series is a 16-bit general purpose high-capacity microcontroller designed for vehicle meter control applications etc.

The instruction set retains the same A T architecture as the FUJITSU original F further refinements including high-level language instructions, expanded addressing mode, enhanced (signed) multipler-divider computation and bit processing.

2

MC-8L and F2MC-16L series, with

In addition, A 32-bit accumulator is built in to enable long word processing.

FEATURES

■■■■

• 16-bit input capture (4 channels) Detects rising, falling, or both edges. 16-bit capture register × 4 Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.

• 16-bit reload timer (2 channels) 16-bit reload timer operation (select toggle output or one-shot output) Event count function selection provided

PACKAGES

■■■■

Plastic QFP, 100-pin Plastic LQFP, 100-pin

(Continued)

(FPT-100P-M06) (FPT-100P-M05)

MB90420G/5G (A) Series

• Clock timer (main clock) Operates directly from oscillator clock. Compensates for oscillator deviation Read/write enabled second/minute/hour register Signal interrupt

• 16-bit PPG (3 channels) Output pins (3) , external trigger input pin (1) Output clock frequencies : f

CP, fCP/2

2

, fCP/24, fCP/2

• Delay interrupt Generates interrupt for task switching. Interruptions to CPU can be generated/deleted by software setting.

• External interrupts (8 channels) 8-channel independent operation Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.

• A/D converter 10-bit or 8-bit resolution × 8 channels (input multiplexed) Conversion time : 6.13 µs or less (at f

CP = 16 MHz)

External trigger startup available (P50/INT0/ADTG) Internal timer startup available (16-bit reload timer 1)

• UART (2 channels) Full duplex double buffer type Supports asynchronous/synchronous transfer (with start/stop bits) Internal timer can be selected as clock (16-bit reload timer 0) Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps Synchronous : 500 Kbps, 1Mbps, 2Mbps (at f

• CAN interface *

1

Conforms to CAN specifications version 2.0 Part A and B. Automatic resend in case of error. Automatic transfer in response to remote frame. 16 prioritized message buffers for data and messages for data and ID Multiple message support Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks Supports up to 1 Mbps CAN WAKEUP function (connects RX internally to INT0)

• LCD controller/driver (1 channel) Segment driver and command driver with direct LCD panel (display) drive capability

• Low voltage/Program Looping detect reset * Automatic reset when low voltage is detected Program Looping detection function

• Stepping motor controller (4 channels) High current output for all channels × 4 Synchronized 8/10-bit PWM for all channels × 2

• Sound generator 8-bit PWM signal mixed with tone frequency from 8-bit reload counter. PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at f Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)

6

CP = 16 MHz)

2

CP = 16MHz)

(Continued)

2

MB90420G/5G (A) Series

(Continued)

• Input/output ports Push-pull output and Schmitt trigger input Programmable in bit units for input/output or peripheral signals.

•Flash memory Supports automatic programming, Embeded Algorithm Flag indicates algorithm completion Minato Electronics flash writer Boot block configuration Erasable by blocks Block protection by external programming voltage

*1 : MB90420G (A) series has 2 channels built-in, MB90425G (A) series has 1 channel built-in *2 : Built-in to MB90420GA/5GA series only. Not built-in to MB90420G/5G series.

Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc.

TM

, write/erase/erase pause/erase resume instructions

3

MB90420G/5G (A) Series

PRODUCT LINEUP

■■■■

•

MB90420G (A) Series

Part number

MB90V420G

MB90F423G *

Parameter

Configuration Evaluation model Flash ROM model Mask ROM model CPU

System clock

On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4) ROM External Flash ROM 128 KB Mask ROM 128 KB RAM 6 KB 6 KB 6 KB CAN interface 2 channels Low voltage/

CPU operation

No No Yes No Yes

detection reset Packages PGA-256 QFP100, LQFP100

1

MB90F423GA *1MB90423G *2MB90423GA *

2

F

MC-16LX CPU

2

Emulator dedicated power supply*

•

MB90425G (A) Series

No 

Part number

MB90F428G MB90F428GA

MB90427G*

2

MB90427GA*

2

MB90428G*

1

MB90428GA*

Parameter

Configuration Flash ROM model Mask ROM model CPU

System clock

On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)

2

F

MC-16LX CPU

ROM Flash ROM 128 KB Mask ROM 64 KB Mask ROM 128 KB RAM 6 KB 4 KB 6 KB CAN interface 1 channel Low voltage/

CPU operation

No Yes No Yes No

Yes

detection reset Packages QFP100, LQFP100 Emulator dedicat-

ed power supply*



1

* : When used with evaluation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-507

Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) . *1 : Under development *2 : Planned

4

PIN ASSIGNMENTS

■■■■

COM0

COM1

100

99

P13/IN2

P14/IN1

P15/IN0

96

97

98

(TOP VIEW)

P06/PPG0/TOT1

P11/TOT0/WOT

P07/PPG1/TIN1

P12/TIN0/IN3

P10/PPG2

91

92

93

94

95

MB90420G/5G (A) Series

P01/SOT0/INT5

P02/SCK0/INT6

P05/SCK1/TRG

P04/SOT1

89

90

P00/SIN0/INT4

P03/SIN1/INT7

V

X1

CC

83

84

85

86

87

88

X0 82

V

SS

81

COM2 COM3

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7

V

SS

SEG8

SEG9 SEG10 SEG11

P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18

V P45/SEG19 P46/SEG20 P47/SEG21

P90/SEG22 P91/SEG23

CC

V0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

C

28 29 30

80

X0A

79

X1A

78

P57/SGA

77

RST

76

P56/SGO/FRCK

75

P55/RX0

74

P54/TX0

73

DV P87/PWM2M3

72

P86/PWM2P3

71

P85/PWM1M3

70

P84/PWM1P3

69

DV

68

P83/PWM2M2

67

P82/PWM2P2

66

P81/PWM1M2

65

P80/PWM1P2

64

DV

63

P77/PWM2M1

62

P76/PWM2P1

61

P75/PWM1M1

60

P74/PWM1P1

59

DV

58

P73/PWM2M0

57

P72/PWM2P0

56

P71/PWM1M0

55

P70/PWM1P0

54

DV

53

P53/INT3

52

MD2

51

SS

CC

SS

CC

SS

31

V1

32

V2

33

34

AVCCV3

35

AVRH

42

41

40

39

38

37

36

V

P63/AN3

P62/AN2

P61/AN1

P60/AN0

AVSSP50/INT0/ADTG

SS

(FPT-100P-M06)

45

44

43

P66/AN6

P65/AN5

P64/AN4

50

49

48

47

46

MD1

MD0

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P67/AN7

(Continued)

5

MB90420G/5G (A) Series

(Continued)

(TOP VIEW)

P06/PPG0/TOT1

P11/TOT0/WOT

P07/PPG1/TIN1

P12/TIN0/IN3

P10/PPG2

P13/IN2

P14/IN1

P15/IN0

COM0

COM1

COM2

COM3

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7

SS

V SEG8 SEG9

SEG10

SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18

V P45/SEG19 P46/SEG20 P47/SEG21

CC

100

97

98

99

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C

25

96

95

94

93

92

91

90

89

P05/SCK1/TRG

P04/SOT1

87

88

P00/SIN0/INT4

P03/SIN1/INT7

83

84

85

86

P01/SOT0/INT5

P02/SCK0/INT6

V

CC

82

X1 81

X0 80

V

SS

79

X0A

78

P57/SGA

X1A

76

77

RST

75

P56/SGO/FRCK

74

P55/RX0

73

P54/TX0

72

DV

71

P87/PWM2M3

70

P86/PWM2P3

69

P85/PWM1M3

68

P84/PWM1P3

67

DV

66 65

P83/PWM2M2

64

P82/PWM2P2

63

P81/PWM1M2

62

P80/PWM1P2

61

DV

60

P77/PWM2M1

59

P76/PWM2P1

58

P75/PWM1M1

57

P74/PWM1P1

56

DV

55

P73/PWM2M0

54

P72/PWM2P0

53

P71/PWM1M0

52

P70/PWM1P0

51

DV

SS

CC

SS

CC

SS

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P53/INT3

MD2

MD1

MD0

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P67/AN7

P66/AN6

P65/AN5

P64/AN4

V

P63/AN3

P62/AN2

P61/AN1

P60/AN0

AVSSP50/INT0/ADTG

AVRH

AVCCV3

V2

V1

V0

P91/SEG23

P90/SEG22

SS

(FPT-100P-M05)

6

PIN DESCRIPTIONS

■■■■

MB90420G/5G (A) Series

Pin no.

Symbol

LQFP QFP

80 82 X0 81 83 X1

78 80 X0A

77 79 X1A 75 77 RST

83 85

84 86

85 87

Circuit

type

High speed oscillator input pin.

A

High speed oscillator output pin. Low speed oscillator input pin. If no oscillator is connected, apply

pull-down processing.

A

Low speed oscillator output pin. If no oscillator is connected, leave open.

B Reset input pin.

P00 SIN0 UART ch.0 serial data input pin. INT4 INT4 external interrupt input pin.

P01

SOT0 UART ch.0 serial data output pin.

INT5 INT5 external interrupt input pin.

P02

SCK0 UART ch.0 serial clock input/output pin.

INT6 INT6 external interrupt input pin.

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

Description

86 88

87 89

88 90

89 91

90 92

91 93

P03 SIN1 UART ch.1 serial data input pin. INT7 INT7 external interrupt input pin.

P04

SOT1 UART ch.1 serial data output pin.

P05

SCK1 UART ch.1 serial clock input/output pin.

TRG 16-bit PPG ch.0-2 external trigger input pin.

P06

PPG0 16-bit PPG ch.0 output pin. TOT1 16-bit reload timer ch.1 TOT output pin.

P07

PPG1 16-bit PPG ch.1 output pin.

TIN1 16-bit reload timer ch.1 TIN output pin.

P10

PPG2 16-bit PPG ch.2 output pin.

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

(Continued)

7

MB90420G/5G (A) Series

Pin no.

LQFP QFP

92 94

93 95

94 to 96 96 to 98

97 to 100

1 to 8,

10 to 13

14 to 15 16 to 17

16 to 20,

22 to 24

99 to 100,

1 to 2

3 to 10,

12 to 15

18 to 22,

24 to 26

Symbol

P11

TOT0 16-bit reload timer ch.0 TOT output pin.

WOT Real-time clock timer WOT output pin.

P12 TIN0 16-bit reload timer ch.0 TIN output pin.

IN3 Input capture ch.3 trigger input pin.

P13 to P15

IN2 to IN0 Input capture ch.0-2 trigger input pins.

COM0 to

COM3

SEG0 to

SEG11

P36 to P37

SEG12 to

SEG13

P40 to P47

SEG14 to

SEG21

Circuit

type

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output ports.

G

I LCD controller/driver common output pins.

I LCD controller/driver segment output pins.

General purpose output ports.

E

LCD controller/driver segment output pins. General purpose input output ports.

E

LCD controller/driver segment output pins.

Description

P90 to P91

26 to 27 28 to 29

34 36

36 to 39,

41 to 44

45 47

46 48

50 52

* : MB90420G (A) series only.

38 to 41,

43 to 46

SEG22 to

SEG23

P50 INT0 INT0 external interrupt input pin.

ADTG A/D converter external trigger input pin.

P60 to P67

AN0 to

AN7

P51 INT1 INT1 external interrupt input pin.

(RX1 *) CAN interface 1 RX intput pin.

P52 INT2 INT2 external interrupt input pin.

(TX1 *) CAN interface 1 TX output pin.

P53 INT3 INT3 external interrupt input pin.

General purpose input output ports.

E

LCD controller/driver segment output pins. General purpose input output ports.

G

General purpose input output ports.

F

A/D converter input pins. General purpose input output port.

G

General purpose input output port.

G

General purpose input output port.

G

(Continued)

8

MB90420G/5G (A) Series

Pin no.

LQFP QFP

52 to 55 54 to 57

57 to 60 59 to 62

62 to 65 64 to 67

67 to 70 69 to 72

Symbol

P70 to P73

PWM1P0

PWM1M0

PWM2P0

PWM2M0

P74 to P77

PWM1P1

PWM1M1

PWM2P1

PWM2M1

P80 to P83

PWM1P2

PWM1M2

PWM2P2

PWM2M2

P84 to P87

PWM1P3

PWM1M3

PWM2P3

PWM2M3

Circuit

type

H

Description

General purpose input output ports.

Stepping motor controller ch.0 output pins.

General purpose input output ports.

Stepping motor controller ch.1 output pins.

General purpose input output ports.

Stepping motor controller ch.2 output pins.

General purpose input output ports.

Stepping motor controller ch.3 output pins.

72 74

P54

General purpose input output port.

G

TX0 CAN interface 0 TX output pin.

73 75

P55

General purpose output port.

G

RX0 CAN interface 0 RX input pin.

74 76

P56 SGO Sound generator SG0 output pin.

General purpose input output port.

G

FRCK Free-run timer clock input pin.

76 78

P57

General purpose input output port.

G

SGA Sound generator SGA output pin.

28 to 31 30 to 33 V0 to V3  LCD controller /driver reference power supply pins.

56, 66 58, 68 DV

51, 61, 71 53, 63, 73 DV

CC 

SS 

High current output buffer with dedicated power supply input pins (pin numbers 54-57, 59-62, 64-67, 69-72) .

High current output buffer with dedicated power supply GND pins

(pin numbers 54-57, 59-62, 64-67, 69-72) . 32 34 AVCC  A/D converter dedicated power supply input pin. 35 37 AV

SS  A/D converter dedicated GND supply pin.

33 35 AVRH  A/D converter Vref + input pin. Vref − AVss.

(Continued)

9

MB90420G/5G (A) Series

(Continued)

Pin no.

Symbol

LQFP QFP

47 48

49 50

MD0 MD1

49 51 MD2 D * Text mode input pin. Connect to V

Circuit

type

B * Test mode input pins. Connect to V

Description

CC.

SS.

25 27 C 

21, 82 23, 84 V

CC  Power supply input pins.

External capacitor pin. Connect an 0.1 µF capacitor between this

pin and V

SS.

9, 40, 79 11, 42, 81 VSS  GND power supply pins.

* : Type C in the flash ROM models.

10

MB90420G/5G (A) Series

I/O CIRCUIT TYPE

■■■■

Type Circuit Remarks

X1

• Oscillation feedback resistance : approx. 1 MΩ

A

X0

Standby control signal

• Pull-up resistance attached : approx. 50 kΩ, hysteresis input

B

Hysteresis input

• Hysteresis input

C

Hysteresis input

• Pull-down resistance attached : approx. 50 kΩ, hysteresis input

Hyteresis input

D

• No pull-down resistance on flash models.

• CMOS output

• LCDC output

• Hysteresis input

E

LCDC output Hysteresis input

(Continued)

11

MB90420G/5G (A) Series

(Continued)

Type Circuit Remarks

• CMOS output

• Hysteresis input

• Analog input

F

Analog input

Hysteresis input

• CMOS output

• Hysteresis input

G

Hysteresis input

• CMOS high current output

• Hysteresis input

High current

H

Hysteresis input

• LCDC output

I

LCDC output

12

MB90420G/5G (A) Series

HANDLING DEVICES

■■■■

When handling semiconductor devices, care must be taken with regard to the following ten matters.

• Strictly observe maximum rated voltages (prevent latchup)

• Stable supply voltage

• Power-on procedures

• Treatment of unused input pins

• Treatment of A/D converter power supply pins

• Use of external clock signals

• Power supply pins

• Proper sequence of A/D converter power supply analog input

• Handling the power supply for high-current output buffer pins (DV

• Pull-up/pull-down resistance

• Precautions when not using a sub clock signal.

Precautions for Handling Semiconductor Devices

• Strictly observe maximum rated voltages (prevent latchup)

CC, DVSS)

When CMOS integrated circuit devices are subjected to applied voltages higher than V pins other than medium- and high-withstand voltage pins, or to voltages lower than V excess of rated le vels are applied between V

CC and VSS, a phenomenon known as latchup can occur . In a latchup

CC at input and output

SS, or when voltages in

condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.

Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AV

Once the digital power supply (V

CC, AVRH, DVCC) and analog input do not exceed the digital power supply (VCC) .

CC) is switched on, the analog power (AVCC,AVRH,DVCC) may be turned on in

any sequence.

• Stable supply voltage

Even within the warranted operating range of V

CC supply voltage, sudden fluctuations in supply voltage can

cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial frequencies (50 to 60 Hz) should be within 10% of the standard V

CC value, and voltage fluctuations that occur during

switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.

• Power-on procedures

In order to prevent abnormal operation of the internal built-in step-down circuits, v oltage rise time during poweron should be attained within 50 µs (0.2 V to 2.7 V) .

• Treatment of unused input pins

If unused input pins are left open, they ma y cause abnormal operation or latchup which may lead to permanent damage to the semiconductor. An y such pins should be pulled up or pulled do wn through resistance of at least 2 kΩ.

Also any unused input/output pins should be left open in output status, or if found set to input status , they should be treated in the same way as input pins.

• Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AV

CC = VCC, and AVSS = AVRH = VSS.

13

MB90420G/5G (A) Series

• Use of external clock signals

Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an e xternal clock is used it should drive only the X0 pin and the X1 pin should be left open, as shown in Figure 3.

X0

OPEN

X1

MB90420G/425G (A) Series

Sample external clock connection

• Power supply pins

Devices are designed to pre vent problems such as latchup when multiple V

CC and VSS supply pins are used, by

providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all such pins should always be connected externally to power supplies and ground.

As shown in Figure 4, all V be handled in the same way. If there are multiple V

CC power supply pins must hav e the same potential. All V SS power supply pins should

CC or VSS systems, the device will not operate properly even

within the warranted operating range.

VCC VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power supply input pins (VCC/VSS)

In addition, care must be given to connecting the V

CC and VSS pins of this device to a current source with as little

impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between V V

SS as close to the pins as possible.

• Proper sequence of A/D converter power supply analog input

A/D converter power (AV (V

CC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off

before the digital power supply is switched on (V AVRH does not exceed AV sure that the input voltage does not exceed AV

CC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply

CC) . In both power-on and shut-off, care should be taken that

CC. Even when pins which double as analog input pins are used as input por ts, be

CC. (There is no problem if analog power supplies and digital

power supplies are turned off and on at the same time.)

14

CC and

MB90420G/5G (A) Series

• Handling the power supply for high-current output buffer pins (DV

CC

, DVSS)

Always apply pow er to high-current output b uffer pins (DV on. Also when switching power off, alw a ys shut off the power supply to the high-current output b uffer pins (DV DV

SS) before s witching off the digital po w er supply (VCC) . (There will be no problem if high-current output buffer

CC, D VSS) after the digital po w er supply (VCC) is turned

CC,

pins and digital power supplies are turned off and on at the same time.) Even when high-current output buff er pins are used as gener al purpose ports, the power for high current output

buffer pins (DV

CC, DVSS) should be applied to these pins.

• Pull-up/pull-down resistance

The MB90420G/5G series does not support inter nal pull-up/pull-down resistance. If necessary, use external components.

• Precautions for when not using a sub clock signal.

If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leav e the X1A pin open.

15

MB90420G/5G (A) Series

BLOCK DIAGRAM

■■■■

X0, X1 X0A, X1A RST

P57/SGA P56/SGO/FRCK P55/RX0 P54/TX0 P53/INT3 P52/INT2 (/TX1) P51/INT1 (/RX1) P50/INT0/ADTG

P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1

P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0

Clock control

circuit

RAM

ROM

Sound generator

CAN controller

Port 5

External interrupt

(8 ch)

UART0/1

Prescaler

Port 0

PPG0/1/2

Port 1

Reload timer

Real-time

Clock timer

ICU0/1/2/3

0/1

CPU

F2MC-16LX core

MC-16LX BUS

2

F

Interrupt

controller

Low voltage

detector reset

Port 8

Stepping

motor

Controller

0/1/2/3

Port 7

Port 6

A/D converter

(8 ch)

Port 9

Port 4

Port 3

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

P67 - P60/ AN7 - AN0

AV

CC/AVSS

AVRH

P91 - P90/

SEG23 - SEG22

P47 - P40/

SEG21 - SEG14

P37 - P36/

SEG13 - SEG12

16

Free-run timer

Evaluation device (MB90V420G) No built-in ROM Built-in RAM is 6 KB.

LCD controller/

driver

SEG11 - SEG0

COM3 - COM0

V3 - V0

MEMORY MAP

■■■■

MB90420G/5G (A) Series

Single chip mode

(with ROM mirror function)

000000H

Peripheral area

0000C0H

000100H

Address #2

003900

004000H

010000H

FF0000H

Address #1

FFFFFFH

Register

RAM area

H

Peripheral area

ROM area

(FF bank image)

ROM area

: Internal access memory : Access prohibited

Parts No. Address #1 Address #2

MB90423G (A) FE0000

H 001900H

MB90427G (A) FF0000H 001100H

MB90428G (A) FE0000H 001900H MB90F423G (A) FE0000H 001900H MB90F428G (A) FE0000H 001900H

MB90V420G FE0000H * 001900H

* : MB90V420G has no built-in ROM. On the tool side this area ma y be considered a R OM

decoder.

Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The

image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example when accessing the address 00C000

H, the actual access is to address FFC000H in ROM. Here the FF bank

ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000 recommended that the ROM data table be stored in the area from FF4000

H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is

H to FFFFFFH.

17

MB90420G/5G (A) Series

I/O MAP

■■■■

• Other than CAN Interface

Address Register name Symbol Read/write Peripheral function Initial value

00

H Port 0 data register PDR0 R/W Port 0 XXXXXXXX

01

H Port 1 data register PDR1 R/W Port 1 - - XXXXXX

02H (Disabled) 03

H Port 3 data register PDR3 R/W Port 3 X X - - - - - -

04

H Port 4 data register PDR4 R/W Port 4 XXXXXXXX

05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06

H Port 6 data register PDR6 R/W Port 6 XXXXXXXX

07

H Port 7 data register PDR7 R/W Port 7 XXXXXXXX

08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09

H Port 9 data register PDR9 R/W Port 9 - - - - - -XX

0A

H to

0F

H

10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0

(Disabled)

11

H Port 1 direction register DDR1 R/W Port 1 - - 0 0 0 0 0 0

12

H (Disabled)

13H Port 3 direction register DDR3 R/W Port 3 0 0 - - - - - 14

H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0

15

H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0

16

H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0

17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0 18

H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0

19

H Port 9 direction register DDR9 R/W Port 9 - - - - - - 0 0

1AH Analog input enable ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1

1B

H to

1F

H

20

H A/D control status register lower ADCSL R/W

(Disabled)

0 0 0 0 0 0 0 0

21H A/D control status register higher ADCSH R/W 0 0 0 0 0 0 0 0

A/D converter

22

H A/D data register lower ADCRL R XXXXXXXX

23

H A/D data register higher ADCRH R/W 0 0 1 0 1 XXX

24H

R/W

XXXXXXXX

Compare clear register CPCLR

25

H R/W XXXXXXXX

18

26

H

Timer data register TCDT

H R/W 0 0 0 0 0 0 0 0

27

R/W 0 0 0 0 0 0 0 0

16-bit free-run timer

28H Timer control status register lower TCCSL R/W 0 0 0 0 0 0 0 0 29

H Timer control status register higher TCCSH R/W 0 - - 0 0 0 0 0

(Continued)

MB90420G/5G (A) Series

Address Register name Symbol Read/write Peripheral function Initial value

2A

H PPG0 control status register lower PCNTL0 R/W

16-bit PPG0

2BH PPG0 control status register higher PCNTH0 R/W 0 0 0 0 0 0 0 -

2C

H PPG1 control status register lower PCNTL1 R/W

16-bit PPG1

2D

H PPG1 control status register higher PCNTH1 R/W 0 0 0 0 0 0 0 -

2E

H PPG2 control status register lower PCNTL2 R/W

16-bit PPG2

2FH PPG2 control status register higher PCNTH2 R/W 0 0 0 0 0 0 0 -

30

H External interrupt enable ENIR R/W

31

H External interrupt request EIRR R/W XXXXXXXX

External interrupt

32H External interrupt level lower ELVRL R/W 0 0 0 0 0 0 0 0 33

H External interrupt level higher ELVRH R/W 0 0 0 0 0 0 0 0

34

H Serial mode register 0 SMR0 R/W

35H Serial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0 36

Input data register 0/

H

Output data register 0

SIDR0/

SODR0

R/W XXXXXXXX

UART 0

0 0 0 0 0 0 0 0

0 0 0 0 0 - 0 0

37

H Serial status register 0 SSR0 R/W 0 0 0 0 1 0 0 0

38H Serial mode register 1 SMR1 R/W 39

H Serial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0

3A 3B

Input data register 1/

H

Output data register 1

H Serial status register 1 SSR1 R/W 0 0 0 0 1 0 0 0

SIDR1/

SODR1

R/W XXXXXXXX

UART1

0 0 0 0 0 − 0 0

3CH (Disabled) 3D

H Clock division control register 0 CDCR0 R/W Prescaler 0 - - - 0 0 0 0

3E

H CAN wake-up control register CWUCR R/W CAN - - - - - - - 0

3FH Clock division control register 1 CDCR1 R/W Prescaler 0 - - - 0 0 0 0

40

H to 4FH Area reserved for CAN interface 0

50

H Timer control status register 0 lower TMCSR0L R/W

51H 52

53

Timer control status register 0 higher

H

Timer register 0/ Reload register 0

H XXXXXXXX

TMCSR0H R/W - - - 0 0 0 0 0

16-bit reload timer 0

TMR0/

TMRLR0

R/W

54H Timer control status register 1 lower TMCSR1L R/W 55 56

57 58H Clock timer control register lower WTCRL R/W 59

Timer control status register 1 high-

H

er

H

Timer register 1/ Reload register 1

H XXXXXXXX

TMCSR1H R/W - - - 0 0 0 0 0

16-bit reload timer 1

TMR1/

TMRLR1

R/W

Real-time

H Clock timer control register higher WTCRH R/W 0 0 0 0 0 0 0 0

clock timer

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 - - 0 0 0

(Continued)

19

MB90420G/5G (A) Series

Address Register name Symbol Read/write Peripheral function Initial value

5A

H Sound control register lower SGCRL R/W

5BH Sound control register higher SGCRH R/W 0 - - - - - 0 0 5C

H Frequency data register SGFR R/W XXXXXXXX

Sound generator

5D

H Amplitude data register SGAR R/W 0 0 0 0 0 0 0 0

5E

H Decrement grade register SGDR R/W XXXXXXXX

5FH Tone count register SGTR R/W XXXXXXXX

0 0 0 0 0 0 0 0

60

H

XXXXXXXX

Input capture register 0 IPCP0 R

61

H XXXXXXXX

Input capture 0/1

62H

XXXXXXXX

Input capture register 1 IPCP1 R

63

H XXXXXXXX

64

H

XXXXXXXX

Input capture register 2 IPCP2 R

65

H XXXXXXXX

Input capture 2/3

66

H

XXXXXXXX

Input capture register 3 IPCP3 R

H XXXXXXXX

67 68H Input capture control status 0/1 ICS01 R/W Input capture 0/1 0 0 0 0 0 0 0 0 69

H (Disabled)

6A

H Input capture control status 2/3 ICS23 R/W Input capture 2/3 0 0 0 0 0 0 0 0

6B

H (Disabled)

6CH LCDC control register lower LCRL R/W 6D

H LCDC control register higher LCRH R/W 0 0 0 0 0 0 0 0

6E

Low voltage detect reset control

H

register

LVRC R/W

LCD controller/

driver

Low voltage detect reset

0 0 0 1 0 0 0 0

1 0 1 1 1 0 0 0

6FH ROM mirror ROMM W ROM mirror XXXXXXX1

70

H to 7FH Area reserved for CAN interface 1

20

80

H PWM control register 0 PWC0 R/W

81H (Disabled) 82

H PWM control register 1 PWC1 R/W

83

H (Disabled)

84H PWM control register 2 PWC2 R/W 85

H (Disabled)

86

H PWM control register 3 PWC3 R/W

87

9D

H to

H

(Disabled)

Stepping motor

controller0

Stepping motor

controller1

Stepping motor

controller2

Stepping motor

controller3

0 0 0 0 0 - - 0

(Continued)

MB90420G/5G (A) Series

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

9E

H ROM correction control register PACSR R/W

9F

H Delay interrupt/release DIRR R/W Delayed interrupt - - - - - - - 0

A0H Power saving mode LPMCR R/W A1

H Clock select CKSCR R/W 1 1 1 1 1 1 0 0

A2

A7

H to

H

(Disabled)

Address match

detection function

Power saving

control circuit

- - - - - 0 - 0

0 0 0 1 1 0 0 0

A8H Watchdog control WDTC R/W Watchdog timer XXXXX 1 1 1 A9

H Time base timer control register TBTC R/W Time base timer 1 - - 0 0 1 0 0

AA

H Clock timer control register WTC R/W

ABH to

AD

H

AE

H Flash control register FMCS R/W Flash interface 0 0 0 X 0 XX 0

AF

H (Disabled)

(Disabled)

B0H Interrupt control register 00 ICR00 R/W B1

H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1

B2

H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1

B3

H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1

Clock timer (sub clock)

1 X 0 0 0 0 0 0

0 0 0 0 0 1 1 1

B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1 B5

H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1

B6

H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1

B7H Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1

Interrupt controller

B8

H Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1

B9

H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1

BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1 BB

H Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1

BC

H Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1

BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1 BE

H Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1

BF

H Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1

C0H to

FF

H

(Disabled)

21

MB90420G/5G (A) Series

Address Register name Symbol Read/write Peripheral function Initial value

1FF0

H ROM correction address 0 PADR0 R/W

1FF1H ROM correction address 1 PADR0 R/W XXXXXXXX 1FF2

H ROM correction address 2 PADR0 R/W XXXXXXXX

1FF3

H ROM correction address 3 PADR1 R/W XXXXXXXX

1FF4

H ROM correction address 4 PADR1 R/W XXXXXXXX

Address match

detection function

1FF5H ROM correction address 5 PADR1 R/W XXXXXXXX

3900

391F

H to

H

(Disabled)

XXXXXXXX

3920

H

PPG0 down counter register PDCR0 R

3921

H 1 1 1 1 1 1 1 1

3922

H

PPG0 cycle setting register PCSR0 W

H XXXXXXXX

3923

16-bit PPG 0

3924H

PPG0 duty setting register PDUT0 W

3925

H XXXXXXXX

3926

3927

H to

H

(Disabled)

3928H

PPG1 down counter register PDCR1 R

3929

H 1 1 1 1 1 1 1 1

392A

H

PPG1 cycle setting register PCSR1 W

H XXXXXXXX

392B

16-bit PPG 1

392CH

PPG1 duty setting register PDUT1 W

392D

H XXXXXXXX

392E

392F

H to

H

(Disabled)

3930H

PPG2 down counter register PDCR2 R

3931

H 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

XXXXXXXX

1 1 1 1 1 1 1 1

XXXXXXXX

1 1 1 1 1 1 1 1

22

3932

H

PPG2 cycle setting register PCSR2 W

H XXXXXXXX

3933 3934

H

16 bit PPG 2

PPG2 duty setting register PDUT2 W

3935

H XXXXXXXX

3936H to

3959

H

(Disabled)

XXXXXXXX

(Continued)

MB90420G/5G (A) Series

Address Register name Symbol Read/write Peripheral function Initial value

395A

H

395B 395C 395D 395E

Sub second data register WTBR R/W

H XXXXXXXX

H - - - XXXXX H Second data register WTSR R/W - - XXXXXX

H Minute data register WTMR R/W - - XXXXXX

Real time

clock timer

XXXXXXXX

395FH Hour data register WTHR R/W - - - XXXXX

3960

396F

3970

397F 3980H

H to

LCD display RAM VRAM R/W

H

H to

H

(Disabled)

LCD controller/

driver

XXXXXXXX

PWM1 compare register 0 PWC10 R/W

3981

H - - - - - - XX

3982

H

PWM2 compare register 0 PWC20 R/W

H - - - - - - XX

3983 3984

H PWM1 select register 0 PWS10 R/W - - 0 0 0 0 0 0

3985

H PWM2 select register 0 PWS20 R/W - 0 0 0 0 0 0 0

3986H to

3987

H

(Disabled)

Stepping motor

controller 0

XXXXXXXX

3988

H

XXXXXXXX

PWM1 compare register 1 PWC11 R/W

3989

H - - - - - - XX

398A

H

PWM2 compare register 1 PWC21 R/W

H - - - - - - XX

398B 398C

H PWM1 select register 1 PWS11 R/W - - 0 0 0 0 0 0

398D

H PWM2 select register 1 PWS21 R/W - 0 0 0 0 0 0 0

398EH to

398F

H

3990

H

(Disabled)

Stepping motor

controller 1

XXXXXXXX

PWM1 compare register 2 PWC12 R/W

3991

H - - - - - - XX

3992H

PWM2 compare register 2 PWC22 R/W

3993

H - - - - - - XX

3994

H PWM1 select register 2 PWS12 R/W - - 0 0 0 0 0 0

Stepping motor

controller 2

XXXXXXXX

3995H PWM2 select register 2 PWS22 R/W - 0 0 0 0 0 0 0

3996

3997

H to

H

(Disabled)

(Continued)

23

MB90420G/5G (A) Series

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

3998

H

XXXXXXXX

PWM1 compare register 3 PWC13 R/W

3999

H - - - - - - XX

399A

H

PWM2 compare register 3 PWC23 R/W

399B

H - - - - - - XX

399C

H PWM1 select register 3 PWS13 R/W - - 0 0 0 0 0 0

Stepping motor

controller 3

XXXXXXXX

399DH PWM2 select register 3 PWS23 R/W - 0 0 0 0 0 0 0

399E

H to

39FF

H

3A00

H to

3AFF

H

3B00H to

3BFF

H

3C00

H to

3CFF

H

3D00

H to

3DFF

H

3E00H to

3EFF

H

Area reserved for CAN interface 0

Area reserved for CAN interface 1

Area reserved for CAN interface 0

Area reserved for CAN interface 1

(Disabled)

• Initial value symbols : “0” initial value 0. “1” initial value 1. “X” initial value undetermined “-” initial value undetermined (none)

• Write/read symbols : “R/W” read/write enabled “R” read only “W” write only

• Addresses in the area 0000

H to 00FFH are reserved for the principal functions of the MCU. Read access

attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.

24

• I/O Map for CAN Interface

Address

CAN0 CAN1

000040

H 000070H

Message buffer valid area BVALR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000041

H 000071H

MB90420G/5G (A) Series

Register name Symbol

Read/

write

Initial value

000042H 000072H 000043

H 000073H

000044H 000074H 000045

H 000075H

000046H 000076H 000047

H 000077H

000048H 000078H 000049

H 000079H

00004AH 00007AH 00004B

H 00007BH

00004CH 00007CH 00004D

H 00007DH

00004EH 00007EH 00004F

H 00007FH

003C00H 003D00H 003C01

H 003D01H

003C02H 003D02H 003C03

H 003D03H

003C04H 003D04H 003C05

H 003D05H

Transmission request register TREQR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Transmission cancel register TCANR (W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Transmission completed register TCR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Receiving completed register RCR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Remote request receiving register RRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Receiving overrun register ROVRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Receiving interrupt enable register RIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Control status register CSR (R/W, R) 0 0 - - - 0 0 0 0 - - - - 0 - 1

Last event indicator register LEIR (R/W) - - - - - - - - 0 0 0 - 0 0 0 0

RX/TX error counter RTEC (R) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C06H 003D06H 003C07

H 003D07H

003C08H 003D08H 003C09

H 003D09H

003C0AH 003D0AH 003C0B

H 003D0BH

003C0CH 003D0CH 003C0D

H 003D0DH

003C0EH 003D0EH 003C0F

H 003D0FH

Bit timing register BTR (R/W) - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IDE register IDER (R/W) XXXXXXXX XXXXXXXX

Transmission RTR register TRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Remote frame receiving wait register RFWTR (R/W) XXXXXXXX XXXXXXXX

Transmission interrupt enable register TIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(Continued)

25

MB90420G/5G (A) Series

Address

CAN0 CAN1

003C10 003C11

H 003D10H H 003D11H

003C12H 003D12H 003C13

H 003D13H

003C14H 003D14H 003C15

H 003D15H

003C16H 003D16H 003C17

H 003D17H

003C18H 003D18H 003C19

H 003D19H

003C1AH 003D1AH 003C1B

003A00H

003A1F

H 003D1BH

to

H

003B00H

to

003B1F 003A20H 003B20H 003A21

H 003B21H

003A22H 003B22H 003A23

H 003B23H

003A24H 003B24H 003A25

H 003B25H

003A26H 003B26H 003A27

H 003B27H

Register name Symbol

Read/

write

Initial value

XXXXXXXX XXXXXXXX

Acceptance mask select register AMSR (R/W)

XXXXXXXX XXXXXXXX

Acceptance mask register 0 AMR0 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

Acceptance mask register 1 AMR1 (R/W)

XXXXX- - - XXXXXXXX

General purpose RAM  (R/W) XXXXXXXX to XXXXXXXX

H

XXXXXXXX XXXXXXXX

ID register 0 IDR0 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 1 IDR1 (R/W)

XXXXX- - - XXXXXXXX

003A28H 003B28H 003A29

H 003B29H

003A2AH 003B2AH 003A2B

H 003B2BH

003A2CH 003B2CH 003A2D

H 003B2DH

003A2EH 003B2EH 003A2F

H 003B2FH

003A30H 003B30H 003A31

H 003B31H

003A32H 003B32H 003A33

H 003B33H

26

XXXXXXXX XXXXXXXX

ID register 2 IDR2 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 3 IDR3 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 4 IDR4 (R/W)

XXXXX- - - XXXXXXXX

(Continued)

MB90420G/5G (A) Series

Address

CAN0 CAN1

003A34 003A35

H 003B34H H 003B35H

003A36H 003B36H 003A37

H 003B37H

003A38H 003B38H 003A39

H 003B39H

003A3AH 003B3AH 003A3B

H 003B3BH

003A3CH 003B3CH 003A3D

H 003B3DH

003A3EH 003B3EH 003A3F

H 003B3FH

003A40H 003B40H 003A41

H 003B41H

003A42H 003B42H 003A43

H 003B43H

Register name Symbol

Read/

write

ID register 5 IDR5 (R/W)

ID register 6 IDR6 (R/W)

ID register 7 IDR7 (R/W)

ID register 8 IDR8 (R/W)

Initial value

XXXXXXXX XXXXXXXX

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXX- - - XXXXXXXX

003A44H 003B44H 003A45

H 003B45H

003A46H 003B46H 003A47

H 003B47H

003A48H 003B48H 003A49

H 003B49H

003A4AH 003B4AH 003A4B

H 003B4BH

003A4CH 003B4CH 003A4D

H 003B4DH

003A4EH 003B4EH 003A4F

H 003B4FH

003A50H 003B50H 003A51

H 003B51H

003A52H 003B52H 003A53

H 003B53H

XXXXXXXX XXXXXXXX

ID register 9 IDR9 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 10 IDR10 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 11 IDR11 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 12 IDR12 (R/W)

XXXXX- - - XXXXXXXX

(Continued)

27

MB90420G/5G (A) Series

Address

CAN0 CAN1

003A54 003A55

H 003B54H H 003B55H

003A56H 003B56H 003A57

H 003B57H

003A58H 003B58H 003A59

H 003B59H

003A5AH 003B5AH 003A5B

H 003B5BH

003A5CH 003B5CH 003A5D

H 003B5DH

003A5EH 003B5EH 003A5F

H 003B5FH

003A60H 003B60H 003A61

H 003B61H

003A62H 003B62H 003A63

H 003B63H

Register name Symbol

Read/

write

Initial value

XXXXXXXX XXXXXXXX

ID register 13 IDR13 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 14 IDR14 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 15 IDR15 (R/W)

XXXXX- - - XXXXXXXX

DLC register 0 DLCR0 (R/W) - - - -XXXX - - - -XXXX

DLC register 1 DLCR1 (R/W) - - - -XXXX - - - -XXXX

003A64H 003B64H 003A65

H 003B65H

003A66H 003B66H 003A67

H 003B67H

003A68H 003B68H 003A69

H 003B69H

003A6AH 003B6AH 003A6B

H 003B6BH

003A6CH 003B6CH 003A6D

H 003B6DH

003A6EH 003B6EH 003A6F

H 003B6FH

003A70H 003B70H 003A71

H 003B71H

003A72H 003B72H 003A73

H 003B73H

003A74H 003B74H 003A75

H 003B75H

DLC register 2 DLCR2 (R/W) - - - -XXXX - - - -XXXX

DLC register 3 DLCR3 (R/W) - - - -XXXX - - - -XXXX

DLC register 4 DLCR4 (R/W) - - - -XXXX - - - -XXXX

DLC register 5 DLCR5 (R/W) - - - -XXXX - - - -XXXX

DLC register 6 DLCR6 (R/W) - - - -XXXX - - - -XXXX

DLC register 7 DLCR7 (R/W) - - - -XXXX - - - -XXXX

DLC register 8 DLCR8 (R/W) - - - -XXXX - - - -XXXX

DLC register 9 DLCR9 (R/W) - - - -XXXX - - - -XXXX

DLC register 10 DLCR10 (R/W) - - - -XXXX - - - -XXXX

(Continued)

28

MB90420G/5G (A) Series

Address

CAN0 CAN1

003A76 003A77

H 003B76H H 003B77H

003A78H 003B78H 003A79

H 003B79H

003A7AH 003B7AH 003A7B

H 003B7BH

003A7CH 003B7CH 003A7D

H 003B7DH

003A7EH 003B7EH 003A7F

003A80H 003A87

003A88

003A8F

003A90 003A87

H 003B7FH

to

H

to

H

to

H

003B80H

to

003B87 003B88H

to

003B8F

003B90H

to

003B97

Register name Symbol

Read/

write

Initial value

DLC register 11 DLCR11 (R/W) - - - -XXXX - - - -XXXX

DLC register 12 DLCR12 (R/W) - - - -XXXX - - - -XXXX

DLC register 13 DLCR13 (R/W) - - - -XXXX - - - -XXXX

DLC register 14 DLCR14 (R/W) - - - -XXXX - - - -XXXX

DLC register 15 DLCR15 (R/W) - - - -XXXX - - - -XXXX

Data register 0 (8 bytes) DTR0 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 1 (8 bytes) DTR1 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 2 (8 bytes) DTR2 (R/W) XXXXXXXX to XXXXXXXX

H

003A98

to

003A9F 003AA0H

to

003AA7 003AA8

to

003AAF 003AB0

to

003AB7 003AB8H

to

003ABF 003AC0

to

003AC7 003AC8

to

003ACF

H

003B98H

003B9F

H

003BA0H

003BA7

H

003BA8H

003BAF

H

003BB0H

003BB7

H

003BB8H

003BBF

H

003BC0H

003BC7

H

003BC8H

003BCF

H

to

Data register 3 (8 bytes) DTR3 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 4 (8 bytes) DTR4 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 5 (8 bytes) DTR5 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 6 (8 bytes) DTR6 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 7 (8 bytes) DTR7 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 8 (8 bytes) DTR8 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 9 (8 bytes) DTR9 (R/W) XXXXXXXX to XXXXXXXX

H

(Continued)

29

MB90420G/5G (A) Series

(Continued)

Address

Register name Symbol

CAN0 CAN1

Read/

write

Initial value

003AD0

to

003AD7 003AD8

to

003ADF 003AE0

to

003AE7 003AE8H

to

003AEF 003AF0

to

003AF7 003AF8

to

003AFF

H

003BD0H

003BD7

H

003BD8H

003BDF

H

003BE0H

003BE7

H

003BE8H

003BEF

H

003BF0H

003BF7

H

003BF8H

003BFF

H

to

Data register 10 (8 bytes) DTR10 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 11 (8 bytes) DTR11 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 12 (8 bytes) DTR12 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 13 (8 bytes) DTR13 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 14 (8 bytes) DTR14 (R/W) XXXXXXXX to XXXXXXXX

H

Data register 15 (8 bytes) DTR15 (R/W) XXXXXXXX to XXXXXXXX

H

30

MB90420G/5G (A) Series

■■■■

INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

2

OS

Interrupt source

EI

compatible

Reset × #08 08 INT9 instruction × #09 09 Exception processing × #10 0A

Interrupt vector

Number Address ICR Address

H FFFFDCH High H FFFFD8H  H FFFFD4H 

CAN0 RX × #11 0BH FFFFD0H CAN0 TX/NS × #12 0CH FFFFCCH CAN1 RX × #13 0DH FFFFC8H CAN1 TX/NS × #14 0EH FFFFC4H Input capture 0 #15 0FH FFFFC0H DTP/external interrupt - ch 0 detected #16 10H FFFFBCH Reload timer 0 #17 11H FFFFB8H DTP/external interrupt - ch 1 detected #18 12H FFFFB4H Input capture 1 #19 13H FFFFB0H DTP/external interrupt - ch 2 detected #20 14H FFFFACH Input capture 2 #21 15H FFFFA8H DTP/external interrupt - ch 3 detected #22 16H FFFFA4H Input capture 3 #23 17H FFFFA0H DTP/external interrupt - ch 4/5 detected #24 18H FFFF9CH

Interrupt control register

ICR00 0000B0H *

ICR01 0000B1H *

ICR02 0000B2H *

ICR03 0000B3H *

ICR04 0000B4H *

ICR05 0000B5H *

ICR06 0000B6H *

1

Priority

2

*

PPG timer 0 #25 19H FFFF98H

ICR07 0000B7H *

1

DTP/external interrupt - ch 6/7 detected #26 1AH FFFF94H PPG timer 1 #27 1BH FFFF90H

ICR08 0000B8H *

1

Reload timer 1 #28 1CH FFFF8CH PPG timer 2 #29 1DH FFFF88H

ICR09 0000B9H *

1

Real time clock timer × #30 1EH FFFF84H Free-run timer over flow × #31 1FH FFFF80H

ICR10 0000BAH *

1

A/D converter conversion end #32 20H FFFF7CH Free-run timer clear × #33 21H FFFF78H

ICR11 0000BBH *

1

Sound generator × #34 22H FFFF74H Time base timer × #35 23H FFFF70H

ICR12 0000BCH *

1

Clock timer (sub clock) × #36 24H FFFF6CH UART 1 RX #37 25H FFFF68H

ICR13 0000BDH *

1

UART 1 TX #38 26H FFFF64H UART 0 RX #39 27H FFFF60H

ICR14 0000BEH *

1

UART 0 TX #40 28H FFFF5CH Flash memory status × #41 29H FFFF58H

ICR15 0000BFH *

1

Delayed interrupt generator module × #42 2AH FFFF54H Low

31

MB90420G/5G (A) Series

2

: Compatible, with EI : Compatible : Compatible when interrupt sources sharing ICR are not in use

× : Not compatible *1 : • Peripheral functions sharing the ICR register have the same interrupt level.

• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other cannot be used.

• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services, the interrupt from the other function cannot be used.

*2 : Priority applies when interrupts of the same level are generated.

OS stop function

32

MB90420G/5G (A) Series

PERIPHERAL FUNCTIONS

■■■■

1. I/O Ports

The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in bit units by the port direction register (DDR) as required. The following list shows each of the functions as well as the shared peripheral function for each port.

• Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG)

• Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/clock timer/ICU)

• Port 3 : General purpose I/O port, shared with peripheral functions (LCD)

• Port 4 : General purpose I/O port, shared with peripheral functions (LCD)

• Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG)

• Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter)

• Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)

• Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)

• Port 9 : General purpose I/O port, shared with peripheral functions (LCD)

(1) List of Functions

Port Pin name

Port 0

Port 1

Port 3

P00/SIN0/INT4 to P07/PPG1

P10/PPG2 to P15/IN0

P36/SEG12 to P37/SEG13

Input

form a t

CMOS

(hysteresis)

Output

form a t

Function bit15 bit14 bit13 bit12

General purpose I/O port 



Peripheral function



General purpose I/O port P15 P14

IN0 IN1

Peripheral function



General purpose I/O port P37 P36  Peripheral function SEG13 SEG12 

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

P40/SEG14 to P47/SEG21

P50/INT0 to P57/SGA

P60/AN0 to P67/AN7

P70/PWM1P0 to P77/PWM2M1

P80/PWM1P2 to P87/PWM2M3

P90/SEG22 to P91/SEG23

Analog CMOS

(hysteresis)

CMOS

(hysteresis)

CMOS

General purpose I/O port  Peripheral function  General purpose I/O port P57 P56 P55 P54

Peripheral function

General purpose I/O port  Peripheral function  General purpose I/O port P77 P76 P75 P74

Peripheral function General purpose I/O port  Peripheral function  General purpose I/O port  Peripheral function 

SGA SGO RX0 TX0

 FRCK 

PWM2M1 PWM2P1 PWM1M1 PWM1P1

33

MB90420G/5G (A) Series

(Continued)

Port bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

P07 P06 P05 P04 P03 P02 P01 P00

Port 0

PPG1 PPG0 SCK1 SOT1 SIN1 SCK0 SOT0 SIN0 TIN1 TOT1 INT7 INT6 INT5 INT4

P13 P12 P11 P10 

Port 1

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

IN2 IN3 WOT PPG2 

 TIN0 TOT0    P47 P46 P45 P44 P43 P42 P41 P40 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14

P53 P52 P51 P50 

INT3 INT2 INT1 INT0 

 TX1 RX1  P67 P66 P65 P64 P63 P62 P61 P60 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

P73 P72 P71 P70 

PWM2M0 PWM2P0 PWM1M0 PWM1P0

P87 P86 P85 P84 P83 P82 P81 P80  P91 P90  SEG23 SEG22 



PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2

Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write

“0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset.

34

(2) Block Diagrams

Ports 0, 1, 3, 4, 5, 7, 8, 9

PDR (Port data register)

MB90420G/5G (A) Series

Peripheral function output

Peripheral function input

Peripheral function output enabled

PDR read

Output latch

Internal data bus

Port 6

PDR write

DDR (Port direction register)

DDR write

DDR read

ADER

PDR (Port data register)

RDR read

Internal data bus

PDR write

DDR (Port direction register)

Direction

latch

Standby control (SPL = 1) or LCD output enabled

Analog input

Output latch

DDR write

DDR read

Direction

latch

Standby control (SPL = 1)

35

MB90420G/5G (A) Series

2. Watchdog Timer/Time Base Timer/Clock Timer

The watchdog timer, timer base timer, and clock timer have the following circuit configuration.

• Watchdog timer : Watchdog counter, control register, watchdog reset circuit

• Time base timer : 18-bit timer, interval interrupt control circuit

• Clock timer : 15-bit timer, interval interrupt control circuit

(1) Watchdog timer function

The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit time base timer or 15-bit clock timer as a clock source, plus a control register and watchdog reset control circuit.

After startup, this function will reset the CPU if not cleared within a given time.

(2) Time base timer function

The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock (base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.

(3) Clock timer function

The clock timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator stabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the cloc k timer uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.

36

•Block Diagram

TBTC

TBC1 TBC0

TBR

TBIE

TBOF

Time base

interrupt

WDTC

WT1

WT0 WTE

AND

Selector

S

QR

Selector

11

2

13

2

16

2

18

2 TBTRES

2-bit

counter

CLR

MB90420G/5G (A) Series

Main base oscillator divided by 2

Clock input

Time base timer

11213216218

2

OF

Watchdog reset generator circuit

CLR

T o WDGRST internal reset generator circuit

WTC

Q

AND

S R

AND

Selector

Q

SGW Power-on reset, sub-clock stop

8

2

9

2

10

2

11

2

12

2

13

S R

2

14

2

16

2 WTRES

2102132142

Clock timer

16

Clock input

WDCS

SCE

MC-16LX bus

2

F

WTC2 WTC0

WTR

WTIE

WTOF

Clock interrupt Sub base oscillator divided by 4

WDTC

PONR

From power-on generator



WRST

ERST SRST

RST pin From RST bit in STBYC

register

37

MB90420G/5G (A) Series

3. Input Capture

This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.

(1) Input capture ( × 4)

The input capture circuits consist of four independent exter nal input pins and corresponding capture registers and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be generated.

• The valid edge (rising edge, falling edge, both edges) of the external signal can be selected.

• The four input capture circuits can operate independently.

• The interrupt can be generated from the valid edge of the external input signal.

(2) 16-bit free-run timer ( × 1)

The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and prescaler. The output values from this counter are used as the base time for the input capture circuits.

• The counter clock operation can be selected from 8 options. The eight internal clock settings are φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle.

• Interrupts can be generated from overflow events, or from compare match events with the compare register. (Compare match operation requires a mode setting.)

• The counter value can be initialized to “0000 register.

H” by a reset, soft clear, or a compare match with the compare

(3) Block diagram

MC-16LX bus

2

F

interrupt #31 (1F

H)

IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0

16-bit free-run timer

16-bit compare clear register Compare circuit

Capture data register 0/2

EG11 EG10 EG01 EG00

Capture data register 1/3

ICP0 ICP1 ICE0 ICE1

Divider

MSI3 ∼ 0

Edge detection

φ

Clock

ICLR

Interrupt #33 (21H)

ICRE

A/D startup

IN0/2

IN1/3

Interrupt #19, #23

Interrupt #15, #21

38

MB90420G/5G (A) Series

4. 16-bit Reload Timer

The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in internal clock mode, or count down at the detection of the designated edge of an external signal. The user may select either function. This timer defines a transition from 0000 underflow occurs when counting from the value [Reload register setting + 1].

A selection of two counter operating modes are av ailable. In reload mode, the counter is reset to the count v alue and continues counting after an underflow, and in one-shot mode the count stops after an underflow . The counter can generate an interrupt when an underflow occurs, and is compatible with the e xpanded intelligent I/O services

2

(EI

OS) .

(1) 16-bit Reload timer operating modes

Clock mode Counter mode 16-bit reload timer operation

Reload mode Soft trigger operation

Internal clock mode

One-shot mode

H to FFFFH as an underflow event. Thus an

External trigger operation

External gate input operation

Event count mode

(external clock mode)

Reload mode

Soft trigger operation

One-shot mode

(2) Internal clock mode

One of three input clocks is selected as the count clock, and can be used in one of the following operations.

• Soft trigger operation When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation starts.Trigger input at the TRG bit is nor mally valid with an external trigger input, as well as an external gate input.

• External trigger operation Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin.

• External gate input operation Counting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin.

(3) Event count mode (External clock mode)

In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at the TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used.

(4) Counter operation

• Reload mode

In down count operation, when an underflow event (transition from “0000

H” to “FFFFH”) occurs, the set count

value is reloaded and count operation continues. The function can be used as an inter val timer by generating an interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can be output from the TOT0/1 pin.

Counter clock Counter clock period Interval time

1

2

/φ (0.125 µs) 0.125 µs to 8.192 ms

Internal clock

External clock 2

3

/φ (0.5 µs) 0.5 µs to 32.768 ms

2

5

2

/φ (2.0 µs) 2.0 µs to 131.1 ms

3

/φ or greater (0.5 µs) 0.5 µs or greater

φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz.

39

MB90420G/5G (A) Series

(5) One-shot mode

In down count operation, the count stops when an underflow event (transition from “0000

H” to “FFFFH”) occurs.

This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave form indicating that the count is in progress can be output form the TOT0 and TOT1 pins.

(6) Block diagram

Internal data bus

TMRLR0 * <TMRLR1>

1

TMR0 * <TMR1>

16-bit timer register (down counter)

Count clock generator circuit

Machine clock φ

Prescaler

Clear

1

16-bit reload register

CLK

Gate input

3

UF

Valid clock

decision circuit

CLK

Reload signal

Reload

control circuit

Wait signal

To UART 0, 1 * <To A/D converter>

1

Internal clock

Pins

P12/TIN0 * <P07/TIN1>

CSL1 CSL0 OUTEOUTL RELD INTE UF CNTE TRG

*1 : Channel 0 and channel 1. Figures in < > are for channel 1. *2 : Interrupt number

Input

control

circuit

1

3 2

Function selection

Timer control status register (TNGSR0)

External clock

Clock

selector Inverted

Select

signal

WOD2WOD1 WOD0

*

Output signal

generator

circuit

EN

Operation

control

circuit

1

Pins

P11/TOT0 * <P06/TOT1>

Interrupt request signal #17 (11h) <#28 (10h)>

2

*

1

40

MB90420G/5G (A) Series

5. Real Time Clock Timer

The real time clock timer is composed of a real time clock timer control register, sub second data register, second/ minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Because the MCU oscillation frequency operates on a given real time clock timer oper ation, a 4 MHz frequency is assumed. The real time clock timer operates as a real world timer and provides real world time information.

•Block diagram

OE

Main oscillator clock

1/2 clock divider

prescaler

EN

Sub second

register

21-bit

CO

OE

WOT

STUPDT

INTE0 INT0

Second

CI

counter

EN LOAD CO CO

6-bit 6-bit 5-bit

Second/minute/hour register

INTE1

INT1 INTE2 INT2 INT3 INT3

Minute

counter

Hour

counter

CO

IRQ

41

MB90420G/5G (A) Series

6. PPG Timer

The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buff er for period setting, and 16-bit compare register with buffer for duty setting, plus pin control circuits.

The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output pulse can be adjusted by rewriting the values in the two 16-bit registers.

(1) PWM function

Programmable to output a pulse, synchronized with a trigger. Can also be used as a D/A converter with an external circuit.

(2) One-shot function

Detects the edge of a trigger input, and outputs a single pulse.

(3) Pin control

• Set to “1” at a duty match (priority) .

• Reset to “0” at a counter borrow event

• Has a fixed output mode to output a simple all “L” ( or “H”) signal.

• Polarity can be specified

(4) 16-bit down counter

• Select from four types of counter operation cloc ks. F our internal clocks (φ, φ/4, φ/16, φ/64) φ : Machine clock cycles.

• The counter value can be initialized to “FFFF

(5) Interrupt requests

• Timer startup

• Counter borrow event (period match)

• Duty match event

• Counter borrow event (period match) or duty match event

(6) Multiple channels can be set to start up at an external trigger, or to restart during operation.

H” at a reset or counter borrow event.

42

(7) Block diagram

Prescaler

1/1

1/4 1/16 1/32

PCSR PDUT

CK

PSCT

16-bit down counter

MB90420G/5G (A) Series

Load

CMP

Machine clock

Trigger input

P05/TRG

Enable

Edge detection

Soft trigger

Start

Borrow

PPG mask

SQ

R

Interrupt selection

PPG output

Inversion bit

Interrupt

43

MB90420G/5G (A) Series

7. Delayed Interrupt Generator Module

The delayed interrupt generator module is a module that generates interrupts for task switching. This module makes it possible to use software to generate/cancel interrupt requests to the F

•Block diagram

F2MC-16LX bus

Delayed interrupt source generate/delete decoder

Source latch

2

MC-16LX CPU.

44

8. DTP/External Interrupt Circuit

MB90420G/5G (A) Series

The DTP (Data transfer peripheral) /e xternal interrupt circuit is located between an externally connected peripheral device and the F

2

MC-16LX CPU and sends interrupt requests or data transfer requests generated from the peripheral device to the CPU, thereby generating e xternal interrupt requests or starting the expanded intelligent I/O services (EI

2

OS) .

(1) DTP/external interrupt function

The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source. And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an external interrupt or start the expanded intelligent I/O service (EI

2

OS) .

When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the

2

EI

OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, then

branching to an interrupt routine after the completion of the specified number of data transfers.

External interrupt DTP function

Input pins 8 pins (P50/INT0 to P53/INT3, P00/INT4 to P03 INT7)

Request level setting register (ELVR) sets the detection level, or selected edge for each pin

Interrupt sources

“H” level/ “L” level/ rising edge/falling edge input

Interrupt numbers #16 (10

H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH)

“H” level/ “L” level input

2

OS) is

Interrupt control DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output Interrupt flags DTP/interrupt enable register (EIRR) stores interrupt sources Process selection When EI

Processing

Branch to external interrupt processing routine

2

OS prohibited (ICR : ISE = 0) When EI2OS is enabled (ICR : ISE = 1)

2

EI

OS performs automatic data transfer, then after a specified number of cycles, branches to an interrupt routine

ICR : Interrupt control register

45

MB90420G/5G (A) Series

(2) Block diagram

Request level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

P03/INT7

P02/INT6

Internal data bus

P01/INT5

P00/INT4

Selector Selector

Selector

Selector Selector

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

Selector

Interrupt request number

P50/INT0

P51/INT1

P52/INT2

P53/INT3

#16 (10H) #18 (12 #20 (14H) #22 (16

#24 (18

H)

H) H)

46

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

#26 (1A

H)

MB90420G/5G (A) Series

9. 8/10-bit A/D Converter

The 8/10-bit A/D converter has functions for using RC sequential comparator con version format to convert analog input voltage into 10-bit or 8-bit digital values . The input signal is selected from 8-channel analog input pins, and the conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input from an external signal pin.

(1) 8/10-bit A/D converter functions

The A/D converter takes analog voltage signals (input v oltage) input at analog input pins, and con v erts these to digital values, providing the following features.

• Minimum conv ersion time is 6.13 µs (at machine clock frequency of 16 MHz, including sampling time) .

• Minimum sampling time is 3.75 µs (at machine clock 16 MHz)

• The conversion method is an RC sequential conversion in comparison with a sample hold circuit.

• Either 10-bit or 8-bit resolution can be selected.

• The analog input pin can select from 8 channels by a program setting.

• At completion of A/D conversion, an interrupt request can be generated, or EI

• Because the conversion data protection function operates in an interrupt enabled state, no data is lost even in continuous conversion.

• The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external trigger input (falling edge) .

2

OS can be started.

Three conversion modes are available

Conversion mode Single conversion operation Scan conversion operation

Converts multiple consecutive channels (up to 8 channels may be specified) one time, then stops.

Converts multiple consecutive channels (up to 8 channels may be specified) repeatedly.

Converts multiple consecutive channels (up to 8 channels may be specified) , however pauses after conversion of each channel, waits until the next start is applied.

Single conversion mode

Continuous conversion

mode

Stop conversion mode

Converts the specified channel (1 channel only) one time, then stops.

Converts the specified channel (1 channel only) repeatedly.

Converts the specified channel (1 channel only) one time, then pauses, waits until the next start is applied.

47

MB90420G/5G (A) Series

(2) Block diagram

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

MPX

Input circuit

Sample & hold circuit

Comparator

Decoder

AVCC

AVRH

AVSS

D/A converter

Sequential comparator

register

A/D data register

ADCRH, L

MC-16LX bus

2

F

16-bit reload timer 1

P50/ADTG

Timer start

Trigger start

φ

A/D control status register, high

A/D control status register, low

ADCSH, L

Operating clock

Prescaler

48

MB90420G/5G (A) Series

10. UART

The UART is a general purpose serial data communication interface for synchronous communication, or asynchronous (start-stop synchronized) communication with external devices. Functions include normal bi-directional functions, as well as master/slave type communication functions (multi-processor mode : master side only supported) .

(1) UART Functions

The UAR T is a general purpose serial data communication interface f or sending and receiving of serial data with other CPU’s or peripheral devices, and provides the following functions.

Functions

Data buffer Full duplex double buffer

Transfer modes

Baud rate

Data length

Signal type NRZ (Non return to zero)

Receiving error detection

Interrupt request

Master/slave type

communication function (multi-processor mode)

Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only.

Operating mode

• Clock synchronous (no start/stop bits)

• Clock asynchronous (start-stop synchronized)

• Exclusive baud rate generator provides a selection of 8 rates

• External clock input enabled

• Internal clock (can use internal clock feed from 16-bit reload timer)

• 7-bit (asynchronous normal mode only)

•8-bit

• Framing errors

• Overrun errors

• Parity errors (not enabled in multiprocessor mode)

• Receiving interrupt (receiving completed, receiving error detection)

• Sending interrupt (sending completed)

• Sending/receiving both compatible with expanded intelligent I/O services

2

(EI

OS)

1 (master) -to-n (slave) communication enabled (only master side supported) .

Data length

No parity Parity

Synchronization Stop bit length

0 Normal mode 7-bit or 8-bit Asynchronous 1 Multi-processor mode 8 + 1 * 2Normal mode 8  Synchronous None

 : Setting not available *1 : “+” indicates an address/data selection bit (A/D) for communication control. *2 : In receiving only one stop bit is detected.

1

 Asynchronous

1-bit or 2-bit *

2

49

MB90420G/5G (A) Series

(2) Block diagram

Exclusive baud rate generator

16-bit reload timer

Pins

P02/SCK0

Clock

selector

Receiving

clock

detection circuit

Receiving

control

circuit

Start bit

Control bus

Sending clock

Sending

control

circuit

Sending start

circuit

Receiving interrupt signals

H) *

#39 (27

<#37 (25H) *>

Sending interrupt signals

#40 (28

<#38 (26H) *>

H) *

Pins

P00/SIN0

Receiving status

judging circuit

SMR0/1

register

Receiving bit

Receiving parity

Receiving

shift register

SIDR0/1

MD1 MD0 CS2 CS1 CS0

SCKE SOE

counter

Rece-

iving

end

Internal data bus

SCR0/1 register

Sending bit

counter

Sending parity

counter

Sending

shift register

SODR0/1

PEN P SBL CL A/D REC RXE TXE

SSR0/1 register

P01/SOT0

Sending start

2

EI

OS receiving error

generator circuit (to CPU)

PE ORE FRE RDRF TDRE BOS RIE TIE

50

∗: Interrupt number

MB90420G/5G (A) Series

11. CAN Controller

The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controller area network) controller is the standard protocol for serial transmissions among automotive controllers and is widely used in the industry.

(1) CAN controller features

The CAN controller has the following features.

• Conforms to CAN specifications version 2.0 A and B. Supports sending and receiving in standard frame and expanded frame format.

• Supports data frame sending by means of remote frame receiving.

• 16 sending/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration

• Supports full bit compare, full bit mask as well as partial bet mask filtering. Provides two receiving mask registers for either standard frame or expanded frame format.

• Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz)

• CAN WAKE UP function

• The MB90420G (A) series has a two-channel built-in CAN controller. The MB90425G (A) series has a 1channel built-in CAN controller.

51

MB90420G/5G (A) Series

(2) Block diagram

F2MC-16LX bus

Machine

clock

PSC

PR

BTR

PH RSJ TOE

TS

RS

CSR

HALT

NIE

NT

NS1,0

RTEC

BVALR

TREQR

TCANR TRTRR RFWTR

TCR TIER RCR RIER

RRTRR ROVRR

AMSR

AMR0 AMR1

IDR0 ~ 15,

DLCR0 ~ 15,

DTR0 ~ 15,

RAM LEIR

Prescaler 1-to-64 frequency divider

Node status change

interrupt generator

TBFx

clear

TBF

TBFx, set, clear

Sending completed

interrupt generator

RBFx, set

Receiving completed

interrupt generator

RBFx, TBFx, set clear

RBFx

set

0 1

RAM address

Send buffer

decision

X

IDSEL

Receiving

filter

generator

Bit timing generator

Node status

change interrupt

Error

control

TBFX

Sending

completed

interrupt

Receiving

completed

interrupt

Receiving bufferx

decision

RBF

X, TBFX, RDLC, TDLC, IDSEL

Data

counter

TDLC RDLC IDSEL

BITER, STFER, CRCER, FRMER, ACKER

X

TQ (operating clock)

SYNC, TSEG1, TSEG2

Send/receive

sequencer

Receiving

filter

control

Send shift

register

CRC

TDLC

Receiving

shift register

ARBLOST

BITER

ACKER

FRMER

generator

CRCER

CRC generator

error check

Acknowledge error

Bus

state

machine

Error

frame

generator

Overload

frame

generator

ARBLOST

Stuffing

ACK

generator

Destuffing/

stuffing

error check

Arbitration

check

Bit error

check

Form error

check

IDLE, SUSPND,

TX, RX, ERR,

OVRLD

Output

driver

STFERRDLC

PH1

Input

latch

TX

RX

52

MB90420G/5G (A) Series

12. LCD Controller/Driver

The LCD controller/driver has a built-in 16 × 8-bit display data memory, and controls the LCD displa y by means of four common outputs and 24 segment outputs. A selection of three duty outputs are a v ailable . This b lock can drive an LCD (liquid crystal display) panel directly.

(1) LCD controller/driver functions

The LCD controller/driver provides functions for directly displa ying the contents of displa y data memory (display RAM) on the LCD panel by means of segment output and common output.

• LCD drive voltage divider resistance is built-in. External divider resistance can also be connected.

• Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used.

• 16-byte display data memory (display RAM) is built-in.

• The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) .

• Drives the LCD directly.

Bias 1/2 duty 1/3 duty 1/4 duty

1/2 bias 1/3 bias ×

: Recommended mode

× : Use prohibited

× ×

Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they

cannot be used for segment output.

53

MB90420G/5G (A) Series

(2) Block diagram

V0 V1 V2 V3

Time base

timer output

Internal data bus

LCDC control register L

(LCRL)

Prescaler

Display RAM,

LCDC control register H

controller

16 × 8 bits

(LCRH)

Timing

24

Divider resistance

4

Common

driver

AC circuit

Segment

driver

COM0 COM1 COM2 COM3

SEG0 SEG1 SEG2 SEG3 SEG4

∼

SEG18 SEG19 SEG20 SEG21 SEG22 SEG23

54

Controller

Driver

MB90420G/5G (A) Series

13. Low voltage/Program Looping Detection Reset Circuit

The Low voltage detection reset circuit is a function that monitors pow er supply voltage in order to detect when a voltage drops below a given voltage level. When a low voltage condition is detected, an inter nal reset signal is generated.

The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal reset signal if not cleared within a given time after startup.

(1) Low voltage detection reset circuit

Detection voltage

4.0 V ± 0.3 V

When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an internal reset signal is output.

Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage condition generates an internal reset and releases stop mode.

During an internal RAM write cycle, an inter nal reset is generated after the completion of writing. During the output of this internal reset, the reset output from the low voltage detection circuit is suppressed.

(2) Program Looping detection reset circuit

The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts automatically after a power-on reset, and must be continually cleared within a giv en time. If the given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has a width of 5 machine cycles.

Interval duration Number of oscillation clock cycles

Approx. 262 ms * 2

* : This value assumes an oscillation clock speed of 4 MHz.

During recovery from standby mode the detection period is the maximum interval plus 20 µs.

This circuit does not operate in modes where CPU operation is stopped. The Program Looping detection reset circuit counter is cleared under any of the following conditions.

1. Writing “0” to the LVRC register CL bit

2. Internal reset

3. Main oscillation clock stop

4. Transition to sleep mode

5. Transition to time base timer mode or clock mode

6. Start of hold

20

cycles

55

MB90420G/5G (A) Series

(3) Block diagram

Program Looping detection circuit

Oscillation clock

Counter

OF

Clear

Voltage comparator circuit

− +

Noise canceller

RESV0 RESV0 RESV1 RESV1 CL LVRF RESV0 CPUF

Low voltage detection reset control register (LVRC)

VCC

VSS

Constant

voltage source

Internal reset

Internal data bus

56

MB90420G/5G (A) Series

14. Stepping Motor Controller

The stepping motor controller is composed of two PWM pulse generators, four motor driv ers and selector logic circuits.

The four motor drivers have a high output drive capacity and can be directly connected to the four ends of two motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse generators.

•Block diagram

Machine clock

OE1

Output enable

Prescaler

P1 P0

SC

CE

CK

PWM1 pulse generator

EN

PWM1 compare register

CK

PWM2 pulse generator

EN

PWM2 compare register

PWM

Selector

PWM1 selector register

OE2

Selector

Load

BS n : 0 ~ 3

PWM2 select register

PWM1Pn

PWM1Mn

Output enable

PWM2Pn

PWM2Mn

57

MB90420G/5G (A) Series

15. Sound Generator

The sound generator is composed of a sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter, and tone pulse counter.

•Block diagram

Clock input

Prescaler

S1 S0

8-bit PWM

pulse generator

Amplitude data

register

Decrement

counter

Decrement grade

register

Tone pulse

counter

CO

EN

PWM

DEC

CO

EN

CO

EN

Frequency

counter

CI

CO

EN

ReloadReload

Frequency data

register

DEC

CI

Toggle

flip-flop

D EN

OE1

Blend

TONE OE2

Q

1/d

SGA

OE1

SGO

OE2

58

Tone count

register

INTE INT ST

IRQ

MB90420G/5G (A) Series

16. Address Match Detect Function

If the address setting is the same as the ROM correction address register, an INT9 instruction is ex ecuted. The ROM correction function can be implemented by processing the INT9 interrupt service routine.

Two address registers are used, each with its own compare enable bit. When there is a match between the address register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is f o rcibly executed by the CPU.

•Block diagram

Address latch

2

F

MC-16LX bus

ROM correction

address register

Enable bit

Compare

2

F

MC-16LX

CPU core

59

MB90420G/5G (A) Series

17. ROM Mirror Function Select Module

The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated to the FF bank to be viewed in the 00 bank.

•Block diagram

2

MC-16LX bus

F

ROM mirror function select register

Address area

FF bank 00 bank

ROM

60

ELECTRICAL CHARACTERISTICS

■■■■

MB90420G/5G (A) Series

1. Absolute Maximum Ratings

Parameter Symbol

V

CC VSS − 0.3 VSS + 6.0 V

AV

CC VSS − 0.3 VSS + 6.0 V AVCC = VCC*

Power supply voltage

VAVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ VAVRH

DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC* Input voltage VI VSS − 0.3 VCC + 0.3 V Output voltage VO VSS − 0.3 VCC + 0.3 V Clamp current I

“L”level maximum output current*

2

“L”level average output current*

3

“L”level maximum total output current

“L”level average total output current

“H”level maximum output current

“H”level average output current

CLAMP −2.0 2.0 mA

IOL1  15 mA Other than P70-P77, P80-P87

IOL2  40 mA P70-77, P80-87 IOLAV1  4 mA Other than P70-P77, P80-P87 I

OLAV2  30 mA P70-77, P80-87

OL1  100 mA Other than P70-P77, P80-P87

ΣI ΣI

OL2  330 mA P70-77, P80-87

OLAV1  50 mA Other than P70-P77, P80-P87

ΣI ΣIOLAV2  250 mA P70-77, P80-87

2

I

OH1*

2

I

OH2*

3

OHAV1*

I

3

IOHAV2*

Rating

Min. Max.

−15 mA Other than P70-P77, P80-P87 −40 mA P70-77, P80-87 −4 mA Other than P70-P77, P80-P87 −30 mA P70-77, P80-87

(VSS

=

AVSS

=

Unit Remarks

1

DVSS

=

0 V)

OH1 −100 mA Other than P70-P77, P80-P87

“H”level maximum total output current

“H”level average total output current

Power consumption P

ΣI ΣI

OH2 −330 mA P70-77, P80-87

4

OHAV1*

ΣI ΣI

4

OHAV2*

D  500 mW

−50 mA Other than P70-P77, P80-P87 −250 mA P70-77, P80-87

Operating temperature TA −40 +105 °C Storage temperature T

*1 : Care must be taken to ensure that AV

STG −55 +150 °C

CC and DVCC do not exceed VCC at power-on etc.

*2 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins. *3 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times “operating factor”.

*4 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times “ operating factor”.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

61

MB90420G/5G (A) Series

2. Recommended Operating Conditions

Parameter Symbol

Power supply voltage

V

CC

AVCC

DVCC

Value

Min. Max.

4.5 5.5 V

3.0 5.5 V

(VSS = DVSS = AVSS = 0.0 V)

Unit Remarks

In normal operation: (MB90F428G/F428GA, MB90428G/428GA, MB90427G/427GA)

Holding stop operation status (MB90F428G, MB90428G, MB90427G)

4.5 5.5 V

Holding stop operation status (MB90F428GA, MB90428GA, MB90427GA)

Use a ceramic capacitor or other capacitor of Smoothing capacitor*

C

S 0.1 1.0 µF

equivalent frequency characteristics. A

smoothing capacitor on the VCC pin should

have a capacitance greater than Cs. Operating

temperature

T

A −40 +105 °C

* : For smoothing capacitor Cs connections, see the illustration below.

• C pin connection

C

S

VSS DVSS

AVSS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

62

3. DC Characteristics

Parameter

Symbol

name

MB90420G/5G (A) Series

(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Conditions

Min. Typ. Max.

Value

Unit Remarks

“H”level input voltage

“L”level input voltage

Power supply current*

3

V

IHS 

VIHM 

ILS 

V

VILM 

ICC

CCS

I

VCC

CTS

I

CCL

I

CCLS



 VCC − 0.3

 VSS − 0.3

Operating frequency F

CP = 16 MHz,

normal operation

Operating frequency F

CP = 16 MHz,

sleep mode

Operating frequency F

CP = 2 MHz,

time base timer mode Operating frequency

F

CP = 8 kHz, TA = 25 °C,

subclock operation Operating frequency

F

CP = 8 kHz, TA = 25 °C,

sub sleep operation

0.8 VCC 



VCC + 0.3

 0.6 VCC V 

VSS + 0.3

 45 72 mA

 38 61 mA

 15 24 mA

 13 21 mA

 0.75 1.0 mA

 0.35 0.7 mA

 40 100 µA

CMOS hysteresis

V

input pin*

VMD pin*

2

CMOS hysteresis input pin*

VMD pin*

2

MB90F428G/GA MB90F423G/GA

MB90428G/GA MB90427G/GA MB90423G/GA

MB90F428G/GA MB90F423G/GA

MB90428G/GA, MB90427G/GA MB90423G/GA

1

Operating frequency

I

CCT

F

CP = 8 kHz, TA = 25 °C,

 40 100 µA

clock mode

*1 : All input pins except X0, X0A, MD0, MD1, MD2 pins. *2 : MD0, MD1, MD2 pins. *3 : Current values are provisional, and ma y be changed without prior notice for purposes of characteristic improve

ment, etc. Supply current values assume external clock f eed from the 1 pin and X1A pin. Users must be a ware that supply current levels differ depending on whether an external clock or oscillator is useed.

(Continued)

63

MB90420G/5G (A) Series

(Continued)

(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter

Power supply current *

3

Input leakage current

Input capacitance 1

Sym

bol

ICCH VCC

IL All input pins

I

C

IN1

Pin name Conditions

TA = 25 °C, stop mode

VCC = DVCC = AVCC = 5.5 V V

SS < VI < VCC

Other than Vcc, Vss, DVcc, DVss, Avcc, Avss, C,

515pF

P70 to P77, P80 to P87

Value

Min. Typ. Max.

 520µA

 40 100 µA

−5  5 µA

Unit Remarks

MB90F428G MB90F423G MB90428G MB90427G MB90423G

MB90F428GA MB90F423GA MB90428GA MB90427GA MB90423GA

Input capacitance 2

Pull-up resistance

Pull-down resistance

Output H voltage 1

Output H voltage 2

Output L voltage 1

Output L voltage 2

R

P70 to P77,

C

IN2

P80 to P87 RST, MD0,

R

UP

MD1

DOWN MD2  25 50 100 kΩ

V

OH1

V

OH2

V

OL1

V

OL2

Other than P70 to P77, P80 to P87

P70 to P77, P80 to P87

Other than P70 to P77, P80 to P87

P70 to P77, P80 to P87

VCC = 4.5 V I

OH = −4.0 mA

VCC = 4.5 V I

OH = −30.0 mA

VCC = 4.5 V I

OL = 4.0 mA

VCC = 4.5 V I

OL = 30.0 mA

15 45 pF

 25 50 100 kΩ

CC −

V

0.5

CC −

V

0.5

V

0.4 V

0.5 V

*3:Current values are provisional, and ma y be changed without prior notice for purposes of characteristic improve

ment, etc. Supply current values assume external clock f eed from the 1 pin and X1A pin. Users must be a ware that supply current levels differ depending on whether an external clock or oscillator is useed.

(Continued)

64

(Continued)

Parameter

Symbol

MB90420G/5G (A) Series

Pin name Conditions

Value

Unit Remarks

Min. Typ. Max.

Large current output drive capacity variation 1

Large current output drive capacity variation 2

LCD divider resistance

COM0 to COM3 output impedance

SEG0 to SEG3 output impedance

LCD leakage current

∆V

R

I

OH2

OL2

LCD

VCOM

VSEG

LCDC

PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3

V0 to V1, V1 to V2, V2 to V3

COMn (n = 0 to 3)

SEGn (n = 00 to 23)

V0 to V3 COMm (m = 00 to 23) SEGn (n = 00 to 23)

V

CC = 4.5 V

I

OH = 30.0 mA

V

OH2 maximum variation

V

CC = 4.5 V

I

OH = 30.0 mA

V

OL2 maximum variation

 50 100 200 kΩ

2.5 kΩ

15 kΩ

−5.0 +5.0 kΩ

0  90 mV *4

*4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simul-

taneously ON. Similarly for other channels.

65

MB90420G/5G (A) Series

4. AC Characteristics

(1) Clock timing (

Parameter Symbol Pin name

F

Base oscillation clock frequency

Base oscillation clock cycle time

Input clock pulse

C X0, X1

F

LC X0A, X1A  32.768  kHz

tCYL X0, X1  250  ns

t

LCYL X0A, X1A  30.5 µs

P

WH, PWL X0 10 ns

width

PWLH, PWLL X0A  15.2 µs

Input clock rise, fall time

Input operating

tcr, tcf X0, X0A  5ns

F

CP  2  16 MHz

clock frequency

FLCP 8.192  kHz Using sub clock

t

Input operating

CP  62.5 — 500 ns

clock cycle time

t

LCP 122.1 µs Using sub clock

Frequency variability ratio*

(locked)

∆f 5 %

V

CC

Condi-

5.0 V±10%

=

tions



V

DV

SS

,

=

AV

SS

=

SS

0.0 V, T

=

Value

Unit Remarks

Min. Typ. Max.

 4  MHz

A

−40 °C to +105 °C)

=

Use duty ratio of 40 to 60% as a guideline

With external clock signal

Using main clock, PLL clock

*: The frequency variability ratio is the maximum proportion of variation from the set central frequency using a

multiplier in locked operation.

+

 α 

∆f = × 100 (%)

fo

Central frequency

+α

fo

−α

−

• X0, X1 clock timing

t

CC

X0

P PLCYL

tcf tcr

0.8 V

0.2 VCC

• X0A, X1A clock timing

tHCYL

CC

X0A

PWH PWL

tcf tcr

0.8 V

0.2 VCC

66

• Range of warranted operation

Relation between internal operating clock frequency and supply voltage

5.5

3.7

3.3

3.0

MB90420G/5G (A) Series

MB90F428GA, MB90428GA, MB90427GA range of warranted operation

PLL range of warranted operation

Supply voltage VCC (V)

MB90F428G, MB90428G, MB90427G range of warranted operation

Internal clock frequency f

CP (MHz)

161282

The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA enter reset mode at supply voltage below 4 V ± 0.3 V.

Relation between oscillator clock frequency and internal operating clock frequency

Internal operating clock frequency

PLL clock

Oscillation clock

frequency

Main clock

4 MHz 2 MHz  8 MHz 12 MHz 16 MHz

Multiplier

× 1

Multiplier

× 2

Multiplier

× 3

Multiplier

× 4

• Sample oscillator circuit

Oscillator

element

Oscillator Frequency C1 C2 R

manufacturer

TBD TBD 4 MHz TBD TBD TBD

X0 X1

R

C2C1

67

MB90420G/5G (A) Series

AC ratings are defined for the following measurement reference voltage values:

• Input signal waveform

• Output signal waveform

Hysteresis input pin

0.8 VCC

0.6 VCC

Output pin

2.4 V

0.8 V

68

(2) Reset input

Parameter Symbol Pin name Conditions

MB90420G/5G (A) Series

(V

CC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Min. Max.

Unit Remarks

Reset input time t

RSTL RST  16 tCP  ns

tRSTL

RST

0.6 VCC

(3) Power-on reset, power on conditions

(V

SS = 0.0 V, TA = −40 °C to +105 °C)

Parameter

Symbol

Power supply rise time t Power supply start voltage V

name

R

OFF  0.2 V

Conditions

Value

Unit Remarks

Min. Max.

0.05 30 ms

VCC 

Power supply attained voltage V

ON 2.7  V

Power supply cutoff time tOFF 50  ms For repeat operation

tR

VCC

Extreme variations in voltage supply may activate a power-on reset. As the illustration below shows, when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however it is permissible to use the PLL clock during a voltage drop of 1mV/s or less.

CC

0 V

V

VSS

5.0 V

4.5 (V) 420G/425G series

3.0 (V) 420GA/425GA series

2.7 V

0.2 V 0.2 V0.2 V

tOFF

A rise slope of 50 mV or less is recommended

RAM data hold

69

MB90420G/5G (A) Series

(4) UART0, UART1 timing

(V

CC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter

Symbol

Pin name

Conditions

Value

Unit Remarks

Min. Max.

Serial clock cycle time t SCK fall to SOT delay time t Valid SIN to SCK rise tIVSH

SCK rise to valid SIN hold time t Serial clock “H” pulse width t

SCYC SCK0, SCK1

SLOV

SCK0, SCK1 SOT0, SOT1

SCK0, SCK1

SHIX 60  ns

SHSL

SIN0, SIN1

SCK0, SCK1

Serial clock “L” pulse width t SCK fall to SOT delay time t Valid SIN to SCK rise t

SCK rise to valid SIN hold time t

SLSH 4 tCP  ns

SLOV

SCK0, SCK1 SOT0, SOT1

IVSH

SCK0, SCK1

SHIX 60  ns

SIN0, SIN1

Notes : • AC ratings are for CLK synchronous mode.

• C

L is load capacitance connected to pin during testing.

• Internal shift clock mode

SCK

0.8 V 0.8 V tSLOV

SOT

2.4 V

0.8 V



tSCYC

8 tCP  ns

−80 80 ns

100  ns

CP  ns

4 t

 150 ns

60  ns

2.4 V

Internal shift clock mode output pin C

L =

80 pF + 1•TTL

External shift clock mode output pin C

L =

80 pF + 1•TTL

70

SIN

• External shift clock mode

SCK

SOT

SIN

tIVSH tSHIX

0.8 V

0.6 VCC

tSLSH tSHSL

0.6 VCC 0.6 VCC tSLOV

2.4 V

0.8 V

tIVSH tSHIX

0.8 V

0.6 VCC

CC

0.8 VCC 0.8 VCC

CC

0.8 VCC

0.6 VCC

0.8 VCC

0.6 VCC

(5) Timer input timing

Parameter Symbol Pin name Conditions

MB90420G/5G (A) Series

(V

CC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Min. Max.

Unit Remarks

TIN0, TIN1,

IN0, IN1, IN2, IN3,

Input pulse width

t

TIWH

tTIWL

• Timer input timing

tTIWH tTIWL

TIN0 ∼ TIN1

IN0 ∼ IN3

0.8 VCC 0.8 VCC

(6) Trigger input timing

(V

Parameter Symbol Pin name Conditions

Input pulse width t

TRGL IRQ0 to IRQ7  5 tCP  ns

 4 t

0.6 VCC 0.6 VCC

CC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

CP  ns

Value

Unit Remarks

Min. Max.

• Trigger input timing

IRQ0 ∼ IRQ7

tTRGH tTRGL

0.8 VCC 0.8 VCC

0.6 VCC 0.6 VCC

71

MB90420G/5G (A) Series

(7) Low voltage detection

Parameter

Symbol

Pin name

Conditions

(V

SS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Min. Typ. Max.

Unit Remarks

Detection voltage V

Hysteresis width V Power supply voltage

fluctuation ratio

dV/dt VCC −0.1  0.02 V/µs

Detection delay time t

VCC

DL VCC

HYS VCC 0.1 V

3.7 4.0 4.3 V



d 35 µs

Internal reset

dV

dt

V

ni

td

VHYS

td

During voltage drop

During voltage rise

72

MB90420G/5G (A) Series

5. A/D Conversion Block

(1) Electrical Characteristics

(V

CC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name

Min. Typ. Max.

Resolution  10 bit Total error  ±5.0 LSB Non-linear error  ±2.5 LSB Differential linear error  ±1.9 LSB

Value

Unit Remarks

Zero transition voltage V Full scale transition

voltage

V

Sampling time t Compare time t

OT AN0 to AN7

FST AN0 to AN7

SMP  2.000 µs*1 CMP  4.125 µs*2

AVSS

− 3.5 LSB AVRH

− 6.5 LSB

SS

AV

+ 0.5 LSB

AVRH

− 1.5 LSB

SS

AV

+ 4.5 LSB

AVRH

+ 1.5 LSB

V

1 LSB = (AVRH − AV

/ 1024

SS)

A/D conversion time tCNV  6.125 µs*3 Analog port

input current

I

AIN AN0 to AN7 10 µAVAVSS = VAIN = VAVCC

Analog input current VAIN AN0 to AN7 0  AVRH V Reference voltage AVR+ AVRH 3.0  AVCC V

Power supply current

Reference voltage feed current

A

AVCC

I

AH  5 µA*4

R AVRH 200 400 600 µAVAVRH = 5.0 V

I

IRH AVRH  5 µA*4

 2.3 6.0 mA

I

Inter-channel variation — AN0 to AN7  4LSB

*1 : At F *2 : At F

CP = 16 MHz, tSMP = 32 × tCP = 2.000 (µs) . CP = 16 MHz, tCMP = 66 × tCP = 4.125 (µs) .

*3 : Equivalent to conversion time per channel at FCP = 16 MHz, and selection of tSMP = 32 × tCP and tCMP = 32 × tCP. *4 : Defined as supply current (when V

CC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in

stop mode.

Notes : •The relative error increases as AVRH is reduced.

•The output impedance (rs) on the external analog input circuit should be used as follows. External circuit output impedance rs = 5 kΩ max.

•If the output impedance on the external circuit is too great, the analog voltage sampling time may be

insufficient.

•If DC inhibitor capacitance is placed between the external circuit and input pin, then a capacitance value

several thousand times the value of the chip internal sampling capacitance (CSH) should be selected in order to suppress the effects of voltage division with CSH.

73

MB90420G/5G (A) Series

• Analog input equivalent circuit

Microcontroller internal circuits

rS

Input pin AN7

VS

External circuits

Input pin AN0

Analog channel selector

CSH

RSH

S/H circuit

Comparator

rs = 5 kΩ or less RSH = approx. 3 kΩ C

SH = approx. 25 pF

Note : These element parameters are intended as guidelines for reference, and are not warranted f or

actual use.

74

MB90420G/5G (A) Series

(2) Definition of terms

• Resolution Indicates the ability of the A/D converter to discriminate in analog conversion. 10-bit resolution indicates that analog voltage can be resolved into 2

• Total error Expresses the difference between actual and logical values. It is the total value of errors that can come from offset error, gain error, non-linearity error and noise.

• Linearity error Expresses the deviation between actual con version char acteristics and a straight line connecting the de vice’s zero transition point (00 0000 0000 ←→ 00 0000 0001) and full scale transition point (11 1111 1110 ←→ 11 1111 1111) .

• Differential linearity error Expresses the deviation of the logical value of input voltage required to create a variation of 1 SLB in output code.

• 10-bit A/D converter conversion characteristics

11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100

10

= 1024 levels.

. . . . . . . .

Digital output

. . . . .

00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000

1 LSB × N + VOT

VOT VNT VFSTV(N + 1)T

Analog input

1 LSB =

Linearity error =

Differential linearity error =

VFST − VOT

1022

V

NT − (1 LSB × N + VOT)

1 LSB

V

(N + 1) T − VNT

1 LSB

Linearity error

[LSB]

− 1

75

MB90420G/5G (A) Series

EXAMPLE CHARACTERISTICS

■■■■

ICC − VCC (TA = +25 °C)

40 35 30 25 20

ICC (mA)

15 10

5 0

3.5 4.5 5.5 V

CCS − VCC (TA = +25 °C)

I

FC = 16 MHz

FC = 11 MHz FC = 8 MHz FC = 5 MHz

FC = 4 MHz FC = 2 MHz

6.5

CC (V)

3.5 3

2.5 2

1.5

ICCS (mA)

1

0.5 0

3.5 4.5 5.5 6.5 VCC (V)

CTS − VCC (TA = +25 °C)

I

900 800 700 600 500 400

ICTS (µA)

300 200 100

0

3.5 4.5 5.5 6.5 VCC (V)

FC = 16 MHz

FC = 11 MHz FC = 8 MHz FC = 5 MHz

FC = 4 MHz FC = 2 MHz

FC = 16 MHz FC = 11 MHz

FC = 8 MHz FC = 5 MHz

FC = 4 MHz FC = 2 MHz

76

(Continued)

MB90420G/5G (A) Series

ICCL − VCC (FC = 8 kHz)

500

400

300

200

ICCL (µA)

100

0

3.5 4.5 5.5 6.5

70 60 50 40 30

ICCLS (µA)

20 10

0

3.5 4.5 5.5 6.5

Ta = 25 °C

Ta = −40 °C

VCC (V)

CCLS − VCC (FC = 8 kHz)

I

Ta = 125 °C

Ta = 25 °C

Ta = −40 °C

VCC (V)

Ta = 125 °C

CCT − VCC (FC = 8 kHz)

I

70 60 50 40 30

ICCT (µA)

20 10

0

3.5 4.5 5.5 6.5

Ta = 125 °C

Ta = 25 °C

Ta = −40 °C

VCC (V)

77

MB90420G/5G (A) Series

INSTRUCTIONS (351 INSTRUCTIONS)

■■■■

Table 1 Explanation of Items in Tables of Instructions

Item Meaning

Mnemonic Upper-case letters and symbols: Represented as they appear in assembler.

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction code. # Indicates the number of bytes. ~ Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG Indicates the number of accesses to the register during execution of the instruction.

B Indicates the correction value for calculating the number of actual cycles during execution of the

Operation Indicates the operation of instruction.

LH Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

AH Indicates special operations involving the upper 16 bits in the accumulator.

I S T N Z V C

RMW Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

It is used calculate a correction value for intermittent operation of CPU. instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed with the value in the “~” column.

Z : Transfers “0”. X : Extends with a sign before transferring. – : Transfers nothing.

* : Transfers from AL to AH. – : No transfer. Z : Transfers 00 X : Transfers 00H or FFH to AH by signing and extending AL.

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. – : No change. S : Set by execution of instruction. R : Reset by execution of instruction.

reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. – : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.

H to AH.

• Number of execution cycles

The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required f or program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is f etched. If data access is interf ered with, theref ore, the n umber of ex ecution cycles is increased.

For each byte of the instruction being e xecuted, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-pow er consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore , add the value of the number of times access is done × the number of cycles suspended as the corrective value to the number of ordinary execution cycles.

78

MB90420G/5G (A) Series

Table 2 Explanation of Symbols in Tables of Instructions

Symbol Meaning

A 32-bit accumulator

The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH

AH

AL SP Stack pointer (USP or SSP)

PC Program counter

PCB Program bank register

DTB Data bank register

ADB Additional data bank register

SSB System stack bank register

USB User stack bank register

SPB Current stack bank register (SSB or USB)

DPR Direct page register

brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB

Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

dir Compact direct addressing

addr16 addr24 ad24 0 to 15 ad24 16 to 23

io I/O area (000000

imm4 imm8 imm16 imm32 ext (imm8)

disp8

disp16

bp Bit offset

vct4 vct8

( )b Bit address

rel PC relative addressing

ear

eam

rlst Register list

Upper 16 bits of A Lower 16 bits of A

Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24

H to 0000FFH)

4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data

8-bit displacement 16-bit displacement

Vector number (0 to 15) Vector number (0 to 255)

Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F)

79

MB90420G/5G (A) Series

Table 3 Effective Address Fields

Code Notation Address format

00 01 02 03 04 05 06 07

08

09 0A 0B

0C 0D 0E 0F

10

11

12

13

14

15

16

17

18

19 1A 1B

R0 R1 R2 R3 R4 R5 R6 R7

RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7

@RW0 @RW1 @RW2 @RW3

@RW0 + @RW1 + @RW2 + @RW3 +

@RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8

@RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16

RL0

(RL0)

RL1

(RL1)

RL2

(RL2)

RL3

(RL3)

Register direct “ea” corresponds to byte, word, and

long-word types, starting from the left

Register indirect

Register indirect with post-increment

Register indirect with 8-bit displacement

Register indirect with 16-bit displacement

Number of bytes in address

extension *

—

0

1

2

1C 1D 1E 1F

Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

80

@RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16

column in the tables of instructions.

Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address

0 0 2 2

MB90420G/5G (A) Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Code Operand

Ri

00 to 07

08 to 0B @RWj 2 1 0C to 0F @RWj + 4 2

10 to 17 @RWi + disp8 2 1

18 to 1B @RWj + disp16 2 1

1C 1D

1E 1F

Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles

Operand

Internal register +0 1 +0 1 +0 2

RWi RLi

@RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16

Number of execution cycles

for each type of addressing

Listed in tables of instructions Listed in tables of instructions

4 4 2 1

(b) byte (c) word (d) long

Cycles Access Cycles Access Cycles Access

Number of register accesses

for each type of addressing

2 2 0 0

Internal memory even address Internal memory odd address

Even address on external data bus (16 bits) Odd address on external data bus (16 bits)

External data bus (8 bits) +1 1 +4 2 +8 4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)

in the tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction Byte boundary Word boundary

Internal memory — +2 External data bus (16 bits) — +3 External data bus (8 bits) +3 —

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for “worst case” calculations.

+0 +0

+1 +1

1 1

+0 +2

+1 +4

1 2

+0 +4

+2 +8

2 4

81

MB90420G/5G (A) Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

Mnemonic # ~

MOV A, dir MOV A, addr16 MOV A, Ri MOV A, ear MOV A, eam MOV A, io MOV A, #imm8 MOV A, @A MOV A, @RLi+disp8 MOVN A, #imm4

MOVX A, dir MOVX A, addr16 MOVX A, Ri MOVX A, ear MOVX A, eam MOVX A, io MOVX A, #imm8 MOVX A, @A MOVX A,@RWi+disp8 MOVX A, @RLi+disp8

MOV dir, A MOV addr16, A MOV Ri, A MOV ear, A MOV eam, A MOV io, A MOV @RLi+disp8, A MOV Ri, ear MOV Ri, eam MOV ear, Ri MOV eam, Ri MOV Ri, #imm8 MOV io, #imm8 MOV dir, #imm8 MOV ear, #imm8 MOV eam, #imm8 MOV @AL, AH /MOV @A, T

2 3 1 2

2+

2 2 2 3 1

2 3 2 2

2+

2 2 2 2 3

2 3 1 2

2+

2 3 2

2+

2

2+

2 3 3 3

3+

2

3 4 2 2

3+ (a)

3 2 3

10

1 3

4 2 2

3+ (a)

3 2 3 5

10

3 4 2 2

3+ (a)

3

10

3

4+ (a)

4

5+ (a)

2 5 5 2

4+ (a)

3

RG

B Operation

byte (A) ← (dir)

(b)

0

byte (A) ← (addr16)

(b)

0

byte (A) ← (Ri)

0

1

byte (A) ← (ear)

0

1

byte (A) ← (eam)

(b)

0

byte (A) ← (io)

(b)

0

byte (A) ← imm8

0

byte (A) ← ((A))

(b)

0

byte (A) ← ((RLi)+disp8)

(b)

2

byte (A) ← imm4

0

byte (A) ← (dir)

(b)

0

byte (A) ← (addr16)

(b)

0

byte (A) ← (Ri)

0

1

byte (A) ← (ear)

0

1

byte (A) ← (eam)

(b)

0

byte (A) ← (io)

(b)

0

byte (A) ← imm8

0

byte (A) ← ((A))

(b)

0

byte (A) ← ((R Wi)+disp8)

(b)

1

byte (A) ← ((RLi)+disp8)

(b)

2

byte (dir) ← (A)

(b)

0

byte (addr16) ← (A)

(b)

0

byte (Ri) ← (A)

0

1

byte (ear) ← (A)

0

1

byte (eam) ← (A)

(b)

0

byte (io) ← (A)

(b)

0

byte ((RLi) +disp8) ← (A)

(b)

2

byte (Ri) ← (ear)

0

2

byte (Ri) ← (eam)

(b)

1

byte (ear) ← (Ri)

0

2

byte (eam) ← (Ri)

(b)

1

byte (Ri) ← imm8

0

1

byte (io) ← imm8

(b)

0

byte (dir) ← imm8

(b)

0

byte (ear) ← imm8

0

1

byte (eam) ← imm8

(b)

0

byte ((A)) ← (AH)

(b)

0

LH AH I S T N Z V C RMW

–

*

–

*

Z

–

*

–

*

Z

–

*

–

*

Z

–

*

–

*

Z

–

*

–

*

Z

–

*

–

*

Z

–

*

–

*

Z

–

*

–

Z

–

*

–

*

Z

–

*

R

–

*

Z

–

*

–

*

X

–

*

–

*

X

–

*

–

*

X

–

*

–

*

X

–

*

–

*

X

–

*

–

*

X

–

*

–

*

X

–

*

–

X

–

*

–

*

X

–

*

–

*

X

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

XCH A, ear XCH A, eam XCH Ri, ear XCH Ri, eam

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

82

2

2+

2

2+

5+ (a)

7

9+ (a)

0 4 2

2× (b)

0

2× (b)

byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam)

byte (A) ↔ (ear)

0

2

4

Z

–

Z

–

MB90420G/5G (A) Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

Mnemonic # ~

MOVW A, dir MOVW A, addr16 MOVW A, SP MOVW A, RWi MOVW A, ear MOVW A, eam MOVW A, io MOVW A, @A MOVW A, #imm16 MOVW A, @RWi+disp8 MOVW A, @RLi+disp8

MOVW dir, A MOVW addr16, A MOVW SP, A MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T

2 3 1 1 2

2+

2 2 3 2 3

2 3 1 1 2

2+

2 2 3 2

2+

2

2+

3 4 4

4+

2

3 4 1 2 2

3+ (a)

3 3 2 5

10

3 4 1 2 2

3+ (a)

3 5

10

3

4+ (a)

4

5+ (a)

2 5 2

4+ (a)

3

RG

BOperation

0

(c)

word (A) ← (dir)

0

(c)

word (A) ← (addr16)

0

word (A) ← (SP)

1

0

word (A) ← (RWi)

1

0

word (A) ← (ear)

0

(c)

word (A) ← (eam)

0

(c)

word (A) ← (io)

0

(c)

word (A) ← ((A))

0

word (A) ← imm16 1 2

0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0

0

word (A) ← ((RWi) +disp8)

(c)

word (A) ← ((RLi) +disp8)

(c) (c)

word (dir) ← (A)

(c)

word (addr16) ← (A)

0

word (SP) ← (A)

0

word (RWi) ← (A)

0

word (ear) ← (A)

(c)

word (eam) ← (A)

(c)

word (io) ← (A)

word ((RWi) +disp8) ← (A)

(c)

word ((RLi) +disp8) ← (A)

(c)

(0)

word (RWi) ← (ear)

(c)

word (RWi) ← (eam)

0

word (ear) ← (RWi)

(c)

word (eam) ← (RWi)

0

word (RWi) ← imm16

(c)

word (io) ← imm16

0

word (ear) ← imm16

(c)

word (eam) ← imm16

(c)

word ((A)) ← (AH)

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

XCHW A, ear XCHW A, eam XCHW RWi, ear XCHW RWi, eam

MOVL A, ear MOVL A, eam MOVL A, #imm32

MOVL ear, A MOVL eam, A

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

2

2+

2

2+

2

2+

5 2

2+

4

5+ (a)

7

9+ (a)

4

5+ (a)

3 4

5+ (a)

2 0 4 2

2 0 0

2 0

0

2× (c)

0

2× (c)

0

(d)

0 0

(d)

word (A) ↔ (ear)

word (A) ↔ (eam)

word (RWi) ↔ (ear)

word (RWi) ↔ (eam)

long (A) ← (ear)

long (A) ← (eam)

long (A) ← imm32

long (ear) ← (A)

long (eam) ← (A)

–

*

–

*

–

*

–

*

–

*

–

83

MB90420G/5G (A) Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

Mnemonic # ~

ADD A,#imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB A, #imm8 SUB A, dir SUB A, ear SUB A, eam SUB ear, A SUB eam, A SUBC A SUBC A, ear SUBC A, eam SUBDC A

ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCWA, ear ADDCWA, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCWA, ear SUBCWA, eam

2 2 2

2+

2

2+

1 2

2+

1 2 2 2

2+

2

2+

1 2

2+

1 1

2

2+

3 2

2+

2

2+

1 2

2+

3 2

2+

2

2+

2 5 3

4+ (a)

3

5+ (a)

2 3

4+ (a)

3 2 5 3

4+ (a)

3

5+ (a)

2 3

4+ (a)

3 2

3

4+ (a)

2 3

5+ (a)

3

4+ (a)

2 3

4+ (a)

2 3

5+ (a)

3

4+ (a)

RG

BOperation

0

byte (A) ← (A) +imm8

0

(b)

byte (A) ← (A) +(dir)

1

0

byte (A) ← (A) +(ear)

0

(b)

byte (A) ← (A) +(eam)

2

0

byte (ear) ← (ear) + (A) 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0

0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0

2× (b)

2× (c)

byte (eam) ← (eam) + (A)

0

byte (A) ← (AH) + (AL) + (C)

0

byte (A) ← (A) + (ear) + (C)

(b)

byte (A) ← (A) + (eam) + (C)

byte (A) ← (AH) + (AL) + (C) (decimal)

0 0

byte (A) ← (A) –imm8

(b)

byte (A) ← (A) – (dir)

0

byte (A) ← (A) – (ear)

(b)

byte (A) ← (A) – (eam)

0

byte (ear) ← (ear) – (A)

byte (eam) ← (eam) – (A)

0

byte (A) ← (AH) – (AL) – (C)

0

byte (A) ← (A) – (ear) – (C)

(b)

byte (A) ← (A) – (eam) – (C)

byte (A) ← (AH) – (AL) – (C) (decimal)

0 0

word (A) ← (AH) + (AL)

0

word (A) ← (A) +(ear)

(c)

word (A) ← (A) +(eam)

0

word (A) ← (A) +imm16

0

word (ear) ← (ear) + (A)

word (eam) ← (eam) + (A)

0

word (A) ← (A) + (ear) + (C)

(c)

word (A) ← (A) + (eam) + (C)

0

word (A) ← (AH) – (AL)

0

word (A) ← (A) – (ear)

(c)

word (A) ← (A) – (eam)

0

word (A) ← (A) –imm16

0

word (ear) ← (ear) – (A)

word (eam) ← (eam) – (A)

0

word (A) ← (A) – (ear) – (C)

(c)

word (A) ← (A) – (eam) – (C)

LH AH I S T N Z V C RMW

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

*

–

Z

–

*

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

*

–

*

Z

–

*

–

Z

–

*

–

Z

–

*

–

Z

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

ADDL A, ear ADDL A, eam ADDL A, #imm32 SUBL A, ear SUBL A, eam SUBL A, #imm32

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

84

2

2+

5 2

2+

5

6

7+ (a)

4 6

7+ (a)

4

2

0

long (A) ← (A) + (ear) 0

(d)

long (A) ← (A) + (eam) 0

0

long (A) ← (A) +imm32 2

0

long (A) ← (A) – (ear) 0

(d)

long (A) ← (A) – (eam) 0

0

long (A) ← (A) –imm32

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

MB90420G/5G (A) Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

Mnemonic # ~

INC ear INC eam

DEC ear DEC eam

INCW ear INCW eam

DECW ear DECW eam

INCL ear INCL eam

DECL ear DECL eam

2+

2

5+ (a)

3

5+ (a)

3

5+ (a)

3

5+ (a)

7

9+ (a)

7

9+ (a)

RG

B Operation

2

0

byte (ear) ← (ear) +1

0

2× (b)

2 0

2× (b)

2 0

2× (c)

2 0

2× (c)

4 0

2× (d)

4 0

2× (d)

byte (eam) ← (eam) +1

0

byte (ear) ← (ear) –1

byte (eam) ← (eam) –1

0

word (ear) ← (ear) +1

word (eam) ← (eam) +1

0

word (ear) ← (ear) –1

word (eam) ← (eam) –1

0

long (ear) ← (ear) +1

long (eam) ← (eam) +1

0

long (ear) ← (ear) –1

long (eam) ← (eam) –1

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

Mnemonic # ~

CMP A CMP A, ear CMP A, eam CMP A, #imm8

CMPW A CMPW A, ear CMPW A, eam CMPW A, #imm16

1 2

2+

2 1

2

2+

3

1 2

3+ (a)

2 1

2

3+ (a)

2

RG

B Operation

0

byte (AH) – (AL)

1

0

byte (A) ← (ear)

0

(b)

byte (A) ← (eam)

0

byte (A) ← imm8

0

word (AH) – (AL)

1

0

word (A) ← (ear)

0

(c)

word (A) ← (eam)

0

word (A) ← imm16

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

CMPL A, ear CMPL A, eam CMPL A, #imm32

2

2+

5

6

7+ (a)

3

2

0

word (A) ← (ear)

0

(d)

word (A) ← (eam)

0

word (A) ← imm32

–

*

–

*

–

*

–

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

85

MB90420G/5G (A) Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

Mnemonic # ~

DIVU A DIVU A, ear DIVU A, eam DIVUW A, ear DIVUW A, eam

MULU A MULU A, ear MULU A, eam

MULUW A MULUW A, ear MULUW A, eam

1 2

2+

2

2+

1 2

2+

1 2

2+

RG

B Operation

1

0

*

2

1

*

3

0

*

4

1

*

5

0

*

8

0

*

9

1

*

10

0

*

0

11

*

1

12

*

0

13

*

word (AH) /byte (AL)

0

Quotient → byte (AL) Remainder → byte (AH)

0

word (A)/byte (ear)

Quotient → byte (A) Remainder → byte (ear)

6

word (A)/byte (eam)

*

Quotient → byte (A) Remainder → byte (eam)

long (A)/word (ear)

0

Quotient → word (A) Remainder → word (ear)

7

long (A)/word (eam)

*

Quotient → word (A) Remainder → word (eam)

byte (AH) *byte (AL) → word (A)

0

byte (A) *byte (ear) → word (A)

0

byte (A) *byte (eam) → word (A)

(b)

word (AH) *word (AL) → long (A)

0

word (A) *word (ear) → long (A)

0

word (A) *word (eam) → long (A)

(c)

LH AH I S T N Z V C RMW

–

*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally. *8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (AH) is zero, and 11 when word (AH) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

–

*

–

*

–

*

–

*

–

*

–

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

86

MB90420G/5G (A) Series

Table 13 Signed Multiplication and Division Instructions (Byte/Wor d/Long Word) [11 Instructions]

RG

Mnemonic # ~

DIV A

DIV A, ear

DIV A, eam

DIVW A, ear

DIVW A, eam

MULU A MULU A, ear MULU A, eam MULUW A MULUW A, ear MULUW A, eam

*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. *2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. *3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. *4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.

Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.

*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for

Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for

*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive , and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is

negative.

2

*1

2

*2

2 +

*3

2

*4

2+

*5

2

*8

2

*9

2 +

*10

2

*11

2

*12

2 +

*13

normal operation.

BOperation

0

word (AH) /byte (AL)

Quotient → byte (AL) Remainder → byte (AH)

1

0

word (A)/byte (ear)

Quotient → byte (A) Remainder → byte (ear)

0

*6

word (A)/byte (eam)

Quotient → byte (A) Remainder → byte (eam)

1

0

long (A)/word (ear)

Quotient → word (A) Remainder → word (ear)

0

*7

long (A)/word (eam)

Quotient → word (A) Remainder → word (eam)

0

byte (AH) *byte (AL) → word (A)

1

0

byte (A) *byte (ear) → word (A)

0

(b)

byte (A) *byte (eam) → word (A)

0

word (AH) *word (AL) → long (A)

1

0

word (A) *word (ear) → long (A)

0

(c)

word (A) *word (eam) → long (A)

LH AH I S T N Z V C RMW

Z

–

*

Z

–

*

Z

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes

two values because of detection before and after an operation.

• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.

• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes” and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”

87

MB90420G/5G (A) Series

Mnemonic # ~

AND A, #imm8 AND A, ear AND A, eam AND ear, A AND eam, A

OR A, #imm8 OR A, ear OR A, eam OR ear, A OR eam, A

XOR A, #imm8 XOR A, ear XOR A, eam XOR ear, A XOR eam, A

NOT A NOT ear NOT eam

ANDW A ANDW A, #imm16 ANDW A, ear ANDW A, eam ANDW ear, A ANDW eam, A

Table 14 Logical 1 Instructions (Byte/Word) [39 Instructions

2 2

2+

2

2+

2 2

2+

2

2+

2 2

2+

2

2+

1 2

2+

1 3 2

2+

2

2+

2 3

4+ (a)

3

5+ (a)

2 3

4+ (a)

3

5+ (a)

2 3

4+ (a)

3

5+ (a)

2 3

5+ (a)

2 2 3

4+ (a)

3

5+ (a)

RG

B Operation

0

byte (A) ← (A) and imm8

1

0

byte (A) ← (A) and (ear)

0

(b)

byte (A) ← (A) and (eam)

2

0

byte (ear) ← (ear) and (A)

0 0

1 0 2 0

0 1 0 2 0

0 2 0

0 0 1 0 2 0

2× (b)

2× (c)

byte (eam) ← (eam) and (A)

0

byte (A) ← (A) or imm8

0

byte (A) ← (A) or (ear)

(b)

byte (A) ← (A) or (eam)

0

byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A)

0

byte (A) ← (A) xor imm8

0

byte (A) ← (A) xor (ear)

(b)

byte (A) ← (A) xor (eam)

0

byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A)

0

byte (A) ← not (A)

0

byte (ear) ← not (ear) byte (eam) ← not (eam)

0

word (A) ← (AH) and (A)

0

word (A) ← (A) and imm16

0

word (A) ← (A) and (ear)

(c)

word (A) ← (A) and (eam)

0

word (ear) ← (ear) and (A) word (eam) ← (eam) and (A)

LH AH I S T N Z V C RMW

–

]

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

–

*

R

–

*

R

–

*

R

–

*

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

ORW A ORW A, #imm16 ORW A, ear ORW A, eam ORW ear, A ORW eam, A

XORW A XORW A, #imm16 XORW A, ear XORW A, eam XORW ear, A XORW eam, A

NOTW A NOTW ear NOTW eam

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

1 3 2

2+

2

2+

1 3 2

2+

2

2+

1 2

2+

2 2 3

4+ (a)

3

5+ (a)

2 2 3

4+ (a)

3

5+ (a)

2 3

5+ (a)

0 0 1 0 2 0

0 2 0

0 0 0

(c)

0

2× (c)

0 0 0

(c)

0

2× (c)

0 0

2× (c)

word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A)

word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A)

word (A) ← not (A) word (ear) ← not (ear) word (eam) ← not (eam)

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

–

*

R

–

*

R

–

*

R

–

*

88

MB90420G/5G (A) Series

Table 15 Logical 2 Instructions (Long Wor d) [6 Instructions]

Mnemonic # ~

ANDL A, ear ANDL A, eam

ORL A, ear ORL A, eam

XORL A, ea XORL A, eam

2

2+

2

2+

2

2+

6

7+ (a)

6

7+ (a)

6

7+ (a)

RG

BOperation

2

0

long (A) ← (A) and (ear)

0

(d)

long (A) ← (A) and (eam)

2

0

long (A) ← (A) or (ear)

0

(d)

long (A) ← (A) or (eam)

2

0

long (A) ← (A) xor (ear)

0

(d)

long (A) ← (A) xor (eam)

LH AH I S T N Z V C RMW

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

*

R

–

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]

Mnemonic # ~

NEG A NEG ear

NEG eam NEGW A

1 2

2+

1

2 3

5+ (a)

2

RG

B Operation

0

byte (A) ← 0 – (A)

2

0

byte (ear) ← 0 – (ear)

0

2× (b)

0

byte (eam) ← 0 – (eam)

0

word (A) ← 0 – (A)

LH AH I S T N Z V C RMW

X

–

*

–

*

–

*

–

*

–

NEGW ear NEGW eam

2

2+

3

5+ (a)

2 0

0

2× (c)

word (ear) ← 0 – (ear) word (eam) ← 0 – (eam)

–

*

–

*

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 17 Normalize Instruction (Long Word) [1 Instruction]

Mnemonic # ~ RG B Operation

NRML A, R0 2

1

1 0 long (A) ← Shift until first digit is “1”

*

LH AH I S T N Z V C RMW

––––––*–– –

byte (R0) ← Current shift count

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

89

MB90420G/5G (A) Series

Table 18 Shift Instructions (Byte/Wor d/Long Word) [18 Instructions]

RG

Mnemonic # ~

RORC A ROLC A

RORC ear RORC eam ROLC ear ROLC eam

ASR A, R0 LSR A, R0 LSL A, R0

ASRWA LSRW A/SHRW A LSL W A/SHLW A

ASRWA, R0 LSRW A, R0 LSLW A, R0

ASRL A, R0 LSRL A, R0 LSLL A, R0

2 2

2

2+

2

2+

2 2 2

1 1 1

2 2 2

2 2

3

5+ (a)

3

5+ (a)

1

*

1

*

1

*

2 2 2

1

*

1

*

1

*

2

*

2

*

2

*

BOperation

0 0

2 0 2 0

1 1 1

0 0 0

1 1 1

2× (b) 2× (b)

byte (A) ← Right rotation with carry

0

byte (A) ← Left rotation with carry

0

byte (ear) ← Right rotation with carry

0

byte (eam) ← Right rotation with carry byte (ear) ← Left rotation with carry

0

byte (eam) ← Left rotation with carry

byte (A) ← Arithmetic right barrel shift (A, R0)

0

byte (A) ← Logical right barrel shift (A, R0)

0

byte (A) ← Logical left barrel shift (A, R0)

0

word (A) ← Arithmetic right shift (A, 1 bit)

0

word (A) ← Logical right shift (A, 1 bit)

0

word (A) ← Logical left shift (A, 1 bit)

0

word (A) ← Arithmetic right barrel shift (A,

0

R0)

0

word (A) ← Logical right barrel shift (A, R0)

0

word (A) ← Logical left barrel shift (A, R0)

long (A) ← Arithmetic right shift (A, R0)

0

long (A) ← Logical right barrel shift (A, R0)

0

long (A) ← Logical left barrel shift (A, R0)

0

*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases.

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

R

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

90

MB90420G/5G (A) Series

Table 19 Branch 1 Instructions [31 Instructions]

Mnemonic # ~

BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel

JMP @A JMP addr16 JMP @ear JMP @eam JMPP @ear * JMPP @eam * JMPP addr24

CALL @ear * CALL @eam * CALL addr16 * CALLV #vct4 * CALLP @ear *

CALLP @eam * CALLP addr24 *

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 3 2

2+

3

2

3

2+

4

2

4

2+

5

3

5

1

6

2

6

2+

7

4

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

* 2

3 3

4+ (a)

5

6+ (a)

4 6

7+ (a)

6 7

10

11+ (a)

10

RG

BOperation

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 0 2 0 0

Branch when (Z) = 1

0

Branch when (Z) = 0

0

Branch when (C) = 1

0

Branch when (C) = 0

0

Branch when (N) = 1

0

Branch when (N) = 0

0

Branch when (V) = 1

0

Branch when (V) = 0

0

Branch when (T) = 1

0

Branch when (T) = 0

0

Branch when (V) xor (N) = 1

0

Branch when (V) xor (N) = 0

0

Branch when ((V) xor (N)) or (Z) = 1

0

Branch when ((V) xor (N)) or (Z) = 0

0

Branch when (C) or (Z) = 1

0

Branch when (C) or (Z) = 0

0

Branch unconditionally

0

word (PC) ← (A)

0

word (PC) ← addr16

0

word (PC) ← (ear)

0

word (PC) ← (eam)

(c)

word (PC) ← (ear), (PCB) ← (ear +2)

0

word (PC) ← (eam), (PCB) ← (eam +2)

(d)

0

word (PC) ← ad24 0 to 15, (PCB) ← ad24 16 to 23

1

(c)

word (PC) ← (ear) 0 0 0 2

2× (c) 2× (c)

2× (c)

word (PC) ← (eam)

(c)

word (PC) ← addr16

Vector call instruction

word (PC) ← (ear) 0 to 15,

(PCB) ← (ear) 16 to 23

2

0

word (PC) ← (eam) 0 to 15,

*

(PCB) ← (eam) 16 to 23 0

2× (c)

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

LH AH I S T N Z V C RMW

–

*1: 4 when branching, 3 when not branching. *2: (b) + 3 × (c) *3: Read (word) branch address. *4: W: Save (word) to stack; R: read (word) branch address. *5: Save (word) to stack. *6: W: Save (long word) to W stack; R: read (long word) R branch address. *7: Save (long word) to stack.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

91

MB90420G/5G (A) Series

Table 20 Branch 2 Instructions [19 Instructions]

Mnemonic # ~

CBNE A, #imm8, rel CWBNEA, #imm16, rel

CBNE ear, #imm8, rel

CBNE eam, #imm8, rel*

CWBNEear, #imm16, rel

CWBNE eam, #imm16, rel*

DBNZ ear , rel DBNZ eam, rel

DWBNZ ear, rel DWBNZ eam, rel

INT #vct8 INT addr16 INTP addr24 INT9 RETI

LINK #imm8

UNLINK

RG

BOperation

1

3 4

4

10

4+

5

10

5+

3

3+

0

*

1

0

*

2

1

*

3

0

*

4

1

*

3

0

*

5

2

*

6

*

2

2× (b)

Branch when byte (A) ≠ imm8

0

Branch when word (A) ≠ imm16

0

Branch when byte (ear) ≠ imm8

0

Branch when byte (eam) ≠ imm8

(b)

Branch when word (ear) ≠ imm16

0

Branch when word (eam) ≠ imm16

(c)

0

Branch when byte (ear) = (ear) – 1, and (ear) ≠ 0 Branch when byte (eam) =

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

(eam) – 1, and (eam) ≠ 0

5

2

3

*

0

Branch when word (ear) =

–

*

–

(ear) – 1, and (ear) ≠ 0

6

2

3+

*

2× (c)

Branch when word (eam) =

–

*

–

*

(eam) – 1, and (eam) ≠ 0

20 16 17 20 15

0

6× (c)

0

6× (c)

0

8× (c)

0 0

0

6

Software interrupt Software interrupt Software interrupt Software interrupt

7

*

Return from interrupt

(c)

At constant entry, save old

–

R

S

–

R

S

–

R

S

–

R

S

–

*

–

2 3 4 1 1

2

8× (c)

frame pointer to stack, set new frame pointer, and allocate local pointer area

(c)

1

0

5

At constant entry , retriev e old

–

frame pointer from stack.

8

RET * RETP *

1

9

4

1

6

(c)

0 0

Return from subroutine

(d)

Return from subroutine

–

*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack

*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

92

–

MB90420G/5G (A) Series

Table 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions]

Mnemonic # ~

PUSHW A PUSHW AH PUSHW PS PUSHW rlst

POPW A POPW AH POPW PS POPW rlst

JCTX @A AND CCR, #imm8

OR CCR, #imm8 MOV RP, #imm8

MOV ILM, #imm8 MOVEA RWi, ear

MOVEA RWi, eam MOVEA A, ear MOVEA A, eam

ADDSP #imm8 ADDSP #imm16

1 1 1 2

1 2

2 2

2+

2

2+

2 3

4 4 4

3

*

3 3 4

2

*

14

3 3

2 2

3

2+ (a)

1

1+ (a)

3 3

RG

B Operation

word (SP) ← (SP) –2, ((SP)) ← (A)

(c)

0

word (SP) ← (SP) –2, ((SP)) ← (AH)

(c)

0

word (SP) ← (SP) –2, ((SP)) ← (PS)

(c)

0

5

4

(SP) ← (SP) –2n, ((SP)) ← (rlst)

*

0 0 0

*

0 0

0 1

1 0 0

0 0

5

6× (c)

word (A) ← ((SP)), (SP) ← (SP) +2

(c)

word (AH) ← ((SP)), (SP) ← (SP) +2

(c)

word (PS) ← ((SP)), (SP) ← (SP) +2

(c)

4

(rlst) ← ((SP)), (SP) ← (SP) +2n

*

Context switch instruction byte (CCR) ← (CCR) and imm8

0

byte (CCR) ← (CCR) or imm8

0

byte (RP) ←imm8

0

byte (ILM) ←imm8

0

word (RWi) ←ear

0

word (RWi) ←eam

0

word(A) ←ear

0

word (A) ←eam

0

word (SP) ← (SP) +ext (imm8)

0

word (SP) ← (SP) +imm16

0

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

MOV A, brgl MOV brg2, A

NOP ADB DTB PCB SPB NCC CMR

1

2 2

1 1 1 1 1 1 1

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

byte (A) ← (brgl)

0

byte (brg2) ← (A)

0

No operation

0

Prefix code for accessing AD space

0

Prefix code for accessing DT space

0

Prefix code for accessing PC space

0

Prefix code for accessing SP space

0

Prefix code for no flag change

0

Prefix code for common register bank

0

Z

*

–

*

–

*

–

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states *2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count × (c), or push count × (c) *5: Pop count or push count.

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

93

MB90420G/5G (A) Series

Table 22 Bit Manipulation Instructions [21 Instructions]

Mnemonic # ~

MOVB A, dir :bp MOVB A, addr16:bp MOVB A, io:bp

MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A

SETB dir:bp SETB addr16:bp SETB io:bp

CLRB dir:bp CLRB addr16:bp CLRB io:bp

BBC dir:bp, rel BBC addr16:bp, rel BBC io:bp, rel

BBS dir:bp, rel BBS addr16:bp, rel BBS io:bp, rel

SBBS addr16:bp, rel

RG

B Operation

3

5

0

(b)

byte (A) ← (dir:bp) b

4

5

0

(b)

byte (A) ← (addr16:bp) b

3

4

0

(b)

byte (A) ← (io:bp) b

3

7

0

2× (b)

4

7

0

2× (b)

3

6

0

2× (b)

3

7

0

2× (b)

4

7

0

2× (b)

3

7

0

2× (b)

3

7

0

2× (b)

4

7

0

2× (b)

3

7

0

2× (b)

1

4 5 4

5

0

*

1

0

*

2

0

*

1

0

*

1

0

*

2

0

*

3

0

*

2× (b)

bit (dir:bp) b ← (A) bit (addr16:bp) b ← (A) bit (io:bp) b ← (A)

bit (dir:bp) b ← 1 bit (addr16:bp) b ← 1 bit (io:bp) b ← 1

bit (dir:bp) b ← 0 bit (addr16:bp) b ← 0 bit (io:bp) b ← 0

(b)

Branch when (dir:bp) b = 0

(b)

Branch when (addr16:bp) b = 0

(b)

Branch when (io:bp) b = 0

(b)

Branch when (dir:bp) b = 1

(b)

Branch when (addr16:bp) b = 1

(b)

Branch when (io:bp) b = 1

Branch when (addr16:bp) b = 1, bit = 1

LH AH I S T N Z V C RMW

Z

*

–

*

–

Z

*

–

*

–

Z

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

* WBTS io:bp WBTC io:bp

4

3

*

4

*

3

5

0 0

Wait until (io:bp) b = 1

*

5

Wait until (io:bp) b = 0

*

–

*1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: Undefined count *5: Until condition is satisfied

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 23 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

Mnemonic # ~

SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW

RG

BOperation

1

3

0

byte (A) 0 to 7 ↔ (A) 8 to 15

1

2

0

word (AH) ↔ (AL)

1

0

byte sign extension

1

2

0

word sign extension

1

0

byte zero extension

1

0

word zero extension

LH AH I S T N Z V C RMW

–

*

–

X

–

*

–

X

–

*

–

Z

–

R

*

–

Z

–

R

*

–

Note: For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles fo r Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

94

MB90420G/5G (A) Series

Table 24 String Instructions [10 Instructions]

Mnemonic # ~

MOVS/MOVSI MOVSD

SCEQ/SCEQI SCEQD

FISL/FILSI MOVSW/MOVSWI

MOVSWD SCWEQ/SCWEQI

SCWEQD FILSW/FILSWI

2 2

2

*

2

*

1

*

1

*

6m +6

2

*

2

*

1

*

1

*

6m +6

RG

BOperation

5

3

Byte transfer @AH+ ← @AL+, counter = RW0

*

5

3

* *

*

Byte transfer @AH– ← @AL–, counter = RW0

*

5

4

Byte retrieval (@AH+) – AL, counter = RW0

*

5

4

Byte retrieval (@AH–) – AL, counter = RW0

*

Byte filling @AH+ ← AL, counter = RW0

5

3

*

8

6

Word transfer @AH+ ← @AL+, counter = RW0

*

8

6

Word transfer @AH– ← @AL–, counter = RW0

*

8

7

Word retrieval (@AH+) – AL, counter = RW0

*

8

7

Word retrieval (@AH–) – AL, counter = RW0

*

Word filling @AH+ ← AL, counter = RW0

8

6

*

LH AH I S T N Z V C RMW

–

*

–

*

–

*

–

*

–

*

–

*

–

m: RW0 value (counter value) n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case *3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-

rately for each. *4: (b) × n *5: 2 × (RW0) *6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)

separately for each. *7: (c) × n *8: 2 × (RW0)

– –

Note : For an e xplanation of “(a)” to “(d)”, refer to T ab le 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

95

MB90420G/5G (A) Series

ORDERING INFORMATION

■■■■

Part number Package Remarks

MB90F428GAPF MB90F423GAPF MB90428GAPF MB90427GAPF MB90423GAPF MB90F428GPF MB90F423GPF MB90428GPF MB90427GPF MB90423GPF

MB90F428GAPFV MB90F423GAPFV MB90428GAPFV MB90427GAPFV MB90423GAPFV MB90F428GPFV MB90F423GPFV MB90428GPFV MB90427GPFV MB90423GPFV

Plastic QFP, 100-pin

(FPT-100P-M06)

Plastic LQFP, 100-pin

(FPT-100P-M05)

96

PACKAGE DIMENSIONS

■■■■

Plastic QFP, 100-pin

(FPT-100P-M06)

MB90420G/5G (A) Series

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

81

INDEX

100

LEAD No.

C

1994 FUJITSU LIMITED F100008-3C-2

1

0.65(.0256)TYP 0.30±0.10

18.85(.742)REF

22.30±0.40(.878±.016)

(.012±.004)

0.10(.004)

"A"

0.13(.005)

5180

50

(.551±.008) (.705±.016)

31

30

M

Details of "A" part

"B"

17.90±0.4014.00±0.20

0.18(.007)MAX

0.53(.021)MAX

0.25(.010)

0.30(.012)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN (STAND OFF)

12.35(.486) REF

0.15±0.05(.006±.002)

Details of "B" part

16.30±0.40 (.642±.016)

0 10°

0.80±0.20

(.031±.008)

Dimensions in mm (inches)

(Continued)

97

MB90420G/5G (A) Series

(Continued)

Plastic LQFP, 100-pin

(FPT-100P-M05)

16.00±0.20(.630±.008)SQ

75 51

14.00±0.10(.551±.004)SQ

INDEX

100

LEAD No.

1

0.50(.0197)TYP

"A"

0.18 .007 –.001

+0.08 –0.03

+.003

0.10(.004)

C

1995 FUJITSU LIMITED F100007S-2C-3

5076

26

25

0.08(.003)

+0.20 –0.10

1.50 .059 –.004

+.008

(.472)

REF

(Mouting height)

15.0012.00

(.591)

NOM

Details of "A" part

0.15(.006)

0.15(.006)MAX

"B"

+0.05 –0.02

M

0.127 .005

+.002 –.001

Details of "B" part

0~10°

Dimensions in mm

0.40(.016)MAX

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

(inches)

98

MB90420G/5G (A) Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608 Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220

http://www.fmap.com.sg/

Korea

FUJITSU MICROELECTRONICS K OREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.

F0012

 FUJITSU LIMITED Printed in Japan

FUJITSU MB90420G, MB90425G (A) DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual