The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed f or automotiv e
and industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and
Part B, while supporting a very flexible message buffer scheme and so off ering more functions than a normal full
CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program
memory up to 512 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F
■■■■
2
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
PACKAGES
100-pin Plastic QFP100-pin Plastic LQFP
(FPT-100P-M06) (FPT-100P-M05)
MB90340 Series
FEATURES
■■■■
••••
Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allow ed among frequency division by two on oscillation cloc k, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without Ssuffix only)
• Minimum ex ecution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied PLL clock).
••••
16 Mbyte CPU memory space
• 24-bit internal addressing
••••
Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
••••
Instruction system compatible with high-level language (C language) and multitask
Boot-block, Flash memory
512 Kbytes : MB90F345/C (S)
384 Kbytes : MB90F343/C (S)
256 Kbytes : MB90F342/C (S) , MB90F349/C (S) , MB90342/C (S) ,
MB90349/C (S)
128 Kbytes : MB90F347A (S) , MB90F347CA (S) , MB90341/C (S) ,
MB90348/C (S) , MB90347A (S) , MB90347CA (S)
64 Kbytes : MB90F346A (S) , MB90F346CA (S) , MB90346A (S)
MB90346CA (S)
20 Kbytes : MB90F343/C (S) , MB90F345/C (S)
16 Kbytes : MB90F342/C (S) , MB90F349/C (S) , MB90341/C (S) ,
MB90342/C (S) , MB90348/C (S) , MB90349/C (S)
6 Kbytes : MB90F347A (S) , MB90F347CA (S) , MB90347A (S) ,
MB90347CA (S)
2 Kbytes : MB90F346A (S) , MB90F346CA (S) , MB90346A (S) ,
MB90346CA (S)
Yes
0.35 µm CMOS with on-chip voltage regulator for internal
power supply + Flash memory with
On-chip charge pump for programming voltage
3.5 V - 5.5 V : at normal operating (not using A/D converter)
4.0 V - 5.5 V : at using A/D converter/Flash programming
4.5 V - 5.5 V : at using external bus
MB90V340(S)
External
30 Kbytes
0.35 µm CMOS with
on-chip voltage
regulator for internal
power supply
5 V ± 10%
Temperature range−40 °C to +105 °C
PackageQFP-100, LQFP-100PGA-299
4 channels5 channels
UART
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2
C (400 kbit/s)
I
A/D
Converter
devices with ‘C’-suffix : 2ch
devices without ‘C’-suffix :
devices with ‘C’-suffix : 24ch
devices without ‘C’-suffix : 16ch
10-bit or 8-bit resolution
2 channel
24 input channels
Conversion time : Min 3 µs include sample time (per one channel)
1
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/2
Supports External Event Count function
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/2
1
, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
2 channels : MB90F342/C (S) , MB90F343/C (S) , MB90F345/C (S) ,
MB90341/C (S) , MB90342/C (S)
1channel : MB90F346A (S) , MB90F346CA (S) , MB90F347A(S) ,
MB90F347CA (S) , MB90F349/C (S) , MB90346A (S) ,
3 channels
MB90346CA (S) , MB90347A (S) , MB90347CA (S) ,
MB90348/C (S) , MB90349/C (S)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
External Interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded inteligent I/O services (EI
2
OS) and DMA
D/A converter2 channels
Up to100 kHz
Subclock for low
power operation
devices with ‘S’-suffix : with subclock
devices without ‘S’-suffix : without subclock
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
(Continued)
5
MB90340 Series
(Continued)
Part Number
Parameter
Flash
Memory
ROM SecurityProtects the content of ROM (MASK ROM device only)
*1 : The devices other than MB90F342/C (S) , MB90F345/C (S) , MB90F346A (S) , MB90F346CA (S) ,
MB90F347A (S) , MB90F347CA (S) , MB90F349/C (S) , MB90346A (S) , MB90346CA (S) , MB90347A (S)
and MB90347CA (S) are under development.
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (except for
MB90F346A(S) and MB90F346CA (S) )
MB90V340(S)
*2 : It is setting of Jumper switch (TOOL V
CC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
AD00 to AD07
INT8 to INT15External interrupt request input pins for INT8 to INT15.
P10
AD08
TIN1Event input pin for the reload timer 1
P11
AD09
TOT1Output pin for the reload timer 1
P12
AD10
SIN3Serial data input pin for UART3
INT11RSub external interrupt request input pin for INT11
P13
AD11
SOT3Serial data output pin for UART3
P14
AD12
SCK3Clock I/O pin for UART3
Circuit
type
Oscillation output
A
EReset input
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
G
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
G
I/O pin for 8th bit of the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
G
I/O pin for 9th bit of the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
I/O pin for 10th bit of the external address/data bus.
N
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
G
I/O pin for 11th bit of the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
G
I/O pin for 12th bit of the external address/data bus.
This function is enabled when the external bus is enabled.
Function
(Continued)
13
MB90340 Series
Pin No.
LQFP100
95 to 9897 to 100
99 to 21 to 4
*2
QFP100
9294
9395
9496
35
Pin name
*1
P15
AD13
SIN4Serial data input pin for UART4 (MB90V340 only)
P16
AD14
SOT4Serial data output pin for UART4 (MB90V340 only)
P17
AD15
SCK4Clock I/O pin for UART4 (MB90V340 only)
P20 to P23
A16 to A19
PPG9,PPGB,
PPGD,PPGF
P24 to P27
A20 to A23
IN0 to IN3Data sample input pins for input captures ICU0 to ICU3
P30
ALE
IN4Data sample input pin for input capture ICU4
Circuit
type
G
G
G
G
G
G
Function
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
I/O pin for 13th bit of the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
I/O pin for 14th bit of the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
I/O pin for 15th bit of the external address/data bus. This function is enabled when the external bus is enabled.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
Output pins for A16 to A19 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
Output pins for PPGs
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
Output pins for A20 to A23 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A20 to A23).
General purpose I/O.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
Address latch enable output pin. This function is enabled when
the external bus is enabled.
(Continued)
14
MB90340 Series
Pin No.
LQFP100
*2
QFP100
46
57
68
79
810
911
Pin name
*1
P31
RD
IN5Data sample input pin for input capture ICU5
P32
/ WR
WRL
RX2RX input pin for CAN2 Interface (MB90V340 only)
INT10RSub external interrupt request input pin for INT10
P33
WRH
TX2TX Output pin for CAN2 (MB90V340 only)
P34
HRQ
OUT4Waveform output pin for output compare OCU4
P35
HAK
OUT5Waveform output pin for output compare OCU6
P36
RDY
OUT6Waveform output pin for output compare OCU5
Circuit
type
G
G
G
G
G
G
General purpose I/O.The register can be set to select whether to
use a pull-up resistor.This function is enabled in single-chip
mode.
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the WR
Write strobe output pin for the data bus. This function is enabled
when both the external bus and the WR
abled. WRL
16-bit access while WR
bus in 8-bit access.
General purpose I/O. The register can be set to select whether to
use a pull-up resistor.This function is enabled either in single-chip
mode or with the WRH
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the
external bus 16-bit mode is selected, and when the WRH output
pin is enabled.
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the hold function disabled.
Hold request input pin. This function is enabled when both the external bus and the hold function are enabled.
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the hold function disabled.
Hold acknowledge output pin. This function is enabled when both
the external bus and the hold function are enabled.
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the external ready function disabled.
Ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
is used to write-strobe 8 lower bits of the data bus in
Function
/WRL pin output disabled.
is used to write-strobe 8 bits of the data
pin output disabled.
/WRL pin output are en-
(Continued)
15
MB90340 Series
Pin No.
LQFP100
*2
QFP100
1012
11 to 1213 to 14
1618
1719
1820
1921
2022
2123
2224
2325
2426
2527
*1
Pin name
Circuit
type
Function
General purpose I/O. The register can be set to select whether
P37
to use a pull-up resistor. This function is enabled either in
single-chip mode or with the CLK output disabled.
G
CLK
CLK output pin. This function is enabled when both the
external bus and CLK output are enabled.
OUT7Waveform output pin for output compare OCU7
P40 to P41FGeneral purpose I/O (devices with S-suffix)
X0A , X1ABOscillator input pins for sub-clock (devices without S-suffix)
P42
General purpose I/O
IN6Data sample input pin for input capture ICU6
F
RX1
RX input pin for CAN1 Interface
(MB90F342/F343/F345/341/342 only)
INT9RSub external interrupt request input pin for INT10
P43
IN7Data sample input pin for input capture ICU7
General purpose I/O
F
TX1TX Output pin for CAN1 (MB90F342/F343/F345/341/342 only)
P44
SDA0Serial data I/O pin for I2C 0 (devices with C-suffix)
General purpose I/O
H
FRCK0Input for the 16-bit I/O Timer 0
P45
SCL0Serial clock I/O pin for I2C 0 (devices with C-suffix)
General purpose I/O
H
FRCK1Input for the 16-bit I/O Timer 1
P46
General purpose I/O
H
SDA1Serial data I/O pin for I2C 1 (devices with C-suffix)
P47
SCL1Serial clock I/O pin for I
P50
AN8Analog input pin for the A/D converter
General purpose I/O
H
General purpose I/O
O
2
C 1 (devices with C-suffix)
SIN2Serial data input pin for UART2
P51
AN9Analog input pin for the A/D converter
General purpose I/O
I
SOT2Serial data output pin for UART2
P52
AN10Analog input pin for the A/D converter
General purpose I/O
I
SCK2Clock I/O pin for UART2
P53
AN11Analog input pin for the A/D converter
General purpose I/O
I
TIN3Event input pin for the reload timers 3
(Continued)
16
MB90340 Series
Pin No.
LQFP100
28, 2930, 31
34 to 4136 to 43
43 to 48,
53, 54
*2
QFP100
2628
2729
45 to 50,
55, 56
5557
5658
5759
5860
5961
6062
6163
Pin name
*1
P54
AN12Analog input pin for the A/D converter
TOT3Output pin for the reload timer 3
P55
AN13Analog input pin for the A/D converter
P56 to P57
AN14 to AN15Analog input pin for the A/D converter
DA00 to DA01D/A converter analog output pins (MB90V340 only)
P60 to P67
AN0 to AN7Analog input pins for the A/D converter
PPG0, 2, 4, 6,
8, A, C, E
P70 to P77
AN16 to AN23Analog input pins for the A/D converter (devices with C-suffix)
INT0 to INT7External interrupt request input pins for INT0 to INT7
P80
TIN0Event input pin for the reload timers 0
ADTGTrigger input pin for the A/D converter
INT12RSub external interrupt request input pin for INT12
P81
TOT0Output pin for the reload timer 0
CKOTOutput pin for the clock monitor
INT13RSub external interrupt request input pin for INT13
P82
SIN0Serial data input pin for UART0
TIN2Event input pin for the reload timers 2
INT14RSub external interrupt request input pin for INT14
P83
SOT0Serial data output pin for UART0
TOT2Output pin for the reload timer 2
P84
SCK0Clock I/O pin for UART0
INT15RSub external interrupt request input pin for INT15
P85
SIN1Serial data input pin for UART1
P86
SOT1Serial data output pin for UART1
Circuit
type
I
I
J
I
I
F
F
M
F
F
M
F
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
Output pins for PPGs
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
Function
(Continued)
17
MB90340 Series
(Continued)
Pin No.
LQFP100
*2
QFP100
*1
Pin name
P87
6264
SCK1Clock I/O pin for UART1
P90 to P93
65 to 6867 to 70
PPG1, 3, 5, 7Output pins for PPGs
P94 to P97
69 to 7271 to 74
OUT0 to
OUT3
PA0
7375
RX0RX input pin for CAN0 Interface
INT8RSub external interrupt request input pin for INT8
PA1
7476
TX0TX Output pin for CAN0
3032AV
CCKVcc power input pin for analog circuits
3133AVRHL
3234AVRLKLower reference voltage input for the A/D Converter
3335AV
SSKVss power input pin for analog circuits
50, 5152, 53MD1, MD0C
4951MD2D
13
63
88
14
42
64
89
15
65
90
16
44
66
91
CCPower (3.5 V to 5.5 V) input pins
V
SSPower (0V) input pins
V
1517CK
Circuit
type
F
F
F
F
F
Function
General purpose I/O
General purpose I/O
General purpose I/O
Waveform output pins for output compares OCU0 to OCU3.
This function is enabled when the OCU enables waveform
output.
General purpose I/O
General purpose I/O
Reference voltage input for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or
equal to AVRH is applied to AV
CC.
Input pins for specifying the operating mode. The pins must be
directly connected to Vcc or Vss
Input pin for specifying the operating mode. The pins must be
directly connected to Vcc or Vss.
This is the power supply stabilization capacitor pin. It should be
connected to a higher than or equal to 0.1 µF ceramic capacitor.
• CMOS inputs (With the standby-time
input shutdown function)
OL = 4 mA, IOH= −4 mA)
• Automotive input (With the standby-time
Nout
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
input shutdown function)
• A/D analog input
HANDLING DEVICES
■■■■
Special care is required for the following when handling the device :
• Prev e nting latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (V
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on
• Notes on using CAN Function
• Flash security Function
CC/VSS)
(External-bus mode)
MB90340 Series
1.Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions
• A voltage higher than V
• A voltage higher than the rated voltage is applied between VCC and VSS.
•The AV
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply v oltage (AV
power-supply voltage.
CC power supply is applied before the VCC voltage.
CC or lower than VSS is applied to an input or output pin.
:
CC, A VRH) e xceed the digital
2.Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3.Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90340 Series
X0
Open
X1
4.Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
23
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