Fairchild Semiconductor MM74HC74ASJX, MM74HC74ACW, MM74HC74AM, MM74HC74AMTC, MM74HC74AMTCX Datasheet
...
September 1983
Revised February 1999
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
© 1999 Fairchild Semiconductor Corporation DS005106.prf www.fairchildsemi.com
MM74HC74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS
technology to achieve operating speeds similar to the
equivalent LS-TTL part. It pos sesse s the high no ise imm unity and low power consumpti on of standard CMOS integrated circuits, along with the ability to drive 1 0 LS-TTL
loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q
outputs. The logic level present at the
data input is transferred to the outp ut during the positivegoing transition of the clock pulse. Preset and clear are
independent of the clock a nd accomplish ed by a low level
at the appropriate input.
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to V
CC
and ground.
Features
■ Typical propagation delay: 20 ns
■ Wide power supply range: 2–6V
■ Low quiescent current: 40 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ Fanout of 10 LS-TTL loads
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Pin Assignments f or DIP, SOIC, SOP and TSSOP
Truth Table
Note: Q0 = the level of Q before the indica t ed input condition s w ere estab-
lished.
Note 1: This configuration i s no nst able; tha t is, i t will n ot pe rsis t whe n p re-
set and clear inputs ret urn to their inactive (HI GH ) level.
Order Number Package Number Package Description
MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Outputs
PR CLR CLK D Q Q
LHXX H L
HL XX L H
L L X X H (Note 1) H (Note 1)
HH ↑ HH L
HH ↑ LL H
HH LX Q0 Q
0
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MM74HC74A
Logic Diagram
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MM74HC74A
Absolute Maximum Ratings(Note 2)
(Note 3)
Recommended Operating
Conditions
Note 2: Absolute Maximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 3: Unless otherwise specified all voltages are referenced to ground.
Note 4: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 5)
Note 5: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current, per pin
(I
CC
) ±50 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 4) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage 0 V
CC
V
(V
IN, OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.3 3.98 3.84 3.7 V
|I
OUT
| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
I
CC
Maximum Quiescent V
I N =VCC
or GND 6.0V 4.0 40 80 µA
Supply Current I
OUT
= 0 µA
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