Fairchild Semiconductor MM74HC4066N, MM74HC4066MTCX, MM74HC4066M, MM74HC4066SJX, MM74HC4066WM Datasheet

© 2000 Fairchild Semiconductor Corporation DS005355 www.fairchildsemi.com

August 1984
Revised January 2000

MM74HC4066 Quad Analog Switch

MM74HC4066
Quad Analog Switch

General Description

The MM74HC4066 devices are digi tally controlled analog
switches utilizing advanced silicon-gate CMOS technology.

These switches have low “ON” resis tance and low “OFF”
leakages. They are bi direc tional s witches , thus any anal og
input may be u sed as an outp ut and visa-ve rsa. Also the
MM74HC4066 switches contain linearization circuitry
which lowers the “ON” res istanc e and i ncreases switch l in­earity. The MM74HC4066 devices allow cont rol of up to
12V (peak) analog signals with digital control signals of the
same range. Each switch has its own contr ol input which
disables each switch when LOW. All analog inputs and out­puts and digital inputs are protected from electrostatic
damage by diodes to V

CC

and ground.

Features

■ Typical switch enable time: 15 ns

■ Wide analog input voltage range: 0–12V

■ Low “ON” resistance: 30 typ. (MM74HC4066)

■ Low quiescent current: 80 µA maximum (74HC)

■ Matched switch characteristics

■ Individual switch controls

Ordering Code:

Devices also available in T ape and Reel. Spec ify by appending the suffi x letter “X” to the ordering code.

Schematic Diagram Connection Diagram

Top View

Truth Table

Order Number Package Number Package Description

MM74HC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC4066SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Input Switch

CTL I/O–O/I

L “OFF”
H“ON”

www.fairchildsemi.com 2

MM74HC4066

Absolute Maximum Ratings(Note 1)

(Note 2)

Recommended Operating
Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the de vice may occur.

Note 2: Unless otherwise specified all voltages are ref erenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V ±10% the worst case on resistance (RON) occurs for HC at 4.5 V. Thus the 4.5V values should be used when designing with

this sup ply. Wor st case V

IH

and VIL occur at V

CC

= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs for
CMOS at the higher voltage an d so the 5.5V values should be used.
Note 5: At supply voltages (V

CC

–GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that

these devices be used to transmit digital only when using these supply voltages.

Supply Voltage (VCC) −0.5 to +15V
DC Control Input Voltage (V

IN

) −1.5 to V

CC

+1.5V

DC Switch I/O Voltage (V

IO

)V

EE

−0.5 to V

CC

+0.5V

Clamp Diode Current (I

IK

, IOK) ±20 mA

DC Output Current, per pin (I

OUT

) ±25 mA

DC V

CC

or GND Current, per pin (ICC) ±50 mA

Storage Temperature Range (T

STG

) −65°C to +150°C

Power Dissipation (P

D

)
(Note 3) 600 mW
S.O. Package only 500 mW

Lead Temperature (T

L

)
(Soldering 10 seconds) 260°C

Min Max Units

Supply Voltage (V

CC

)212V

DC Input or Output Voltage

(V

IN

, V

OUT

)0V

CC

V

Operating Temperature Range (T

A

) −40 +85 °C

Input Rise or Fall Times

(t

r

, tf) V

CC

= 2.0V 1000 ns

V

CC

= 4.5V 500 ns

V

CC

= 9.0V 400 ns

Symbol Parameter Conditions

V

CC

TA = 25°CTA = −40 to 85°CTA = −55 to 125°C

Units

Typ Guaranteed Limits

V

IH

Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V

9.0V 6.3 5.3 6.3 V

12.0V 8.4 8.4 8.4 V

V

IL

Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V

9.0V 2.7 2.7 2.7 V

12.0V 3.6 3.6 3.6 V

R

ON

Maximum “ON” Resistance V

CTL

= VIH, IS = 2.0 mA 4.5V 100 170 200 220 Ω

(Note 5) V

IS

= VCC to GND 9.0V 50 85 105 110 Ω

(Figure 1) 12.0 30 70 85 90 Ω

2.0V 120 180 215 240 Ω

V

CTL

= VIH, IS = 2.0 mA 4.5V 50 80 100 120 Ω

V

IS

= VCCor GND 9.0V 35 60 75 80 Ω

(Figure 1) 12.0V 20 40 60 70 Ω

R

ON

Maximum “ON” Resistance V

CTL

= V

IH

4.5V 10 15 20 20 Ω

Matching V

IS

= VCC to GND 9.0V 5 10 15 15 Ω

12.0V 5 10 15 15 Ω

I

IN

Maximum Control V

IN

= VCC or GND ±0.1 ±1.0 ±1.0 µA

Input Current V

CC

= 2−6V

I

IZ

Maximum Switch “OFF” V

OS

= VCC or GND 6.0V 10 ±60 ±600 ±600 nA

Leakage Current V

IS

= GND or V

CC

9.0V 15 ±80 ±800 ±800 nA

V

CTL

= VIL (Figure 3) 12.0V 20 ±100 ±1000 ±1000 nA

I

IZ

Maximum Switch “ON” V

IS

= VCC to GND 6.0V 10 ±40 ±150 ±150 nA

Leakage Current V

CTL

= V

IH

9.0V 15 ±50 ±200 ±200 nA

VOS = OPEN (Figure 2) 12.0V 20 ±60 ±300 ±300 nA

I

CC

Maximum Quiescent V

IN

= VCC or GND 6.0V 2.0 20 40 µA

Supply Current I

OUT

= 0 µA 9.0V 4.0 40 80 µA

12.0V 8.0 80 160 µA

3 www.fairchildsemi.com

MM74HC4066

AC Electr ic al C h ar acteristi cs

V

CC

= 2.0V−6.0V VEE = 0V−12V, CL = 50 pF (unless otherwise specified)

Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation).
Note 7: V

IS

is centered at VCC/2.

Note 8: Adjust input for 0 dBm.

Symbol Parameter Conditions

V

CC

TA = 25°CTA = −40 to 85°CTA = −55 to 125°C

Units

Typ Guaranteed Limits

t

PHL

, t

PLH

Maximum Propagation 2.0V 25 50 30 75 ns
Delay Switch In to Out 4.5V 5 10 13 15 ns

9.0V 4 8 10 12 ns

12.0V 3 7 11 13 ns

t

PZL

, t

PZH

Maximum Switch Turn RL = 1 kΩ 2.0V 30 100 125 150 ns

“ON” Delay 4.5V 12 20 25 30 ns

9.0V 6 12 15 18 ns

12.0V 5 10 13 15 ns

t

PHZ

, t

PLZ

Maximum Switch Turn RL = 1 kΩ 2.0V 60 168 210 252 ns
“OFF” Delay 4.5V 25 36 45 54 ns

9.0V 20 32 40 48 ns

12.0V 15 30 38 45

f

MAX

Minimum Frequency RL = 600Ω 4.5V 40 MHz
Response (Figure 7) V

IS

= 2 VPP at (VCC/2) 9.0V 100 MHz
20 log (VO/VI) = −3 dB (Note 6) (Note 7)
Crosstalk Between RL = 600Ω, F = 1 MHz
any Two Switches (Note 7) (Note 8) 4.5V −52 dB
(Figure 8) 9.0V −50 dB
Peak Control to Switch RL = 600Ω, F = 1 MHz 4.5V 100 mV
Feedthrough Noise (Figure 9) CL = 50 pF 9.0V 250 mV
Switch OFF Signal RL = 600Ω, F = 1 MHz
Feedthrough V

(CT)VIL

Isolation (Note 7) (Note 8) 4.5V −42 dB
(Figure 10) 9.0V −44 dB

THD Total Harmonic RL = 10 kΩ, CL = 50 pF,

Distortion F = 1 kHz
(Figure 11) V

IS

= 4 V

PP

4.5V .013 %

V

IS

= 8 V

PP

9.0V .008 %

C

IN

Maximum Control 5 10 10 10 pF
Input Capacitance

C

IN

Maximum Switch 20 pF
Input Capacitance

C

IN

Maximum Feedthrough V

CTL

= GND 0.5 pF

Capacitance

C

PD

Power Dissipation 15 pF
Capacitance