Fairchild Semiconductor MM74C00MX, MM74C00M Datasheet

October 1987
Revised January 1999

MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter

© 1999 Fairchild Semiconductor Corporation DS005877.prf www.fairchildsemi.com

MM74C00 • MM74C02 • MM74C04
Quad 2-Input NAND Gate •

Quad 2-Input NOR Gate •
Hex Inverter

General Description

The MM74C00, MM74C02, and MM74C04 logic gates
employ complementary MOS (CMOS) to achieve wide
power supply operating range, low power consumption,
high noise immunity a nd symmet ric contr olled ri se and fall
times. With features such as this the 74C logic family is
close to ideal for use in digital systems. Function and pin
out compatibility with series 74 devices minimizes de sign
time for those designer s already familiar wi th the standard
74 logic family.

All inputs are protected from damage due to static dis­charge by diode clamps to V

CC

and GND.

Features

■ Wide supply voltage range: 3V to 15V

■ Guaranteed noise margin: 1V

■ High noise immunity: 0.45 V

CC

(typ.)

■ Low power consumption: 10 nW/package (typ.)

■ Low power: TTL compatibility:

Fan out of 2 driving 74L

Ordering Code:

Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.

Connection Diagrams

Pin Assignments for DIP and SOIC

MM74C00

Top View

MM74C02

Top Vi ew

MM74C04

Top View

Order Number Package Number Package Description

MM74C00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C02N M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2

MM74C00 • MM74C02 • MM74C04

Absolute Maximum Ratings(Note 1)

Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the

safety of the device cannot be guaranteed. Ex ce pt for “O perating Tempera­ture Range” they are not mean t to imply that the devices sho uld be oper­ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device op eration.

DC Electrical Characteristics

Min/Max limits apply across the guaranteed temperature range unless otherwise noted

AC Electrical Charac teristics (Note 2)

TA = 25°C, CL = 50 pF, unless otherwise specified

Note 2: AC Parameters are guara nt eed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C

PD

determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion No te—

AN-90.

Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Operating V

CC

Range 3.0V to 15V

Maximum V

CC

Voltage 18V

Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature

(Soldering, 10 seconds) 300°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5.0V 3.5 V

VCC = 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5.0V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5.0V, IO = 10 µA0.5V

VCC = 10V, IO = 10 µA1.0V

I

IN(1)

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA

I

IN(0)

Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

I

CC

Supply Current VCC = 15V 0.01 15 µA

LOW POWER TO CMOS

V

IN(1)

Logical “1” Input Voltage 74C, VCC = 4.75V VCC − 1.5 V

V

IN(0)

Logical “0” Input Voltage 74C, VCC = 4.75V 0.8 V

V

OUT(1)

Logical “1” Output Voltage 74C, VCC = 4.75V, IO = −10 µA4.4 V

V

OUT(0)

Logical “0” Output Voltage 74C, VCC = 4.75V, IO = 10 µA0.4V

CMOS TO LOW POWER

V

IN(1)

Logical “1” Input Voltage 74C, VCC = 4.75V 4.0 V

V

IN(0)

Logical “0” Input Voltage 74C, VCC = 4.75V 1.0 V

V

OUT(1)

Logical “1” Output Voltage 74C, VCC = 4.75V, IO = −360 µA2.4 V

V

OUT(0)

Logical “0” Output Voltage 74C, VCC = 4.75V, IO = 360 µA0.4V

OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current)

I

SOURCE

Output Source Current VCC = 5.0V, V

IN(0)

= 0V, V

OUT

= 0V −1.75 mA

I

SOURCE

Output Source Current VCC = 10V, V

IN(0)

= 0V, V

OUT

= 0V −8.0 mA

I

SINK

Output Sink Current VCC = 5.0V, V

IN(1)

= 5.0V, V

OUT

= V

CC

1.75 mA

I

SINK

Output Sink Current VCC = 10V, V

IN(1)

= 10V, V

OUT

= V

CC

8.0 mA

Symbol Parameter Conditions Min Typ Max Units

MM74C00, MM74C02, MM74C04

t

pd0

, t

pd1

Propagation Delay Time to VCC = 5.0V 50 90 ns
Logical “1” or “0” VCC = 10V 30 60 ns

C

IN

Input Capacitance (Note 3) 6.0 pF

C

PD

Power Dissipation Capacitance Per Gate or Inverter (Note 4) 12 pF