Fairchild Semiconductor KSR2007 Datasheet
KSR2007
KSR2007
Switching Application
(Bias Resistor Built In)
• Switching circuit, Inverter, Interface circuit, Driver Circuit
• Built in bias Resistor (R
=22KΩ, R2=47KΩ)
1
• Complement to KSR1007
1
TO-92
1. Emitter 2. Collector 3. Base
Equivalent Circuit
R1
B
R2
PNP Epitaxial Silicon Transistor
Absolute Maximum Ratings
Symbol Parameter Value Units
V
V
V
I
P
T
T
CBO
CEO
EBO
C
C
J
STG
Collector-Base Voltage -50 V
Collector-Emitter Voltage -50 V
Emitter-Base Voltage -10 V
Collector Current -100 mA
Collector Power Dissipation 300 mW
Junction Temperature 150 °C
Storage Temperature -55 ~ 150 °C
Ta=25°C unless otherwise noted
C
E
Electrical Characteristics
Ta=25°C unless otherwise noted
Symbol Parameter Tes t Condition Min. Typ. Max. Units
BV
CBO
BV
CEO
I
CBO
h
FE
(sat) Collector-Emitter Saturation Voltage IC= -10mA, IB= -0.5mA -0.3 V
V
CE
C
ob
Collector-Base Breakdown Voltage IC= -10µA, IE=0 -50 V
Collector-Emitter Breakdown Voltage IC= -100µA, IB=0 -50 V
Collector Cut-off Current VCB= -40V , IE=0 -0.1 µA
DC Current Gain VCE= -5V, IC= -5mA 68
Output Capacitance VCB= -10V , IE=0
5.5 pF
f=1MHz
f
T
(off) Input Off Voltage VCE= -5V, IC= -100µA-0.4 V
V
I
(on) Input On Voltage VCE= -0.3V, IC= -2mA -2.5 V
V
I
R
1
R
1/R2
©2002 Fairchild Semiconductor Corporation Rev. A3, October 2002
Current Gain-Bandwidth Product VCE= -10V , IC= -5mA 200 MHz
Input Resistor 15 22 29 KΩ
Resistor Ratio 0.42 0.47 0.52
Typical Characteristics
KSR2007
1000
100
10
, DC CURRENT GAIN
FE
h
1
-0.1 -1 -10 -100
IC[mA], COLLECTOR CURRENT
Figure 1. DC current Gain Figure 2. Input On Voltage
-10k
-1k
-100
A], COLLECTOR CURRENT
-10
µ
[
C
I
-1
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3 -1.5 -1.7 -1.9 -2.1
VI(OFF)[V], INPUT OFF VOLTAGE
VCE = - 5V
R1 = 22K
R2 = 47K
VCE = - 5V
R1 = 22K
R2 = 47K
-100
VCE =- 0.3V
R1 = 22K
R2 = 47K
-10
-1
(on)[V], INPUT VOLTAGE
I
V
-0.1
-0.1 -1 -10 -100
IC[mA], COLLECTOR CURRENT
400
350
300
250
200
150
100
[mW], POWER DISSIPATION
C
50
P
0
0 255075100125150175
Ta[oC], AMBIENT TEMPERATURE
Figure 3. Input Off Voltage Figure 4. Power Derating
©2002 Fairchild Semiconductor Corporation
Rev. A3, October 2002
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