Fairchild Semiconductor KSR2001 Datasheet
KSR2001
Switching Application (Bias Resistor Built In)
• Switching circuit, Inverter, Interface circuit, Driver Circuit
• Built in bias Resistor (R
• Complement to KSR1001
=4.7KΩ, R2=4.7KΩ)
1
KSR2001
1
TO-92
1. Emitter 2. Collector 3. Base
Equivalent Circuit
R1
B
R2
C
PNP Epitaxial Silicon Transistor
E
Absolute Maximum Ratings
Symbol Parameter Value Units
V
V
V
I
P
T
T
CBO
CEO
EBO
C
C
J
STG
Collector-Base Voltage -50 V
Collector-Emitter Voltage -50 V
Emitter-Base Voltage -10 V
Collector Current -100 mA
Collector Power Dissipation 300 mW
Junction Temperature 150 °C
Storage Temperature -55 ~ 150 °C
Electrical Characteristics
Symbol Parameter Tes t Condition Min. Typ. Max. Units
BV
CBO
BV
CEO
I
CBO
h
FE
(sat) Collector-Emitter Saturation Voltage IC= -10mA, IB= -0.5mA -0.3 V
V
CE
f
T
C
ob
V
(off) Input Off Voltage VCE= -5V, IC= -100µA-0.5 V
I
(on) Input On Voltage VCE= -0.3V, IC= -20mA -3 V
V
I
R
1
R
1/R2
Collector-Base Breakdown Voltage IC= -10µA, IE=0 -50 V
Collector-Emitter Breakdown Voltage IC= -100µA, IB=0 -50 V
Collector Cut-off Current VCB= -40V , IE=0 -0.1 µA
DC Current Gain VCE= -5V, IC= -10mA 20
Current Gain Bandwidth Product VCE= -5mA, IC= -10V 200 MHz
Output Capacitance VCB= -10V , IE=0
Input Resistor 3.2 4.7 6.2 KΩ
Resistor Ratio 0.9 1 1.1
Ta=25°C unless otherwise noted
Ta=25°C unless otherwise noted
5.5 pF
f=1.0MHz
©2002 Fairchild Semiconductor Corporation Rev. A2, October 2002
Typical Characteristics
KSR2001
1000
100
, DC CURRENT GAIN
FE
h
10
-1 -10 -100 -1000
IC[mA], COLLECTOR CURRENT
Figure 1. DC current Gain Figure 2. Input On Voltage
-1000
-100
A], COLLECTOR CURRENT
µ
[
C
I
-10
-0.0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4
VI(OFF)[V], INPUT OFF VOLTAGE
VCE = - 5V
R1 = 4.7 K
R2 = 4.7 K
VCE = - 5V
R1 = 4.7K
R2 = 4.7K
-100
VCE =- 0.3V
R1 = 4.7 K
R2 = 4.7 K
-10
-1
(on)[V], INPUT VOLTAGE
I
V
-0.1
-0.1 -1 -10 -100
IC[mA], COLLECTOR CURRENT
400
350
300
250
200
150
100
[mW], POWER DISSIPATION
C
50
P
0
0 255075100125150175
Ta[oC], AMBIENT TEMPERATURE
Figure 3. Input Off Voltage Figure 4. Power Derating
©2002 Fairchild Semiconductor Corporation
Rev. A2, October 2002
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