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KSE2955T
General Purpose and Switching Applications
• DC Current Gain Specified to IC = 10 A
• High Current Gain Bandwidth Product : f
= 2MHz (Min.)
T
KSE2955T
1
TO-220
1.Base 2.Collector 3.Emitter
PNP Silicon Transistor
Absolute Maximum Ratings
Symbol Parameter Value Units
V
V
V
I
IB
P
CBO
CEO
EBO
C
C
Collector-Base Voltage - 70 V
Collector-Emitter Voltage - 60 V
Emitter-Base Voltage - 5 V
Collector Current - 10 A
Base Current - 6 A
Collector Dissipation (TC=25°C) 75 W
Collector Dissipation (T
T
J
T
STG
Junction Temperature 150 °C
Storage T emperature - 55 ~ 150 °C
Electrical Characteristics
Symbol Parameter Test Condition Min. Max. Units
BV
CEO
I
CEO
I
CEX1
I
CEX2
I
EBO
h
FE
V
(sat) * Collector-Emitter Saturation Voltage IC = - 4A, IB = - 0.4A
CE
(on) * Base-Emitter On Voltage V
V
BE
f
T
* Pulse test: PW≤300µs, duty cycle≤2% Pulse
Collector- Emitter Breakdown Voltage IC= - 200mA, IB = 0 -60 V
Collector Cut-off Current V
Collector Cut-off Current V
Collector Cut-off Current V
Emitter Cut-off Current V
* DC Current Gain
Current Gain Bandwidth Product V
TC=25°C unless otherwise noted
=25°C) 0.6 W
a
TC=25°C unless otherwise noted
= - 30V, IB = 0 -700 µA
CE
= - 70V, VBE(off) = 1.5V -1 mA
CE
= - 70V, VBE(off) = 1.5V
CE
@ T
= 150°C
C
= - 5V, IC = 0 -5 mA
EB
V
= - 4V, IC = - 4A
CE
= - 4V, IC = - 10A
V
CE
-5 mA
20 5100
-1.1
= - 10A, IB = - 3.3A
I
C
= - 4V, IC = - 4A -1.8 V
CE
= - 10V, IC = - 500mA 2 MHz
CE
-8
V
V
©2000 Fairchild Semiconductor International Rev. A1, December 2000
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Typical Characteristic
KSE2955T
1000
100
10
, DC CURRENT GAIN
FE
h
1
-0.01 -0.1 -1 -10
IC[A], COLLECTOR CURRENT
Figure 1. DC current Gain Figure 2. Base-Emitter Saturation Voltage
-100
-10
-1
[A], COLLECTOR CURRENT
C
I
-0.1
-1 -10 -100
VCE[V], COLLECTOR-EMITTER VOLTAGE
1ms
5ms
DC
VCE = -2V
100
µ
-10
-1
VBE(sat)
-0.1
(sat)[V], SATURATION VOLTAGE
CE
(sat), V
BE
V
-0.01
-0.1 -1 -10 -100
VCE(sat)
IC = 10I
B
IC[A], COLLECTOR CURRENT
Collector-Emitter Saturation Voltage
105
90
75
s
60
45
30
[W], POWER DISSIPATION
C
P
15
0
0 255075100125150175
TC[oC], CASE TEMPERATURE
Figure 3. Safe Operating Area Figure 4. Power Derating
©2000 Fairchild Semiconductor International
Rev. A1, December 2000