Fairchild Semiconductor FDN358P Datasheet
March 1998
FDN358P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
D
358
S
SuperSOT -3
TM
G
-1.5 A, -30 V, R
R
= 0.125 Ω @ VGS = -10 V
DS(ON)
= 0.20 Ω @ VGS = - 4.5 V.
DS(ON)
High power version of industry SOT-23 package: identical
pin out to SOT-23; 30% higher power handling capability.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SO-8 SOT-223
D
G
SOIC-16
S
Absolute Maximum Ratings T
= 25oC unless other wise noted
A
Symbol Parameter FDN358P Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain/Output Current - Continuous -1.5 A
- Pulsed -5
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1998 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
FDN358P Rev.D
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
I
GSSF
I
GSSR
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = -250 µA, Referenced to 25 oC
VDS = -24 V, V
GS
= 0 V
-28
-1 µA
TJ = 55°C
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
mV/ oC
-10 µA
-100 nA
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.5 -2 V
Gate Threshold Voltage Temp. Coefficient
/∆T
J
Static Drain-Source On-Resistance
ID = -250 µA, Referenced to 25 oC
VGS = -10 V, ID = -1.5 A
3
0.11 0.125
mV/ oC
TJ =125°C 0.15 0.21
0.175 0.2
7 S
I
g
D(ON)
FS
VGS = -4.5 V, ID = -1.2 A
On-State Drain Current VGS = -4.5 V, VDS = -5 V -5 A
Forward Transconductance
VDS = -10 V, I
= -1.5 A
D
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, VGS = 0 V,
Output Capacitance 150 pF
f = 1.0 MHz
270 pF
Reverse Transfer Capacitance 45 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 7 14 ns
VDD = -15 V, ID = -1 A,
VGS = -10 V, R
GEN
= 6 Ω
Turn - Off Delay Time 17 27 ns
Turn - Off Fall Time 10 1.8 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1 nC
Gate-Drain Charge 1.1 nC
VDS = -5 V, ID = -1.5 A,
VGS = -10 V
8 16 ns
6.5 9.1 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Note:
1. R
JA
θ
design while R
Typical R
Maximum Continuous Drain-Source Diode Forward Current -0.42 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 A (Note 2) -0.74 -1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
using the board layouts shown below on FR-4 PCB in a still air environment :
JA
θ
is guaranteed by
JC
θ
Ω
o
a. 250
C/W when mounted on a
0.02 in2 pad of 2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
o
b. 270
C/W when mounted on
2
a 0.001 in
pad of 2oz Cu.
FDN358P Rev.D
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