Fairchild Semiconductor FDN308P Datasheet
FDN308P
P-Channel 2.5V Specified PowerTrench
MOSFET
FDN308P
February 2001
General Description
This P-Channel 2.5V specif ied MOSFE T uses a rugged
gate version of Fairchild’s advanced PowerTrench
process. It has been opt imized for power management
applications with a wide range of gate drive voltage
(2.5V – 12V).
Applications
• Power management
• Load switch
• Battery protection
Features
• –20 V, –1.5 A. R
R
• Fast switching speed
• High performance trench te chnology for extremely
low R
• SuperSOT
power handling capability than SOT23 in the same
footprint
DS(ON)
TM
-3 provides low R
= 125 mΩ @ VGS = –4.5 V
DS(ON)
= 190 mΩ @ VGS = –2.5 V
DS(ON)
and 30% higher
DS(ON)
D
D
S
G
SuperSOT -3
TM
Absolute Maximum Ratings T
G
o
=25
C unless otherwise noted
A
Symbol Parameter Ratings Units
V
Drain-Source Voltage –20 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1a) –1.5 A
– Pulsed
PD
TJ, T
STG
Maximum Power Dissipation (Note 1a)
Operating and Storage Junction Temperature Range –55 to +150
(Note 1b)
±12
–10
0.5
0.46
S
V
W
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 250
(Note 1) 75
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
308 FDN308P 7’’ 8mm 3000 units
2001 Fairchild Semiconductor Corporation
°C/W
°C/W
FDN308P Rev B(W)
FDN308P
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
∆BVDSS
∆T
I
Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1
DSS
I
GSSF
I
GSSR
Breakdown Voltage Temperature
Coefficient
J
Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –12 V VDS = 0 V –100 nA
= 0 V, ID = –250 µA
V
GS
= –250 µA,Referenced to 25°C
I
D
–20 V
–13
mV/°C
µA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
I
On–State Drain Current VGS = –4.5 V, VDS = –5 V –5 A
D(on)
= VGS, ID = –250 µA
V
DS
= –250 µA,Referenced to 25°C
I
D
VGS = –4.5 V, ID = –1.5 A
= –2.5 V, ID = –1.3 A
V
GS
V
= –4.5 V, ID = –1.5A TJ=125°C
GS
gFS Forward Transconductance VDS = –5 V, ID = –1.5 A 12 S
–0.6 –1.0 –1.5 V
3
86
136
114
125
190
178
mV/°C
mΩ
Dynamic Characteristics
C
Input Capacitance 341 pF
iss
C
Output Capacitance 83 pF
oss
C
Reverse Transfer Capacitance
rss
t
Turn–On Delay Time 8 16 ns
d(on)
tr Turn–On Rise Time 10 20 ns
t
Turn–Off Delay Time 12 22 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 3.8 5.4 nC
Qgs Gate–Source Charge 0.8 nC
Qgd Gate–Drain Charge
= –10 V, V
V
DS
GS
f = 1.0 MHz
= –10 V, ID = –1 A,
V
DD
= –4.5 V, R
V
GS
V
= –10V, ID = –1.5 A,
DS
= –4.5 V
V
GS
GEN
= 0 V,
43 pF
= 6 Ω
8 16 ns
1.0 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current –0.42 A
VSD Drain–Source Diode Forward
Voltage
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
is guaranteed by design while R
θJC
a) 250°C/W when mounted on a
2
pad of 2 oz. copper.
0.02 in
θCA
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
V
= 0 V, IS = –0.42 (Note 2)
GS
is determined by the user's board design.
b) 270°C/W when mounted on a
minimum pad.
–0.7
–1.2 V
FDN308P Rev B(W)
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