Fairchild Semiconductor DM74LS283N, DM74LS283MX, DM74LS283M, DM74LS283CW Datasheet

August 1986 Revised March 2000

DM74LS283 4-Bit Binary Adder with Fast Carry

General Description

These full adders perfor m the addition of two 4-bi t binary numbers. The sum (∑) outputs are pr ovided for each bit and the resultant car ry (C4 ) is obt aine d from the f ourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the econom y and red uced packa ge count of a ripple-carry implementation.

The adder logic, i ncluding the carry, is implemente d in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Features

■ Full-carry look-ahead across the four bits

■ Systems achieve partial look-ahead performance with

the economy of ripple carry

■ Typical add times Two 8-bit words 25 ns Two 1 6-bit words 45 ns

■ Typical power d issipation per 4-bit adder 95 mW

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74LS283M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS283N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74LS283

Function Table

H = HIGH Level, L = LOW Level Input conditions at A1, B1, A2, B2, and C0 are us ed to determine outputs ∑1 and ∑2 and the value of the internal c arry C2.

The values at C2, A3 , B3, A4, and B4 are then use d to determine outputs ∑3, ∑4, and C4.

Logic Diagram

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