Fairchild Semiconductor DM74AS245WM, DM74AS245SJX, DM74AS245SJ, DM74AS245N Datasheet

© 2000 Fairchild Semiconductor Corporation DS006299 www.fairchildsemi.com

October 1986
Revised February 2000

DM74AS245 Octal Bus Transceiver with 3-STATE Outputs

DM74AS245
Octal Bus Transceiver with 3-STATE Outputs

General Description

This advanced Schottky device contains 8 pairs of
3-STATE logic elements con figu red as octal bu s transc eiv­ers. These circuits ar e design ed for use i n m emory, micro­processor systems and in asynchro nous bidirectional da ta
buses. Two way communication between buses is con­trolled by the (DIR) input. Data transm its either f rom the A
bus to the B bus or from the B bus to the A bus. Both the
driver and receiver outputs can be disabled via the (G

)
enable input which causes outputs to enter the high imped­ance mode so that the buses are effectively isolated.

Features

■ Advanced oxide-isolated, ion-implanted Schottky
TTL process

■ Non-inverting logic output

■ 3-STATE outputs independently controlled on

A and B buses

■ Low output impedance to drive terminate d transmission
lines to 133Ω

■ Switching response specified into 500Ω/50 pF

■ Specified to interface with CMOS at V

OH

= VCC − 2V

■ PNP inputs reduce input loading

■ Switching specifications guaranteed over full

temperat ure and V

CC

range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

Order Number Package Number Package Description

DM74AS245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74AS245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Control

Inputs Operation

G

DIR

L L B Data to A Bus
L H A Data to B Bus

H X Hi-Z

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DM74AS245

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings” are those values beyond which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s
for actual device operation.

Recommended Operating Conditions

Electrical Characteristics

over recommended operating free air temperature range

Switching Characteristics

over recommended operating free air temperature range

Supply Voltage, V

CC

7V

Input Voltage

Control Inputs 7V

I/O Ports 5.5V
Operating Free Air Temperature Range 0°C to 70°C
Storage Temperature Range −65°C to +150°C
Typical θ

JA

N Package 51.5°C/W

M Package 76.0°C/W

Symbol Parameter Min Typ Max Units

V

CC

Supply Voltage 4.5 5 5.5 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −15 mA

I

OL

LOW Level Output Current 48 mA

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

V

IK

Input Clamp Voltage VCC = 4.5V, IIN = −18 mA −1.2 V

V

OH

HIGH Level Output VCC = 4.5V, IOH = −3 mA 2.4 3.2
Voltage VCC = 4.5V, IOH = −15 mA 2 2.3 V

IOH = −2 mA, VCC = 4.5V to 5.5V VCC − 2

V

OL

LOW Level Output Voltage VCC = 4.5V, IOL = Max 0.35 0.55 V

I

I

Input Current at Max VCC = 5.5V, VIN = 7V,

0.1 mA

Input Voltage (VIN = 5.5V for A or B Ports)

I

IH

HIGH Level Input Current VCC = 5.5V, Control Inputs 20

µA

VIN = 2.7V A or B Ports 70

I

IL

LOW Level Input Current VCC = 5.5V, Control Inputs −0.5

mA

VIN = 0.4V A or B Ports −0.75

I

O

Output Drive Current VCC = 5.5V, V

OUT

= 2.25V −50 −150 mA

I

CC

Supply Current VCC = 5.5V Output HIGH 62 97

Output LOW 95 149 mA
3-STATE 79 123

Symbol Parameter Conditions From To Min Max Units

t

PLH

Propagation Delay Time VCC = 4.5V to 5.5V,

A or B B or A 2 7.5 ns

HIGH-to-LOW Level Output R1 = R2 = 500Ω,

t

PHL

Propagation Delay Time CL = 50 pF

A or B B or A 2 7 ns

HIGH-to-LOW Level Output

t

PZL

Output Enable Time to LOW Level G A or B 2 8.5 ns

t

PZH

Output Enable Time to HIGH Level G A or B 2 9 ns

t

PLZ

Output Disable Time from LOW Level G A or B 2 9.5 ns

t

PHZ

Output Disable Time fr om HI GH Leve l G A or B 2 5.5 ns