Fairchild Semiconductor DM74AS169AN, DM74AS169AMX, DM74AS169AM Datasheet

© 2000 Fairchild Semiconductor Corporation DS006292 www.fairchildsemi.com

April 1984
Revised March 2000

DM74AS169A Synchronous 4-Bit Binary Up/Down Counter

DM74AS169A
Synchronous 4-Bit Binary Up/Down Counter

General Description

These synchronous presettabl e counters feature an inter­nal carry look ahe ad for c ascading i n high speed co unting
applications. The DM74AS169 is a 4-bit binary up/down
counter. The carry output is decoded to prevent spikes dur­ing normal mode of counting operation. Synchronous oper­ation is provided so th at outputs change coincident with
each other when so in structed by count ena ble inputs a nd
internal gating. This mode of op eration elim inates the out­put counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive going)
edge of clock input waveform.

These counters are fully programmable; that is, the outputs
may each be preset either HIGH or LOW. The load input
circuitry allows loading with carry-enable output of cas­caded counters. As loading is synchr onous, setting up a
LOW level at the load input disables the counter and
causes the outputs to a gree with the data inputs after the
next clock pulse.

The carry look-ahead cir cuitry permits casca ding counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (P

and T) must be LOW to count.
The direction of the co unt is determ ined b y the leve l of t he
up/down input. When the input is HIGH, the counter counts
UP; when LOW, it counts DOWN . Inpu t T is fed fo rwa rd to
enable the carry outputs. The carry output thus enabled will
produce a LOW level output pulse w ith a d uration appro xi­mately equal to the HIGH portio n of the QA output when
counting UP, and approximately equal to t he LOW port ion
of the QA output when counting DOWN. This LOW level
overflow carry pulse can be used to enable s uccessively
cascaded stages. Transitions at the enable P

or T inputs

are allowed regardless of the level of the clock input.
The control function s for these counters are fully synchr o-

nous. Changes at control inpu ts (enab le P

, enable T, load,
up/down) which modify the opera ting mode have no effect
until clocking occurs. The func tion of the counte r (whether
enabled, disabled, loading or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.

Features

■ Switching Specifications at 50 pF

■ Switching Specifications gua ranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart

■ Improved AC performance over Schottky and low power
Schottky counterparts

■ Synchronously programmable

■ Internal look ahead for fast counting

■ Carry out put for n-bit cascading

■ Synchronous counting

■ Load control line

■ ESD inputs

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Order Number Package Number Package Description

DM74AS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74AS169A

Connection Diagram

Logic Diagram

DM74AS169A