Fairchild Semiconductor 74LVTH373WMX, 74LVTH373WM, 74LVTH373SJX, 74LVTH373SJ, 74LVTH373MTCX Datasheet

© 1999 Fairchild Semiconductor Corporation DS012015 www.fairchildsemi.com

September 1999
Revised October 1999

74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs

74LVT373 • 74LVTH373
Low Voltage Octal Transparent Latch

with 3-STATE Outputs

General Description

The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH . Wh en LE is LOW, the data satisfying
the input timing requir ements is latche d. Data appears on
the bus when the Output Enable (OE

) is LOW. When OE is

HIGH, the bus output is in a high impedance state.
The LVTH373 data inputs include bush old, eliminati ng the

need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)

V

CC

applications, but with the capability to provide a TTL

interface to a 5V environme nt. The LVT373 and LVTH373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.

Features

■ Input and output interface capability to systems at
5V V

CC

■ Bushold data inputs elimina te the nee d for exte rnal pul l­up resistors to hold unused inputs (74LVTH373), also
available without bushold feature (74LVT373).

■ Live insertion/extraction per mitt ed

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs source/sink −32 mA/+64 mA

■ Functionally compatible with the 74 series 373

Ordering Code:

Logic Symbols

IEEE/IEC

Order Number Package Number Package Description

74LVT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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74LVT373 • 74LVTH373

Connection Diagram Pin Descriptions

Tr uth Table

H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O

0

= Previous O0 before HIGH-to-LOW transition of Latch Enable

Functional Description

The LVT373 and LVTH373 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the D

n

inputs enters the

latches. In this condition the latches are transpar ent, i.e., a
latch output will change state each time its D input
changes. When LE is LOW, the latches store the informa­tion that was pres ent on th e D inp uts a s etup ti me preced -

ing the HIGH-to-LOW transition of LE. The 3-STATE
standard outputs are cont rolled by the Output E nable (OE

)

input. When OE

is LOW, the standard outputs are i n the 2-

state mode. When OE

is HIGH, the standard outputs are in
the high impedance m ode but this does not in terfere with
entering new data into the latches.

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

D

0–D7

Data Inputs
LE Latch Enable Input
OE

Output Enable Input
O

0–O7

3-STATE Latch Outputs

Inputs Outputs

LE OE

D

n

O

n

XHXZ
HLLL
HLHH
LLXO

0

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74LVT373 • 74LVTH373

Absolute Maximum Ratings(Note 1)

Recommended Operating Conditions

Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indica te d m ay adversely affect dev ic e reliability. Functional operation under absolute maxim um rated conditions is not imp lied.
Note 2: I

O

Absolute Maximum Rating must be observed.

Symbol Parameter Value Conditions Units

V

CC

Supply Voltage −0.5 to +4.6 V

V

I

DC Input Voltage −0.5 to +7.0 V

V

O

DC Output Voltage −0.5 to +7.0 Output in 3-STATE V

−0.5 to +7.0 Output in HIGH or LOW State (Note 2) V

I

IK

DC Input Diode Current −50 VI < GND mA

I

OK

DC Output Diode Current −50 VO < GND mA

I

O

DC Output Current 64 VO > VCCOutput at HIGH State

mA

128 V

O

> VCCOutput at LOW State

I

CC

DC Supply Current per Supply Pin ±64 mA

I

GND

DC Ground Cu rrent per Ground Pin ±128 mA

T

STG

Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

V

CC

Supply Voltage 2.7 3.6 V

V

I

Input Voltage 0 5.5 V

I

OH

HIGH Level Output Current −32 mA

I

OL

LOW Level Output Current 64 mA

T

A

Free-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate, V

IN

= 0.8V–2.0V, VCC = 3.0V 0 10 ns/V