Fairchild Semiconductor 74LVTH32245, 74LVT32245 Datasheet

March 2002
Revised June 2002

74LVT32245 • 74LVTH32245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs

74LVT32245 • 74LVTH32245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs

General Description

The LVT32245 and LVTH32245 contain thirty-two non­invertin g bidi rec tio nal bu ff er s wit h 3-STATE output s and ar e
intended for bus oriented applications. The devices are
byte controlled. Each byte has separate control inputs
which can be shorted tog eth er for full 32-bit opera tion. The
T/R

inputs determine th e di rection of data flow throug h the
device. The OE
placing them in a high impedance state.

The LVTH32245 data inputs includ e bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.

These non-inverting tr ansc ei ver s ar e de signe d fo r l ow vo lt­age (3.3V) V

vide a TTL interface to a 5V environment. Th e LVT32245
and LVTH32245 are fabricated with an adva nced B iCMOS
technology to achieve high speed ope ration similar to 5V
ABT while maintaining low power dissipation.

inputs disable bo th the A and B ports by

applications, but with the capability to pro-

CC

Features

■ Input and output interface capability to systems at
5V V

CC

■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32245),
also available without bushold feature (74LVT32245).

■ Live insertion/extraction per mi tt ed

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs source/sink

■ ESD performance:

Human-body model
Machine model
Charged-device model

■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

−32 mA/+64 mA

> 2000V

> 200V

Ordering Code:

Order Number Package Number Package Description

74LVT32245G
(Note 1)(Note 2)

74LVTH32245G
(Note 1)(Note 2)

Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

BGA96A

(Preliminary)

BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Logic Symbol

> 1000V

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Connection Diagram

74LVT32245 • 74LVTH32245

(Top Thru View)

Pin Descriptions

Pin Names Description

OE
T/R
A

0–A31

B

0–B31

n

n

Output Enable Input (Active LOW)
Transmit/Receive Input

Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs

FBGA Pin Assignments

123456

A B
B B
C B
D B
E B
F B

G B

H B
J B

K B
L B

M B

N B
P B
R B

T B

B0T/R1OE1A

1

B2GND GND A2A

3

B4V

5
7

9
11
13B12

14B15
17B16

19B18
21B20VCC2VCC2A20A21
23B22
25B24
27B26VCC2VCC2A26A27
29B28

30B31

CC1VCC1A4

B6GND GND A
B8GND GND A

B10V

CC1VCC1A10A11

GND GND A

T/R2OE2A
T/R3OE3A

GND GND A

GND GND A
GND GND A

GND GND A

T/R4OE4A

A

0

A
A

6

A

8

12A13
15A14
16A17

18A19

22A23
24A25

28A29
31A30

1
3
5
7
9

Truth Tables

Inputs

T/R

OE

1

1

L L Bus B0–B7 Data to Bus A0–A
L H Bus A0–A7 Data to Bus B0–B
HXHIGH–Z State on A0–A7,B0–B

Inputs

T/R

OE

2

2

L L Bus B8–B15 Data to Bus A8–A
L H Bus A8–A15 Data to Bus B8–B
H X HIGH–Z State on A8–A15,B8–B

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

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Outputs

7
7

7

Outputs

15
15

15

Inputs

OE3T/R

3

Outputs

L L Bus B16–B23 Data to Bus A16–A
L H Bus A16–A23 Data to Bus B16–B

H X HIGH–Z State on A16–A23,B16–B

Inputs

OE4T/R

4

Outputs

L L Bus B24–B31 Data to Bus A24–A
L H Bus B24–A

Data to Bus B24–B

31

H X HIGH–Z State on A24–A31,B24–B

23
23

23

31
31

31